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Names: »D50«
└─⟦1e8064b49⟧ Bits:30005867/disk07.imd Dokumenter (RCSL m.m.)
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T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
1. GENEREL ................................................ 1
1.1 Components ........................................ 1
1.1.1 MBA 201 .................................... 2
1.1.2 MBA 601 .................................... 3
1.1.3 MBA 603 .................................... 3
2. SPECIFICATIONS ......................................... 4
2.1 Performance Specifications ........................ 4
2.2 Electrical Specifications ......................... 4
2.3 Environmental Specifications ...................... 4
2.4 Physical Specifications ........................... 4
3. IDENTIFICATION OF ITEMS ................................ 5
4. INSTALLATION ........................................... 6
4.1 Installation of MBA 201 ........................... 6
4.2 Installation of MBA 601/603 ....................... 6
4.2.1 Installation of MBA 601 .................... 7
4.2.2 Installation of MBA 603 .................... 7
4.3 Straps and Switches ............................... 8
4.3.1 Straps on MBA 201 .......................... 8
4.3.2 Straps and Switches on MBA 603 ............. 10
4.3.3 Straps and Switches on MBA 601 ............. 12
\f
1_._ _ _ _ _ _ _ _ _G_E_N_E_R_E_L_ 1.
The MBA (Multi Bus Adapter) family is designed as an inter-
connection method between RC computersystems via the Intel
Multibus.
This connection method enables large expansion of systems in
capacity, performance and in reliability. It also extends the
repertoire of external devices available to the individual
systems.
An important effect of using the widely acknowledged industri
standard which the Multibus makes out, is the possibility to take
immediate advantage of non-RC controllers and processors develop-
ed for this bus.
The Multibus connection may be viewed as the closest intercon-
nection medium in a distributed system architecture, where the
more distant interconnections are made up by CIRCUIT, Ethernet
and conventional datatransmission links.
1_._1_ _ _ _ _ _ _ _C_o_m_p_o_n_e_n_t_s_ 1.1
At the present the MBA family contains the members and combina-
tions:
MBA 601
MBA 201 - or
MBA 603
MBA 601
IFP 701 - or
MBA 603
and
IFP 801 - MBA 602
\f
MBA 201 connects to RC3502
IFP 701 - - RC3600
IFP 801 - - RC8000
MBA 601 - - Multibus as master
MBA 602 - - - - slave
MBA 603 - - - - master
In all cases the cable is a 50 lead ribbon-cable of length up to
12 m (RC8402 S/M/L).
MBA 601 and MBA 603 are compatible and differ only in that MBA
601 in contrast to MBA 603 has 32 K bytes on board dual port
memory plus a memory-write-interrupt feature. MBA 601/603 is
installed in the Multibus as a master; this requires considera-
tions to be made about priority and clockgenerators.
MBA 601 has memory, which is accessible from the Multibus; this
memory must have assigned an area in the address space of the
Multibus. This assignment is made at installation time.
MBA 602 which connects to IFP 801 gives the Multibus access to a
memory physically located on the IFP 801 board. This memory must
have assigned an area and a size in the address space of the
Multibus. This assignment is made at installation time.
MBA 201 and MBA 701 both give their hosts (RC3502 and RC3600)
access to most of the address-space on the Multibus via MBA 601
or MBA 603.
1_._1_._1_ _ _ _ _ _M_B_A_ _2_0_1_ 1.1.1
MBA 201 is an RC3502-controller in double Euroboard format. It
occupies one slot in the RC3502 crate, 8 interrupt levels and all
memory address-space from a certain threshold and up. The address
threshold from which MBA responds to all memory addresses as well
as the first of the eight interrupt levels must be defined and
set on a switch array at installationtime.
\f
1_._1_._2_ _ _ _ _ _M_B_A_ _6_0_1_ 1.1.2
MBA 601 connects to the Multibus both as a master and a slave.
As a master MBA 601 addresses memory and I/O devices on the
Multibus as commanded by the remote MBA. The 64 K highest memory
addresses are not reachable from the remote MBA, because these
addresses sent from the remote MBA convert into I/O addressing.
As a master MBA 601 is also able to respond to interrupts on the
Interrupt lines of the Multibus and transmit the state of seven
of them to the remote MBA.
As a slave MBA 601 gives other masters on the Multibus access to
the 32 Kbytes of dual port RAM, which is physically located on
the MBA 601 board. The dual port memory occupies an area in the
Multibus address space, the location of which is the same when
seen from the remote MBA as when seen from the Multibus.
When the remote MBA addresses the dual port memory, the Multibus
is not affected, and the access is not delayed by the Multibus
being assigned to another master at this moment, unless this
other master is accessing the dual port memory simultaneously.
1_._1_._3_ _ _ _ _ _M_B_A_ _6_0_3_ 1.1.3
MBA 603 is essentially an MBA 601 without dual port memory.
\f
F_ 2_._ _ _ _ _ _ _ _ _S_P_E_C_I_F_I_C_A_T_I_O_N_S_ 2.
2_._1_ _ _ _ _ _ _ _P_e_r_f_o_r_m_a_n_c_e_ _S_p_e_c_i_f_i_c_a_t_i_o_n_s_ 2.1
Transfer speed between RC3502 and the Multibus does not exeed 400
K bytes/second in burst operations, provided 16 bit transfers.
For byte transfers the speed is 200 K bytes/sec. max.
When single operations or short bursts are to be transferred, the
capture time for the Multibus must be taken into consideration.
The capture time may vary from zero to tens of microseconds
depending on the total Multibus load.
2_._2_ _ _ _ _ _ _ _E_l_e_c_t_r_i_c_a_l_ _S_p_e_c_i_f_i_c_a_t_i_o_n_s_ 2.2
Power requirement:
MBA 201: +5 V +_0,25 V, 2 A
MBA 601: +5 V +_0,25 V, 3 A
+12 V +_0,6 V, 1 A
MBA 603: +5 V +_0,25 V, 2 A
2_._3_ _ _ _ _ _ _ _E_n_v_i_r_o_n_m_e_n_t_a_l_ _S_p_e_c_i_f_i_c_a_t_i_o_n_s_ 2.3
Ambient temperature: 16-32C (60-90F)
Relative Humidity: 20-80% (no condensation)
2_._4_ _ _ _ _ _ _ _P_h_y_s_i_c_a_l_ _S_p_e_c_i_f_i_c_a_t_i_o_n_s_ 2.4
Mounting: MBA 201: 1 slot in RC3502 crate
MBA 601 or
MBA 603: 1 slot in Multibus crate.
\f
F_ 3_._ _ _ _ _ _ _ _ _I_D_E_N_T_I_F_I_C_A_T_I_O_N_ _O_F_ _I_T_E_M_S_ 3.
The following items make out an RC3502 Multibus interconnection.
I_t_e_m_ R_e_f_e_r_e_n_c_e_ _N_o_ D_e_s_c_r_i_p_t_i_o_n_
1 MBA 201 Multibusadaptor in RC3502
2 MBA 601 or - - Multibus
MBA 603 - - -
without dual port memory.
3 CBL 950 or Interconnection cable 2 m
CBL 951 or - - 5 m
CBL 958 - - 12 m
\f
F_ 4_._ _ _ _ _ _ _ _ _I_N_S_T_A_L_L_A_T_I_O_N_ 4.
The following information serves as an aid for installation of an
RC3502 to Multibus connection.
4_._1_ _ _ _ _ _ _ _I_n_s_t_a_l_l_a_t_i_o_n_ _o_f_ _M_B_A_ _2_0_1_ 4.1
a: Choose which memory modul number to be the threshold for
memory access on the Multibus, and set the switches
correspondingly, see subsection 4.4.1.
b: Select the first of the eight interrupt levels (deviceno's),
and set the switches correspondingly.
c: Insert the MBA 201 into the RC3502 crate in a slot to the
right of all controllers with higher level numbers than the
numbers selected for the MBA 201 and to the left of all
controllers having lower level numbers. In other words RC3502
controllers must be installed in the order of decreasing
interrupt level numbers from left to right, as seen from the
front of the crate.
4_._2_ _ _ _ _ _ _ _I_n_s_t_a_l_l_a_t_i_o_n_ _o_f_ _M_B_A_ _6_0_1_/_6_0_3_ 4.2
For both boards the following considerations must be made:
1. Is the Multibus a 4-slot crate or a 16-slot crate?
In the first case, stap st4 must be installed, and no free
slots must exist over the MBA 601/603.
In the second case, the crate has parallel arbitration, so you
need not fill up the slots from left to right, but the
leftmost masters get highest priority.
\f
2. Is the MBA the first or the only master on the Bus?
In that case the straps st2 and st3 must be installed,
otherwise they must be removed.
3. Strap st1 need never to be installed.
4_._2_._1_ _ _ _ _ _I_n_s_t_a_l_l_a_t_i_o_n_ _o_f_ _M_B_A_ _6_0_1_ 4.2.1
a. Make the considerations and do the strapping as described
above.
b. Select the location of the dual port memory in the Multibus
address space, and set the switches accordingly. See subsec-
tion 4.4.2.
c. Select on which of the eight interrupt levels, the dual port
write interrupt is to be received, and strap accordingly. See
subsection 4.4.2.
d. Insert the board in the slot, and connect the MBA cable.
4_._2_._2_ _ _ _ _ _I_n_s_t_a_l_l_a_t_i_o_n_ _o_f_ _M_B_A_ _6_0_3_ 4.2.2
a. Make the considerations and do the strapping as described
above.
b. Select the first of the eight I/O addresses, on which the
outgoing interrupts are to be cleared, and set the switches
accordingly (see subsection 4.4.3).
c. Insert the board in the slot and connect the MBA cable.
\f
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _S_I_L_5_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
_ _ _S_1_ _ _ _ _ _S_2_ _ _ _ _ _ _S_3_ _ _ _ _S_4_ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
8 4 2 1 8 4 2 1
Device No Memory moduls
Physical arrangement of the switches on the MBA 201 board.
Switch settings Device No Memory area
8421
0000 0-7 00000-FFFFF
0001 8-F 10000-FFFFF
0010 10-17 20000-FFFFF
0011 18-1F 30000-FFFFF
0100 20-24 40000-FFFFF
0101 28-2F 50000-FFFFF
0110 30-37 60000-FFFFF
0111 38-3F 70000-FFFFF
1000 40-47 80000-FFFFF
1001 48-4A 90000-FFFFF
1010 50-57 A0000-FFFFF
1011 58-5F B0000-FFFFF
1100 60-67 C0000-FFFFF
1101 68-6F D0000-FFFFF
1110 70-77 E0000-FFFFF
1111 78-7F F0000-FFFFF
Selection of devicenumbers and memory area threshold.
\f
4_._3_ _ _ _ _ _ _ _S_t_r_a_p_s_ _a_n_d_ _S_w_i_t_c_h_e_s_ 4.3
These subsections describe the setting of switches and straps on
the MBA boards.
4_._3_._1_ _ _ _ _ _S_t_r_a_p_s_ _o_n_ _M_B_A_ _2_0_1_
\f
4_._3_._2_ _ _ _ _ _S_t_r_a_p_s_ _a_n_d_ _S_w_i_t_c_h_e_s_ _o_n_ _M_B_A_ _6_0_3_ 4.3.2
ST1: If ST1 is installed, MBA 603 will release the Multibus
immediately after each access, when not in locked state.
Otherwise the mastership is kept until Common Busrequest is
received from another Multibus controller.
ST2: If ST2 is installed, this MBA 603 is the generator of Common
Clock. *)
ST3: If ST3 is installed, this MBA 603 is the generator of Bus
Clock. *)
ST4: If ST4 is installed, serial buspriority out is generated.
This is used in connection with four-slots Multibusses.
*) N.B. One and only one controller in each Multibus must
generate CCLK and BCLK.
\f
The switches are used to select the I/O addresses for reset of
outgoing interrupts.
The three least significant addressbits (Adr. 0 to 2) select
which interrupt is to be cleared.
The remaining are compared with the switch settings to determine
selection.
The switches should thus be set corresponding to the choosen I/O
addresses.
A one is indicated with a red dot.
The address high enable swich should be set to zero in systems
supporting only eight I/O address bits.
\f
4_._3_._3_ _ _ _ _ _S_t_r_a_p_s_ _a_n_d_ _S_w_i_t_c_h_e_s_ _o_n_ _M_B_A_ _6_0_1_ 4.3.3
ST1: If ST1 is installed, MBA 601 will release the Multibus
immediately after each access, when not in locked state.
Otherwise the mastership is kept until Common Busrequest is
received from another Multibus controller.
ST2: If ST2 is installed, this MBA 601 is the generator of Common
Clock. *)
ST3: If ST3 is installed, this MBA 601 is the generator of Bus
Clock. *)
ST4: If ST4 is installed, serial buspriority out is generated.
This is used in connection with four-slots Multibusses.
*) N.B. One and only one controller in each Multibus must
generate CCLK and BCLK.
\f
A B
ST10 . . . Example: Interrupt level 5
ST11 . . . carries the dual port
ST12 . . . write interrupt.
ST13 . . .
ST14 . . .
ST15 . . .
ST16 . . .
ST17 . . .
The straps ST10 to ST17 are used to select the interrupt level to
transfer the dual port write interrupt. The selected level cannot
transfer the state of the corresponding Multibus interrupt line.
All straps are mounted in the B position except the one corres-
ponding to the selected interrupt level. This strap is mounted in
the A position.
The switches S1-S3 determine in increments of 32K, where in the
Multibus memory address space the on board dual port memory is
located.
The "Dual port disable" switch inhibits any addressing of the
dual port memory if set to one.
\f
F_
\f
i
T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
1. DESCRIPTION ............................................ 1
2. BLOCK DIAGRAM .......................................... 2
3. TIMING DIAGRAMS ........................................ 3
4. LOGIC DIAGRAMS AND FUNCTIONAL DESCRIPTION .............. 6
5. MICROPROGRAM ........................................... 42
5.1 Functional Description ............................ 42
5.2 Microprogram Format ............................... 44
5.3 Microprogram Assembler Listing .................... 46
5.4 Microprogram Flow Diagram ......................... 86
6. CONTROLLER FIRST CHECK OUT ............................. 87
6.1 Check Procedure ................................... 87
6.2 Repeat Command Loops .............................. 88
7. MPCC 2652 DATA SHEET ................................... 89
8. ASSEMBLY DRAWING ....................................... 107
9. PLUG LISTS ............................................. 108
10. PROM LISTINGS .......................................... 112
\f
ii
\f
F_ 1
1_._ _ _ _ _ _ _ _ _D_E_S_C_R_I_P_T_I_O_N_ 1.
The VDC 201/291 consists of the data paths shown in the block
diagram.
The controller communicates with the host cpu through eight words
in the controller register file, corresponding to the general
I/O-registers of two interrupt levels.
The register file is normally used by the controller micropro-
gram, but whenever the host cpu executes an I/O instruction to
the controller the data phase of the instruction will be extended
until the current microinstruction is finished. Then the register
file will be connected to the cpu-bus and the data phase is
finished by the controller issuing an XFERACK. The microprogram
then continues from where it was stopped and will at a later time
interrogate the word corresponding to "Write Control" to see if a
new command has arrived.
Blocks of data are transferred to/from cpu-memory by micropro-
grammed DMA. Bytes from the 2652 MPCC are packed into two-byte
words before a DMAREQuest is issued and the data is written to
memory.
Similarly data from memory is read one word at a time and
unpacked by microprogram.
The register file contains a buffer description and status infor-
mation for each of the eight possible terminals connected to the
line. What is left in the register file is used by the micropro-
gram as workspace.
The 2652 MPCC performs zero insertion/deletion and generates and
checks CRC words in each frame transmitted/received.
The modem uses an FM modulation in which a mid cell (each cell is
4 microsec. wide), transistion corresponds to a logic zero.
\f
F_ 6
SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
MSEL 0-7 CPU-BUS Module select
MSEL0 : 1 = memory
0 = I/O device
When memory is selected:
MSEL 1 = 1 , MSEL 2 = 0
and MSEL 7 indicates address
or data on the bus
0 = address, 1 = data
-,FORWREAD CPU-BUS Forward read to memory.
-,MODSEL 5 Module selected by CPU
during an I/O instruction.
LOGIC 1 P1 3 Logic one.
MOD 1-6 2 Module number selected by
switches.
MODE 0-1 15 Mode select lines, can be
sensed by microprogram.
LOGIC 1 P1 1,3 Logic one
VDC 1
\f
F_ 8
SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-,BUS 0-15 CPU-BUS Bidirectional data bus
-,BUS IN 0-7 11 Bus data in (left byte),
buffered, selected as source
for internal registers by
REGINSEL.
BUS IN 8-9 3,11 Bus data in (right byte)
buffered.
BUS IN 10 5,11 Bus data in (right byte)
buffered.
BUS IN 11-14 11 Bus data in (right byte)
buffered.
BUS IN 15 3,11 Bus data in (right byte)
buffered.
VDC 2
\f
F_ 10
SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
LEVEL 3 Level high (1) or low (0)
register selection.
HD 1-0 3 Header bit 0 and 1 selects
which register to access
-,HD 0 7 Write enable for CPU access
to registers.
REGA 0-5 12 Internal register file
address.
VDC 3
\f
p_p_ 12
m_m_ SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
16 MC 4,15 16 MHz master clock.
EXTACK 3,4,5,6,10 External acknowledge stops
microprogram and grants CPU
-,EXTACK 3,7,11 access to I/O registers.
LONG 4 Long microinstructioncycle
(with CPCOM pulse).
-,CP 4
CP 4,9,13,15 Microprogram clock.
-,CPDEST 4 Destination clock gate.
CPREGXF 5,7 Data strobe for CPU write to
I/O-register. Terminates
-,EXTEND.
CPCOM 16 375 nS data strobe for 2652
COMM. CONTROLLER.
STROBE 4 Strobes MP0 and MP1 when
data from microprogram has
setteled. Enables a
LONG-cycle.
8MC Clock for microprogram clock
-,8MC 4 sequences.
PROCEED 4 Enables 8MC clock except
when a bus cycle requires an
extended read or write.
CPD 6 Internal bus destination
-,CPD 7 clock pulse.
LOGIC 1 P4 4 Logic one.
VDC 4
\f
P_ 14
M_ SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-,REGISTER I/O 4 Module has been selected for
I/O-data transfer to/from
internal registers.
-,DEV HEAD 3 Device, header register
selected (write only)
-,INTR FF 5 Interrupt FF's selected for
set or clear.
-,EXTEND BUS, 4 Controller extends during
register I/O transfers.
-,WRBUF 3,7 Bus write to controller.
-,XACK BUS,4 Transfer acknowledge (rising
edge) terminates an extended
read or write.
-,RDBUF 7 Bus read from controller.
-,INTLO 5 Set low level interrupt.
-,INTHI 5 Set high level interrupt.
HILEVEL 15 High level int. status.
MOD 7 2 LSB of interrupting module
number.
LOLEVEL 15 Low level int. status.
INT REQ 5 Interrupt request from
controller.
-,INTPOUT BUS Interrupt priority chain
out.
-,GSEL 2 Group select enables module
number to the CPU data bus.
-,BUSIN 10 5 Selects clear or set
interrupt. (BUSIN 10=1 sets
interrupts).
-,RESET BUF 5,9,16 Master reset from CPU-bus.
Clears interrupts,
microprogram counter and
2652 MPCC.
-,IORS 0,1 BUF 5 I/O register select from
CPU-bus.
VDC 5
\f
p_p_p_ 16
m_m_m_ SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-,DMAOUT BUS DMA priority chain out
-,DMAREQ BUS DMA request (open collector)
BUSACK* 6,7,9 Busacknowledge, CPU-bus may
be used by controller.
-,BUSLP BUS Data bus parity lines
-,BUSRP BUS
-,WRITE BUS,5 Bus write.
-,READ BUS,5 Bus read.
-,BYTE EN BUS Enable byte transfer on Bus
right, to/from memory.
MSEL7 BUS,1 Module select LSB to BUS.
-,PROM ADD BUS Prom address enable. Prom is
never addressed by
controller.
-,REG FLAG 12 Register flag to internal
registers. Used for two
purposes:
1- Generates parity on data
from 2652 MPCC to data
buffer register
(EXTACK=0, MP17=0).
2- Handshake flag on
registers shared by
microprogram and CPU I/O
instructions. (registers
56 to 63 dec.). An
I/O-write to a register
(EXTACK=1, MP17=1) will
set the flag while a
microprogram write to a
register (EXTACK=0) will
either clear the flag
(MP17=1) or load the
parity of the A-bus
(MP17=0).
VDC 6 \f
p_ 18
m_ SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-,LDACC 14 Load ACC register pulse
-,LDADDR 3 Load register file
address register.
-,LDCONTROL 15 Load control register.
-,LDMSEL 1 Load Module select
register.
-,BUSWR 6 Write pulse to CPU-bus.
-,SET LO 5 Set low level interrupt
FF.
-,SETHI 5 Set high level interrupt
FF.
-,BUSREQ 6 Busrequest is active
while the controller
wants to use the CPU-bus.
-,ENMSELOUT 1,6 Enable modul select out
to CPU-bus while bus is
used by controller.
TESTXFERACK 4 Enables a memory data
transfer to be extended.
-,ENBUSOUT 2,6 Enable Data bus drivers
out to CPU-bus.
-,REGWRITEH 12 Load register file high
byte
-,REGWRITEL 12 Load register file low
byte.
VDC 7
\f
F_ 20
SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-,COND 9 Condition signal selected
by MP 19-22.
VDC 8
\f
F_ 22
SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
MA 0-8 10 Microprogram address
lines.
S0-1 9 Current microprogram
address source selection.
RXDA 8 Receiver data available
syncrhonized by CP, to
cond.sel.
RXSA 8 Receiver status available
synchronized by CP, to
cond. sel.
-,FE 9 File enable to 2911,
enables push or pop of
stack.
RMP18 9 MP18 clocked by CP,
selects push or pop of
stack.
BUSACK 7,8 Busacknowledge
synchronized by CP, to
cond. selector and bus
driver enable logic.
S0*-S1* 9 Next microprogram address
source selection.
-,FE* 9 File enable in next
microstep.
LOGIC1 P9 16,18 Logic one.
VDC 9
\f
p_p_p_ 24
m_m_m_ SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Microprogram signals, for
more detailed use of
these signals, see table
of microprogram format.
MP 0-1 4,9 Microinstr. type.
MP 2 14 Forces all ones to
B-input of adder instead
of ACC contents.
MP 3-6 14 ALU-function
(MP6 = carry in)
LOADREGH/MP7 7 Enables write to register
LOADREGL/MP8 7 file high and/or low
byte.
MP 9-11 7 Sumbus destination
select.
MP 12-14 13 ALU Source select.
MP 15 3 Register file addr.
select.
0 - Addr. register
1 - MP26 - MP31.
MP 16 9 Microinstr. type.
MP 17 6,9 Flag control or
true/false select.
MP 18 6,7,9 MSEL7 control or push/pop
select.
MP 19 8 Condition select.
MP 20-22 8, 16 Condition select or 2652
register no.
MP 23 9 Next address MSB (page
no.).
MP 24-25 9,13 Constant, Jump address or
Register file address
MP 26-31 3,9,13 dependent on microin-
struction type.
VDC 10
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SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-,REG DATA 8-15 12 Register file input data
inverted. Low byte.
-,REG DATA 0-7 12 Register file input data
inverted. High byte.
REGINSEL 2 Register file input
select:
0 - Internal Sumbus.
1 - CPU-databus.
VDC 11
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SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
RDAT 0-15 2,13 Register file data out.
FLAG H/LP 6,15 Flag from high byte to
status register and
Parity to BUS-left byte
during a bus write.
RP 6 Bus right parity bit
druing a bus write.
NOTE: Parity is not
defined during a memory
address write.
VDC 12
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SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ABUS 0-7 13,14,15,16 ALU A-input source bus,
and in/out bus for 2652.
-,REGLEN 13 Enable Registerfile low
to ABUS.
-,REGHEN 13 Enable Registerfile high
to ABUS.
-,CONSTEN 13 Enable constant from
MP24-31 to ABUS.
-,STATUSEN 15 Enable status register to
ABUS.
-,BUSOUT 7 Enable BUS out drivers
(register file to
CPU-bus) if BUSACK.
-,BUSIN 6,7,11 Enables a Bus read pulse,
testxack and selects
CPU-bus as source for
register file.
-,R/W COMM 16 Enables 2652 data to
ABUS.
VDC 13
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SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
SUM 0-1 1,11,14,15 ALU-function output to
MSEL register, Reg file
SUM 2-7 1,3,11,14,15 address register,
Register file input data,
accumulator and control
register.
CARRY OUT 8 ALU carry to condition
selector.
ACC 0-7 14 ALU B-input from
accumulator if MP2 = 0
else all ones.
ABUF 0-7 14,6,8 ABUS data buffered to ALU
A-inputs, Parity
generator and condition
selector.
VDC 14
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m_ SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ABUS 0-7 13,14,16 ALU A-input source bus.
RXENABLE 16 Receiver enable (RXE) to
2652.
TXENABLE 16,17 Transmitter enable (TXE)
to 2652, enables line
driver.
MM 16 Maintenance Mode to 2652.
START/STOP 15 Start stop signal for
signature analysis when
looping in microprogram
initialize (MODE SWITCH 0
set).
-,BYEN 6 Byte enable to CPU-bus.
Always one as the
controller reads or
writes one word at a
time.
BUSREQ 7 Busrequest. Active while
the controller wants to
use the CPU-bus.
4MHz 17 4 MHz clock to line
demodulator sequencer. 16
x baud-rate.
TXC2 17 500 KHz clock to
modulator.
TXCLOCK 16,17 250 KHz clock to 2652
transmitter and to
modulator.
VDC 15
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SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ABUS 0-7 13,14,15 ALU A-input source bus.
RXA 17 Receiver active controls
the BLOCK IN lamp, and
lights it while a frame
is being received.
RXDA* 9 Receiver data buffer
full.
RXSA* 9 Receiver status
available.
TXA 17 Transmitter active lights
the BLOCK OUT lamp during
a fram transmission.
TXBE* 15 Transmitter databuffer
empty.
TXU* 15 Transmitter underrun.
TXDATA 17 Transmitter serial data
out to modulator.
VDC 16
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SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
TXDC 17 Modulated transmitter
data to line driver.
LINE 0-1 FRONT-CONN. Bidirectional CIRCUIT
line may be terminated on
the controller by
connecting JJ1-7 to JJ1-8
in the cable plug.
RXDC 17 Modulated received data
to demodulator.
CKFAIL* 15 Clockfailure. Time
interval between two
clock edges too long.
Cleared by each new
transition of RXDC.
RXDATA 16 Demodulated received
data, valid only at the
rising edge of RXCLOCK.
RXCLOCK 16 Receiver clock extracted
from RXDC signal.
LOGIC1 P17 6,17 Logic one.
VDC 17
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SIGNAL DESTINATION DESCRIPTION
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ABUS 0-7 13,14,15,16 ALU A-input source bus.
LOGIC 1CC 16 Logic one to 2652. For
future use may be changed
to +12V by ST1.
-5V 17 -5V supply to line
receiver.
VDC 18
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5_._ _ _ _ _ _ _ _ _M_I_C_R_O_P_R_O_G_R_A_M_ 5.
5_._1_ _ _ _ _ _ _ _F_u_n_c_t_i_o_n_a_l_ _D_e_s_c_r_i_p_t_i_o_n_ 5.1
The microprogram sequences shown in the following block diagram
is non pipelined, having registers on the microprogram address
only.
Next microprogram address can be selected from one of three
sources:
- Microprogram counter in normal microinstruction, or when a jump
condition is not fulfilled.
- Microprogram stack in "Return" and "Stack" instructions
(JSTACK does not change the stack pointer). The stack allows
subroutine nesting to four levels.
- Jump register in "Jump" instructions. Jump to the address
specified in the constant field MP(24:31) and MP(23).
Note that conditional jumps can not cross the page boundary set
by MP(23).
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5_._2_ _ _ _ _ _ _ _M_i_c_r_o_p_r_o_g_r_a_m_ _F_o_r_m_a_t_ 5.2
The microinstruction layout is shown on the next page.
It specifies a setup of data paths and ALU-operation together
with information on how the next microprogram address should be
generated.
A set of microinstructions has been selected by the macrodefini-
tions as shown in the first part of the program listing.
A microinstruction may be composed of one or two source text
lines.
If two lines are used then the first line specifies bus-source,
ALU-operation and destination while the second line controls next
address generation.
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6_._ _ _ _ _ _ _ _ _C_O_N_T_R_O_L_L_E_R_ _F_I_R_S_T_ _C_H_E_C_K_ _O_U_T_ 6.
In case a controller should malfunction when used on an RC3502
CPU it is recommended to check it on an RC3503 CPU, which makes
it easier to trace hardware faults.
6_._1_ _ _ _ _ _ _ _C_h_e_c_k_ _P_r_o_c_e_d_u_r_e_ 6.1
- Set the device number switches to device number 8 and the
MO-switch to 1.
- Place the controller correctly in the CPU-chassis with respect
to other I/O-controller device numbers.
- Check that the debug bit map of I/O levels present, include
levels 8 and 9. Levels 0 to 7 and 24 to 31 are normally present
in a 3503 CPU (two IOM controllers).
- Check that negative going pulses appear at TP1 (START/STOP)
indicating that the microprogram loops in its initialize
routine. Pulses should be 1125 nS wide and repeat each 123
microseconds.
- Set switch MO back to 0.
The microprogram should now proceed to the schedule loop where
it will wait for a command from the CPU.
- Load the tape with the Repeat command loops. Fill in the
desired command (and parameters) in the proper memory
locations. Set Wo registers as follows:
L 00: 0104
L 08: 0200 (1 word command) or
0400 (4 word command)
L 09: 0300
(Stop CPU before changing Wo registers) CPU may then be single
stepped or run at full speed.
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