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T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
1. INTRODUCTION ........................................... 1
1.1 Notation for Character Values ..................... 1
2. COMMUNICATION FROM RC8000 CONSOLE ...................... 2
2.1 Program Start Up .................................. 2
2.2 Alarms ............................................ 3
2.3 Program Close Down ................................ 5
2.3.1 Breaking the SMM Process ................... 5
2.3.2 Removing the NPM Process ................... 6
3. COMMUNICATION WITH NETWORK TERMINAL .................... 7
3.1 Session Establishment ............................. 7
3.2 Inputs ............................................ 7
3.2.1 Interrupts ................................. 7
3.2.2 Text Block Primitives ...................... 8
3.2.3 Control Block Primitives ................... 9
3.2.4 Parameter Block Primitives ................. 9
3.2.5 Negitiation Phase Commands ................. 9
3.2.6 Input Conversion ........................... 9
3.3 Outputs ........................................... 10
3.3.1 Interrupts ................................. 10
3.3.2 Text Block Primitives ...................... 10
3.3.3 Control Block Primitives ................... 11
3.3.4 Parameter Block Primitives ................. 11
3.3.5 Negotiation Phase Commands ................. 11
3.3.6 Output Conversion .......................... 11
3.4 Normal Printouts .................................. 11
3.5 Errors ............................................ 12
3.6 Session Termination ............................... 13
3.6.1 Abort and Disconnect Causes ................ 14
4. PSEUDONET .............................................. 15
4.1 Npm _message Coroutine ............................. 16
4.2 Npm _answer Coroutine .............................. 16
4.3 Input Syntax ...................................... 17
4.3.1 Implementation Details ..................... 18
\f
ii
T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _(_c_o_n_t_i_n_u_e_d_)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_
A_P_P_E_N_D_I_C_E_S_:
A. REFERENCES ............................................. 21
B. SURVEY OF SMM PARAMETERS ............................... 23
\f
F_ 1_._ _ _ _ _ _ _ _ _I_N_T_R_O_D_U_C_T_I_O_N_ 1.
This paper describes - briefly - how to use the RC8000 Scroll
Mode Mapping Module (SMM) when it is applied to the CENTERNET
Scroll Mode Terminal Module (SMT).
The paper contains two main chapters. Chapter 2 is the operating
guide for the SMM on the RC8000, i.e. the procedures for start up
and close down are described together with the possible alarms
and printouts which may occur on the RC8000 console. Chapter 3 is
the user's guide for the network terminal using the Virtual
Terminal Protocol on the X.28 interface in order to access the
RC8000 as a host computer.
Chapter 4 describes a tool for debugging the SMM program in a
stand-alone fashion, i.e. without making access to the network.
This tool is called a pseudonet.
Appendix A lists the references to other manuals and appendix B
gives a survey of the possible parameters for the SMM program.
1_._1_ _ _ _ _ _ _ _N_o_t_a_t_i_o_n_ _f_o_r_ _C_h_a_r_a_c_t_e_r_ _V_a_l_u_e_s_ 1.1
Character values are given in the same way as in ref. 2. A
character value is defined by <column>/<row> referring to the
IA5 Basic Code Table.
I.e. 2/0 corresponds to the character value 2*16 + 0 = 32 (= SP)
and 6/13 = 6*16 + 13 = 109 (= m).
\f
F_ 2_._ _ _ _ _ _ _ _ _C_O_M_M_U_N_I_C_A_T_I_O_N_ _F_R_O_M_ _R_C_8_0_0_0_ _C_O_N_S_O_L_E_ 2.
The SMM module is started from an RC8000 console as a program in
an internal process (by means of the File Processor (FP)).
2_._1_ _ _ _ _ _ _ _P_r_o_g_r_a_m_ _S_t_a_r_t_ _U_p_ 2.1
Via the operating system 's' an internal process is created. The
processname is the identification of the application used during
session establishment, see section 3.1.
The size and the other resources reserved by the process must be
sufficient to run the SMM module (= program).
There are a number of parameters to the program which can be
stated when the program is activated by FP, e.g. number of ter-
minals and NPM processname. A survey of the possible parameters
is given in appendix B.
When the program is started, it prints the release identification
and a verification of the program parameters. See example 1.
Example 1: Activation of the SMM program from RC8000 main console.
\f
2_._2_ _ _ _ _ _ _ _A_l_a_r_m_s_ 2.2
Alarms are printouts on the RC8000 console when the execution of
SMM is stopped. They are all serious errors which cannot be re-
paired by SMM, e.g. program errors (index, field and the like)
and the network program is not accessible.
The alarms provided by the ALGOL8 running system are not listed,
but can be found in ref. 3, 4 and 5.
The alarms are given in alphabetic order.
appl mess <res> One of the application message corou-
tines cannot be started. <res> is the
result received from the ALGOL8 proce-
dure new _activity, cf. ref. 4.
break 6 Too many buffers used, cf. ref. 3.
fatal <no> A fatal error has been discovered and
<no> =
1 an output message to the network is
greater than the network buffer size
2 the application process, which has
sent a message to SMM, is not
available when SMM wants to access
its process description in order to
get its name
3 illegal action
4 illegal state
5 operation received from the delay
semaphore
7 pseudonet only: the message area
cannot be accessed
8 pseudonet only: the answer area can-
not be accessed
9 pseudonet only: the buffer area of a
message or an answer cannot be ac-
cessed.
\f
netinput <res> As 'appl mess' but concerning the net-
work input coroutine.
npm ans <res> As 'appl mess' but concerning the
pseudonet coroutine: npm answer.
npm mess <res> As 'appl mess' but concerning the
pseudonet coroutine: npm message.
npm res <res> Dummy answer received from the npm pro-
cess. <res> is the result from the moni-
tor function wait _answer (18), cf. ref.
6.
ps create <res>*1000 + <index>
If <res> is greater than zero then the
creation of the pseudo process corres-
ponding to <index> was unsuccessful.
<res> is the result received from the
monitor function create _pseudo _process
(80), cf. ref. 6.
If <res> is zero the creating of the
pseudo process corresponding to <index>
was reported correctly but the investi-
gation of the process description by
means of the monitor function
process _description (4) failed.
<index> less than or equal to the number
of terminals indicates pseudo processes
named 'smm01', 'smm02' and so on, while
<index> equal to 1 + number of terminals
indicates the pseudonet named 'npm' or
the name given as fp-parameter 'netname'
in the call of SMM.
start <res> As 'appl mess' but concerning the start
network input coroutine.
\f
terminal <res> As 'appl mess' but concerning one of the
terminals.
2_._3_ _ _ _ _ _ _ _P_r_o_g_r_a_m_ _C_l_o_s_e_ _D_o_w_n_ 2.3
The program may be closed down in two different ways, either by
breaking the SMM process or by removing the NPM process.
Before the program stops, it tries to close all the ports and to
remove the pseudo processes created for the terminals and the
pseudonet. These actions are provided by the trap routine. In
order to inform the operator about the state of the clearing, the
trap routine produces a printout at entry, when a close port
attempt has been performed, when a remove pseudo process has been
executed and finally at exit. At last the ALGOL8 printout 'end
<blocksread>' will appear.
2_._3_._1_ _ _ _ _ _B_r_e_a_k_i_n_g_ _t_h_e_ _S_M_M_ _P_r_o_c_e_s_s_ 2.3.1
This possibility is the ordinary way of closing the SMM program.
It is achieved by the s-command BREAK. See example 2.
Example 2: Normal Close down of SMM program by means of s-command
BREAK.
\f
2_._3_._2_ _ _ _ _ _R_e_m_o_v_i_n_g_ _t_h_e_ _N_P_M_ _P_r_o_c_e_s_s_ 2.3.2
This possibility may only be used in emergency cases because the
ports cannot be closed if the NPM process does not exist, when
the SMM program attempts to close them. See example 3.
Example 3: Emergency Close down of SMM program by removing the
NPM process.
\f
F_ 3_._ _ _ _ _ _ _ _ _C_O_M_M_U_N_I_C_A_T_I_O_N_ _W_I_T_H_ _N_E_T_W_O_R_K_ _T_E_R_M_I_N_A_L_ 3.
The communication between SMM and the network terminal is based
on the X.28 interface and the Virtual Terminal Protocol (VTP),
see ref. 2 and 1 respectively.
3_._1_ _ _ _ _ _ _ _S_e_s_s_i_o_n_ _E_s_t_a_b_l_i_s_h_m_e_n_t_ 3.1
Sessions can only be established on initiative of the terminal
operator, i.e. use the selection command.
Example: keying
.recau,.smm NL
will connect the terminal to the RC8000 located at RECAU provided
that the SMM module is in service under the pseudonym 'smm', i.e.
the process name.
3_._2_ _ _ _ _ _ _ _I_n_p_u_t_s_ 3.2
3_._2_._1_ _ _ _ _ _I_n_t_e_r_r_u_p_t_s_ 3.2.1
INT interrupts the current operation, if any. If an
input operation is interrupted, the application is
answered status = timer and no characters are for-
warded, and a clear mechanism is started. Other-
wise the text 'att' is sent to the terminal en-
abling the operator to write the processname. The
processname may be empty which means same name as
current process.
Note that the first interrupt on the terminal must
be an INT in order to define the processname.
INTD interrupts the current operation, if any. If an
input operation is interrupted, a clear mechanism
is started. The processname cannot be changed,
i.e. an INTD equals INT + EOM without any text
characters.
\f
XPARAM is ignored.
RESET interrupts the current operation, if any and a
clear mechanism similar to the one in SMT, see
ref. 1, is activated.
PLEASE acts as INT when the terminal is either idle or
receiving output from the application. In any
other state, the PLEASE primitive is ignored.
(PLEASE is not defined as an interrupt, but in
this case it is treated as a sort of an inter-
rupt).
EOM(2) in addition to terminate the input line as any
other EOM indicator, EOM(2) acts as an INT, but
the clear mechanism is not activated.
(EOM(2) is not defined as an interrupt, but in
this case it is treated more like an interrupt
than a text block primitive).
3_._2_._2_ _ _ _ _ _T_e_x_t_ _B_l_o_c_k_ _P_r_i_m_i_t_i_v_e_s_ 3.2.2
TEXT-SEG is accepted when the terminal has the turn, i.e.
when either a process name may be stated or when
the application wants input.
The characters from one or more TEXT-SEG are
stored in a buffer either until the buffer is full
or until an EOM is received.
EOM(2) see subsection 3.2.1: Interrupts.
All other text block primitives are illegal and will start a
clear mechanism.
\f
3_._2_._3_ _ _ _ _ _C_o_n_t_r_o_l_ _B_l_o_c_k_ _P_r_i_m_i_t_i_v_e_s_ 3.2.3
PLEASE see subsection 3.2.1: Interrupts.
CLEAR-MARK the primitive is used in the clear mechanism.
ASSIGN illegal, i.e. a clear mechanism is started.
3_._2_._4_ _ _ _ _ _P_a_r_a_m_e_t_e_r_ _B_l_o_c_k_ _P_r_i_m_i_t_i_v_e_s_
All parameter block primitives are illegal and will cause the
start of a clear mechanism.
3_._2_._5_ _ _ _ _ _N_e_g_o_t_i_a_t_i_o_n_ _P_h_a_s_e_ _C_o_m_m_a_n_d_s_ 3.2.5
CONN a connect block is accepted if the parameter TER-
MINAL-MODE is selected as scroll mode. If more
parameters are given, they must allow the default
values, cf. ref. 1.
No other negotiation phase commands are valid, i.e. they will
abort the session.
3_._2_._6_ _ _ _ _ _I_n_p_u_t_ _C_o_n_v_e_r_s_i_o_n_ 3.2.6
Capital letters are converted to small letters in order to serve
terminals where small letters cannot be input.
The conversion condition is set to true when
- the terminal is connected
- the text att has been written on the terminal (after INT
and PLEASE, if not ighnored)
- an INTD or EOM(2) is accepted
\f
The conversion condition is set to false when
- a small letter is received.
When the conversion condition is true, the capital letters A
through Z and the 3 national letters (e.g. Æ, Ø, Å) (i.e. 4/1
through 5/13) are converted to the small letters (i.e. 6/1
through 7/13).
The characters (5/14) and (7/14) are converted to NUL (0/0)
no matter what the conversion condition is.
When data are forwarded to the application, they are finished by
an NL character (0/10).
3_._3_ _ _ _ _ _ _ _O_u_t_p_u_t_s_ 3.3
3_._3_._1_ _ _ _ _ _I_n_t_e_r_r_u_p_t_s_ 3.3.1
The only interrupt sent by SMM to the terminal is RESET.
RESET is sent whenever the program discovers an illegal
situation during normal VTP communication, as long
as this situation can be repaired, otherwise the
session is aborted.
3_._3_._2_ _ _ _ _ _T_e_x_t_ _B_l_o_c_k_ _P_r_i_m_i_t_i_v_e_s_ 3.3.2
TEXT-SEG is sent during output from an application or when
SMM wants to inform the operator about a change in
current state, e.g. shift in communicating process
(to <proc>, from <proc>), before receiving a new
process name (att) and in an error situation.
NL is sent after an EOM is received from the terminal
in order to simulate an ordinary RC8000 communica-
tion and to indicate that the input has been re-
ceived.
\f
3_._3_._3_ _ _ _ _ _C_o_n_t_o_l_ _B_l_o_c_k_ _P_r_i_m_i_t_i_v_e_s_ 3.3.3
The only control block primitive used is CLEAR-MARK. The primi-
tive is sent in a clear situation only.
3_._3_._4_ _ _ _ _ _P_a_r_a_m_e_t_e_r_ _B_l_o_c_k_ _P_r_i_m_i_t_i_v_e_s_ 3.3.4
No parameter blocks are sent from SMM.
3_._3_._5_ _ _ _ _ _N_e_g_o_t_i_a_t_i_o_n_ _P_h_a_s_e_ _C_o_m_m_a_n_d_s_ 3.3.5
The only negotiation command used by SMM is CACC. The parameters
received in the CONN command are answered in the CACC by means of
the default values given in ref. 1 except the TERMINAL-MODE as
this one must be scroll mode.
3_._3_._6_ _ _ _ _ _O_u_t_p_u_t_ _C_o_n_v_e_r_s_i_o_n_ 3.3.6
The data from the application are sent to the terminal in text
blocks without EOM (i.e. EOM(0)).
The NL character (0/10) is sent as an NL primitive whereas the
characters SP through å, except (i.e. 2/0 through 7/13 except
5/14) are sent - without conversion - as TEXT-SEG primitives. All
other characters are ignored. One TEXT-SEG primitive holds at
most 60 characters.
3_._4_ _ _ _ _ _ _ _N_o_r_m_a_l_ _P_r_i_n_t_o_u_t_s_ 3.4
During normal communication a number of printouts are produced by
SMM, i.e.
NLatt indicates that a (new) process name may be written
on the terminal.
\f
NL receipt on an input operation implying that the
characters have been forwarded to the application
or a process name has been received.
NLto <process>NL
indicates that <process> is able to receive data.
The text is sent only if the former process was
different to <process>.
NLfrom <process>NL
is written if the succeeding data is sent by an
other process than latest active application.
EOM(2) indicates that the application is able to receive
input; the turn is changed in order to enable the
operator to enter data and the bell is activated.
3_._5_ _ _ _ _ _ _ _E_r_r_o_r_s_ 3.5
Errors are printouts indicating an illegal situation, which is
not serious, e.g. misspelling a process name.
The errors are listed in alphabetic order.
disconnectedNL Dummy answer (4) on an attention message
to the application.
does not existNL Dummy answer (5) on an attention message
to the application.
illegalNL The process name is not the name of an
internal process.
NLlast inputline skippedNL
The last input line has not been for-
warded to the application because it was
longer than wanted by the application or
similar errors.
\f
no answerNL The application did not answer the at-
tention message within a certain (op-
tional) time limit. The attention mes-
sage has been regretted by SMM.
rejectedNL Dummy answer (2) on an attention message
to the application.
unintelligibleNL Dummy answer (3) on an attention message
to the application.
unknownNL The process does not exist. The name is
either the one just typed or current
process name if the name was omitted.
unnormalNL Dummy answer (1); usually that answer
means normal answer but if this error
occurs it denotes an unnormal situation
in SMM (close to an alarm case).
3_._6_ _ _ _ _ _ _ _S_e_s_s_i_o_n_ _T_e_r_m_i_n_a_t_i_o_n_ 3.6
When the operator wants to terminate a session, the CLR command
is entered, and a receipt is forwarded to the terminal either
informing about the accept from SMM or the reason for an abnormal
termination.
A session may be terminated by the SMM; when it happens, the
cause is described by a number in the receipt.
\f
3_._6_._1_ _ _ _ _ _A_b_o_r_t_ _a_n_d_ _D_i_s_c_o_n_n_e_c_t_ _C_a_u_s_e_s_ 3.6.1
The cases used when sending abort or disconnect messages are:
cause explanation
0 disc confirmation
164 clear procedure error
166 connect procedure error
170 unexpected VTP CONN
176 SC protocol error
244 parameters not acceptable.
\f
F_ 4_._ _ _ _ _ _ _ _ _P_S_E_U_D_O_N_E_T_ 4.
The pseudonet substitutes the network interface and therefore the
whole network too. It has been implemented in order to debug the
SMM module as a stand-alone program.
The pseudonet receives all the message destinated for Network
Port Module (NPM) and creates answers to them controlled by the
input commands read from current input.
The message/answer flow can be viewed as follows:
M_ _ _ _ _ _ _ _ _ _p_s_e_u_d_o_n_e_t_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _S_M_M_ _ _ _ _ _ _ _
NPM MESSAGE _ _ _o_u_t_p_u_t_ _m_e_s_s_a_g_e_ _ _
_ _ _ _ _ _ _a_n_s_w_e_r_ _ _ _ _ _ _
_ _ _c_l_o_s_e_ _m_e_s_s_a_g_e_ _ _
_ _ _ _ _ _ _a_n_s_w_e_r_ _ _ _ _ _ _
_ _ _o_p_e_n_ _m_e_s_s_a_g_e_ _ _ _ _
_ _i_n_p_u_t_ _m_e_s_s_a_g_e_ _ _ _ _
answer (not ok)
open letter telegram event message
pool pool pool pool pool
NPM
current ANSWER
input
create _ _ _ _ _ _ _a_n_s_w_e_r_ _ _ _ _ _ _
answer (open/input)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
P_
log of read
answers
\f
The pseudonet consists of two coroutines npn _message and
npn _answer.
4.1 Npm _message Coroutine M_M_m_m_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ P_P_p_p_
The coroutine npn _message receives all messages to the network
process (usually named 'npm'). Close messages are answered
immediately with status = 0, and the state of the port is set to
closed in the port survey (activ(port):= 0).
Output messages are answered immediately too, but the status
depends on the state of the port; status = 0 if the port is open
(activ(port) <> 0) and status = 1<20 (i.e. ack timeout) if the
port is closed.
If the port is closed, input messages are answered with status =
1<20 (i.e. ack timeout). On the other hand if the port is open,
the input message is queued on one of the semaphores letter _pool,
telegram _pool and event _pool depending on the sc _mode in the
message.
Open messages are - in any case - queued on the semaphore
open _pool.
4.2 Npm _answer Coroutine M_M_m_m_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ P_P_p_p_
The coroutine npm _answer reads commands from current input de-
scribing the tasks, i.e. wait a certain amount of seconds, anwer
a letter, a telegram or an event concerning a specific port or
open a specific port. If the task is wait, the coroutine delays
itself the specified amount of time. Otherwise it demands an
operation from one of the semaphore pools corresponding to the
operation and with the specified port address (if not an open
task). When the operation is received, the possible parameters
for the answer are read from current input, and the answer is
returned; if it was an open the state is changed in the port
survey (activ(port):= 1). Every parameter read from current input
is echoed on current output.
\f
As a matter of fact, the pseudonet is implemented as a part of
the SMM program. Nevertheless the communication is realistic
enough, because the entry to the pseudonet is implemented as a
pseudo process, i.e.
SMM
monitor
send message
wait answer
pseudonet
send answer
wait message
pseudonet entry
4_._3_ _ _ _ _ _ _ _I_n_p_u_t_ _S_y_n_t_a_x_ 4.3
Task Command Syntax Event results
open o<port address> *
telegram t<port address> <element>*
c connect request
d disconnect request
M_m_m_ a abnormal termination
event e<port address> <element>* NL EM
P_p_p_ l low layer error
p protocol error
i illegal
letter l<port address> <element>*
wait w<time>
where
<port address> is a number from 1 to number of ter-
minals
<element>* is a list of parameters to be used in
the answer. There could be none, one or\f
more parameters for one answer. Each
element results in one character in the
answer. An element is either an integer
with the character value or it is a
textstring. If it is a textstring, the
element starts with the number 256 and
one character ending the reading of the
number (e.g. one space); The textstring
itself is ended by a delimiter (class >
6, e.g. space).
<time> is a number determining the waiting time
given as number of seconds times ten.
NL is the character value 10.
EM is the character value 25.
4_._3_._1_ _ _ _ _ _I_m_p_l_e_m_e_n_t_a_t_i_o_n_ _D_e_t_a_i_l_s_ 4.3.1
The letters in front of the commands are read by read _char and
the succeeding integer is read by the standard procedure read,
leaving the possibility of writing letters, delimiters etc. be-
tween the leading letter and the integer.
The open and the wait command are skipping all characters until
the next NL or EM character. The event command skips all
characters after the port address until the first letter in the
range of a to z. This letter is interpreted as a result and all
illegal letters are treated as i.
The elements are read by the standard procedure read; when an
element equals 256, a text is read by means of read _string. The
list of elements are ended when the last read character is either
NL or EM. This implementation permits comments consisting of let-
ters, delimiters etc. between the elements.
Example 4 shows a legal sequence of commands for the pseudonet.
\f
Example 4: Commands for the pseudonet which form an ordinary
SMT-SMM communication.
\f
F_
\f
F_ A_._ _ _ _ _ _ _ _ _R_E_F_E_R_E_N_C_E_S_ A.
1 RCSL No 43-GL10486:
CENTERNET, Virtual Terminal Protocol (VTP).
Per Høgh, Inger Marie Toft Hansen, August 1980.
This document contains the specifications of the Virtual
Terminal Protocol for CENTERNET. The protocol covers the
three terminal classes, data entry, scroll and native. The
protocol definition is mainly based on the Data Entry Pro-
tocol for EURONET (VTP-D/Issue 4). Scroll and native mode
terminals and parameters selection during a session have
been added.
(62 printed pages).
2 RCSL No 43-GL10964:
CENTERNET, X.28-SMT Character Standards for Terminals.
Inger Marie Toft Hansen, January 1981.
This manual defines character standards for the asynchronous
terminals supported by the X.28-SMT Module.
3 RCSL No 42-i0781:
ALGOL7, User's Manual, Part 1.
Bodil Larsen, August 1979.
Description of the ALGOL7 programming language.
(148 printed pages).
4 RCSL No 31-D581:
ALGOL8.
Jørgen Zachariassen, November 1979.
Description of the ALGOL8 programming language, as exten-
sions to ALGOL7. ALGOL8 includes the activity concept, al-
lowing procedures to act as coroutines with current I/O
transfers, format 8000 procedures for IBM3270 compatible
transaction processing, new layout possibilities, character
constants and a few minor changes to ALGOL7.
\f
5 RCSL Nr. 31-D639:
ALGOL8, Coroutine System, Brugervejledning.
Jesper Tågholt.
(Not printed yet).
6 RCSL No 31-D477:
RC8000 Monitor, Part 2, Reference Manual.
Tove Ann Aris, Bo Tveden-Jørgensen, January 1978.
This manual describes monitor conventions, monitor
procedures and format of monitor tables.
(129 printed pages).
\f
F_ B_._ _ _ _ _ _ _ _ _S_U_R_V_E_Y_ _O_F_ _S_M_M_ _P_A_R_A_M_E_T_E_R_S_ B.
\f
F_
\f
TABLE OF CONTENTS
1 RC 3703 SPECIFICATIONSpage 7
1.1 Central processor unit 7
1.2 Memory 7
1.3 Input/output 7
1.4 Interrupt capability 8
1.5 Data channel 8
1.6 Power fail 8
1.7 Real time clock 9
1.8 Diagnostic front panel 9
1.9 Console interface 9
2 INTERNAL CONFIGURATION10
2.1 Introduction10
2.2 Program structure10
2.2.1 Program execution10
2.2.2 Program flow alternation11
2.2.3 Program size12
2.2.4 Program flow interruption12
2.3 Information format13
2.3.1 Fundamental concepts14
2.3.2 Bit numbering14
2.3.3 Binary representation15
2.3.4 Octal representation16
2.3.5 Hexadecimal notation17
2.4 Numerical quantities17
2.4.1 Integers17
2.4.2 Logical quantities19
2.5 Addressing20
2.5.1 Word addressing20
2.5.1.1 Page zero addressing21
2.5.1.2 Relative addressing21
2.5.1.3 Index register addressing21
2.5.1.4 Indirect addressing22
2.5.1.5 Auto locations22
2.5.2 Byte addressing23
3 INSTRUCTIONS24
3.1 Introduction24
3.2 Instruction formats24
3.3 Mnemonic description24
3.4 Program flow control25
3.4.1 Jump26
3.4.2 Jump to subroutine26\f
3.4.3 Increment and skip if zeropage27
3.4.4 Decrement andd skip if zero27
3.5 Data transfer operation27
3.5.1 Load accumulator28
3.5.2 Store accumulator29
3.6 Integer arithmetic and logical operations29
3.6.1 Add34
3.6.2 Subtract34
3.6.3 Negate35
3.6.4 Add complement35
3.6.5 Move36
3.6.6 Increment36
3.6.7 Complement37
3.6.8 And37
3.6.9 Examples37
3.6.9.1 Deciding the sign of a number38
3.6.9.2 Dividing a number by a power of two38
3.6.9.3 Changing locations simultaneously
inverting the order39
3.7 Byte manipulation40
3.7.1 Load byte40
3.7.2 Store byte40
4 INPUT/OUTPUT41
4.1 Introduction41
4.2 Operation of I/O devices41
4.3 Interrupt system42
4.4 Priority interrupts43
4.5 Direct memory access data channel45
4.6 I/O instructions46
4.6.1 Data in A47
4.6.2 Data in B48
4.6.3 Data in C48
4.6.4 Data out A48
4.6.5 Data out B49
4.6.6 Data out C49
4.6.7 I/O skip49
4.6.8 No I/O transfer50
4.7 Central processor functions50
4.7.1 Interrupt enable51
4.7.2 Interrupt disable52
4.7.3 Read switches52
4.7.4 Interrupt acknowledge52
4.7.5 Mask out53
4.7.6 I/O reset53
4.7.7 Halt54
4.7.8 CPU skip54\f
5 PROCESSOR FEATURES page 55
5.1 Introduction55
5.2 Power fail55
5.3 Real time clock55
5.4 Teletype controller57
5.4.1 Instructions57
5.4.1.1 Read character buffer58
5.4.1.2 Load character buffer58
5.4.2 Programming58
5.4.2.1 Input58
5.4.2.2 Output59
5.4.3 Programming examples59
5.4.3.1 Example 159
5.4.3.2 Example 259
5.4.3.3 Example 360
5.4.3.4 Example 460
6 PROGRAM LOAD63
6.1 Introduction63
6.2 Automatic loading63
7 SWITCHES AND INDICATORS69
7.1 Switches69
7.1.1 Autoload device select69
7.1.2 Baud rate select69
7.1.3 Stop bit select70
7.2 Indicators70
7.2.1 Right parity error70
7.2.2 Left parity error70
7.2.3 Fetch70
APPENDIX A72
APPENDIX B75
APPENDIX C80
APPENDIX D81
APPENDIX E88\f
1 RC 3703 SPECIFICATIONS
1.1 Central processor unit
The RC 3703 Central Processor Unit is a micro-programmed, general
purpose stored-program computer with four accumulators. The CPU
works on the basis of a unit of information called a word which
consists of 16 bits. Arithmetic and logical operations are per-
formed on operands held in the accumulators, which consequently
also are 16 bits in length. Two of the accumulators can be used as
index registers for addressing purposes.
T_ 1.2 Memory
The main memory is a dynamic semiconductor memory with a capaci-
ty of 32K words and a cycle time of 580 ns.
The CPU can directly address 32K words of core memory and provi-
des for base page, relative, indexed and multi-level indirect
addressing modes.
Word length in memory is 16 + 2 = 18 bits. The two extra bits
are parity check bits. They are generated during each memory
write cycle and are checked during each memory read cycle. The
detection of a parity error will not affect the operation of the
CPU. The error can be indicated on the front frame of the CPU
board while processing continues uninterrupted.
T_ 1.3 Input/Output
All peripheral devices are connected to the CPU through the Input/
Output bus. This consists of a six-line device selection network,
interrupt circuitry, command circuitry and sixteen data transmis-
sion lines. Each individual Input/Output device has a unique six-
bit device code and will only respond to commands if its own devi-
ce code is transmitted through the device selection network of the
Input/Output bus.
The six bits in the device code allows for 64 separate codes. A
number of these codes are reserved for specific uses, but the re-
maining codes makes it possible to obtain an extremely flexible
handling of Input/output devices.
\f
T_ 1.4 Interrupt Capability
The interrupt circuitry included in the Input/Output bus provi-
des the capability for any peripheral device to interrupt normal
&_ program execution whenever the device is in need of attention.
When a peripheral device has requested an interrupt the proces-
sor will transfer control of operations to the main interrupt
service routine, which will handle the servicing of the device.
The interrupt service routine will establish the source of the
interrupt either by polling all Input/Output devices connected
to the CPU or it can use a special instruction to identify the
device in question.
The interrupt system also provides the capability of implement-
ing up to sixteen levels of priority in connection with inter-
rupts, so that each individual peripheral device is associated
with a specific priority level. A standard priority assignment
is implemented by Regnecentralen, but the programmer can change
these assignments according to his own choice.
T_ 1.5 Data Channel
Data transfers between peripheral devices and main memory under
program control occupies processor time and retards the rate of
&_ information transfer.
To avoid this restriction the Input/Output bus contains cir-
cuitry allowing high-speed access direct to memory through the
data channel, this permits a peripheral device to transfer data
directly into/out of memory using a minimum of processor time.
At the maximum transfer rate the data channel effectively stops
the processor, but at lower rates processing continues while the
data transfer takes place.
T_ 1.6 Power Fail
The RC 3703 computer incorporates a feature providing for an-
interrupt in the event of an unexpected power loss. The delay
&_ between the initial decrease of voltage and the actual automatic
shut-down of the processor is utilized to bring the interrupt
service routine into action. This routine will underthese cir-
cumstances use the available interval of timne to terminate cur-
rent program execution and halt the CPU. The CPU will not restart
again when the power has been restored. \f
T_ 1.7 Real Time Clock
A Real Time Clock is included on the RC 3703 CPU-board. This
clock will generate a train of pulses independently of processor
timing, this will allow the interrupt system to be activated at
precisely spaced intervals of time. The pulse train frequency can
be selected by the programmer among the following possibilities:
10 Hz, 50 Hz, 100 Hz, 1 KHz, 5 KHz, 10 KHZ, 50 KHz and 100 KHz.
T_ 1.8 Diagnostic Front Panel
A Diagnostic Front Panel can be connected to the CPU by using a
&_ Debug Unit. This will allow external, manual control of the CPU
and will thus facilitate error detection and correction. The Dia-
gnostic Front Panel and the Debug Unit is not described in detail
in this manual, for further information concerning this consult
the Reference Manual for the Diagnostic Front Panel - RCSL 52-AA
542 and the Techincal Manual for the Debug Unit - RCSL 52-AA 780.
1.9 Console Interface
A teletype, controller is included on the RC 3703 CPU-board.
The teletype controller provides for two-way communication be-
tween the computer and the operator. The transmission speed (bits
per sec.) can be set by hardware to the following rates: 110,
300, 600, 1200, 2400, 4800, 9600 and 19200 bps.\f
2 INTERNAL CONFIGURATION
2.1 Introduction
This chapter and the following deals in some detail with the ba-
sic concepts underlying the actual modus operandi of the RC 3703
CPU. A more intimate knowledge of this subject is not strictly
necessary for ordinary everyday use of the computer, because the
high-level programming languages available are designed to allow
symbolic programs to be written without reference to the more spe-
cific information contained in this manual. Thus the intention is
not to establish guidelines for actual programming, for which
purpose separate manuals are available, but to provide a source
of background information for the programmer and/or operator.
T_ 2.2 Program Structure
Information about the type of operation - arithmetical or other
- which the computer at any particular time must perform, is gi-
&_ ven to the CPU in the shape of an "instruction". The CPU will
carry out successive instructions in strict sequence according to
the order in which the instructions have been specified. The com-
plete set of instructions is called a "program" and this must at
the time of execution reside in main memory in order to be
accessible to the CPU.
T_ 2.2.1 P_r_o_g_r_a_m_ _E_x_e_c_u_t_i_o_n_
Each individual instruction occupies a space in memory called a
"word" and although these words will usually occupy adjacent
&_ physical locations in memory, the program may incorporate instruc-
tions with the specific purpose of altering the sequence in which
the instructions should be carried out.
Thus the CPU must be able to locate the correct word at the cor-
rect point in the sequence in order to execute the program pro-
perly. The actual physical location of a word is called its
"address" and consequently the establishing of location is called
"addressing".
Addressing the instructions is arranged by incorporating a count-
ing circuit called the "program counter". The programcounter con-
tains one integer number, which always indicates the memory add-
ress of the instruction currently being carried out. When the o-
peration specified by the particular instruction has been com-\f
pleted, the number in the program counter is incremented by one
and the CPU will then retrieve the next instruction to be carried
out from the memory location now being indicated by the number in
the program counter. Succeeding addresses will thus form a strict-
ly ascending numerical sequence and this method of operation is
consequently called "sequential operation".
T_ 2.2.2 P_r_o_g_r_a_m_ _F_l_o_w_ _A_l_t_e_r_a_t_i_o_n_
The programmer can however purposely arrange to deviate from the
strict sequential operation. This is done by using the appropria-
&_ te program flow control instructions which will make it possible
to achieve two distinctly different types of program flow varia-
tion.
The "jump" type instruction will cause an arbitrary new number -
either larger or smaller than the current one - to be inserted
in the program counter. Thus when the jump instruction has been
executed, the next instruction to be located can have any of all
the possible addresses.
The "conditional skip" type instruction will first determine whe-
ther a specified test condition is true or not. If true, it will
then cause the program counter to be increased by one, if false,
nothing further will be done. When the conditional skip instruc-
tion has been executed, the program counter will be increased by
one as in the usual sequential operation and thus the next in-
struction to be located will have either of the two following
addresses depending on the outcome of the test. Normal sequential
operation will be resumed after the completion of either type of
instruction - using the updated value of the program counter -
and will continue until the next program flow alteration occurs.
An illustration showing the two types of program flow alteration
appears on the following page. Fig. 2.2.2. \f
T_ Fig. 2.2.2
SEQUENTIAL
PROGRAM
FLOW
INCREASING
ADDRESSES
I JUMP
N PROGRAM
S FLOW
T
R
U
C
T
I SKIP
O PROGRAM
N FLOW
S
T_ 2.2.3 P_r_o_g_r_a_m_ _S_i_z_e_
The integer number contained in the program counter will have a
magnitude between 0 and 32, 767 (both included) and will thus ma-
&_ ke it possible to address 32,768 separate memory locations which
is then the maximum program size. The program need not necessari-
ly start in memory location 0, but if the program counter reaches
the value 32,767 the next incrementation will produce the value 0
and sequential operation will then continue from here as previous-
ly explained. Notice should be taken of the fact, that no indica-
tion whatsoever of this particular situation will be given.
T_ 2.2.4 P_r_o_g_r_a_m_ _F_l_o_w_ _I_n_t_e_r_r_u_p_t_i_o_n_
During the normal running of a program a variety of situations
may arise which will make it necessary to interrupt the normal
&_ program flow, i.e. to stop ordinary processing temporarily. This
may be due to either quite normal occurrences - for instance the
necessity of performing an Input/Output operation - or it may be
due to exceptional occurences - external or internal faults or
malfunctions.
In both cases the address of the next sequential instruction is\f
saved by the CPU while the interrupt condition lasts. On termina-
tion of the interrupt condition the address saved by the CPU is
placed in the program counter anew and the interrupted program
resumes operation at the correct point in the sequence.
An illustration showing this variation in program flow appears
below. Fig. 2.2.4.
SEQUENTIAL
PROGRAM
FLOW
INCREASING I/O
ADDRESSES INTERRUPT
I OCCURS
N
S
T JUMP
R
U
C
T SKIP
I
O
N CONTINUED
S PROGRAMRETURN
FLOW
Fig. 2.2.4
&_
T_ 2.3 Information Formats
In any computer information is basically represented by some phy-
&_ sical quantity - usually electric current or magnetism. The ac-
tual nature of this quantity as well as its magnitude carries no
importance with respect to use of the computer; the important
property is that the relevant quantity can either be present or
not present.
\f
2.3.1 F_u_n_d_a_m_e_n_t_a_l_ _C_o_n_c_e_p_t_s_
The two possible - but mutually exclusive - states as mentioned
&_ above form the basis for all considerations of information pro-
cessing. The two states are normally indicated by the numerals 0
(zero) and 1 (one) and the nucleus of information thus represent-
ed is called a "binary digit" - usually shortened to "bit".
In the RC 3703 computer the standard unit of information is how-
ever the "word", which is a string of 16 individual bits. As each
bit can attain either of two different states, the string of 16
bits can represent 2UU16DD = 65,536 different pieces of information,
for instance the integer numbers from 0 up to 65,535. It should
here be noted, that although the wellknown mathematical symbolism
- i.e. numbers - is often used to describe the information con-
tent of a word (or a part of a word), this is in reality only a
matter of convenience and does not restrict the actual meaning of
the information to this particular subject; nor does it restrict
the use to which it may be put. Although the word is the standard
unit of information handled by the RC 3703 computer it can at
times be convenient to subdivide a word into two parts of 8 bits
each. Such a half-word is called a "byte" and is capable of
representing 2UU8DD = 256 different pieces of information.
T_
2.3.2 B_i_t_ _N_u_m_b_e_r_i_n_g_
When considering the information contained in bytes or words it
is convenient to establish a definite method of referencing the
&_ individual bits of the byte or word. This is done simply by or-
dinary numbering of the bits within the word or byte. The number-
ing always proceeds from left to right, i.e. the leftmost bit in
a word is bit 0 while the rightmost bit in a word is bit 15.
Similarly the leftmost bit in a byte is bit 0 while the rightmost
bit in a byte is bit 7. Notice that the numbering always starts
with bit 0.
The convention adopted here is illustrated in the figure below.
Fig. 2.3.2.
WORD WORD
BYTE BYTE BYTE BYTE
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Fig. 2.3.2
&_ \f
T_ It should also be noted that the adoption of this convention
means, that if for instance the word contains a number then the
highest-order digit will have the lowest bit number while the
lowest-order digit will have the highest bit number.
T_ 2.3.3 B_i_n_a_r_y_ _R_e_p_r_e_s_e_n_t_a_t_i_o_n_
If the conventional mathematical notation is adopted by using
&_ the numerical values 0 and 1 to indicate the two possible states
of the bit, then a word will be read simply as an ordinary 16-di-
git number - although the number will be written in somewhat un-
usual manner which in mathematics is called "binary notation".
From our everyday lives we are accustomed to use of numbers in
very many contexts; take for instance an arbitrary number like
315. The important feature of a number like this is that the ac-
tual value of the individual digit depends on its p_o_s_i_t_i_o_n_ in the
written number. In effect the way the number is written is just a
convenient short-hand way of indicating the magnitude:
3 x 100 + 1 x 10 + 5 x 1 = 3 x 10UU2DD + 1 x 10UU1DD + 5x 10UU0DD.
This is called "decimal notation" or "base 10" representation be-
cause successive digit positions in the number form a sequence of
increasing powers of 10.
To indicate that a number is written in base 10 representation a
subscript is used whenever there exists a possibility of confu-
sion:
315DD10UU.
It is obvious that decimal notation will require ten different
symbols to indicate the possible values of the individual di-
gits, namely the symbols: 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.
Binary notation - or base 2 representation - is in exactly the
same way a positional system, the only difference being that in
this case successive positions in the number form a sequence of
powers of 2. Whereas base 10 representation required ten diffe-
rent symbols for the individual digits base 2 representation will
only require two different symbols, namly 0 and 1; this is of
course the reason for its dominant position in all aspects of com-
puter technology.
A binary number can of course be used to indicate any magnitude
just as well as a decimal number; consequently a binary number\f
can always be converted to the equivalent decimal number and vice
versa. Thus:
100111011DD2UU =
1 x 2UU8DD + 0 x 2UU7DD + 0 x 2UU6DD + 1 x 2UU5DD + 1 x 2UU4DD + 1 x 2UU3DD +
0 x 2UU2DD + 1 x 2UU1DD + 1 x 2UU0DD =
1 x 256DD10UU + 0 x 128DD10UU + 0 x 64DD10UU + 1 x 32DD10UU + 1 x 16DD10UU +
1 x 8DD10UU + 0 x 4DD10UU + 1 x 2DD10UU + 1 x 1DD10UU =
256DD10UU + 32DD10UU + 16DD10UU + 8DD10UU + 2DD10UU+ 1DD10UU =
315DD10UU.
T_ 2.3.4 O_c_t_a_l_ _R_e_p_r_e_s_e_n_t_a_t_i_o_n_
Internally the CPU will only recognize information given in base
2 representation, but from the example given above it will be
clear that the simplicity of binary numbers, owing to the limit-
ed number of different symbols used, is counteracted by the ne-
cessity of using more digit positions to indicate any given mag-
nitude, i.e. binary numbers tend to become rather long and un-
wieldy.
Extensive application of binary notation in a manual like this
can therefore be somewhat awkward and might even lead to con-
fusion. It cannot be completely avoided, but very often numerical
representation to yet another base is used instead.
Noting that a three-digit binary number can represent numerical
values from 000DD2UU = 0DD10UU to 111DD2UU = 7DD10UU it is easily realised,
realised, that each group of three bits can be uniquely repre-
sented by the eight digits 0, 1, 2,....6 and 7. Therefore the use
of a representation to base 8 - so-called octal notation - will
retain the basic structure of the binary format, but it will on
the other hand only require one third of the positional places
needed in pure binary notation.
Expressing the example used on the preceding page in octal nota-
tion will yield:
315DD10UU = 100111011DD2UU = 473DD8UU.
\f
Thus by dividing any string of bits into groups of three and us-
ing octal notation a fairly compact and convenient representation
is achieved. The subdivision of the string always starts with the
rightmost group of three bits and proceeds towards the left. If
the number of places in the binary number is not divisible by
three the leftmost group will contain only one or two bits. This
is however of no particular consequence: conversion to octal no-
tation will take place as outlined above on the additional as-
sumption that the leftmost group is filled-up to three digits by
prefixing the necessary one or two zeroes.
T_ 2.3.5 H_e_x_a_d_e_c_i_m_a_l_ _N_o_t_a_t_i_o_n_
In some cases still another base is used to represent binary
information, namely base 16 - also called hexadecimal notation
&_ ("hex"). Just as in the case of octal notation the binary number
is formed into groups, but now each group will consist of four
bits. These four bits can express the numerical values from
0000DD2UU = 0DD10UU to 1111DD2UU = 15DD10UU, and in "hex" it will consequently
be necessary to use sixteen individually different symbols for
the digits. The numerals from 0 to 9 are of course still used to
represent their usual values, whereas the values from 10DD10UU to 15DD10UU will be
will be represented by the initial six letters of the alphabet:
A to F. The example previously used will then yield:
315DD10UU = 100111011DD2UU = 473DD8UU = 13BDD16UU.
T_ 2.4 N_u_m_e_r_i_c_a_l_ _Q_u_a_n_t_i_t_i_e_s_
The CPU does not intrinsically recognize one type of information
as being different from another, but it is quite obvious that in
&_ terms of application of the computer numerical quantities do ap-
pear in the majority of situations. Numerical quantities basi-
cally accepted by the CPU can be either integers or logical quan-
tities.
T_ 2.4.1 I_n_t_e_g_e_r_s_
Operations on integer quantities can be performed on signed or
unsigned binary numbers, which may be carried by the CPU in
either single or multiple precision. Single precision integers
are two bytes long (16 bits), while multiple precision integers
are four or more bytes long.
\f
Unsigned integers use all available bits to represent the magnitu-
de of the number; thus an unsigned, single precision integer can
range in value from 0DD10UU to 65,535DD10UU (2UU16DD - 1)corresponding to
the sixteen bits available. Similarly two words taken together as
an unsigned, double precision integer can range in value from
0DD10UU to 4,294,967,295DD10UU (2UU32DD - 1) corresponding to the thirtytwo
bits available. Signed integers use bits 1 to 15 to represent the
magnitude of the number while bit 0 is reserved for use a sign
bit. The aforesaid assumes single precision; if multiple preci-
sion is employed the first (leftmost) word will be structured in
this same way while the following word(s) will use all available
bits to represent numerical information.
For positive numbers the sign bit is 0 and the remaining bits re-
present the magnitude of the number in standard binary notation as
explained above.
For negative numbers the sign bit is 1 and the remaining bits re-
present the magnitude of the number in complemented binary nota-
tion (also called two>s complement form).
Complementing a number - whether in decimal, binary or any other
notation - simply means writing the negative number as the sum of
two numbers: a large negative number which is a power of the base
plus that positive number which will yield the original number
when added to the large negative one. For instance in decimal no-
tation:
- 315 = - 1,000,000,000 + 999,999,685.
The advantage of this form is that when working within a set num-
ber of digit positions, the large negative number will "vanish" -
leaving simply a row of zeroes.
To produce the complement - "mechanically" speaking - of a deci-
mal number just subtract the individual digit from 9 to give the
digit value of the complement - and then finally add 1 to the last
digit. In exactly the same way binary complements are produced by
subtracting the individual digit from 1 and then adding 1 to the
last (rightmost) digit.
In exactly the same way binary complements are produced by sub-
tracting the individual digit from 1 and then adding 1 to the
last (rightmost) digit. \f
Thus:
315DD10UU = 0 000 000 100 111 011
1 111 111 011 000 100 - complementation
+______________________1_
- 315DD10UU = 1 111 111 011 000 101
&_
Note that the complementation of a negative number will of cour-
se produce the positive of that number.
Complementing zero will produce a carry out of the leftmost bit
and leave the number again as zero:
0 000 000 000 000 000 - zero
1 111 111 111 111 111 - complementation
+_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _1_
0 000 000 000 000 000 - zero
Note that zero is a positive number!
As shown above complementation of zero will again produce zero
and there will thus always be one more negative number than the-
re are non-negative numbers within the given range of digit po-
sitions. The numerically largest negative number is a number with
the sign bit 1 and all remaining bits 0. The positive value of
this number cannot be represented in the same number of digit po-
sitions as used to represent the negative number.
Thus a single precision signed integer can lie in the range from
- 32,768 to + 32,767 while a double precision signed integer can
lie in the range from - 2,147,483,648 to + 2,147,483,647.
Note that addition and subtraction of signed numbers in two>s
complement form is identical to the same operations on unsigned
numbers; the CPU just treats the sign bit as the most signifi-
cant (highest-order) magnitude bit.
T_ 2.4.2 L_o_g_i_c_a_l_ _Q_u_a_n_t_i_t_i_e_s_
Operations on logical quantities can be performed on individual
bits, bytes or words. In all cases the quantities operated on
&_ are treated as simple un-structured binary quantities. The logi-
cal value "true" is represented by 1 while the logical value
"false" is represented by 0. Two logical quantities are identical
if and only if they have identical values in corresponding bit
positions. \f
The number of bits, bytes or words operated on will depend on
the instruction actually being used.
T_ 2.5 Addressing
It has already been mentioned in the section "Program Execution"
(section 2.2.1) that the CPU must be able to locate the instruc-
tions stored in main memory. Similarly the CPU must be able to
locate the data involved in the operation to be performed - the
address of which data will usually be indicated in the instruc-
tion.
T_ 2.5.1 W_o_r_d_ _A_d_d_r_e_s_s_i_n_g_
Main memory is subdivided into a number of words - the actual
magnitude of which depends on the CPU configuration actually be-
&_ ing employed. Every single word in memory has a definite address,
which is given as a number: the first word in memory has the add-
ress 0, the next word has the address 1, the next word has the
address 2 and so on. It will be recalled that the address of the
instruction currently in effect is held in the one-word program
counter during the execution of a program. The instruction itself
must contain information about the address of data to be used
during the execution of that particular instruction.
In contrast to the address held in the program counter the address
information contained in the instruction will not always directly
specify the necessary address but may form the basis for a calcu-
lation whose result will be the desired address. This calculation
is called "effective address calculation" and the result of this
is the "effective address".
The six instructions which directly reference memory in this way
use eleven bits of the word containing the instruction for effec-
tive address calculation. The format of these six instructions is
shown below:
T_
IN-
@ DEX DISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
The eleven bits concerned are bits 5 to 15; of these bit 5 is\f
called the indirect bit, bits 6 and 7 are called the index bits
and the remaining eight bits (bits 8 to 15) are called the dis-
placement bits.
There are four essentially different modes of effective address
calculation available:
T_ 2.5.1.1 P_a_g_e_ _Z_e_r_o_ _A_d_d_r_e_s_s_i_n_g_. Page zero addressing is indicated by the
index bits being 00. Then the displacement bits are taken as an
&_ ordinary unsigned integer number indicating directly the effec-
tive address. An 8-bit number will lie in the range from 0 to
255DD10UU; this first block of 256DD10UU words in memory, whichcan
be addressed directly in this way, is known as page zero.
T_ 2.5.1.2 R_e_l_a_t_i_v_e_ _A_d_d_r_e_s_s_i_n_g_. Relative addressing is signified by the in-
dex bits being 01. In this case the displacement bits are taken
as a signed, two>s complement integer number. This number is add-
&_ ed to the address - contained in the program counter - of the
instruction currently in effect; the result of the addition is
the effective address. By this means the effective address can be
any address in memory accessible to the program as it is defined
relative to the address of the instruction. A signed 8-bit number
will lie in the range from -128DD10UU to +127DD10UU andrelativeaddress-
ing therefore gives access to a block of 256DD10UU words distributed
evenly on either side of the instruction.
T_ 2.5.1.3 I_n_d_e_x_ _R_e_g_i_s_t_e_r_ _A_d_d_r_e_s_s_i_n_g_. Index register addressing is signifi-
ed by the index bits being either 10 or 11. If they are 10 then
&_ accumulator 2 is used as an index register; if they are 11 then
accumulator 3 is similarly used.
In both cases the displacement bits are taken as a signed, two>s
complement integer number; this number is added to the number
contained in the accumulator indicated by the choice of index
bits. The result of the addition is the effective address.
N_O_T_E_: The addition performed in relative and index register
addressing is clipped to 15 bits, i.e. the high-order
bit (bit 0) of the resulting address is set to 0. For
example: if the displacement bits are 01 001 111 and
(in relative addressing) the program counter stands at
111 111 110 101 011, then the addition should produce
the result: 1 000 000 000 011 010, but bit 0 will be
set to 0 so that the result reads:
0 000 000 000 011010. \f
When index register addressing is used the addition of the dis-
placement to the number contained in the accumulator does not
change the value contained in the accumulator.
T_ 2.5.1.4 I_n_d_i_r_e_c_t_ _A_d_d_r_e_s_s_i_n_g_. While discussing the three addressing modes
hitherto covered it has been tacitly assumed, that the indirect
&_ bit (bit 5) of the instruction was 0, since only then will the
result of the address calculation be the effective address.
If the indirect bit is 1 then the word addressed by either of
the three previously mentioned address calculations is expected
in itself to contain an address (level 1 indirection). The word
concerned will of course contain the usual 16 bits of which now
bit 0 will be the indirect bit and bits 1 to 15 will contain the
address proper.
If now the indirect bit in the level 1 indirection address is 0
then the address contained in bits 1 to 15 is assumed to be the
effective address, but if the indirect bit is 1 then the level 1
indirection address is again expected to contain a further add-
ress (level 2 indirection). This procedure will then be repeated
until an address is eventually retrieved where bit 0 is 0 and
bits 1 to 15 consequently will be taken to be the effective add-
ress.
It should be noted that there is no limit to the levels of indi-
rection accepted by the CPU. Neither is there any indication if
the chain of indirect addresses due to an error should form a
closed loop thus continuing indefinitely.
T_ 2.5.1.5 A_u_t_o_ _L_o_c_a_t_i_o_n_s_. Two areas of main memory are reserved for speci-
al addressing purposes.
&_ Locations in the range from 20DD8UU to 27DD8UU areauto-increment loca-
tions, which means that if an indirect addressing chain referen-
ces an address in this range then the word in that location will
be retrieved, the number contained in the word will be increment-
ed by one and this will then be written back into the location.
The updated value is then used to continue the chain of indirect
addresses.
\f
Locations in the range from 30DD8UU to 37DD8UU are auto-drecrement loca-
tions. Exactly the same procedure as outlined above applies here
except that the contents of the location will be decremented in-
stead of incremented.
N_O_T_E_: When auto-increment or auto-decrement locations are re-
ferenced in an indirection chain the state of bit 0
b_e_f_o_r_e_ the incrementation or decrementation will be
condition determining the continuation of the chain.
For example: if an auto-increment location containing
the number 177777DD8UU is referenced during an indirec-
tion chain then the next address in the chain will be
location 000000DD8UU - and it will be assumed thatthis
location in itself will contain an address due to the
fact, that the original word contained in the auto-in-
crement location (177777DD8UU) had a 1 bit in bit 0.
2.5.2 B_y_t_e_ _A_d_d_r_e_s_s_i_n_g_
Although the ordinary addressing routines will only allow
&_ addressing of complete 16-bit words in memory a convenient
programming method is available which will allow handling of
individual bytes.
This method involves the use of a "byte pointer" which is a word
containing in bits 0 to 14 address of normal two-byte word in
memory and where bit 15 is the "byte indicator". If the byte
indicator is 0 the referenced byte will be the leftmost byte
(containing bits 0 to 7) of the word whose address is given in
bits 0 to 14 of the byte pointer; if the byte indicator is 1 the
referenced byte will correspondingly be the rightmost byte
(containing bits 8 to 15).
Programming routines to handle individual bytes in this way are
listed in Appendix D of this manual.
For details about the LOAD BYTE and STORE BYTE instructions refer
to section 3.7 \f
3 I_N_S_T_R_U_C_T_I_O_N_S_
3.1 Introduction
The complete set of operation instructions available for RC 3703
CPU is divided into four subsets. These are instruction sets for
program flow control, data transfer operations, integer arithme-
tic and logical operations and a special subset for programming
the processor functions plus the features: Real Time Clock, Power
Fail/Monitor and Teletype interface.
T_ 3.2 Instruction Formats
All instructions in the set are one 16-bit word in length but
&_ the lay-out will differ depending on the type of operation to be
performed; more specifically this will bear on the number of
accumulators employed in the execution of the instruction. In
the following description of the different subsets a discussion
of the general format in each separate case will appear initial-
ly followed by a description of the individual instructions which
make up that particular subset.
T_ 3.3 Mnemonic Desricption
In the description of individual instructions the specific form
&_ of the instruction is given in the following generalized format:
MNEMONIC optional mnemonic' OPERAND STRING optional operands'
The main mnemonic is a group of letter symbols which must be us-
ed to initiate the operation concerned in the instruction. To
this may in some cases be appended the optional mnemonics, which
will cause a modification of the execution of the instruction.
The operand string consists of the actual operands necessary to
the execution of the instruction. To this may likewise be append-
ed optional operands.
The symbols ' and == are used as an aid in defining the
\f
specific form of each individual instruction:
' indicates optional mnemonics or operands
==== used as underlining to identify where definite substitu-
tion is required, i.e. where the actual identification
of accumulator, address, name, number or mnemonic must
be inserted in the instruction string.
The following abbreviations are used throughout this manual:
AC Accumulator
ACD Destination accumulator
ACS Source accumulator.
T_ 3.4 Program Flow Control
Program flow control operations are handled by way of the pro-
&_ gram counter - as outlined in section 2.2.1 - and thus do not
explicitly utilize any of the available accumulators. The in-
struction lay-out in this subset is as follows:
T_ OP In-
0 0 0 Code @ dex DISPLACEMENT
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In this format bits 0, 1 and 2 are 000, bits 3 and 4 contain the
operation code and bits 5 to 15 contain the memory address as de-
scribed in section 2.5.1.
The symbol @ - placed anywhere in the effective address operand
string - will set the indirect bit (bit 5) to 1.
The index bits (bit 6 and 7) are set by a comma followed by one
of the digits 0 to 3 as the last operand of the operand string.
If no index is coded, the index bits are automatically set to
00. The index bits can be set to 01 by using the character "pe-
riod" (.) at the beginning of the effective address operand
string. When the period is used, it is followed by either a plus
or a minus sign and the appropriate displacement, e.g. ".+7" or
".-2".
The subset contains the following four instructions: JUMP, JUMP
TO SUBROUTINE, INCREMENT AND SKIP IF ZERO and DECREMENT AND SKIP
IF ZERO.
\f
T_ 3.4.1 J_u_m_p_
JMP @' displacement ,index'
=================
In-
0 0 0 0 0 @ dex DISPLACEMENT
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The instruction will cause the effective address to be computed
and subsequently placed in the program counter. Sequential opera-
tion will then continue with the word addressed by this new value
of the program counter.
T_ 3.4.2 J_u_m_p_ _t_o_ _S_u_b_r_o_u_t_i_n_e_
JSR @' displacement ,index'
=================
In-
0 0 0 0 1 @ dexDISPLACEMENT
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The instruction will cause the effective address to be computed.
The current value of the program counter is incremented by one
and this number is placed in AC 3, whereupon the previously cal-
culated effective address is placed in the program counter and
sequential operation then continues with the word addressed by
this new value of the program counter.
N_O_T_E_: The computation of the effective address is completed
before the incremented value in the program counter is
written into AC 3. This means that if the effective
address calculation involves AC 3 as an index regi-
ster, the original value contained in this register
will be used in the calculation before it is overwrit-
ten with the incremented program counter.
As this instruction saves the incremented value of the program
counter in AC 3 the use of this instruction for subroutine calls
makes the return to the proper point in the main program extre-
mely simple necessitating only the instruction JMP 0,3.
\f
T_ 3.4.3 I_n_c_r_e_m_e_n_t_ _a_n_d_ _S_k_i_p_ _i_f_ _Z_e_r_o_
ISZ @' displacement ,index'
=================
In-
0 0 0 1 0 @ dex DISPLACEMENT
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will cause the effective address to be comput-
ed. The word in this location is incremented by one and the re-
sult is written back into the original location. If the result of
the incrementation is zero then the next sequential instruction
is skipped.
T_ 3.4.4 D_e_c_r_e_m_e_n_t_ _a_n_d_ _S_k_i_p_ _i_f_ _Z_e_r_o_
DSZ @' displacement,index'
=================
In-
0 0 0 1 1 @ dexDISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_ This instruction will cause the effective address to be comput-
ed. The word in this location is decremented by one and the re-
sult is written back into the location. If the result of the de-
crementation is zero then the next sequential instruction will be
skipped.
T_ 3.5 Data Transfer Operation
Data transfer operations always involve one of the available
&_ accumulators as terminal point for the operation (except when
the Direct Memory Access feature is utilized, see section 4.5).
There are however slight differences in the instruction format
depending on whether the data transfer is internal (between main
memory and accumulator) or external (between peripheral device
and accumulator). This section will only describe the instruc-
tions pertaining to internal data transfers, whileexternal\f
transfers will be dealt with in chapter 4: Input/Output.
Internal data transfer instructions use the following lay-out:
T_ OP In-
0 codeAC @dexDISPLACEMENT
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In this format bit 0 is 0, bits 1 and 2 contain the operation co-
de, bits 3 and 4 specify the accumulator to be used in the opera-
tion and bits 5 to 15 contain the memory address as outlined in
section 2.5.1.
The symbol @ - placed anywhere in the effective address operand
string - will set the indirect bit to 1.
The index bits (bits 6 and 7) are set by a comma followed by one
of the digits 0 to 3 as the last operand of the operand string.
If no index is coded, the index bits are automatically set to 00.
The index bits can be set to 01 by using the character "period"
(.) at the beginning of the effective address operand string.
When the period is used it is followed by either a plus or a mi-
nus sign and the appropriate displacement, e.g. ".+7" or ".-2".
The internal data transfer subset comprises the following two in-
structions: LOAD ACCUMULATOR and STORE ACCUMULATOR.
T_ 3.5.1 L_o_a_d_ _a_c_c_u_m_u_l_a_t_o_r_
LDA ac,@'displacement ,index'
== =================
In-
0 0 1 AC @ dexDISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_ This instruction will cause the effective address to be computed
and the word contained in this location will then be retrieved
and subsequently written into the accumulator specified. The pre-
vious contents of that accumulator will be lost; the contents of
the location addressed will remain unchanged. \f
3.5.2 S_t_o_r_e_ _a_c_c_u_m_u_l_a_t_o_r_
STA ac,@'displacement,index'
== =================
In-
0 1 0 AC @ dexDISPLACEMENT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_ This instruction will cause the effective address to be computed
and the word presently located in the accumulator specified will
be retrieved and subsequently written into the main memory loca-
tion indicated by the result of the effective address calcula-
tion. The previous contents of this location will be lost; the
contents of the accumulator will remain unchanged.
T_ 3.6 Integer Arithmetic and Logical Operations
Arithmetical and logical operations always use two of the avail-
&_ able accumulators - usually designated "source accumulator" and
"destination accumulator" - to hold the operands involved. In-
structions in this subset have the following lay-out:
T_
OP
1 ACS ACD Code SH C # SKIP
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In this format bit 0 is 1, bits 1 and 2 specify the source ac-
cumulator, bits 3 and 4 specify the destination accumulator, bits
5 to 7 contain the operation code, bits 8 and 9 specify the ac-
tion of the shifter, see figure 3.6, bits 10 and 11 specify the
initializing value of the carry, bit 12 indicates whether the
result of the operation must be loaded into the destination
accumulator or not and finally bits 13 to 15 specify the skip
test.
All operations initiated by instructions in this subset are
performed by way of an arithmetic unit whose logicalorganisation
is illustrated below: \f
T_ Fig. 3.6
ORGANIZATION OF ARITHMETIC UNIT
17 BITS
FUNCTIONSHIFTER
GENERATOR
17 BITS
1 BIT ACS ACD
16 16SKIP SENSOR
CARRY BITSBITS
Initializer
CARRY Accumulators
1 ACD17
BIT 16 BITS BITS
LOAD NO LOAD
&_
The instruction specifies two accumulators containing the two
operands which will have to be supplied to the function genera-
tor. This then performs the desired function as specified in bits
5 to 7 of the instruction. In addition to the actual function re-
sult the function generator will produce a carry bit, whose value
depends on three quantities: an initial value specified by the
instruction, the input operands themselves and the function ac-
tually performed.
The initial value of the carry bit may be derived from a pre-
vious value of same or a completely independent value may be spe-
cified via the instruction.
The 17-bit output from the function generator - made up of the
carry bit and the 16-bit function result - is then placed in the
shifter. Here the 17-bit result can be shifted one place either
to the right or to the left; alternatively the two 8-bit halves
of the function result can be swapped without affecting the car-
ry bit. The output from the shifter can then be tested for a
skip. The skip sensor will test whether the carry bit or the fun-
ction result itself is equal to zero or not.
After the skip test the output may be loaded into the carry bit
and the destination accumulator respectively. Note however that
loading is not an absolute necessity. \f
The diagrams below illustrate the possible actions taken by the
shifter:
T_
Optional Shifter
Mnemonic Operation
L All bits are moved one position to the left.
Hereby bit 0 is shifted into the carry position
while the carry bit is shifted into bit 15.
C 0-15
&_
T_ R All bits are moved one position to the right.
Hereby bit 15 is shifted into the carry position
while the carry bit is shifted into bit 0.
C 0-15
&_
T_ S The two halves of the 16-bit function result
change places bit by bit. The carry bit is not
affected by this operation.
C 0-7 8-15
C 0-7 8-15
&_
The following table lists the various options available for use
with the instruction format embodying the two-accumulator multip-
le operation. The characters in the column headed "Class Abbre-
viation" refer to the specific fields of the instruction format
as given at the beginning of this section. The characters in the
column headed "Optional Mnemonics" are those which mayoptionally
bve appended to the main mnemonic. The binary numbers in the column\f
headed "Bit Settings" show the actual bits which will appear in
the appropriate field of the instruction word. The comments in
the column headed "Operation" describe the resultant action of
the option in question.
F_\f
T_ _ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ _ _ __ __ ___
Class Optional Bit
A_b_b_r_e_v_i_a_t_i_o_n_ _ _ _M_n_e_m_o_n_i_c_ _ _ _S_e_t_t_i_n_g_s_ _ _ _ _ _ _ _ _ _O_p_e_r_a_t_i_o_n_ ____________
C 00 Do not initialize the carry
(Carry bit.
Preset) Z 01 Initialize the carry bit to
0.
O 10 Initialize the carry bit to
1.
C 11 Initialize the carry bit to
the complement of its
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _p_r_e_s_e_n_t_ _v_a_l_u_e_._ _ _ ___________
SH 00 Leave the result of the
(Shifter) arithmetic or logical
operation unaffected.
L 01 Combine the carry and the
16-bit result into a 17-bit
number and shift it one bit
to the left.
R 10 Combine the carry and the
16-bit result into a 17-bit
number and shift it one bit
to the right.
S 11 Exchange the two 8-bit
halves of the 16-bit result
without affecting the carry
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _b_i_t_._ _______________________
# 0 Load the result of the
(Load) shift operation into ACD.
# 1 Do not load the result of
the shift operation into
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _A_C_D_._ _______________________
SKIP 000 Never skip.
SKP 001 Always skip.
SZC 010 Skip if carry equal to
zero.
SNC 011 Skif if carry not equal to
zero.
SZR 100 Skip if result equal to
zero.
SNR 101 Skip if result not equal to
zero.
SEZ 110 Skip if either carry or
result equal to zero.
SBN 111 Skip if both carry and
&_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _r_e_s_u_l_t_ _n_o_t_ _e_q_u_a_l_ _t_o_ _z_e_r_o_._ \f
The instruction subset pertaining to integer arithmetic and logi-
cal operations include the following instructions: ADD, SUBTRACT,
NEGATE, ADD COMPLEMENT, INCREMENT and MOVE, all of which refer to
arithmetical operations, and the logical operations COMPLEMENT
and AND.
Integer arithmetic is performed in fixed point mode on 16-bit,
signed or unsigned operands in the accumulators. Logical opera-
tions are performed on 16-bit unstructured binary operands in the
accumulators.
T_ 3.6.1 A_d_d_
ADDc'sh'#'acs,acd,skip'
= == === === ====
1 ACS ACS 1 1 0 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the speci-
fied value. Then the number in ACS is added to the number in ACD
and the result is placed in the shifter. If the addition produces
a carry = 1 out of the high-order bit (bit 0) the carry bit will
be complemented, i.e. this will happen if the sum of the two num-
bers being added is greater than 65,535DD10UU. The specified shift
operation is then performed and the result of this is placed in
ACD provided that the load bit of the instruction has been set to
0. If the skip test demanded results in the condition being true
the next sequential instruction will be skipped.
T_ 3.6.2 S_u_b_t_r_a_c_t_
SUBc'sh'#'acs,acd,skip'
= == === === ====
1 ACS ACS 1 0 1 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the spe-
cified value. Then the number in ACS is subtracted from the num-
ber in ACD (the actual operation being performed by first forming
the two>s complement of the number in ACS and thenadding this to\f
the number in ACD) and the result of the subtraction placed in
the shifter. If the operation produces a carry = 1 out of the
high-order bit (bit 0) the carry bit will be complemented, i.e.
this will happen if the number in ACS is less than or equal to
the number in ACD. The specified shift operation is performed
and the result of this is placed in ACD provided that the load
bit of the instruction has been set to 0. If the skip test de-
manded results in the condition being true the next sequential
instruction will be skipped.
T_ 3.6.3 N_e_g_a_t_e_
NEGc'sh'#'acs,acd,skip'
= == === === ====
1 ACS ACD 0 0 1 SH C #SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the spe-
cified value. Then the two's complement of the number in ACS will
be formed and placed in the shifter. If the complementation pro-
duces a carry out of the high-order bit (bit 0) the carry bit
will be complemented, i.e. this happens if the number in ACS is
zero. The specified shift operation is performed and the result
of this is placed in ACD provided that the load bit of the in-
struction has been set to 0. If the skip test demanded results in
the condition being true the next sequential instruction will be
skipped.
T_ 3.6.4 A_d_d_ _c_o_m_p_l_e_m_e_n_t_
ADCc'sh'#'acs,acd,skip'
= == === === ====
1 ACS ACD 1 0 0 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the spe-
cified value. Then the logical complement of the number in ACS is
added to the number in ACD and the result is placed inthe shif-
ter. In addition produces a carry out of the high-order bit (bit
0) the carry bit will be complemented, i.e. this happens if the\f
number in ACS is less than the number in ACD. The specified shift
operation is performed and the result is placed in ACD provided
that the load bit of the instruction has been set to 0. If the
skip test demanded results in the condition being true the next
sequential instruction will be skipped.
T_ 3.6.5 M_o_v_e_
MOVc'sh'#'acs,acd,skip'
= == === === ====
1 ACS ACD 0 1 0 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the spe-
cified value. Then the number in ACS is placed in the shifter,
the specified shift operation is performed and the result of this
is placed in ACD provided that the load bit of the instruction
has been set to 0. If the skip test demanded results in the test
condition being true the next sequential instruction will be skip-
ped.
T_
T_ 3.6.6 I_n_c_r_e_m_e_n_t_
INCc'sh'#'acs,acd,skip'
= == === === ====
1 ACS ACD 0 1 1 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the spe-
cified value. Then the number in ACS is incremented by one and
the result is placed in the shifter. If the incrementation pro-
duces a carry out of the high-order bit (bit 0) the carry bit
will be complemented, i.e. this will happen if the number in ACS
is 177777DD8UU. The specified shift operation is performed and the
result of this placed in ACD provides that the load bit of the
instruction has been set to 0. If the skip test demanded results
in the test condition being true the next sequential instruction
will be skipped.
\f
3.6.7 C_o_m_p_l_e_m_e_n_t_
COMc'sh'#'acs,acd,skip'
= == === === ====
1 ACS ACD 0 0 0 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the speci-
fied value. The logical complement of the binary quantity in ACS
is formed and placed in the shifter. The specified shift operation
is performed and the result of this is placed in ACD provided
that the load bit of the instruction has been set to 0. If the
skip test demanded results in the test condition being true the
next sequential instruction will be skipped.
T_ 3.6.8 A_n_d_
ANDc'sh'#'acs,acd,skip'
= == === === ====
1 ACS ACD 1 1 1 SH C # SKIP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will first initialize the carry bit to the spe-
cified value. Then the logical "and" of the two binary quantities
in ACS and ACD is formed and placed in the shifter. Each bit pla-
ced in the shifter is 1 if and only if the two corresponding bits
in ACS and ACD respectively are both 1; in all other cases the
result bit placed in the shifter will be 0. The specified shift
operation is performed and the result of this is placed in ACD
provided that the load bit of the instruction has been set to 0.
If the skip test demanded results in the test condition being
true the next sequential instruction will be skipped.
T_ 3.6.9 E_x_a_m_p_l_e_s_
To show how these different instructions may be used under va-
&_ rious circumstances consider the following examples: \f
T_ 3.6.9.1 D_e_c_i_d_i_n_g_ _t_h_e_ _s_i_g_n_ _o_f_ _a_ _n_u_m_b_e_r_. To determine whether an integer
contained in an accumulator is positive or negative can be done
&_ in several ways, but the most efficient will be to use the MOVE
instruction and thus the inherent power of the two-accumulator
multiple-operation format.
Assume that the number in question is contained in AC 3. Use of
the instruction:
MOVL#3,3,SZC
will place the number in the shifter and shift the number one
place to the left. This will place the original sign bit in the
carry bit position and the skip test can then be used to deter-
mine whether this bit is 0 or 1. The two following instructions
in the program must of course be chosen in such a way that ap-
propriate action is taken in either case.
Note that by using the optional mnemonic # the load bit is set
to 1; thus the output from the shifter will not be loaded back
into AC 3 and the original number contained herein will there-
fore be retained for further use.
T_ 3.6.9.2 D_i_v_i_d_i_n_g_ _a_ _n_u_m_b_e_r_ _b_y_ _a_ _p_o_w_e_r_ _o_f_ _t_w_o_. To divide a binary number
by 2 is simply equivalent to shifting all digits one position to
the right (compare with decimal notation where division with 10
- i.e. the base - is readily acknowledged to be produced by
this expedient). The fact that the rightmost bit of the origi-
&_ nal number will be discarded after the shift means that the re-
sult of the division will be rounded down to the nearest inte-
ger.
The division can be performed simply and efficiently by employ-
ing the MOVE instruction as follows:
MOVL# 2,2,SZC
MOVOR 2,2,SKP
MOVZR 2,2,SKP
MOVOR 2,2,SKP
MOVOR 2,2
The number being divided is supposed to be placed in AC 2. The
first instruction is simply a repetition of the previous example
of deciding the sign of the number. If the number is positive
the second instruction will be skipped and operations will con-
tinue with the third instruction. This will shift the number one
place to the right thus resulting in the division by 2 whileat
the same time initializing the carry bit to 0 so that when this\f
bit is shifted into the sign bit position the number will re main-
positive. Note that after division the number is now loaded into
AC 2 so that this accumulator now holds the result of the divi-
sion. Finally the fourth instruction is skipped and the fifth re-
peats the division once more - following which there is no fur-
ther skip. The repetition means that the end effect will be that
the original number has been divided by four. If the number is
negative exactly the same sequence of operations are performed
with the appropriate alterations to cope with the negative sign -
the instructions now in force being the second and fourth.
T_ 3.6.9.3 C_h_a_n_g_i_n_g_ _l_o_c_a_t_i_o_n_s_ _s_i_m_u_l_t_a_n_e_o_u_s_l_y_ _i_n_v_e_r_t_i_n_g_ _t_h_e_ _o_r_d_e_r_. Assume
that a block of 30DD10UU words, which at present occupy locations
2000DD8UU to 2035DD8UU, must be moved to locations 5150DD8UU to5205DD8UU
&_ in such a way that the order of the individual words in the block
will be inverted.
To do this a section of a program is set up which will auto-incre-
ment through one set of locations, auto-decrement through the
other set and decrement a control count to determine when the
block transfer has been completed. The program section listed be-
low will accomplish this:
LDA 0,CNT ;comment: set up
STA 0,21 ; auto-increment location
LDA 0,CNT + 1 ; set up
STA 0,35 ; auto-decrement location
LOOP: LDA 0, @ 21 ; get a word
STA 0, @ 35 ; store it
DSZ CNT + 2 ; count down word count
JMP LOOP ; jumb back for next word,
skip to here when count
is zero
.
.
.
CNT: 001777 ; 1 before source block
+ 1: 005206 ; 1 after destinationblock
+ 2: 36 ; word count
\f
3.7 Byte Manipulation
In addition to performing operations on structured and unstruc-
tured 16-bit quantities, the instruction set of the RC 3703
allows loading and storing of 8-bit bytes.
3.7.1 L_o_a_d_ _B_y_t_e_
LDB
0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The 8-bit byte addressed by the byte pointer contained in AC1 is
placed in bits 8-15 of the AC0. Bits 0-7 of the AC0 are set to 0.
The contents of AC2 and AC3 remain unchanged.
The byte address in AC1 is a word address left shifted one and
with a one added in bit 15 if the byte addressed within the word
placed in bit 8:15.
3.7.2 S_t_o_r_e_ _B_y_t_e_.
STB
0 1 1 0 0 1 1 0 1 0 0 0 0 0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Bits 8-15 of AC0 are placed in the byte addressed by thepointer
contained in AC1. Bits 0-7 of AC0 are don>t care and not affec-
ted.
The contents of AC2 and AC3 remain unchanged. Note that the re-
maning part of the word addressed is untouched.
The byte address in AC1 is a word address left shifted one and
with a one added in bit 15 if the byte addressed with the word
placed in bit 8:15. \f
4 I_N_P_U_T_/_O_U_T_P_U_T_
4.1 Introduction
All useful information processing to be performed by the computer
depends on the existence of some means of communication between
the CPU and the outside world. For this purpose the CPU is connec-
ted to a number of peripheral or Input/Output devices the actual
type, size and number of which is completely independent of the
internal logical structure of CPU.
The program must of course contain instructions designed to hand-
le the external data transfer operations; these are all normally
termed Input/Output - usually shortened to I/O - operations and
allow for the transfer of information in units of bits, bytes,
words or groups of words called "records" depending on the device
in use.
All instructions in the I/O subset are basically similar to the
previously mentioned internal transfer instructions (section
3.5) except for the fact that addressing as such is not rele-
vant; on the other hand the CPU must have information as to which
peripheral unit is to be employed for the actual data transfer
and secondly there must be instituted some means of allocating
the necessary time for the transfer.
To handle the control of peripheral devices - of which there may
be several units of widely differing types connected to the CPU
at any given time - the RC 3703 CPU is equipped with a six-line
device selection network. To initiate operation on a specific de-
vice a signal must be transmitted on the selection network, but
each individual peripheral device will only respond to this sig-
nal if it is identical to the device's own device code. The de-
vice code is a six-bit integer number corresponding to the lines
in the selection network.
T_ 4.2 Operation of I/O Devices
In general all operations on individual I/O devices are handled
&_ by manipulation of two control bits which are called the "Busy"
and "Done" flags respectively. If the Busy and Done flags are
both 0 the device is idle and cannot perform any operation. To
initiate operation on a device the Busy flag must be set to 1, and\f
if the Done flag is not already 0 it must be set to this value.
When the device has finished its operation it will itself set
the Busy flag to 0 and the Done flag to 1. (If the Busy and Done
flags are both - erroneously - set to 1 the situation is meaning-
less and will produce unpredictable effects.)
Thus to initiate operation on a particular device the program
must first determine whether that device is currently performing
an operation or not, i.e. it must check the state of the Busy
and Done flags. If the Busy and Done flags are 0 and 1 respecti-
vely, the program will be able to start the operation by setting
Busy to 1 and Done to 0 as described above. When the operation
has been completed the device will reset the two flags and will
thus be available for another operation whenever necessary.
There are two ways in which the program can test the state of
the Busy and Done flags. One is to use the instruction I/O SKIP
(cf. section 4.6.7), the other is to employ the Interrupt Sys-
tem whichis standard on the RC 3703.
T_ 4.3 Interrupt System
The interrupt system consists of an interrupt request line to
&_ which each I/O device is connected, an Interrupt On flag in the
CPU and a 16-bit interrupt priority mask.
An interrupt is initiated by an I/O device at the time when it
completes its operation and resets the Busy and Done flags; si-
multaneously the device places an interrupt request on the in-
terrupt request line provided that the bit in the interrupt prio-
rity mask, which corresponds to the priority level on the device,
is 0 (cf. section 4.4). If that particular bit of the mask is
1, the device will still set the flags, but it will not place an
interrupt request on the line.
The Interrupt On flag controls the state of the interrupt system
in the sense that if the Interrupt On flag is set to 1 the CPU
will respond to the process interrupt requests; if the Interrupt
On flag is set to 0 it will not do so but will simply go on with
normal sequential execution of the program.
The CPU responds to an interrupt request by immediately setting
the Interrupt On flag to 0 so that no further interrupts can in-
terfere with the interrupt service routine. The CPU then places\f
the program counter in memory location 0 and executes a "jump in-
direct" to memory location 1 on the underlying assumption, that
this location contains the address - direct or indirect - of the
interrupt service routine.
When control has been transferred to the interrupt service rou-
tine this routine will first ensure, that the contents of accumu-
lators to be used by the routine are saved, so that these values
again can be made available when control is eventually returned
to the program proper. The same applies to the carry bit. When
this has been accomplished the routine will determine which de-
vice requested the interrupt; following this it will proceed with
the operations relevant to the servicing of the interrupt.
The determination of which device is in need of service can be
accomplished through either the I/O SKIP instruction or the
INTERRUPT ACKNOWLEDGE instruction. This last-mentioned instruc-
tion returns the six-bit device code of the device requesting the
interrupt, thereby initiating operation of that particular de-
vice. If more than one device has requested an interrupt, the
code returned will be that belonging to the device which is phy-
sically closest to the CPU on the I/O bus.
When the I/O device has completed its operation, the interrupt
service routine will restore all previously saved values, set
the Interrupt On flag to 1 and finally return control to the in-
terrupted program. For this purpose the instruction, that will
set the Interrupt On flag to 1, will allow the processor to exe-
cute one further instruction before the next interrupt can take
place. This extra instruction must be the instruction which re-
turns control to the main program; otherwise the interrupt ser-
vice routine may go into a loop. However, since the updated value
of the program counter - as related above - was placed in loca-
tion 0 upon responding to the interrupt request, the final in-
struction in the servicing routine can simply be the instruction
"JMP @ 0"; this will transfer control to the main program as in-
tended.
T_ 4.4 Priority Interrupts
If the Interrupt On flag remains 0 throughout the interrupt ser-
vice routine - as assumed above - all further interrupts will be
&_ ignored and there is thus only one level of device priority. This
level of priority - i.e. which devices will be able to secure an
interrupt - will be determined either by the order in which I/O
\f
SKIP instructions are issued or - if the INTERRUPT ACKNOWLEDGE in-
struction is used - by the relative physical locations on the I/O
bus of the various devices.
If the complete computer installation embodies I/O devices of wi-
dely differing speeds of operation - such as for example a tele-
typewriter versus a fixed head disc - it can be convenient for
the programmer to set up a multi-level interrupt schedule; this
is accomplished by the use of the priority mask coupled with the
appropriate instructions.
The priority mask is one 16-bit word to which the individual I/O
devices are connected in such a way, that each I/O device is as-
signed to one specific bit of the mask. The standard mask bit
assignment are arranged in such a manner, that devices having
roughly the same speed of operation will correspond to the same
bit in the mask and will therefore be on the same priority level.
(Appendix A of this manual contains - in addition to the device
codes - the standard RC mask bit assignments.) Although this
standard is relevant for most purposes it is not necessary to
comply with it, and the programmer is completely free to define
his own levels of priority for the individual devices by using
the MASK OUT instruction (cf. section 4.7.5). Whenever a bit in
the priority mask is set to 1 all devices in the priority level
corresponding to that particular bit will be prevented from re-
questing an interrupt. In addition all pending interrupt requests
from devices in that priority level will be ignored.
When multi-level priority handling is implemented, the interrupt
service routine must be written in such a way that it may itself
be interrupted without damage. This is done by arranging for the
main interrupt routine to save the state of the machine, - the
contents of the four accumulators, the carry bit and the return
address - whenever it takes over control.
The information concerned must be stored in separate locations
for each time the interrupt handler is entered, so that a higher
level of interrupt will not overlay the return information cor-
responding to a lower priority level. Having thus saved the ne-
cessary return information the main interrupt routine must de-
termine which device has requested service and then transfer
control to the correct interrupt handling routine. The actual
transfer is effected in the same way as for the previously de-
scribed single-level interrupt handler.
When the correct service routine has received control it will sa-
ve the current priority mask, establish the new priority mask\f
and activate the interrupt system. When it has finished servic-
ing the I/O device, the routine will de-activate the interrupt
system, reset the priority mask to its original form, restore the
state of the machine, again activate the interrupt system and fi-
nally return control to the interrupted program.
T_ 4.5 Direct Memory Access Data Channel
The handling of data transfers under program control as describ-
ed above requires an interrupt plus the execution of several in-
&_ structions for each word transferred and therefore occupies va-
luable time on the processor.
To avoid this and at the same time to obtain higher transfer ra-
tes the RC 3703 CPU is equipped with a separate data channel
through which an I/O device - at its own request - can gain di-
rect access to main memory.
When an I/O device is ready to send or to receive data it re-
quests access to memory via the data channel. All such requests
are synchronized by the CPU at the beginning of each memory cyc-
le. The CPU will then pause at specified points during the exe-
cution of an instruction; at each pause it will accept all pre-
viously synchronized requests in which instance a word will be
transferred directly via the channel from the device to memory or
vice versa without interference with the program.
All requests are honoured in relation to the relative physical
positions on the I/O bus of the different requesting devices;
that is: the device being physically closest to the CPU is ser-
viced first, then the next closest device and so on until all
requests have been processed. As synchronization of new requests
occur continuously even while previous requests are being attend-
ed to, a device can in effect saturate the channel if it requests
transfer continually. All devices further out on the bus cannot
gain access to the channel until the transfers involving the clo-
ser device have been processed, although of course devices which
are closer still on the bus will not be affected.
In addition to the pause intervals during the execution of an in-
struction data channel request will be handled on completion of
an instruction. At this point furthermore, all outstandingI/O\f
interrupt requests will be accepted. When all such data trans-
fers have been accomplished the CPU will continue with normal se-
quential operation.
T_ 4.6 I/O Instructions
All I/O instructions use the format given below:
0 1 1 AC OP Con-
CODE trol DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
In this format bits 0, 1 and 2 are 011, bits 3 and 4 specify the
accumulator involved, bits 5 to 7 contain the operation code,
bits 8 and 9 control the Busy and Done flags in the device and
bits 10 to 15 contain the device code. The six bits provided for
the device code will define 64DD10UU unique devices, but thetotal
number of separate devices which can be employed simultaneously
on any given installation will be slightly lower than this as
some of the available device codes are reserved for the CPU and
certain processor features. Of the remaining codes some have been
assigned to specific devices by Regnecentralen. A complete
listing of device codes appear in Appendix A.
The subset of I/O instructions has a number of options that can
be obtained by appending the appropriate optional mnemonic to
the standard mnemonic of the instruction. These optional mne-
monics are listed in the table on the following page; the column
headings correspond to those given in section 3.6.
\f
T_ _ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ _ _ __ __ ___
Class Optional Bit
A_b_b_r_e_v_i_a_t_i_o_n_ _ _ _M_n_e_m_o_n_i_c_ _ _ _S_e_t_t_i_n_g_s_ _ _ _ _ _ _ _ _ _O_p_e_r_a_t_i_o_n_ ____________
F 00 Does not affect the Busy
(Flags) and Done flags.
S 01 Start the device by set-
ting Busy = 1 and Done = 0.
C 10 Idle the device by setting
both Busy and Done to 0.
P 11 Pulse the special in-out
bus control line. Theeffect
- if any - dependson the
actual device.
________________________________________________________________
T BN 00 Tests for Busy = 1.
(Tests) BZ 01 Tests for Busy = 0.
DN 10 Tests for Done = 1.
DZ 11 Tests for Done = 0.
&_ ________________________________________________________________
The I/O instruction subset contains the following instructions:
DATA IN A, DATA IN B, DATA IN C, DATA OUT A, DATA OUT B, DATA
OUT C, I/O SKIP and NO I/O TRANSFER.
T_ 4.6.1 D_a_t_a_ _i_n_ _A_
DIAf' ac,device
= == ======
0 1 1 AC 0 0 1 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will place the contents of the A input buffer on
the specified device in the AC specified in the instruction. Af-
ter the data transfer has been completed the Busy and Done flags
are set as specified by "f".
The number of data bits moved depends on the size of the buffer
and the mode of operation of the device selected. Bits in the AC
not receiving any data are set to 0.
\f
4.6.2 D_a_t_a_ _i_n_ _B_
DIBf' ac,device
= == ======
0 1 1 AC 0 1 1 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will have exactly the same effect as the one pre-
viously described - except that it will utilize the B buffer of
the peripheral device.
T_ 4.6.3 D_a_t_a_ _i_n_ _C_
DICf' ac,device
= == ======
0 1 1 AC 1 0 1 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will have exactly the same effect as the two
previously described - except that it will utilize the C buffer
of the peripheral device.
T_ 4.6.4 D_a_t_a_ _o_u_t_ _A_
DOAf' ac,device
= == ======
0 1 1 AC 0 1 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will place the contents of the specified AC in
the A output buffer of the selected device. After the data trans-
fer has been completed, the Busy and Done flags are set as speci-
fied by "f". The contents of the AC will remain unaltered.
The number of data bits moved will depend on the size of the buf-
fer and on the mode of operation of the device. \f
T_ 4.6.5 D_a_t_a_ _o_u_t_ _B_
DOBf' ac,device
= == ======
0 1 1 AC 1 0 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will have exactly the same effect as the one pre-
viously described - except that it will utilize the B buffer of
the peripheral device.
T_ 4.6.6 D_a_t_a_ _o_u_t_ _C_
DOCf' ac,device
= == ======
0 1 1 AC 1 1 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will have exactly the same effect as the two pre-
viously described - except that it will utilize the C buffer of
the peripheral device.
T_ 4.6.7 I_/_O_ _S_k_i_p_
SKPt' device
= ======
0 1 1 0 0 1 1 1 T DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will test the state of the Busy and Done flags
and will thus enable the programmer to decide on actions to be
taken in consequence of the values of these flags, i.e. whether
a device is in need of service from the interrupt system or not.
The test performed depends on the value of bits 8 and 9 of the
instruction and is selected by appending the appropriateoptional
mnemonic to the instruction according to the table given in\f
section 4.6. If the test condition specified by "T" is true the
next sequential instruction will be skipped.
T_ 4.6.8 N_o_ _I_/_O_ _T_r_a_n_s_f_e_r_
NIO f' device
= ======
0 1 1 0 0 0 0 0 F DEVICE CODE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will set the Busy and Done flags in the selec-
ted device according to the control code specified by "F".
T_ 4.7 Central Processor Functions
I/O instructions with a device code of 77DD8UU will performanum-
&_ ber of special functions rather than control a specific periphe-
ral device. With the exception of the I/O SKIP instruction all
I/O instructions having a device code of 77DD8UU will usebits 8 and
9 of the instruction format to control the state of the Interrupt
On flag. The I/O SKIP instruction - when used with a device code
of 77DD8UU - will cause a test of the state of the InterruptOn flag.
(Alternatively it may be used to test the state of the Power Fail
flag; see section 5.2). The optional mnemonics for these special
instructions are the same as for normal I/O instructions. The
table below lists the resulting actions for these instructions
when used with the special device code 77DD8UU.
\f
T_ _ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ _ _ __ __ ___
Class Optional Bit
A_b_b_r_e_v_i_a_t_i_o_n_ _ _ _M_n_e_m_o_n_i_c_ _ _ _S_e_t_t_i_n_g_s_ _ _ _ _ _ _ _ _ _O_p_e_r_a_t_i_o_n_ ____________
F 00 Does not affect the state
(Flags) of the Interrupt On flag.
S 01 Set the Interrupt On flag
to 1.
C 10 Set the Interrupt On flag
to 0.
P 11 Does not affect the state
of the Interrupt On flag.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___________________________
T BN 00 Tests for Interrupt On = 1.
(Tests) BZ 01 Tests for Interrupt On = 0.
DN 10 Tests for Power Fail = 1.
DZ 11 Tests for Power Fail = 0.
&_ ________________________________________________________________
In addition to use of the ordinary I/O instructions with the spe-
cial device code 77DD8UU, there is a subset of special instructions
for processor functions which contains the following instruc-
tions: INTERRUPT ENABLE, INTERRUPT DISABLE, READ SWITCHES, INTER-
RUPT ACKNOWLEDGE, MASK OUT, I/O RESET, HALT and CPU SKIP.
T_ 4.7.1 I_n_t_e_r_r_u_p_t_ _e_n_a_b_l_e_
INTEN
NIOS CPU
0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will set the Interrupt On flag to 1. If
the state of the Interrupt On flag is hereby changed, the CPU
will allow one more instruction to be executed before the first
I/O interrupt can occur.
\f
T_ 4.7.2 I_n_t_e_r_r_u_p_t_ _d_i_s_a_b_l_e_
T_ INTDS
NIOC CPU
0 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1
&_ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This set of instructions will set the Interrupt On flag to 0.
&_
T_ 4.7.3 R_e_a_d_ _S_w_i_t_c_h_e_s_
READS ac
==
DIA f' ac,CPU
= ==
0 1 1 AC 0 0 1 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will place the current setting of the
data switches on the front frame of the CPU-board in the AC spe-
cified in the instructions. After the transfer has been complet-
ed, the Interrupt On flag is set according to the control code
specified by "F".
T_ 4.7.4 I_n_t_e_r_r_u_p_t_ _a_c_k_n_o_w_l_e_d_g_e_
INTA ac
==
DIB f' ac,CPU
= == ===
0 1 1 AC 0 1 1 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will cause the six-bit device code of
that device, which is physically closest to the CPU on the I/O
bus, to be placed in bits 10 to 15 of the AC specified in the\f
instructions. Bits 0 to 9 of the AC involved will be set to 0.
After the transfer has been completed the Interrupt On flag is
set according to the control code specified by "F".
T_ 4.7.5 M_a_s_k_ _o_u_t_
MSKO ac
==
DOB f' ac,CPU
= ==
0 1 1 AC 1 0 0 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will place the contents of the AC speci-
fied in the priority mask. After the transfer has been completed,
the Interrupt On flag is set according to the control code speci-
fied by "F". The contents of the AC remain unaltered.
N_O_T_E_: The digit 1 in any bit position disables interrupt re-
quests from any peripheral device in the corresponding
priority level.
T_ 4.7.6 I_/_O_ _R_e_s_e_t_
IORST
DIC f' ac,CPU
= == ===
0 1 1 AC 1 0 1 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will cause the Busy and Done flags in
all I/O devices to be set to 0; simultaneously all bits in the
16-bit priority mask are set to 0. The Interrupt On flag is set
according to the control code specified by "F".
\f
T_ 4.7.7 H_a_l_t_
HALT
DOC f' ac,CPU
= ==
0 1 1 AC 1 1 0 F 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This set of instructions will set the Interrupt On flag accord-
ing to the control code specified by "F". Following this the pro-
cessor is stopped.
T 4.7.8 C_P_U_ _S_k_i_p_
SKP t' CPU
= ===
0 1 1 0 0 1 1 1 T 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will cause the Interrupt On flag or the Power
Fail flag to be tested depending on the control code specified
by "T". If the test condition is true the next sequential in-
struction will be skipped.
F_\f
5 P_R_O_C_E_S_S_O_R_ _F_E_A_T_U_R_E_S_
5.1 Introduction
Features included in the RC 3703 computer are a power monitor
which will handle automatic shut-down in the event of a failure
of the power supply, real time clock and Teletype Controller
T_ 5.2 Power Fail
In the event of an unexpected power failure the voltage will ra-
pidly decrease from its normal value to the value where the pro-
cessor automatically shuts down completely. There will however be
an interval of time - roughly one or two milliseconds - between
the initial drop-off of voltage and the actual shut-down. The Po-
wer Fail circuit will sense the beginning reduction of voltage,
set the Power Fail flag and request an interrupt. The interrupt
service routine will then be able to utilize the interval before
shut-down to terminate current program execution and finally it
will execute a HALT. As one or two milliseconds is sufficient
time to execute up to 1500 instructions there is ample time to
perform the power fail routine.
The power fail feature has no device code and no interrupt dis-
able bit in the priority mask. Neither does it respond to the IN-
TERRUPT ACKNOWLEDGE instruction. The Power Fail flag can be tested
by means of the CPU SKIP instruction as described in section
4.7.8.
5.3 Real Time Clock
The Real Time Clock generates a continuous sequence of pulses in-
dependently of processor timing. The clock can be used primarily
for low resolution timing as compared to processor speed, but it
has a high long-term accuracy.
Following a power turn-on the various frequencies are only avail-
able after an interval of 5 seconds, because the crystal must be
given this amount of time to settle down after excitation in or-
der to emit a steady pulse train.
Selection of clock frequency is accomplished by means of the I/O
instruction DATA OUT A, Real Time Clock: \f
T_ DOA f' ac,RTC
= ==
0 1 1 AC 0 1 0 F 0 0 1 1 0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will select the clock frequency according to
the values of bits (13 : 15) in the specified AC as listed be-
low:
DOA RTC
BIT 13 14 15 SELECTED TIME
0 0 0 50 Hz
0 0 1 10 Hz
0 1 0 100 Hz
0 1 1 1 KHz
1 0 0 5 KHz
1 0 1 10 KHz
1 1 0 50 KHz
1 1 1 100 KHz
In addition the instruction will cause the Busy and Done flags to
be set according to the control code specified by "F" (cf. section
4.6). Setting the Busy flag by means of this instruction will al-
low the next pulse from the clock to set Done thus requesting an
interrupt if the Interrupt On flag is 1.
The interrupt priority level of this device is associated with
bit 13 of the interrupt priority mask.
The DATA OUT A instruction applied to select the clock frequency
is needed only once. The first interrupt after this instruction
has set Busy = 1 can come at any time up to the clock frequency,
but once the first interrupt has appeared the following interrupts
will adhere to the selected frequency - provided that the program
sets Busy = 1 before the next interrupt is due. This is done by
the instruction:
NIOS 14.
The I/O RESET instruction will - whether it appears in the pro-
gram or is generated by using the Diagnostic Front Panel - reset
the clock to a frequency of 50 Hz. \f
5.4 Teletype Controller
The Teletype Controller provides for two-way communication be-
tween the computer and the operator. The input device is the Te-
&_ letype keyboard and the output device is the Teletype printer.
All information exchanges between the computer and the keyboard/
printer use a subset of the 128 character alphanumeric ASCII code
as listed in Appendix B. In addition to a keyboard and a printer,
some models of the Teletype terminal can be equipped with a paper
tape reader/punch combination. Terminals so equipped are designa-
ted Automatic Send/Receive (ASR) terminals, while those not so
equipped are designated Keyboard Send/Receive (KSR) terminals.
T_ 5.4.1 I_n_s_t_r_u_c_t_i_o_n_s_
Since the terminal is in effect two peripheral devices coupled
&_ together, the controller contains both an input buffer and an
output buffer. These buffers are independent of one another and
are both 8 bits in length.
Similarly two completely separate sets of Busy and Done flags
are available for input and output operations respectively.
The Busy and Done flags are controlled by means of the two stand-
ard device flag commands in the instructions according to the
following list:
"F" = S Sets Busy = 1 and Done = 0 and either reads a charac-
ter into the input buffer or transfers a character in
the output buffer to the printer (or the punch).
"F" = C Sets Busy = 0 and Done = 0 thereby stopping all data
transfer operations. This command - if issued while a
transfer is in process - will result in partial
reception of the character code being transferred.
"F" = P No effect.
The instructions used to read the character buffer and to load
the character buffer are the standard I/O instructions with the
appropriate device codes. An extract of Appendix A containing
these codes appear below:
T_
Octal
Code Mnemonic Maskbit Device
10 TTI 14 Teletype input
11 TTO 15Teletypeoutput\f
5.4.1.1 R_e_a_d_ _c_h_a_r_a_c_t_e_r_ _b_u_f_f_e_r_
DIA f' ac,TTI
= ==
0 1 1 AC 0 0 1 F 0 0 1 0 0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
&_
This instruction will place the contents of the input buffer in
bits 8 to 15 of the AC specified in the instruction. Bit 8 is a
parity check bit while bits 9 to 15 contain the character code
proper. Bits 0 to 7 of the AC are all set to 0.
After the data transfer has been completed the controller's Busy
and Done flags for input are set according to the control code
specified by "F".
T_ 5.4.1.2 L_o_a_d_ _c_h_a_r_a_c_t_e_r_ _b_u_f_f_e_r_
DOA f' ac,TTO
= ==
0 1 1 AC 0 0 1 F 0 0 1 0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
This instruction will place bits 9 to 15 of the specified AC in
the output buffer of the controller. After the transfer has been
completed the controller>s Busy and Done flags for output are
set according to the control code specified by "F". The contents
of the AC specified in the instruction will remain unaltered.
T_ 5.4.2 P_r_o_g_r_a_m_m_i_n_g_
On account of the two-sided nature of the Teletype terminal this
section will describe input and output procedures separately.
&_
T_ 5.4.2.1 I_n_p_u_t_. Input operations - whether full- or half-duplex - do not
have to be initialized by the program because the striking of a
key on the keyboard automatically will transmit the correspond-
&_ ing character code to the controller. When the character has been
assembled the input Busy flag is set to 0, the input Done flag is
set to 1 and a program interrupt consequently requested - provid-
ed that the priority mask bit is 0.
\f
The character can then be read by issuing the READ CHARACTER BUF-
FER instruction (DIA). The instruction should be issued with
either a C or an S command so that the input Done flag is set to
0; this will allow the controller to initiate a further program
interrupt request when the next character has been fully assembl-
ed.
T_ 5.4.2.2 O_u_t_p_u_t_. Output operations are initiated by the program using the
LOAD CHARACTER BUFFER instruction (DOA). The instruction should
be issued with an S command, which will set the Busy flag to 1
&_ and allow the transmitting of the character to the terminal. When
the transmission has been completed the output Busy flag is set
to 0 and the output Done flag is set to 1 thus issuing a program
interrupt request.
The output buffer must be reloaded by means of the LOAD CHARAC-
TER BUFFER instruction every time a character is to be sent to
the terminal. Thus to transmit a multi-character message a se-
quence of LOAD CHARACTER BUFFER instructions with S commands must
be issued. The program must make allowance for complete transmis-
sion of every single character before transmission of the next
character is initiated.
T_ 5.4.3 P_r_o_g_r_a_m_m_i_n_g_ _E_x_a_m_p_l_e_s_
The following examples show sections of programs which will hand-
&_ le character operations involving the Teletype keyboard,and
printer.
Example 1 reads a character from the Teletype keyboard, and exam-
ple 2 prints a character on thee Teletype printer.
5.4.3.1 E_x_a_m_p_l_e_ _1_._
NIOS TTI ;Start input
SKPDN TTI ;Frame buffer loaded yet?
JMP .-1 ;No
DIAC 1,TTI ;Read frame and clear Done flag
&_
T_ 5.4.3.2 E_x_a_m_p_l_e_ _2_._
SKPBZ TTO ;Printer free?
JMP .-1 ;No, try again
DOAS 1,TTO ;Print character
&_ \f
T_ 5.4.3.3 E_x_a_m_p_l_e_ _3_._ The subroutine shown in this example and called from
the main program by a JUMP TO SUBROUTINE instruction (JSR to
TTYRD) illustrates reading and echoing characters on the Telety-
&_ pe, with Teletype interrupts disabled. AC 0 is used to store the
character.
TTYRD: SKPDN TTI ;Has character been typed?
JMP .-1 ;No, then wait
DIAC 0,TTI ;Yes, then read character and
clear Done flag
SKPBZ TTO ;Is TT0 ready?
JMP .-1 ;No, then wait
DOAS 0,TTO ;Yes, then echo character
JMP 0,3 ;Return
T_ 5.4.3.4 E_x_a_m_p_l_e_ _4_._ This example shows how Teletype may be programmed us-
ing the program interrupt facility. To do so makes it possible to
&_ perform a number of calculations in the intervals of time between
Teletype characters.
This routine will read a line and echo it on the Teletype prin-
ter using the interrupt priority system. The characters are read
into a buffer area beginning at location 1000DD8UU. The routineis
terminated by either a carriage return character or line over-
flow. Line overflow is determined by the value of MAXLL (maximum
line length).
\f
.LOC O ;
0 ;Program counter stored here when
an interrupt occurs.
IHAND ;Address of interrupt handler
.LOC 400 ;
T_ START: LDA 1,BUFFER ;Set up buffer pointer in
auto-increment location 23
STA 1,23 ;
LDA 1,MAXLL ;Get maximum line length
STA 1,CNTR ;Initialize line overflow counter
SUBZL 1,1 ;Set AC 1 = 1
DOBS 1,CPU ;Mask out TTO and turn on
interrupts
.
&_ .
.
HANG: LDA 0,CNTR ;When need full line to continue
hang up here until reading is all
done
MOV 0,0,SZR ;
JMP .-2 ;
.
.
.
.
BUFFR: 777 ;Buffer begins at location 1000
MAXLL: 110 ;Maximum of 72DD10UUcharacters
per line
CNTR: 0 ;Line overflow counter
.
.
.
IHAND: SKPDN TTI ;Make sure TTI caused the
interrupt
HALT ;Error - some other peripheral
interrupted
STA 0,SAV0 ;Save accumulators that will be
used
STA 1,SAV1 ;
DIAC 0,TTI ;Read character and clear Done
STA 0, 23 ;Store character in buffer
SKPBZ TTO ;Make sure TT0 not busy
JMP .-1 ;
DOAS 0,TTO ;Echo character \f
LDA 1,CR ;Is it a carriage return?
SUB 0,1,SZR ;
JMP .+4 ;No
SUBC 0,0 ;Yes, clear AC 0 without changing
carry
STA 0,CNTR ;Zero out CNTR to indicate line
done
JMP .+3 ;
DSZ CNTR ;If not a carriage return,
decrement CNTR
JMP OUT ;Line not yet done, go dismiss
LDA 0,TTMSK ;Line is done
MSKO 0 ;Mask out TTI (and TT0) to inhibit
further input
OUT: LDA 0,SAV0 ;Restore accumulators
LDA 0,SAV1 ;
INTEN ;Turn interrupts back on
JMP 0 ;Return to interrupted program
SAV0: 0
SAV1: 0
CR: 215
TTMSK: 3
F_\f
6 P_R_O_G_R_A_M_ _L_O_A_D_I_N_G_
6.1 Introduction
Whenever the computer is used for information processing of any
kind the program must - as previously mentioned - reside in main
memory. But to read a program into memory is in itself a kind of
information processing and therefore requires the existence in
memory of a program - called a loading program - to perform this
duty.
The loading program is read into memory by a small, specialized
loading program which is called a "bootstrap loader" and whose
only function is to read into memory the more general-purpose
loading program.
Two methods are available for entering the bootstrap loader into
memory. One is for the operator to enter it manually utilizing
the data switches and the deposit switch on the Diagnostic Front
Panel. The other is to use the Automatic Program Load option if
the computer in question is so equipped.
In this chapter only automatic program loading is described. For
details about manual loading the reader must consult the Technical
Manual for the Debug Unit - RCSL: 52-AA780.
CAUTION: When entering the Loading Program using the Debug Unit
T_ and Diagnostic Panel, the operator should remember,
that "READS" - instruction will read the switches on
the frame of the CPU board and not switches on the
Diagnostic Panel.
This means that when the operator starts the loader
with sw (o:15) = 1 on the Diagnostic Panel, sw(0) on
the CPU frame must too be set to 1.
6.2Automatic Loading
To use the Automatic Program Load option, the operator must first
select the input device and set up the loading program on this
device in preparation to be read. In addition the device code of
this unit must be set up in its binary form on the data switches\f
10 to 15 on the front frame of the CPU board (cf. the illustra-
tion appearing in the following chapter). The setting of data
switch 0 on the front panel depends on the type of input device
selected. If this is a data channel device - for instance magne-
tic tape - data switch 0 must be set to 1. If it is a low-speed
device - for instance a paper tape reader - data switch 0 must be
set to 0.
When this has been done, push the AUTOLOAD switch on the opera-
tor panel. This will cause the bootstrap loader to be read, de-
posited in memory locations 0 to 37DD8UU and started location 0.The
bootstrap loader will then read the data switches (0 and 10 to
15), set up its own I/O instructions with the device code as read
and finally perform a program load procedure which depends on the
setting of data switch 0.
If data switch 0 has been set to 1, the bootstrap loader will
start the device for data channel transfer starting storage at
location 0 and will then loop at location 377DD8UUuntil adatachan-
nel transfer places a word in this location. When this happens,
the word placed in this location is executed as an instruction;
typically this will be a JUMP into the data which have been
placed in locations 0 to 376DD8UU.
N_O_T_E_: For proper program loading via the data channel the de-
vice in use must be initialized for the reading opera-
tion by an I/O RESET instruction followed by a NIOS
instruction. Furthermore the device must stop reading
when 256DD10UU words has been read; otherwise the avail-
able memory locations will overflow.
If data switch 0 has been set to 0, the bootstrap loader will
read the loading program via programmed I/O. The device must supp-
ly data as 8-bit bytes; each pair of bytes read will be memory
stored in as a single word wherein the first and second byte will
become respectively the left and right halves of the word. To simp-
lify the positioning of the input medium - for instance paper tape
- the bootstrap loader will ignore leading null characters, i.e.
it will not store any word until it has read a non-zero synchroni-
zation byte.
The first word following this synchronization byte must be the
negative of the total number of words to be read including this
first word. The number of words to be read - including the first
- cannot exceed 192DD10UU. The bootstrap loader will storethe words
read in memory starting in location 100DD8UU. When the lastword has
been read the bootstrap loader will transfer control to that lo-
cation. \f
The Automatic Loading hardware in RC 3703 is capable of containing
T_ up to 16 times 32 word programs, one of this programs is listede
on the following pages, a bootstrap loader capable of loading in
either of the manners described above.
A list of the available bootstrap loaders in the Automatic Pro-
gram Load option, F10A is too shown.
For details about the RC 3703 program load refer to:
GENERAL INFORMATION
Hardware Testprograms and Program Load to RC 3703
RCSL - 52AA764
\f
T_ B_O_O_T_S_T_R_A_P_ _L_O_A_D_E_R_ _F_O_R_
A_U_T_O_M_A_T_I_C_ _P_R_O_G_R_A_M_ _L_O_A_D_
Fig. 6.1
00000 060477 BEG: READS 0 ;READ SWITCHES INTO AC0
00001 105120 MOVZL 0,1 ;ISOLATE DEVICE CODE
00002 124240 COMOR 1,1 ;-DEVICE CODE -1
00003 010011 LOOP: ISZ OP1 ;COUNT DEVICE CONTROL INTO
ALL
00004 010031 ISZ OP2 ;I0 INSTRUCTIONS
00005 010033 ISZ OP3 ;
00006 010014 ISZ OP4 ;
00007 125404 INC 1,1,SZR ;DONE?
00010 000003 JMP LOOP ;NO INCREMENT AGAIN
00011 060077 OP1: 060077 ;START DEVICE;(NIOS 0) -1
00012 030017 LDA 2,C377 ;YES,PUTJMP 377INTO
LOCATION 377
00013 050377 STA 2,377 ;
00014 063377 OP4: 063377 ;BUSY ? :( SKPBN 0 ) -1
00015 000011 JMP OP1 ;NO, GO TO OP1
00016 101102 MOVL 0,0,SZC ;LOW SPEED DEVICE?(TEST
SWITCH 0)
00017 000377 C377: JMP 377 ;NO, GO TO 377 AND WAIT
FOR CHAN.
00020 004031 LOOP2:JSR GET+1 ;GET A FRAME
00021 101065 MOVC 0,0.SNR ;IS IT NONZERO?
00022 000020 JMP LOOP2 ;NO, IGNORE AND GET ANOTHER
00023 004030 LOOP4:JSR GET ;YES, GET A FULL WORD
00024 046027 STA 1,ÆC77 ;STORE STARTING AT 100
00025 010100 ISZ 100 ;COUNT WORD - DONE?
00026 000023 JMP LOOP4 ;NO, GET ANOTHER
00027 000077 C77: JMP 77 ;YES - LOCATION COUNTER AND
JUMP TO LAST WORD
00030 126420 GET: SUBZ 1,1 ;CLEAR AC1, SET CARRY
OP2:
00031 063577 LOOP3:063577 ;DONE ? : ( SKPDN 0)-1
00032 000031 JMP LOOP3 ;NO, WAIT
00033 060477 OP3: 060477 ;YES, READ INTO AC0:(DIAS
0,0) -1
00034 107363 ADDCS 0,1,SNC ;ADD 2 FRAMES SWAPPED-
GOTSECOND? \f
00035 000031 JMP LOOP3 ;NO, GO BACK AFTER IT.
00036 125300 MOVS 1,1 ;YES, SWAP AC1
00037 001400 JMP 0,3 ;RETURN WITH FULL WORD
\f
L_I_S_T_ _O_F_ _A_V_A_I_L_A_B_L_E_
P_R_O_G_R_A_M_ _L_O_A_D_S_ _i_n_ _F_1_0_A_
AUTOLOAD
DEVICE NO. PROGRAM MODULE
(OCTAL) BIT O NO. FUNCTION
0 x 0CONSOLE INITIALIZATION
(BAUD RATE - NO. OF STOP BITS
AND MEMORY RESET
1 x 1 MEMORY TESTPROGRAM
202CONSOLE ECHO PROGRAM
212CONSOLE CHARACTER GENERATOR
3-15
7
21-55 0 3 STANDARD AUTOLOAD
57-60LOW SPEED DEVICE
62-72(i.e. Ptr Dev. 12DD8UU)
74-77
3-15
17
21-5513STANDARD AUTOLOAD
57-60DATA CHANNEL PROGRAM LOAD
62-72(Mag. tape Dev 30DD8UU)
74-77(FPA Dev 46, Dev 74)
16x4CARD READER PROGRAM LOAD (CDR)
56x4CARD READER PROGRAM LOAD (CDR)
6105FLEXIBLE DISC PROGRAM LOAD (FDD)
6115NO FUNCTION
7306DISC PROGRAM LOAD (DKP)
(incl. a Disc recalibration)
7316DISC PROGRAM LOAD (DKP)
(no recalibration)
2007Disc Storage Module PROGRAMLOAD
RELATION BETWEEN DEVICE NO,
(SET ON THE FRONT PANEL OF RC 3703)
AND THE SELECTED PROGRAM MODULE
Fig. 6.2 \f
7 SWITCHES AND INDICATORS
In this chapter the switches and indicators placed on the Front
Panel of the CPU board are described. For details about the out-
line of the Front Panle refer to Fig. 7.1
7.1 Switches
7.1.1 A_u_t_o_l_o_a_d_ _D_e_v_i_c_e_ _S_e_l_e_c_t_
If a Read Switches (READS) instruction is executed the state of
these switches is loaded into the selected AC. BIT 1-9 read as
logic zeros.
Switch 10-15 is set up with the device address for the autoload
device.
Switch (10:15) = 0 selects a program to initialize the TTY con-
troller (set baud rate and number of stop bits) and a reset of
the semiconductor memory. This program is automatically executed
after power up.
Switch (10:15) = 1 selects a memory test designed to detect mal-
functions in the memory address selection logic.
Switch (10:15) = 2 selects a Console interface Exercises.
If switch 0 = 0 an ECHO program is selected
If switch 0 = 1 lines containing 80 characters are written on the
console.
For details about setting of the AUTOLOAD DEVICE SELECTS switches
refer to RCSL: 52 - AA764
GENERAL INFORMATION
HARDWIRED TESTPROGRAMS AND PROGRAM LOAD TO RC 3703 REV. 0
7.1.2 B_a_u_d_ _R_a_t_e_ _S_e_l_e_c_t_
This switches is used to control the transmissionb speed for the
TTY controller. The contents of these switches is only transfer-
red to the TTY controller after power on and after AUTOLOAD with
switch (10:15) = 0
N_O_T_E_:_ Only change of the BAUD RATE select switches will not
change transmission speed; but the cpu must be powered\f
down, or the operator push AUTO with switch (10:15) = 0.
7.1.3 S_t_o_p_ _B_i_t_ _S_e_l_e_c_t_
This switch selects 1 or 2 stopbits in the dataformat for the TTY
controller. The contents of this switch is only tranferred to the
TTY controller after power on and after AUTOLOAD with switch
(10:15) = 0.
7.2 Indicators
7.2.1 R_i_g_h_t_ _P_a_r_i_t_y_ _E_r_r_o_r_
This indicator is lit, if a parity error is detected during a me-
mory read cycle in the right byte (bit 8-15).
This indicator is only cleared by power reset or IORST.
7.2.2 L_E_F_T_ _P_a_r_i_t_y_ _E_r_r_o_r_
This indicator is lit, if a parity error is detected during a me-
mory read cycle in the left byte (bit 0-7).
7.2.3 F_e_t_c_h_
This indicator is lit, whenever the CPU is reading an instruction
from memory.\f
FRONT FRAME OF CPU BOARD\f
APPENDIX A
I/O DEVICE CODES AND MNEMONICS
Decimal Octal
code code Mnemonic Maskbit Device
01 01
01 02 Central Processor
03 03
04 04
05 05 ASL Automatic Syystem Load
06 06
07 07
08 10 TTI 14 Teletype Input
09 11 TTO 15 Teletype Output
10 12 PTR 11 Paper Tape Reader
11 13 PTP 13 Paper Tape Punch
12 14 RTC 13 Real Time Clock
13 15 PLT 12 Incremental Plotter
SPC2 9 Third Standard Parallel
Controller
14 16 CDR 10 Card Reader
15 17 LPT 12 Line Printer
16 20 DSC 4 Disc Storage Channel
17 21 SPC 9 Standard Parallel Control
ler
18 22 SPC1 9 Second Standard Parallel
Controller
19 23 PTR1 11 Second Paper Tape Reader
20 24 AMX3 2 Fourth 8 Channel Asynchro-
nous Multiplexor
TMX10 0 Second 64 Channel
21 25 TMX11 1 Asynchronos Multiplexor
22 26 TMX10 0 64 Channel Asynchronous
23 27 TMX1 1 Multiplexor
24 30 MT 5 Magnetic Tape
25 31 PTP1 13 Second Paper Tape Punch
26 32 TTI2 14 Third Teletype Input
OCP-Function Button Out
27 33 TTO2 15 Third Teletype Output
OCP-Functioonm Button In
28 34 TTI3 14 Fourth Teletype Input
OCP-Numeric Keyboard In
29 35 TTO3 15 Fourth Teletype Output
DISP 7 OCP-Display
30 36 OCP-Autoload
31 37 LPS 12 Serial Printer \f
Decimal Octal
code code Mnemonic Maskbit Device
32 40 REC 8 BSC Controller
33 41 XMT 8
34 42 REC1 8 Second BSC Controller
35 43 XMT1 8
36 44 MT1 5 Second Magnetic Tape
37 45 CLP 12 Charaband Printer
38 46 FPAR 3 Inter Processor Channel
Receiver
39 47 FPAX 3 Inter Processor Channel
Transmitter
40 50 TTI1 14 Second Teletype Input
41 51 TTO1 15 Second Teletype Output
42 52 AMX 2 8 Channel Asynchronous
Multiplexor
43 53 AMX1 2 Second 8 ChannelAsynchro-
nous Multiplexor
44 54 HLC 8 HDLC Controller
FPAR2 3 Third Inter Processor
Channel Receiver
45 55 HLC1 8 Second HDLC Controller
FPAX2 3 Third Inter Processor Chan-
nel Transmitter
46 56 CDR1 10 Second Card Reader
47 57 LPT1 12 Second Line Printer
LPS2 12 Third Serial Printer
48 60 SMX Synchronous Multiplexor
49 61 FDD 7 Flexible Disc Drive
50 62 CRP 10 Card Reader Punch
51 63 CLP1 12 Second Charaband Printer
52 64 FDD1 7 Second Felxible Disc Drive
53 65 LPS3 12 Fourth Serial Printer
54 66 DTC 9 Digital Cartridge Control-
ler
LPS4 12 Fifth Serial Printer
55 67 LPS1 12 Second Serial Printer
56 70 DST Digital Sense
57 71 DOT Digital Output
58 72 CNT Digital Counter
Dial-up Controller
59 73 DKP 7 Moving Head Disc Channel \f
Decimal Octal
code code Mnemonic Maskbit Device
60 74 FPAR1 3 Second inter Processor
Channel Receiver
61 75 FPAX1 3 Second Inter Processor
Cahnnel Transmitter
62 76 AMX2 2 Third 8 Channel Asynchro-
nous Multiplexor
63 77 CPU Central Processor\f
Appendix B
T_ ASCII C_H_A_R_A_C_T_E_R_ _C_O_D_E_S_
To Produce Even
ASCII On TTY Mod Parity
Deci- Cha- 33,35 8-bit
mal Octal Hex racter Control Function Cntr Shift Char code
0 000 00 NUL Null P 00
1 001 01 SOH Start of Heading A 81
2 002 02 STX Start of Text B 82
3 003 03 ETX End of Text C 03
4 004 04 EOT End of Transmission D 84
5 005 05 ENQ Enquiry E 05
6 006 06 ACK Acknowledge F 06
7 007 07 BEL Bell G 87
8 010 08 BS Backspace H 88
9 011 09 HT Horizontal Tap I 09
10 012 0A NL New Line line feed 0A
J OA*
line feed 8A
11 013 0B VT Vertical Tab K 8B
12 014 0C FF Form Feed L 0C
13 015 0D RT Return return 8D
M 8D*
return 0D
14 016 0E SO Shift Out N 8E
15 017 0F SI Shift In O 0F
16 020 10 DLE Data Link Escape P 90
17 021 11 DC1 Device Control 1 Q 11
18 022 12 DC2 Device Control 2 R 12
19 023 13 DC3 Device Control 3 S 93
* on even parity Teletypes these codes have odd parity
&_ B-1 \f
T_ To Produce Even
ASCII On TTY Mod Parity
Deci- Cha- 33,35 8-bit
mal Octal Hex racter Control Function Cntr Shift Char code
20 024 14 DC4 Device Control 4 T 14
21 025 15 NAK Negative Acknow-
ledge U 95
22 026 16 SYN Synchronous Idle V 96
23 027 17 ETB End Transmission
Block W 17
24 030 15 CAN Cancel X 18
25 031 19 EM End of Medium Y 99
26 032 1A SUB Substitute Z 9A
27 033 1B ESC Escape esc 1B
K 1B
28 034 1C FS File Separator L 9C
29 035 1D GS Group Separator M 1D
30 036 1E RS Record Separator N 1E
31 037 1F US Unit Separator O 9F
32 040 20 SP Space space A0
33 041 21 ! 1 21
34 042 22 " 2 22
35 043 23 # 3 A3
36 044 25 < 4 24
37 045 25 % 5 A5
38 046 26 & 6 A6
39 047 27 > 7 27
40 050 28 ( 8 28
41 051 29 ) 9 A9
42 052 2A * : AA
43 053 2B + ; 2B
44 054 2C , , 2C
&_ B-2 \f
T_ To Produce Even
ASCII On TTY Mod Parity
Deci- Cha- 33,35 8-bit
mal Octal Hex racter Control Function Cntr Shift Char code
45 055 2D - - 2D
46 056 2E . . 2E
47 057 2F / / AF
48 060 30 0 0 30
49 061 31 1 1 B1
50 062 32 2 2 B2
51 063 33 3 3 33
52 064 34 4 4 B4
53 065 35 5 5 35
54 066 36 6 6 36
55 067 37 7 7 B7
56 070 38 8 8 B8
57 071 39 9 9 39
58 072 3A : : 3A
59 073 3B ; ; BB
60 074 3C , 36
61 075 3D = - BD
62 076 3E . BE
63 077 3F ? / 3F
64 100 40 @ P C0
65 101 41 A A 41
66 102 42 B B 42
67 103 43 C C 43
68 104 44 D D 44
69 105 45 E E C5
&_ RC 3603 B-3 \f
T_ To Produce Even
ASCII On TTY Mod Parity
Deci- Cha- 33,35 8-bit
mal Octal Hex racter Control Function Cntr Shift Char code
70 106 46 F F C6
71 107 47 G G 47
72 110 48 H H 48
73 111 49 I I C9
74 112 4A J J CA
75 113 4B K K 4B
76 114 4C L L CC
77 115 4D M M 4D
78 116 4E N N 4E
79 117 4F O O CF
80 120 50 P P 50
81 121 51 Q Q D1
82 122 52 R R D2
83 123 53 S S 53
84 124 54 T T D4
85 125 55 U U 55
86 126 56 V V 56
87 127 57 W W D7
88 130 58 X X D8
89 131 59 Y Y 59
90 132 5A Z Z 5A
91 133 5B K DB
92 134 5C L 5C
93 135 5D M DD
94 136 5E N DE
&_ B-4 \f
T_ To Produce Even
ASCII On TTY Mod Parity
Deci- Cha- 33,35 8-bit
mal Octal Hex racter Control Function Cntr Shift Char code
95 137 5F _ O 5F
96 140 60 60
97 141 61 a E1
98 142 62 b E2
99 143 63 c 63
100 144 64 d E4
101 145 65 e 65
102 146 66 f 66
103 147 67 g E7
104 150 68 h E8
105 151 69 i 69
106 152 6A j 6A
107 153 6B k EB
108 154 6C l 6C
109 155 6D m ED
110 156 6E n EE
111 157 6F o 6F
112 160 70 p F0
113 161 71 q 71
114 162 72 r 72
115 163 73 s F3
116 164 74 t 74
117 165 75 u F5
118 166 76 v F6
119 167 77 w 77
120 170 78 x 78
121 171 79 y F9
122 172 7A z FA
123 173 7B 7B
124 174 7C FC
125 175 7D 7D
126 176 7E 7E
127 177 7F DEL rubout FF
&_ B-5 \f
Appendix C
D_O_U_B_L_E_ _P_R_E_C_I_S_I_O_N_ _A_R_I_T_H_M_E_T_I_C_
A double length number consists of two words concatenated into a
32-bit string wherein bit 0 is the sign and bits 1-31 are the
magnitude in two>s complement notation. The high-order part of a
negative number is therefore in one>s complement form unless the
low-order part is null (at the right only 0>s are null regard-
less of sign). Hence, in processing double length numbers, two>s
complement operations are usually confined to the low-order
parts, whereas one>s complement operations are generally requir-
ed for the high-order parts.
Suppose we wish to negate the double length number whose high
and low-order words respectively are in AC0 and AC1. We negate
the low-order part, but we simply complement the high-order part
unless the low order part is zero. Hence
T_ NEG 1,1,SNR
NEG 0,0,SKP ;LOW ORDER ZERO
&_ COM 0,0 ;LOW ORDER NON-ZERO
Note that the magnitude parts of the sequence of negative num-
bers from the most negative toward zero are the positive numbers
from zero upward. In other words, the negative representation -x
is the sum of x and the most negative number. Hence, in multiple
precision arithmetic, low-order words can be treated simply as
positive numbers. In unsigned addition a carry indicates that
the low-order result is just too large and the high-order part
must be increased. We add the number in AC2 and AC3 to the num-
ber in AC0 and AC1.
ADDZ 3,1,SZC
INC 0,0
ADD 2,0
In two>s complement subtraction a carry should occur unless the
subtrahend is too large. We could increment as in addition, but
since incrementing in the high-order part is precisely the dif-
ference between a one>s complement and a two>s complement, we
can always manage with only two instructions. We subtract the
number in AC2 and AC3 from that in AC0 and AC1.
T_ SUBZ 3,1,SZC
SUB 2,0,SKP
ADC 2,0
&_ C-1\f
T_ Appendix D
I_N_S_T_R_U_C_T_I_O_N_ _U_S_E_ _E_X_A_M_P_L_E_S_
On the following pages are examples of how the instruction set
of the RC 3703 computer may be used to perform some common
functions.
1. Clear an AC and the carry bit.
SUBO AC,AC
2. Clear an AC and preserve the carry bit.
SUBC AC,AC
3. Generate the indicated constants.
SUBZL AC,AC ;GENERATE +1
ADC AC,AC ;GENERATE -1
ADCZL AC,AC ;GENERATE -2
4. Let ACX be any accumulator whose contents are zero.
Generate the indicated constants in ACX.
INCZL ACX,ACX ;GENERATE +2
INCOL ACX,ACX ;GENERATE +3
INCS ACX,ACX ;GENERATE +400DD8UU
5. Subtract 1 from an accumulator without using a constant from
memory.
NEG AC,AC
COM AC,AC
6. Check if both bytes in an accumulator are equal.
MOVS ACS,ACD
SUB ACS,ACD,SZR
JMP --- ;NOT EQUAL
--- --- ;EQUAL
D-1\f
T_ 7. Check if two accumulators are both zero.
MOV ACS,ACS,SNR
SUB# ACS,ACD,SZR
JMP --- ;NOT BOTH ZERO
--- --- ;BOTH ZERO
8. Check an ASCII character to make sure it is a decimal
digit. The character is in ACS and is not destroyed
by the test. Accumulators ACX and ACY are destroyed.
LDA ACX,C60 ;ACX=ASCII ZERO
LDA ACY,C71 ;ACY=ASCII NINE
ADCZ# ACY,ACS,SNC ;SKIPS IF (ACS) 9
ADCZ# ACS,ACX,SZC ;SKIPS IF (ACS) D=U0
JMP --- ;NOT DIGIT
--- --- ;DIGIT
C60: 60 ;ASCII ZERO
C71 71 ;ASCII NINE
9. Test an accumulator for zero.
MOV AC,AC,SZR
JMP --- ;NOT ZERO
--- --- ;ZERO
10.Test an accumulator for -1.
COM# AC,AC,SZR
JMP --- ;NOT -1
--- --- ;-1
11.Test an accumulator for 2 or greater.
MOVZR# AC,AC,SNR
JMP --- ;LESS THAN 2
--- --- ;2 OR GREATER
&_ D-2\f
T_ 12. Assume it is known that AC contains 0, 1, 2, or 3.
Find out which one.
MOVZR# AC,AC,SEZ
JMP THREE ;WAS 3
MOV AC,AC,SNR
JMP ZERO ;WAS 0
MOVZR# AC,AC,SZR
JMP TWO ;WAS 2
--- --- ;WAS 1
13.Multiply an AC by the indicated value.
MOV ACX,ACX ;MULTIPLY BY 1
MOVZL ACX,ACX ;MULTIPLY BY 2
MOVZL ACX,ACY ;MULTIPLY BY 3
ADD ACY,ACX
ADDZL ACX,ACX ;MULTIPLY BY 4
MOV ACX,ACY ;MULTIPLY BY 5
ADDZL ACX,ACX
ADD ACY,ACX
MOVZL ACX,ACY ;MULTIPLY BY 6
ADDZL ACY,ACX
MOVZL ACX,ACY ;MULTIPLY BY 7
ADDZL ACY,ACY
SUB ACX,ACY ;IN ACY
ADDZL ACX,ACX ;MULTIPLY BY 8
MOVZL ACX,ACX
MOVZL ACX,ACY;MULTYPLY BY 9
ADDZL ACY,ACY
ADD ACY,ACX
MOV ACX,ACY ;MULTIPLY BY 10DD10UU
ADDZL ACX,ACX
ADDZL ACY,ACX
MOVZL ACX,ACY ;MULTIPLY BY 12DD10UU
ADDZL ACY,ACX
MOVZL ACX,ACX
MOVZL ACX,ACY ;MULTIPLY BY 18DD10UU
ADDZL ACY,ACY
ADDZL ACY,ACX
&_ D-3\f
T_ 14. Perform the inclusive OR of the operands in AC0 and
AC1. The result is placed in AC1. The carry bit is
unchanged.
COM 0,0
AND 0,1
ADC 0,1
15. Perform the exclusive OR of the operands in AC0 and
AC1. The result is placed in AC1. The contents of
AC2 and the carry bit are destroyed.
MOV 1,2
ANDZL 0,2
ADD 0,1
SUB 2,1
16. Move 30 words from locations 2000DD8UU-2035DD8UU to loca-
tions 3000DD8UU-3035DD8UU. The auto-increment locations are
used to hold the source and destination addresses.
LDA 0,ADDRS ;SET UP SOURCE ADDRESS
STA 0,20
LDA 0,ADDRD ;SET UP DESTINATION ADDRESS
STA 0,21
LOOP: LDA 0,Æ20 ;INCREMENT SOURCE ADDRESS
; AND GET WORD
STA 0,Æ21 ;INCREMENT DESTINATION
; ADDRESS AND STORE WORD
DSZ CNT ;DECREMENT COUNT
JMP LOOP ;GO BACK FOR NEXT WORD
... ;SKIP HERE WHEN COUNT IS
; ZERO
...
ADDRS: 1777 ;SOURCE ADDRESS MINUS ONE
ADDRD: 2777 ;DESTINATION ADDRESS MINUS
; ONE
CNT: 36 ;WORD COUNT --36DD8UU EQUALS 3DD10UU
&_ D-4\f
T_ 17. Perform the following unsigned integer comparisons.
SUB# ACS,ACD,SZR ;SKIP IF CONTENTS OF ACS =
; CONTENTS OF ACD
SUB# ACS,ACD,SNR ;SKIP IF CONTENTS OF ACS =
; CONTENTS OF ACD
ADCZ# ACS,ACD,SNC ;SKIP IF CONTENTS OF ACS
; CONTENTS OF ACD
SUBZ# ACS,ACD,SNC ;SKIP IF CONTENTS OF ACS '_
; CONTENTS OF ACD
SUBZ# ACS,ACD,SZC ;SKIP IF CONTENTS OF ACS '
; CONTENTS OF ACD
ADCZ# ACS,ACD,SZC ;SKIP IF CONTENTS OF ACS _
; CONTENTS OF ACD
18. Compare the signed, two>s complement integer contained in
ACS to 0.
MOV# ACS,ACS,SZR ;SKIP IF CONTENTS OF ACS EQ 0
MOV# ACS,ACS,SNR ;SKIP IF CONTENTS OF ACS NE 0
ADDO# ACS,ACS,SBN ;SKIP IF CONTENTS OF ACS GT 0
MOVL# ACS,ACS,SZC ;SKIP IF CONTENTS OF ACS GE 0
MOVL# ACS,ACS,SNC ;SKIP IF CONTENTS OF ACS LT 0
ADDO# ACS,ACS,SEZ ;SKIP IF CONTENTS OF ACS LE 0
19. Simulate the operation of the MULTIPLY instruction.
.MPYU: SUBC 0,0 ;CLEAR AC0, DON'T DISTURB CARRY
.MPYA: STA 3,.CB03 ;SAVE RETURN
LDA 3,.CB20 ;GET STEP COUNT
:CB99 MOVR 1,1,SNC ;CHECK NEXT MULTIPLIER BIT
MOVR 0,0SKP ;0 SHIFT
ADDZR 2,0 ;1 - ADD MULTIPLICAND AND SHIFT
INC 3,3,SZR ;COUNT STEP, COMPLEMENTING CARRY ON
; FINAL COUNT
JMP .CB99 ;ITERATE LOOP
MOVCR 1,1 ;SHIFT IN LAST LOW BIT (WHICH WAS
; COMPLEMENTED BY FINAL COUNT) AND
JMP @.CB03 ;RESTORE CARRY
.CB03: 0
.DB20: -20 ;16DD10UU STEPS
&_ D-6\f
T_ 20. Simulate the operation of the DIVIDE instruction.
.DIVI: SUB0,0 ;INTEGER DIVIDE CLEAR HIGH PART
.DIVU: STA 3,.CC03 ;SAVE RETURN
SUB# 2,0,SZC ;TEST FOR OVERFLOW
JMP .CC99 ;YES, EXIT(AC0 AC2)
LDA 3,.CC20 ;GET STEP COUNT
MOVZL 1,1 ;SHIFT DIVIDEND LOW PART
.CC98 MOVL 0,0 ;SHIFT DIVIDEND HIGH PART
SUB# 2,0,SZC ;DOES DIVISOR GO IN?
SUB 2,0 ;YES
MOVL 1,1 ;SHIFT DIVIDEND LOW PART
INC 3,3,SZC ;COUNT STEP
JMP CC98 ;ITERATE LOOP
SUB0 3,3,SKP ;DONE, CLEAR CARRY
.CC99 SUBZ 3,3 ;SET CARRY
JMP @.CC03 ;RETURN
.CC03 0
.CC20 20 ;16DD10UU STEPS
21. Load a byte from memory. The routine is called via a JSR. The
byte pointer for the requested byte is in AC2. The requested
byte is returned in the right half of AC0. The left half of
AC0 and the carry are set to 0. AC1 and AC2 are unchanged.
AC3 is destroyed.
LBYT: STA 3,LRET ;SAVE RETURN ADDRESS
LDA 3,MASK
MOVR 2,2,SNC ;TURN BYTE POINTER INTO WORD ADDRESS
; AND SKIP IF REQUEST BYTE IS RIGHT
; BYTE
MOVS 3,3 ;SWAP MASK IF REQUESTED BYTE IS LEFT
; BYTE
LDA 0,0,2 ;PLACE WORD IN AC0
AND 1,0,SNC ;MASK OFF UNWANTED BYTE AND SKIP IF
; SWAP IS NOT NEEDED
MOVS 0,0 ;SWAP REQUESTED BYTE INTO RIGHT HALF
; OF AC0
MOVL 2,2 ;RESTORE BYTE POINTER AND CARRY
JMP @ LRET ;RETURN
LRET: 0 ;RETURN LOCATION
MASK: 377
&_ D-7\f
T_ 22. Store a byte in memory. The routine is called via a JRS. The
byte to be stored is in the right half of AC0 with the left
half of AC0 set to 0. The byte pointer is in AC2. The word
written is returned in AC0. AC1 and AC2 are unchanged. AC3
and the carry bit are destroyed.
SBYT: STA 3,SRET ;SAVE RETURN
STA 1,SAC1 ;SAVE AC1
LDA 3,MASK
MOVR 2,2,SNC ;CONVERT BYTE POINTER TO WORD
; ADDRESS AND SKIP IF BYTE IS TO BE
; RIGHT HALF
MOVS 0,0,SKP ;SWAP BYTE AND LEAVE MASK ALONE
MOVS 3,3 ;SWAP MASK
LDA 1,0,2 ;LOAD WORD THAT IS TO RECEIVE BYTE
AND 3,1 ;MASK OFF BYTE THAT IS TO RECEIVE
; NEW BYTE
ADD 1,0 ;ADD MEMORY WORD ON TOP OF NEW BYTE
STA 0,0,2 ;STORE WORD WITH NEW BYTE
MOVL 2,2 ;RESTORE BYTE POINTER AND CARRY
LDA 1,SAC1 ;RESTORE AC1
JMP Æ SRET ;RETURN
SRET: 0 ;RETURN LOCATION
SAC1: 0
MASK: 377
&_ D-8\f
T_ Appendix E
I_N_S_T_R_U_C_T_I_O_N_ _E_X_E_C_U_T_I_O_N_ _T_I_M_E_S_
INSTRUCTION MNEMONIC RC 3703
LDA 2.28 s
STA 2.21 s
ISZ, DSZ 3.4 s
JMP 1.1 s
JSR 1.7 s
COM, NEG, MOV, INC 1.7 s
ADC, SUB, ADD, AND
Each level of Æ, add 1 s
Each autoindex, add 1 s
Base register addr, add 0 s
Shift R, L, add 0.3 s
Swap, add 0 s
If SKIP occurs, add 0.3 s
I/O INPUT (incl. READS, INTA) 3.3 s
I/O OUTPUT (MSKO) 3.3 s
NIO (INTEN, INTDS) 3.3 s
I/O SKIP 2.0 s
If SKIP occurs, add 0.3 s
For S, C and P, add 0 s
D_A_T_A_ _C_H_A_N_N_E_L_
DMA Input 2.9 s
DMA Output 2.6 s
DMA Increment 3.6 s
DMA Add to Memory 3.9 s
STB 4.8 s
LDB 3.7 s
E-1\f
\f
«eof»