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Presents historical artifacts from the history of:

Philips Data Systems

This is an automatic "excavation" of a thematic subset of
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See our Wiki for more about Philips Data Systems

Excavated with: AutoArchaeologist - Free & Open Source Software. 

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⟦33df7aaa4⟧ 

    Length: 17460 (0x4434)
    Notes: pts_type(SC)
    Names: »DRDCS1.SC«

Derivation

└─⟦fce1dcf99⟧ Bits:30009704 Philips computer tape "KMD15"
    └─⟦this⟧ »DLCSPY/DRDCS1.SC«

PTS(SC)

	IDENT DRDCS1	REL 1.1 78-04-21  870150340110
****************************************************************
* 
*	DRIVER FOR TEST TOOL
* 
*	SDLC DRIVER FOR LINE LOGG 
* 
*	O. HANSSON     77.01.25 
* 
******************************************************************
* 
* 
*	ENTRIES 
* 
* 
	ENTRY	DCS1ON	POWER ON RECOVERY 
	ENTRY	DWS101	CONTROL DWT1
	ENTRY	DWS102	INPUT DWT1
	ENTRY	IHLGI1	RECEIVER 1
	ENTRY	IHLGI2	RECEIVER 2
* 
* 
*	EXTERNAL REFERENCES 
* 
* 
	EXTRN	DWTECB	ECBADDRESS
	EXTRN	TENDIO	END OF EVENT
	EXTRN	TDISP	DISPATCHER 
	EXTRN	DISIOE 
	EXTRN	SAVE8	SAVE 8 REGS ON A15 STACK 
	EXTRN	SETIME	SET TIMER 
* 
	EXTRN	DWTST	DWT STATUS 
	EXTRN	DWTOR	DWT ORDER
	EJECT
* 
*	DEVICE ADRESSES 
* 
* 
LCAIN1	EQU	/02
LCAIN2	EQU	/22
* 
* 
* 
* 
*	RELATIVE ECB EQUATES
* 
* 
ECBBA	EQU	2 
ECBRL	EQU	4 
ECBEL	EQU	6 
ECBRC	EQU	8 
ECBCW	EQU	/A
	EJECT
* 
* 
*	INSTRUCTION EQUATES 
* 
* 
CINRTS	EQU	/1	NO REQUEST TO SEND
CIT4WP	EQU	/2	TRANSMIT 4-WIRE PC
CIT2WP	EQU	/3	TRANSMIT 2-WIRE PC
CIT4WM	EQU	/A	TRANSMIT 4-WIRE MUX 
CIT2WM	EQU	/B	TRANSMIT 2-WIRE MUX 
CIIDLE	EQU	/4	TRANSMIT IDLE '1' 
* 
* 
*	CIO START IN COMMANDS 
* 
* 
CICMO	EQU	/2	CONNECT MODEM
CIDISC	EQU	/1	DISCONNECT MODEM
CIWAIC	EQU	/3	WAIT FOR CALL 
CIREPC	EQU	/5	RECEIVE ON PC 
CIAREP	EQU	/4	RECEIVE ALARM ON PC 
CIREMX	EQU	/B	RECEIVE ON MUX
CIAREM	EQU	/E	RECEIVE ALARM ON MUX
* 
* 
* 
*	DEVICE WORK AREA EQUATES
* 
* 
DWTSAV	EQU	/20	REGISTER SAVE AREA 
DWTA4	EQU	DWTSAV+6	A4 SAVE AREA 
DWTA5	EQU	DWTSAV+8	A5,SAVE AREA 
STB	EQU	/1E	RELATIVE STACK BASE 
	EJECT
* 
* 
*	WORK AREAS
* 
* 
BFULL	DATA	0
PBUFIN	DATA	BSTART
PBUFUT	DATA	BSTART
BSTART	EQU	*
	RES	3000 
BEND	EQU	*-2
	RES	15 
STBI	RES	1	INPUT STACK
	RES	15 
STBC	RES	1	CONTROL STACK
	EJECT
* 
* 
*DRIVER ACTIVATION* 
* 
*INPUT REQUEST
* 
* 
DRLGIA	DATA	LGINAC	DWT REFERENCE
* 
* 
LGINAC	SUK	A7,1 
	RF(Z)	ENDR	ORDER 01: READ GENERAL
LIA100	ABL	DISIOE	ILLEGAL ORDER 
* 
	EJECT
* 
* 
* END READ REQUEST? 
* 
* 
ENDR	EQU	*
	INH
	LDKL	A5,STBI 
	LDKL	A6,DWS102 
	LD	A8,DWTECB,A6
	LD	A1,PBUFUT 
ENDR10	CW	A1,PBUFIN 
	RF(E)	ENDR20	NO NEW CHARACTEIN BUFFER
	ADK	A1,2 
	CWK	A1,BEND
	RF(NE)	ENDR15	NOT END OF BUFFER
	LDKL	A1,BSTART 
ENDR15	EQU	*
	LDR*	A2,A1 
	ANKL	A2,/FF00
	RF(NZ)	ENDR30	PCOUNTER OR COMMENT
	LD	A2,BFULL
	SUK	A2,1 
	RF(Z)	ENDR50	BUFFER FULL 
	EJECT
* 
* 
*ORDINARY CHARACTER 
* 
	ST	A1,PBUFUT 
	LDR*	A2,A1	FETCH CHARACTER 
	CF	A5,STORA	STORE IN REQUEST BUFFER
	SUK	A2,/FF 
	RF(E)	ENDR17	COMPLETE REQUEST ON MARK HOLD 
	LD	A2,ECBEL,A8 
	CW	A2,ECBRL,A8 
	RB(NE)	ENDR10	NOT END OF REQUESTED LINE
ENDR17	LDK	A1,0 
ENDEND	CF	A15,TENDIO
	ABL	TDISP
* 
* NO ENDING OF REQUEST
* 
ENDR20	EQU	*
	CF	A15,SETIME
	DATA	ENDR,5
	CM	BFULL 
	ABL	TDISP
	EJECT
* 
* 
ENDR30	EQU	*
	LD	A3,ECBEL,A8 
	RB(NZ)	ENDR17	COMPLETE PREVIOUS REQUEST
	ST	A1,PBUFUT	POLL/COMMENT
	LDR*	A2,A1 
* 
* COMMENT 
* 
ENDR40	EQU	*
	CF	A5,STORA
	LDKL	A1,/2000	RETURN CODE
	RB	ENDEND
* 
* BUFFER FULL 
ENDR50	EQU	*
	LD	A3,ECBEL,A8 
	RB(NZ)	ENDR17
	IM	BFULL 
	LDKL	A2,/240 
	RB	ENDR40
	EJECT
* 
* 
* STORE CHATACTER IN A2 IN REQUEST BUFFER 
* 
* 
STORA	LD	A3,ECBBA,A8
	AD	A3,ECBEL,A8 
	SCR	A2,A3
	IM	ECBEL,A8
	RTN	A5 
	EJECT
* 
* 
*	CONTROL COMMANDS
* 
* 
DRLGOA	DATA	LGOPAC	DWT REFERENCE
* 
* 
LGOPAC	EQU	*
	LDKL	A5,STBC 
	LD	A8,DWTECB,A6
	LD	A7,ECBCW,A8 
	ANK	A7,/F
	LDR	A1,A7
	SUK	A1,1 
	RF(Z)	OPEN	OPEN RECEIVERS
	SUK	A1,1 
	RF(Z)	CLOSE	CLOSE RECEIVERS
	SUK	A1,1 
	RF(Z)	RESET	RESET INPUT BUFFER 
	SUK	A1,1 
	RF(Z)	DEFTCU	DEFINE TCU TO BE LOGGED 
	RB	LIA100	ILLEGAL ORDER
	EJECT
CLOSE	LDKL	A5,STBI
	CF	A5,DISCON 
	LDKL	A1,BSTART 
	ST	A1,PBUFIN 
	ST	A1,PBUFUT 
	LDKL	A2,/242 
	CF	A5,STOR8
	RF	RESET0
* 
* 
*	DEFINE TCU TO BE LOGGED 
* 
* 
DEFTCU	EQU	*
	LD	A1,ECBBA,A8 
	LDR	A2,A1
	ANK	A1,/FF 
	ST	A1,TCUADR 
	SRL	A2,8 
	ST	A2,PSUP 
	RF	RESET1
	EJECT
* 
* 
*	OPEN RECEIVER 
* 
* 
OPEN	EQU	*
	LDKL	A5,STBC 
	CM	RRX 
	CF	A5,DISCON	HALT COMMUNICATION
	CF	A5,CONMOD	CONNECT MODEM 
	LDKL	A1,BSTART 
	ST	A1,PBUFIN	RESET BUFFER
	ST	A1,PBUFUT 
OP250	LDK	A1,0
	CF	A15,TENDIO
	LDKL	A2,REC200	PRELOAD STACK 
	ST	A2,STB2 
	LDKL	A2,STB2-4 
	ST	A2,LCA25
	LDK	A1,5 
	CIO	A1,1,LCAIN2
	IM	SSTX2 
	ABL	REC100	OPEN REC100ER 
	EJECT
* 
* 
*	DISCONNECT MODEM
* 
* 
DISCON	EQU	*
	LDK	A1,0 
	CIO	A1,0,LCAIN1
	CIO	A1,0,LCAIN2
	IM	SSTX1 
	IM	SSTX2 
	CF	A5,READ1
	CF	A5,READ2
	LDK	A1,CIDISC
	CIO	A1,1,LCAIN1
	RF(NA)	DISC10
	CIO	A1,1,LCAIN2
	RF(NA)	DISC10
	RF	CONM10
DISC10	RTN	A5 
* 
* 
*	CONNECT MODEM 
* 
* 
CONMOD	EQU	*
	LDK	A2,1 
	LDK	A1,CICMO 
	CIO	A1,1,LCAIN1
	RB(NA)	DISC10
	CIO	A1,1,LCAIN2
	RB(NA)	DISC10
CONM10	EQU	*
	IM	SSTX1 
	IM	SSTX2 
	CF	A5,READ1
	CF	A5,READ2
	RTN	A5 
	EJECT
* 
* 
*RESET BUFFER 
* 
* 
RESET	EQU	* 
	LDKL	A1,BSTART 
	ST	A1,PBUFIN 
	ST	A1,PBUFUT 
RESET0	EQU	*
	LDKL	A2,/241	COMMENT: BUFFER RESET 
	CF	A5,STOR8
	LDK	A1,/0
	ST	A1,BFULL	RESET,BFULL
RESET1	EQU	*
	LDK	A1,0 
	CF	A15,TENDIO
	ABL	TDISP
	EJECT
* 
* 
*	LOGG WORK AREAS 
* 
* 
RRBUF	DATA	0,0	RR SAVE AREA 
RECBL1	DATA	0	LENGTH 1
RECBF1	RES	150	BUFFER 1 
	RES	15	STACK 1 
STB1	DATA	REC100
RECBL2	DATA	0	LENGTH 2
RECBF2	RES	150	BUFFER 2 
	RES	15	STACK 2 
STB2	DATA	REC200
RRX	DATA	0	RR,P SWITCH
TCUADR	DATA	0	TCU BEEING LOGGED 
PSUP	DATA	0	POLL SUPRESSION SWITCH
SSTX1	DATA	0
SSTX2	DATA	0
	EJECT
* 
* 
*	RECEIVER 1
* 
* 
REC100	EQU	*
	LDKL	A5,STB1 
	CM	RRX 
REC110	EQU	*
	CM	SSTX1 
	CF	A5,STINP1	START INPUT 
	LD	A1,RRX
	RF(Z)	REC120	PREVIOUS NOT RR 
	CM	RRX 
	CF	A5,STORC
	LD	A1,RRBUF	GET LAST RR
	CF	A5,STOR16	STORE 16 BITS 
	LD	A1,RRBUF+2
	CF	A5,STOR16	STORE CHLC STATUS 
REC120	EQU	*
	LD	A1,RECBF1 
	ANK	A1,/1F 
	SUK	A1,/11	RR ?
	RF(NZ)	REC130	NO 
* 
*	RR RECEIVED 
* 
	LD	A1,RECBF1 
	ST	A1,RRBUF	SAVE RR
	LD	A1,RECBF1+2 
	ST	A1,RRBUF+2	STORE CHLC STATUS
	IM	RRX 
	RB	REC110
* 
*	RR NOT RECEIVED 
* 
REC130	EQU	*
	CM	RRX 
	CF	A5,STORC
	LD	A3,RECBL1	GET LENGTH
	LDKL	A4,RECBF1 
REC140	EQU	*
	LCR	A2,A4
	ANK	A2,/FF 
	CF	A5,STOR8	STORE 1 CHARACTER
	ADK	A4,1 
	SUK	A3,1 
	RB(NZ)	REC140
* 
*	END OF BUFFER 
* 
	RB	REC110
	EJECT
* 
* 
*	RECEIVER 2
* 
* 
REC200	EQU	*
	LDKL	A5,STB2 
REC210	EQU	*
	CM	SSTX2 
	CF	A5,STINP2	START INPUT 
	LD	A1,RRX
	RF(NZ)	REC230	NO IDLE POLL 
REC215	EQU	*
	CF	A5,STORT
	LD	A3,RECBL2	GET LENGT 
	LDKL	A4,RECBF2 
REC220	EQU	*
	LCR	A2,A4
	ANK	A2,/FF 
	CF	A5,STOR8	STORE ONE CHARACTER
	ADK	A4,1 
	SUK	A3,1 
	RB(NZ)	REC220	NOT END
	RB	REC210
REC230	EQU	*
	CM	RRX 
	LD	A1,PSUP 
	RF(Z)	REC240	NO SUPRESSION 
	LD	A1,RECBF2 
	ANKL	A1,/FF1F
	LD	A2,RRBUF
	ANKL	A2,/FF1F
	CWR	A1,A2
	RB(E)	REC210	SUPRESS 
* 
* 
*	RR NOT RECEIVED 
* 
* 
REC240	EQU	*
	CF	A5,STORC
	LD	A1,RRBUF	GET LAST RR
	CF	A5,STOR16	STORE IT
	LD	A1,RRBUF+2
	CF	A5,STOR16 
	RB	REC215
	EJECT
* 
* 
*	STORE 'C:' IN LOGG BUFFER 
* 
* 
STORC	EQU	* 
	LDKL	A2,/200 
STO10	EQU	* 
	CF	A5,STOR8	STORE COMMENT
	RTN	A5 
* 
* 
*	STORE 'T:' IN LOGG BUFFER 
* 
* 
STORT	EQU	* 
	LDKL	A2,/201 
	RB	STO10 
	EJECT
* 
* 
*STORE ONE CHARACTER
* 
* 
STOR8	EQU	* 
	STR	A1,A15 
	STR	A2,A15 
	LD	A1,BFULL
	RF(NZ)	STOR20
	LD	A1,PBUFIN 
	ADK	A1,2 
	CWK	A1,BEND
	RF(NE)	STOR10	NOT END OF RING BUFFER 
	LDKL	A1,BSTART 
STOR10	CW	A1,PBUFUT 
	RF(E)	STOR30	BUFFER FULL 
STOR15	STR	A2,A1	STORE CHAR.
	ST	A1,PBUFIN 
STOR20	LDR*	A2,A15
	LDR*	A1,A15
	RTN	A5 
* 
*BUFFER FULL
* 
STOR30	EQU	*
	IM	BFULL 
	RB	STOR20
	EJECT
* 
* 
*	STORE 16 BITS OF A1 
* 
* 
STOR16	EQU	*
	LDR	A2,A1
	SRL	A2,8 
	CF	A5,STOR8
	LDR	A2,A1
	ANK	A2,/FF 
	CF	A5,STOR8
	RTN	A5 
	EJECT
* 
* 
*	START RECEIVER 1
* 
* 
STINP1	EQU	*
	LDK	A1,5 
	CIO	A1,1,LCAIN1	START INPUT PC 
	CM	RECBL1	RESET LENGTH 
	CF	A5,READ1	READ A FRAME 
	LD	A1,TCUADR 
	RF(Z)	STINP3 
	LC	A1,RECBF1 
	ANK	A1,/FF 
	CW	A1,TCUADR 
	RB(NE)	STINP1	TC NOT SPECIFIED,DISCARD 
	RTN	A5 
* 
* 
*	START RECEIVER 2
* 
* 
STINP2	EQU	*
	LDK	A1,5 
	CIO	A1,1,LCAIN2	START INPUT
	CM	RECBL2	RESET LENGTH 
	CF	A5,READ2	READ A FRAME 
	LD	A1,TCUADR 
	RF(Z)	STINP3 
	LC	A1,RECBF2 
	ANK	A1,/FF 
	CW	A1,TCUADR 
	RB(NE)	STINP2	TC NOT SPECIFIED,DISCARD 
STINP3	EQU	*
	RTN	A5 
	EJECT
* 
* 
*	READ ON CHLC 1
* 
* 
READ1	EQU	* 
	ST	A5,LCA15
	ST	A6,LCA16
	ABL	TDISP
* 
* 
*	READ ON CHLC 2
* 
* 
READ2	EQU	* 
	ST	A5,LCA25
	ST	A6,LCA26
	ABL	TDISP
	EJECT
* 
* 
*	RESTORE A5,A6 
* 
* 
LDREG1	EQU	*
	LDKL	A5,STB1-4 
LCA15	EQU	*-2 
	LDKL	A6,0
LCA16	EQU	*-2 
	ADKL	A15,4 
	ABR*	A15 
* 
* 
*	RESTORE A5,A6 
* 
* 
LDREG2	EQU	*
	LDKL	A5,STB2-4 
LCA25	EQU	*-2 
	LDKL	A6,0
LCA26	EQU	*-2 
	ADKL	A15,4 
	ABR*	A15 
	EJECT
* 
* 
*	INTERRUPT HANDLER 1 
* 
* 
IHLGI1	EQU	*
	CF	A15,SAVE8 
	CF	A15,LDREG1
	INR	A2,0,LCAIN1
	RF(NA)	IHLG10	NOT ACCEPTED 
	LD	A4,RECBL1	GET INDEX 
	ST	A2,RECBF1,A4	STORE 16 BITS
	ADK	A4,2 
	ST	A4,RECBL1	SAVE INDEX
	IM	SSTX1 
	ABL	READ1
IHLG10	EQU	*
	SST	A1,LCAIN1
	RF(NA)	IHLG12
	LD	A2,SSTX1
	RF(NZ)	IHLG11	SST WANTED 
	ANK	A1,1 
	RF(NZ)	IHLG13	MODEM NOT READY
	LDK	A1,5 
	CIO	A1,1,LCAIN1	START INPUT
	RB	READ1 
IHLG11	EQU	*
	CM	SSTX1 
	LD	A4,RECBL1 
	ST	A1,RECBF1,A4	STORE STATUS 
	ADK	A4,2 
	ST	A4,RECBL1 
IHLG12	EQU	*
	RTN	A5 
* 
*	MODEM INOPERABLE
* 
IHLG13	EQU	*
	LDKL	A2,/243 
IHLG14	EQU	*
	CF	A5,STOR8
	ABL	TDISP
	EJECT
* 
* 
*	INTERRUPT HANDLER 2 
* 
* 
IHLGI2	EQU	*
	CF	A15,SAVE8 
	CF	A15,LDREG2
	INR	A2,0,LCAIN2
	RF(NA)	IHLG20	NOT ACCEPTED 
	LD	A4,RECBL2	GET INDEX 
	ST	A2,RECBF2,A4	STORE 16 BITS
	ADK	A4,2 
	ST	A4,RECBL2	SAVE INDEX
	IM	SSTX2 
	ABL	READ2
IHLG20	EQU	*
	SST	A1,LCAIN2
	RB(NA)	IHLG12
	LD	A2,SSTX2
	RF(NZ)	IHLG21	SST WANTED 
	ANK	A1,1 
	RF(NZ)	IHLG22	MODEM NOT READY
	LDK	A1,5 
	CIO	A1,1,LCAIN2	START INPUT
	RB	READ2 
IHLG21	EQU	*
	CM	SSTX2 
	LD	A4,RECBL2 
	ST	A1,RECBF2,A4	STORE STATUS 
	ADK	A4,2 
	ST	A4,RECBL2 
	RTN	A5 
* 
*	MODEM INOPERABLE
* 
IHLG22	EQU	*
	LDKL	A2,/244 
	RB	IHLG14
	EJECT
* 
* 
* POWER ON RECOVERY 
* 
* 
DCS1ON	EQU	*
	LDK	A1,0 
	ST	A1,BFULL
	LDKL	A1,BSTART 
	ST	A1,PBUFIN 
	ST	A1,PBUFUT 
	CM	RRX 
	CM	BFULL 
	RTN	A15
* 
* 
* 
* 
*	LOG INPUT CHLC 2
* 
* 
DWLGI2	DATA	/22	DEVICE ADDRESS
	DATA	/8000	STATUS
	DATA	0	ECB ADDRESS 
	DATA	0	ORDER 
	DATA	DRLGIA	DRIVER ADDRESS BLOCK 
	DATA	0	TASK TABLE ADDRESS
	DATA	0	WAIT/ACTIVATE INDICATOR 
	DATA	0	TASK QUEUE FOR THIS DEVICE
	RES	8	SUBROUTINE STACK 
	RES	5	SAVE AREA FOR A1 - A5
	DATA	DWLGI2	THIS DWT ADDRESS FOR A6
	DATA	DWS102	CORRESPONDING INPUT DWT IN A7
	RES	1	SAVE AREA FOR A8 
	DATA	0,0,0,0	WORK AREA 
* 
	EJECT
* 
* 
*	LOG INPUT CHLC 1
* 
* 
DWS102	DATA	/02	DEVICE ADDRESS
	DATA	/8000	STATUS
	DATA	0	ECB ADDRESS 
	DATA	0	ORDER 
	DATA	DRLGIA	DRIVER ADDRESS BLOCK 
	DATA	0	TASK TABLE ADDRESS
	DATA	0	WAIT/ACTIVATE INDICATOR 
	DATA	0	TASK QUEUE FOR THIS DEVICE
	RES	8	SUBROUTINE STACK 
	RES	5	SAVE AREA FOR A1 - A5
	DATA	DWS102	CORRESPONDING INPUT DWT IN A7
	DATA	DWLGI2	THIS DWT ADDRESS FOR A6
	RES	1	SAVE AREA FOR A8 
	DATA	0,0,0,0	WORK AREA 
* 
	EJECT
* 
* 
*	LOG CONTROL IO
* 
* 
DWS101	DATA	/02	DEVICE ADDRESS
	DATA	/8000	STATUS
	DATA	0	ECB ADDRESS 
	DATA	0	ORDER 
	DATA	DRLGOA	DRIVER ADDRESS BLOCK 
	DATA	0	TASK TABLE ADDRESS
	DATA	0	WAIT/ACTIVATE INDICATOR 
	DATA	0	TASK QUEUE FOR THIS DEVICE
	RES	8	SUBROUTINE STACK 
	RES	3	SAVE AREA FOR A1 - A5
	DATA	DWS102	INPUT DWT
	RES	1	SAVE A5
	DATA	DWS101	THIS DWT ADDRESS FOR A6
	DATA	DWLGI2	CORRESPONDING DWT IN A7
	RES	1	SAVE AREA FOR A8 
	DATA	0,0,0,0	WORK AREA 
* 
* 
* 
* 
	END

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