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DataMuseum.dkPresents historical artifacts from the history of: Philips Data Systems |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about Philips Data Systems Excavated with: AutoArchaeologist - Free & Open Source Software. |
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Length: 1460 (0x5b4)
Notes: pts_type(SC)
Names: »DW0701.SC«
└─⟦110b7ed5e⟧ Bits:30009664 Philips computer tape "600106"
└─⟦this⟧ »TOSSWORK/DW0701.SC«
IDENT DW0701 REL 9.2 79-11-16 870105040920 * * DEVICE WORK TABLE FOR DATA-COMMUNICATION DEVICE 1 * ENTRY DW0701 TABLE ENTRY EXTRN DC07AD POINTER TO ADDRESS-BLOCK * MMUPAG EQU 0 * DW0701 EQU * TABLE ENTRY DATA 0 CHANNEL PARAMETER DATA /8000 STATUS./8000 MEANS DEVICE READY DATA 0 ECB-ADDRESS DATA DWTEND-DW0701 RIGHT BYTE=ORDER DATA DC07AD POINTER TO ADDRESS-BLOCK DATA 'DC' TTAB-ADDRESS DATA 0 WAIT/ACTIVATE INDICATOR DATA 0 TERMINAL QUEUE * IFT MMUPAG=1 DATA 0 USER ECB ADDRESS DATA DC:ECB MMU ECB ADDRESS XIF * DATA 0 TIMER POINTER DATA 0 WRITE QUEUE DATA 0 BUFFER QUEUE ANCHOR DATA 0 TIMER FOR BUFFER QUEUE DATA 0 REQUEST TIMER VALUE * IFT MMUPAG=1 DC:ECB EQU * MMU ECB DATA 0,0,0,0,0,0 XIF * DWTEND EQU * END
0x000…036 (0, 0, 400) Head {h00=0x0032, h01=0x0050, text=» IDENT DW0701 REL 9.2 79-11-16 870105040920 «, t00=0x0000, t01=0x0004}
0x036…03e Head {h00=0x0004, h01=0x0050, t00=0x0000, t01=0x003a}
0x03e…048 Head {h00=0x0006, h01=0x0050, text=»* «, t00=0x0000, t01=0x0042}
0x048…086 Head {h00=0x003a, h01=0x0050, text=»* DEVICE WORK TABLE FOR DATA-COMMUNICATION DEVICE 1 «, t00=0x0000, t01=0x004c}
0x086…090 Head {h00=0x0006, h01=0x0050, text=»* «, t00=0x0000, t01=0x008a}
0x090…0b2 Head {h00=0x001e, h01=0x0050, text=» ENTRY DW0701 TABLE ENTRY «, t00=0x0000, t01=0x0094}
0x0b2…0e0 Head {h00=0x002a, h01=0x0050, text=» EXTRN DC07AD POINTER TO ADDRESS-BLOCK«, t00=0x0000, t01=0x00b6}
0x0e0…0ea Head {h00=0x0006, h01=0x0050, text=»* «, t00=0x0000, t01=0x00e4}
0x0ea…0fe Head {h00=0x0010, h01=0x0050, text=»MMUPAG EQU 0«, t00=0x0000, t01=0x00ee}
0x0fe…108 Head {h00=0x0006, h01=0x0050, text=»* «, t00=0x0000, t01=0x0102}
0x108…128 Head {h00=0x001c, h01=0x0050, text=»DW0701 EQU * TABLE ENTRY«, t00=0x0000, t01=0x010c}
0x128…14a Head {h00=0x001e, h01=0x0050, text=» DATA 0 CHANNEL PARAMETER «, t00=0x0000, t01=0x012c}
0x14a…17e Head {h00=0x0030, h01=0x0050, text=» DATA /8000 STATUS./8000 MEANS DEVICE READY «, t00=0x0000, t01=0x014e}
0x17e…19a Head {h00=0x0018, h01=0x0050, text=» DATA 0 ECB-ADDRESS «, t00=0x0000, t01=0x0182}
0x19a…1b6 Head {h00=0x0018, h01=0x0050, text=» DATA DWTEND-DW0701 «, t00=0x0001, t01=0x000e}
0x1b6…1d2 Head {h00=0x0018, h01=0x0050, text=» RIGHT BYTE=ORDER «, t00=0x0001, t01=0x002a}
0x1d2…200 Head {h00=0x002a, h01=0x0050, text=» DATA DC07AD POINTER TO ADDRESS-BLOCK «, t00=0x0001, t01=0x0046}
0x200…220 Head {h00=0x001c, h01=0x0050, text=» DATA 'DC' TTAB-ADDRESS «, t00=0x0001, t01=0x0074}
0x220…248 Head {h00=0x0024, h01=0x0050, text=» DATA 0 WAIT/ACTIVATE INDICATOR «, t00=0x0001, t01=0x0094}
0x248…266 Head {h00=0x001a, h01=0x0050, text=» DATA 0 TERMINAL QUEUE«, t00=0x0001, t01=0x00bc}
0x266…270 Head {h00=0x0006, h01=0x0050, text=»* «, t00=0x0001, t01=0x00da}
0x270…286 Head {h00=0x0012, h01=0x0050, text=» IFT MMUPAG=1 «, t00=0x0001, t01=0x00e4}
0x286…2a6 Head {h00=0x001c, h01=0x0050, text=» DATA 0 USER ECB ADDRESS«, t00=0x0001, t01=0x00fa}
0x2a6…2ca Head {h00=0x0020, h01=0x0050, text=» DATA DC:ECB MMU ECB ADDRESS«, t00=0x0001, t01=0x011a}
0x2ca…2d6 Head {h00=0x0008, h01=0x0050, text=» XIF«, t00=0x0001, t01=0x013e}
0x2d6…2e0 Head {h00=0x0006, h01=0x0050, text=»* «, t00=0x0001, t01=0x014a}
0x2e0…2fe Head {h00=0x001a, h01=0x0050, text=» DATA 0 TIMER POINTER «, t00=0x0001, t01=0x0154}
0x2fe…31a Head {h00=0x0018, h01=0x0050, text=» DATA 0 WRITE QUEUE «, t00=0x0001, t01=0x0172}
0x31a…33e Head {h00=0x0020, h01=0x0050, text=» DATA 0 BUFFER QUEUE ANCHOR «, t00=0x0001, t01=0x018e}
0x33e…364 Head {h00=0x0022, h01=0x0050, text=» DATA 0 TIMER FOR BUFFER QUEUE«, t00=0x0002, t01=0x0022}
0x364…388 Head {h00=0x0020, h01=0x0050, text=» DATA 0 REQUEST TIMER VALUE «, t00=0x0002, t01=0x0048}
0x388…392 Head {h00=0x0006, h01=0x0050, text=»* «, t00=0x0002, t01=0x006c}
0x392…3a8 Head {h00=0x0012, h01=0x0050, text=» IFT MMUPAG=1 «, t00=0x0002, t01=0x0076}
0x3a8…3c4 Head {h00=0x0018, h01=0x0050, text=»DC:ECB EQU * MMU ECB«, t00=0x0002, t01=0x008c}
0x3c4…3de Head {h00=0x0016, h01=0x0050, text=» DATA 0,0,0,0,0,0 «, t00=0x0002, t01=0x00a8}
0x3de…3ea Head {h00=0x0008, h01=0x0050, text=» XIF«, t00=0x0002, t01=0x00c2}
0x3ea…3f4 Head {h00=0x0006, h01=0x0050, text=»* «, t00=0x0002, t01=0x00ce}
0x3f4…408 Head {h00=0x0010, h01=0x0050, text=»DWTEND EQU *«, t00=0x0002, t01=0x00d8}
0x408…414 Head {h00=0x0008, h01=0x0050, text=» END«, t00=0x0002, t01=0x00ec}
0x414…418 Head {h00=0x4004, h01=0x0000}
0x418…41c 00 02 00 f8 ┆ ┆
0x41c…424 (3, 1, 8) 20 04 00 00 00 03 00 04 ┆ ┆
0x424…474 (4, 0, 400) 20 41 4c 52 45 41 44 59 20 53 45 54 00 1b 01 7c 00 10 00 50 5c 4c 44 4b 5c 41 31 2c 2f 46 45 20 00 1c 00 14 00 26 00 50 5c 41 4e 53 5c 41 31 2c 44 57 54 53 54 2c 41 36 5c 53 45 54 20 44 45 56 49 43 45 20 52 45 41 44 59 20 00 1c 00 28 00 28 ┆ ALREADY SET | P LDK A1,/FE & P ANS A1,DWTST,A6 SET DEVICE READY ( (┆
0x474…4c4 00 50 5c 4c 44 4b 4c 5c 41 32 2c 44 43 53 54 51 5c 47 45 54 20 54 48 52 55 20 51 55 45 55 45 20 41 4e 43 48 4f 52 00 1c 00 52 00 26 00 50 5c 43 46 5c 41 31 35 2c 49 4e 53 57 51 31 5c 49 4e 53 45 52 54 20 44 57 54 20 49 4e 20 51 55 45 55 45 ┆ P LDKL A2,DCSTQ GET THRU QUEUE ANCHOR R & P CF A15,INSWQ1 INSERT DWT IN QUEUE┆
0x4c4…514 00 1c 00 7e 00 0e 00 50 5c 4c 44 4b 5c 41 32 2c 36 20 00 1c 00 a8 00 22 00 50 5c 53 54 5c 41 32 2c 44 57 54 4f 52 2c 41 36 5c 52 45 50 4c 41 43 45 20 4f 52 44 45 52 20 00 1c 00 ba 00 10 00 50 5c 43 4d 5c 45 43 42 52 4c 2c 41 38 00 1c 00 e0 ┆ ~ P LDK A2,6 " P ST A2,DWTOR,A6 REPLACE ORDER P CM ECBRL,A8 ┆
0x514…564 00 1a 00 50 5c 41 42 4c 5c 44 43 52 54 4e 5c 44 49 53 50 41 54 43 48 45 52 20 00 1c 00 f4 00 10 00 50 44 43 53 53 54 31 5c 45 51 55 5c 2a 00 1c 01 12 00 14 00 50 5c 4c 44 5c 41 31 2c 45 43 42 43 57 2c 41 38 20 00 1c 01 26 00 24 00 50 5c 41 ┆ P ABL DCRTN DISPATCHER PDCSST1 EQU * P LD A1,ECBCW,A8 & $ P A┆
0x564…5b4 4e 4b 4c 5c 41 31 2c 4e 42 49 54 30 5c 49 47 4e 4f 52 45 20 53 54 41 54 55 53 20 42 49 54 00 1c 01 3e 00 12 00 50 5c 4c 44 4b 5c 41 33 2c 44 49 44 4c 53 54 00 1c 01 66 00 0e 00 50 5c 41 44 52 5c 41 33 2c 41 36 00 1c 01 7c 00 10 00 50 44 43 ┆NKL A1,NBIT0 IGNORE STATUS BIT > P LDK A3,DIDLST f P ADR A3,A6 | PDC┆