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Length: 112896 (0x1b900)
Types: TextFileVerbose
Names: »rc3503«
└─⟦2c55ea56f⟧ Bits:30001844 SW-save af projekt 1000, Alarm-system
└─⟦093e2ad1c⟧
└─⟦this⟧ »rc3503«
;; rc3503 microprogram, disassembled version
;;
;; this listing is produced by disassembling the original rc3503
;; microprogram listing.
;; during the process of disassembling some information (especially
;; concerning the use of the alu slice) is lost. the disassembled
;; listing specifies the same logical function as the original
;; microprogram, but the way of doing it may differ. as a consequence
;; the binary output from the disassembler may differ from the original
;; binary output, and the original binary output listing should
;; therefore be consulted whenever information about the binary
;; microinstruction word is needed.
;;
;; please note that all constants generated by the disassembler are
;; represented as hexadecimal numbers, whereas the comments in the
;; listing are unchanged and hence may contain numbers in any
;; number representation.
.p
;; rc3503 microprogram description.
;;
;; date 1980.11.11 kneh.
;; listing rcsl 52 - aa 1005
;; source tape rcsl 52 - aa 1006
;; macro source rcsl 52 - aa 1007
;;
;; des35 source rcsl 52 - aa 1008
;; def1 source rcsl 52 - aa 1009
;;
;; slice register layout.
;; w0 save current w0.
;; w1 current level number.
;; w2 save read address (m:ram).
;; w3 ea (effective address)
;; w4 op (operand).
;; w5 current i/o level.
;; w6 enable/disable flag; =4 if enable else =5.
;; w7 scratch register.
;; w8 constant 8.177000
;; w9 constant 8.400
;; w10 constant 8.2
;; w11 module select.
;; w12 constant 8.37
;; w13 current level shift logical left 3 positions.
;; w14 memory address to mem read/write routines.
;; w15 data to/from mem read/write routines.
.p!0002 m3503
;; rc3503 microprogram description.
;; the microprogram listing has the following format:
;;
;; microaddress word1 word2 word3 word4
;; xxxx xxxx xxxx xxxx xxxx
;; x means hex ciffer.
;; xxxx --> bit 0-15
;;
;; word1 :
;;--------
;; bit 0-3 next i0-3 next microinstruction.
;; 0 jz jump zero.
;; 1 cjs cond jsb pl.
;; 2 jmap jump map.
;; 3 cjp cond jump pl.
;; 4 push push/cond ld cntr
;; 5 jsrp cond jsb r/pl.
;; 6 cjv cond jump vector.
;; 7 jrp cond jump r/pl.
;; 8 rfct repeat loop,cntr<>0
;; 9 rpct repeat pl,cntr<>0.
;; a crtn cond rtn.
;; b cjpp cond jump pl&pop.
;; c ldct ld cntr&continue.
;; d loop test end loop
;; e cont continue.
;; f twb three-way branch.
;;
;; bit 4-7 cond 0-3 condition select.
;; bit 8-11 asel 0-3 a-slice register select.
;; bit 12-15 bsel 0-3 b-slice register select.
.p!0003 m3503
;; rc3503 microprogram description.
;; word2 :
;; -------
;; bit 0-2 slice 0-2 alu destination control.
;; bit 3-6 alu func 0-2,c alu function and carry.
;; bit 7-9 alu op 0-2 alu source operand.
;; bit10 enable hold
;; bit 11-12 cload 0-1 carry load control field
;; bit 13-15 wreg 0-2 w-register ram address control.
;;
;; word 3 :
;; --------
;; bit 0-3 dummy
;; bit 4 escape/polx
;; bit5 -,sup itr.
;; bit 6 test ack.
;; bit 7 -,byte en/nxt mar 0.
;; bit 8 -,update alu status.
;; bit 9 -,update carry.
;; bit 10 -,set base
;; bit 11 -,syn itr/-,sign extend.
;; bit12 -,reg load.
;; bit 13 -,ccen
;; bit14 -,forward read.
;; bit 15 -,inta.
.p!0004 m3503
;; rc3503 microprogram description.
;;
;; word 4 :
;; -------
;; bit 0-2 bus source control field.
;; bit 3-5 bus destination field.
;; bit 6-15 nxt mar 1-10.
.p!0005 m3503
;; log: rcm35 03b -- bj --
;;
;; date 1980-11-11
;;
.w0=0
.w1=1
.w2=2
.w3=3
.w4=4
.w5=5
.w6=6
.w7=7
.w8=8
.w9=9
.w10=0a
.w11=0b
.w12=0c
.w13=0d
.w14=0e
.w15=0f
nop=0
aucon= 1ff
citr= 40
cpuve= 3b
fi5= 3ff
fi4= 3fe
fi3= 3fd
fi2= 3fc
fi1= 3fb
fi0= 3fa
fia = 3ef ; save of parity error information
fib = 3ee
fic = 3ed
fid = 3ec
fie = 3eb
fif = 3ea
perro= 41
ritr= 0
sitr= 20
timer= 140
waits= 06
wctim= 08
.p!0006 m3503
;; 1980.11.04 kneh.
;; rc3503 microprogram.
;; initialization routine.
;; place the following constants in slice registers:
;; w10:= 2
;; w9:= 400
;; w06:= 4
;; w11:= 1
;; w12:= 37
;; w8:= 1000
;; enable interrupt
init:
w10:=2,, ;
w9:=100,, ;
w11:=1,, ;
w12:=1f,, ;
w8:=200,, ;
led:=4,w6:=4,, ;
ra:=80,w13:=80,, ;
ba:=w1:=,,cjp uptab ;
;; debug initialization routine.
debug:
w0,,cjv 6 map45 ;
dupdat:
w0,,cjp cr dupdat ;
w0,,cjp not c7 debug ;
ccr,w0,, ;
ir:=w0,,cjp fetch ;
;; exec one instruction.
fetcd:
w6 and w11,s,cjp cr fetcd ;
int,w0,,cjp fetca ;
nop
.p!0007 m3503
;; rc3503 microprogram. 1979.10.07 kneh.
;; shift rotate-instructions with ir(7:8)=00.
;; the number of shifts of shifts is specified by ir(12:15).
shiti:
w15:=0f and q,s, ;
;b01:= w(current level).
shlop:
w0,,cjp zro nupdat ;
rc:=w15--,,ldct ;
; q and a13 -----> a17. a17-1 ----> n-counter (am2910).
w7:=zdw,s,cjp not st7 shrop;
,,cjv 0d rleft ;
; if ir11=1 then jump vector "rleft" else continue.
shrop:
w0,,cjv 0d rright ;
nop
nop
nop
;; shift rotate-instructions with ir(7:8) <> 00.
;; the number of shifts is specified by x(12:15).
shitx:
w7:=0f,, ;
w15:=zdx and w7,s,cjp shlop;
; (x) and a07 -----> a17.
nop
.p!0008 m3503
;; rc3503 microprogram.
;; main loop.fetch routine.
yfetch:
w1:=int,,cjp not cr debug ;
ra:=w1,,cjs gint1 ;
xfetca:
c:=rd,w0:=rd,, ;
bf:=0c0,w0,h , ;
bd:=w14:=w0,h r , ;
led:=5,w0,h , ;
ir:=bd,q:=bd,h w s, ;
led:=w6,w2:=,,cjv 3 sparf ;
fetrd:
rm:=w0:=w10+w0,,jmap 0 ;
nop
.p!0009 m3503
;; rc 3503 microprogram
;; jump to address calculation map.
;; ir jump to routine:
;; 78901234
;; 00xxxxxx ir(0:4)<24 format a, x=0 fax0
;; 01xxxxxx ir(0:4)<24 format a, x<>0 faxn
;; 10xxxxxx ir(0:4)<24 format a ,x<>0 faxn
;; 11xxxxxx ir(0:4)<24 format a, x<>0 faxn
;; 00011110 format b,x=0,i=0 bx001
;; 00111110 format b,x=0,i=1 bx0i1
;; 01011110 format b,x<>0,i=0 bxn01
;; 10011110 format b,x<>0,i=0 bxn01
;; 11011110 format b,x<>0,i=0 bxn01
;; 01111110 format b,x<>0,i=1 bxni1
;; 10111110 format b,x<>0,i=1 bxni1
;; 11111110 format b,x<>0,i=1 bxni1
;; 00011111 format c,x=0,i=0 cx001
;; 00111111 format c,x=0,i=1 cx0i1
;; 01011111 format c,x<>0,i=0 cxn01
;; 10011111 format c,x<>0,i=0 cxn01
;; 11011111 format c,x<>0,i=0 cxn01
;; 01111111 format c,x<>0,i=1 cxni1
;; 10111111 format c,x<>0,i=1 cxni1
;; 11111111 format c,x<>0,i=1 cxni1
;; xx011000 read status/word rxc
;; xx111000 read block of bytes/word rbx
;; 00011001 write control/word,x=0 wxcx0
;; 01011001 write control/word,x<>0 wxcxn
;; 10011001 write control/word,x<>0 wxcxn
;; 11011001 write control/word,x<>0 wxcxn
;; xx111001 write block of bytes/word wbx
;; 00x11100 shift/rotate,x=0 shiti
;; 01x11100 shift/rotate,x<>0 shitx
;; 10x11100 shift/rotate,x<>0 shitx
;; 11x11100 shift/rotate,x<>0 shitx
;; xxx11010 interlevel load ild
;; xxx11011 interlevel store ist
;; xxx11101 not used update
;; xxx01110 not used update
.p!0010 m3503
;; rc3503 microprogram.
;; address calculation. format a. x=0.
;; when called:
;; w0=w0(current);
;; q=d(sign extended);
;; return:
;; w3=ea; w4=operand
fax0:
w3:=q,, ;
w4:=q,,jmap not 0 ;
;; address calculation. format a. x<>0.
;; call: w0=w0(current); q=d(displacement sign extended);
;; return: w3=ea; w4=operand;
faxn:
w3:=zdx+q,, ;
bd:=w14:=w3,h r ,cjs ywread;
w4:=w15,,jmap not 0 ;
.p!0011 m3503
;; rc3503 microprogram.
;; address calculation. format c.(ir(0:4))=31. x<>0.i=0.
;; call: w0=w0(current); q=d(displacement sign extended);
;; return: w3=ea; w4=operand;
cxn01:
bd:=w14:=w0,h r ,cjs ywread;
; w15:= a( next word);
w3:=zdx+w15,, ;
; w3:= ea;
bd:=w14:=w3,h r ,cjs ywread;
rm:=w0:=w10+w0,, ;
; w15:= st( xn+a);
w4:=w15,,jmap not 8 ;
;; address calculation. format c. ir(0:4)=31. x<>0. i=1.
;; call: w0=w0(current); q=d(displacement sign extended);
;; return: w3= ea; w4= operand = ea;
cxni1:
bd:=w14:=w0,h r ,cjs ywread;
w3:=zdx+w15,, ;
rm:=w0:=w10+w0,, ;
w4:=w3,,jmap 8 ;
.p!0012 m3503
;; rc3503 microprogram.
;; address calculation. format c. ir(0:4)=31. x=0. i=0.
;; call: w0=w0(current); q=d(displacement sign extended);
;; return: w3=ea; w4=operand= st(ea);
cx001:
bd:=w14:=w0,h r ,cjs ywread;
w3:=w15,, ;
bd:=w14:=w15,h r ,cjs ywread;
rm:=w0:=w10+w0,, ;
w4:=w15,,jmap not 8 ;
;; address calculation .format c. ir(0:4)=31. x=0. i=1.
;; call: w0=w0(current); q=d(displacement sign extended);
;; return: w3=ea; w4=operand;
cx0i1:
bd:=w14:=w0,h r ,cjs ywread;
w3:=w15,, ;
rm:=w0:=w10+w0,, ;
w4:=w15,,jmap not 8 ;
.p!0013 m3503
;; rc3503 microprogram.
;; address calculation. format b. ir(0:4)=30. x<>0. i=0.
;; call: w0=w0(current);
;; return: w3=ea ; w4=operand;
bxn01:
w3:=zdx,, ;
bd:=w14:=w3,h r ,cjs ywread;
w4:=w15,,jmap not 8 ;
;; address calculation. format b. ir(0:4)=30. x<>0. i=1.
;; call: w0=w0(current);
;; return: w3=ea; w4=operand;
bxni1:
w3:=zdx,, ;
w4:=w3,,jmap 8 ;
;; rc3503 microprogram.
;; address calculation. format b. ir(0:4)=30. x=0. i=1.
bx0i1:
w3:=,, ;
w4:=w3,,jmap not 8 ;
;; address calculation. format b. ir(0:4)=30. x=0. i=1.
;; call: w0=w0(current);
;; return: w3=ea; w4=operand.
bx001:
w3:=,, ;
bd:=w14:=,h r ,cjs ywread ;
w4:=w15,,jmap not 8 ;
nop
nop
nop
nop
nop
nop
nop
nop
.p!0014 m3503
;; interlevel store (ist).
;; store the w-register into the working register specified by x
;; from interruption level n. the contents of w remain unchanged.
;; control the status of the interruption system as follows:
;; x(nth level):= w(current level).
;; if code= d then enable:=0.
;; if code= e then enable:=1.
;; if code= s then interrupt(n):=1.
ist:
w7:=zdw,, ;
; b07:= w(current level).
ra:=w3:=w12 and q,, ;
; q and a14 ---> wadd register.
istx:
w14:=rd,, ;
ra:=w14,, ;
zdx:=w7,, ;
; b07 ---> x(nth level).
ra:=w13,,cjv 0d upitr ;
; b15 ---> wadd register (set cur level).
nop
nop
;; interlevel load (ild).
;; load the w-register with the working register specified by x from
;; interruption level n.control the status of the interruption system as
;; follows:
;; w(current level):= x(nth level).
;; if code= d then enable:= 0.
;; if code= e then enable:= 1.
;; if code= s then interrupt(n):=1.
ild:
ra:=w3:=w12 and q,, ;
; q and a14 --> wadd,b16.
ildx:
w14:=rd,, ;
ra:=w14:=w14,, ;
w7:=zdx,, ;
; b02:= (x).
ra:=w13,, ;
; b15 --> wadd.
zdw:=w7,,cjv 0d upitr ;
; b02---> w(current level).
nop
nop
.p!0015 m3503
;; rc3503 microprogram.
;; subroutines.
;; routine to set the interrupt level specified in a16(9:15).
sitrn:
bf:=w14+w8,,200 ;
; a17:= a16+(-, iors0=1,-,iors1=0).
w15:=sitr,, ;
; load set condition in reg 17 (bus 10= 1).
bd:=w15 ior w14,h w ,crtn ;
; set intr. and return.
nop
;; routine to reset the interrupt level specified in a16(9:15).
citrn:
bf:=w14+w8,,200 ;
; a17:= a16 +(-,iors0=1,-,iors1=0).
; modul select + set/clear condition
bd:=w12 and w14,h w ,crtn ;
; clear interrupt and return.
nop
nop
nop
nop
.p!0016 m3503
;; rc3503 microprogram.
;; arithmetic and logical instructions.
;; ldr. load register. format a.
ldr1:
zdw:=w4,,cjp cupdat ;
nop
nop
nop
nop
;; arithmetic and logical instructions.
;; ldr. load register. format b&c.
ldr23:
zdw:=w4,,cjp not i10 cupdat;
w4:=zdx+w10,, ;
zdx:=w4,,cjp cupdat ;
nop
nop
nop
nop
.p!0017 m3503
;; rc3503 microprogram.
;; arithmetic and logical instructions.
;; ldc. load complement. format a.
;; w:= -operand (w4); carry:= alu carry.
ldc1:
zdw:=-w4,s, ;
c:-w4,,cjp nupdat ;
nop
nop
nop
;; arithmetic and logical instructions.
;; ldc. load complement. format b&c.
ldc23:
zdw:=-w4,s, ;
c:-w4,,cjp not i10 nupdat ;
w4:=zdx+w10,, ;
zdx:=w4,,cjp nupdat ;
nop
;; rc3503 microprogram.
;; arithmetic and logical instructions.
;; ldi. load indirect.
ldi1:
bd:=w14:=w4,h r ,cjs ywread;
zdw:=w4:=w15,,cjp nupdat ;
w0,,cjp fetch ;
nop
;; arithmetic and logical instructions.
;; ldi. load indirect. format b&c.
ldi23:
bd:=w14:=w4,h r ,cjs ywread;
zdw:=w15,,cjp not i10 nupdat;
w4:=zdx+w10,, ;
zdx:=w4,,cjp nupdat ;
nop
nop
.p!0018 m3503
;; rc3503 microprogram.
;; arithmetic and logical instructions.
;; str.store register. format a.
;; st(ea):= w.
str1:
w14:=w3,, ;
w15:=zdw,,cjs wwrite ;
w0:=rd,,cjp qupdat ;
nop
nop
;; arithmetic and logical instructions.
;; str. store register. format b&c.
;; if i=0 then st(ea):= w;
;; if i=1 and x<>0 then x:=w;
;; if i=1 and x=0 then st(ea):=w;
;; if n=1 then x:=x+2;
stri0:
w14:=w3,, ;
w15:=zdw,,cjs wwrite ;
w4:=zdx+w10,,cjp not i10 nupdat;
zdx:=w4,,cjp nupdat ;
strix:
w4:=zdw,, ;
zdx:=w4,,cjp not i10 nupdat;
zdx:=w10+w4,,cjp nupdat ;
nop
nop
;; rc3503 microprogram.
;; arithmetic and logical instructions.
;; store indirect. format a.
;; st(operand):= w;
sti1:
w14:=w4,, ;
w15:=zdw,,cjs wwrite ;
w0:=rd,,cjp qupdat ;
nop
nop
;; arithmetic and logical instructions.
;; store indirect. format b&c.
sti23:
w14:=w4,, ;
w15:=zdw,,cjs wwrite ;
w4:=zdx+w10,,cjp not i10 nupdat;
zdx:=w4,,cjp nupdat ;
nop
nop
.p!0019 m3503
;; rc3503 microprogram.
;; arithmetic and logical instructions.
;; xsr. exchange register and store. format a.
;; i=1(x=0); st(ea):=w; w:=ea;
;; i=0(x<>0); a:=st(ea);st(ea):=w;w:=a;
xsrai:
w14:=w3,, ;
w15:=zdw,,cjs wwrite ;
zdw:=w4,,cjp nupdat ;
nop
nop
;; arithmetic and logical instructions.
;; xsr.exchange register and store. format b&c.
;; if i=0 then a:=st(ea);st(ea):=w;w:=a;
;; if i=1 and x=0 then st(ea):=w;w:=ea.
;; if i=1 and x<>0 then a:=x;x:=w;w:=a;
xsrb0:
w14:=w3,, ;
w15:=zdw,,cjs wwrite ;
zdw:=w4,,cjp not i10 nupdat;
w4:=zdx+w10,, ;
zdx:=w4,,cjp nupdat ;
xsrbx:
w3:=zdw,, ;
zdw:=w4,, ;
zdx:=w3,,cjp not i10 nupdat;
zdx:=w10+w3,,cjp nupdat ;
nop
nop
.p!0020 m3503
;; rc3503 microprogram.
;; arithmetic and logical instructions.
;;ldb. load byte. format a.
lba:
1 and w3,s, ;
w4,,cjp zro ldbal ;
w4:=0ff and w4,, ;
zdw:=w4,,cjp nupdat ;
ldbal:
w4:=swp,, ;
w4:=0ff and w4,, ;
zdw:=w4,,cjp nupdat ;
nop
nop
;; ldb. load byte. format b&c.
ldbb:
1 and w3,s, ;
w4,,cjp zro ldbbl ;
ldbl:
w4:=0ff and w4,, ;
zdw:=w4,,cjp not i10 nupdat;
w4:=zdx++,, ;
zdx:=w4,,cjp nupdat ;
ldbbl:
w4:=swp,,cjp ldbl ;
nop
nop
.p!0021 m3503
;; rc3503 microprogram.
;; arithmetic and logical instruction.
;; stb. store byte. format a.
stba:
w14:=w3,, ;
w15:=zdw,,cjs bwrite ;
w0:=rd,,cjp qupdat ;
nop
nop
;; stb. store byte. format b&c.
;; if n=1 then x:=x+1
stbb:
w14:=w3,, ;
w15:=zdw,,cjs bwrite ;
w4:=zdx++,,cjp not i10 nupdat;
zdx:=w4,,cjp nupdat ;
nop
nop
;; rc3503 microprogram.
;; arithmetic and logical instruction.
;; add. add integer word. format a.
;; w:= w+operand.
adda:
w4:=c:zdw+w4,, ;
zdw:=w4,,cjp nupdat ;
nop
nop
;; add. add integer word. format b&c.
;; w:= w+operand;
;; if n=1 then x:=x+2;
addb:
w4:=c:zdw+w4,, ;
logll:
zdw:=w4,,cjp not i10 nupdat;
w4:=zdx+w10,, ;
zdx:=w4,,cjp nupdat ;
nop
nop
.p!0022 m3503
;; rc3503 microprogram.
;; arithmetic and logical instruction.
;; sub. subtract integer word. format a.
;; w:=w-operand; carry:=alu carry.
suba:
w4:=c:zdw-w4,, ;
zdw:=w4,,cjp nupdat ;
nop
nop
;; sub.subtract integer word. format b&c.
;; w:=w-operand;
;; if n=1 then x:=x+2;
subb:
w4:=c:zdw-w4,,cjp logll ;
nop
nop
.p!0023 m3503
;; rc3503 microprogram.
;; arithmetic and logical instruction.
;; and. logic and. format a.
;; w:=w and operand.
anda:
w4:=zdw and w4,, ;
zdw:=w4,,cjp cupdat ;
nop
nop
;; logic and . format b&c.
andb:
w4:=zdw and w4,,cjp cogll ;
nop
nop
;; lor. logic or. format a.
;; w:= w or operand.
lora:
w4:=zdw ior w4,, ;
zdw:=w4,,cjp cupdat ;
nop
nop
;; lor. logic or . format b&c.
lorb:
w4:=zdw ior w4,,cjp cogll ;
nop
nop
;; xor. logical exclusive or. format a.
xora:
w4:=w4 xor zdw,, ;
zdw:=w4,,cjp cupdat ;
nop
nop
;; xor. logical exclusive or. format b&c.
xorb:
w4:=w4 xor zdw,,cjp cogll ;
nop
nop
.p!0024 m3503
;; rc3503 microprogram.
;; arithmetic and logical instructions.
;; lce. load clear enable. format a.
lce1:
zdw:=w4,, ;
lcec:
bf:=w1+w8,, ;
bd:=w12 and w1,h w ,cjp eupdat;
nop
nop
nop
nop
nop
;; lce. load clear enable. format b&c.
lce23:
zdw:=w4,,cjp not i10 lcec ;
w4:=zdx+w10,, ;
zdx:=w4,,cjp lcec ;
nop
nop
;; rc3503 microprogram.
;; arithmetic and logical instructions.
;; rsw. read switches. format a.
rsw1:
ra:=0d4,w0,, ;
rd,w0,, ;
w5:=swp,, ;
ra:=0dc,w0,, ;
w5:=rd+w5,, ;
ra:=w13,, ;
zdw:=w5,,cjp nupdat ;
nop
nop
;; rsw. read switches. format b&c.
rsw23:
w4:=zdx+w10,,cjp not i10 rsw1;
zdx:=w4,,cjp rsw1 ;
nop
nop
.p!0025 m3503
;; rc3503 microprogram.
;; branch and continue instructions.
;; bgw. branch if greater. format b&c.
;; w0:= if w>operand then b else w0+2;
bgwb:
w7:=w4 xor zdw,s, ;
w7,s, ;
zdw+w4,s,cjp not b0 blp10 ;
zdw--w4,s,cjp not b0 carg1 ;
w0,,cjp blp01 ;
blp03:
w10+w0,,cjp acy carg1 ;
blp01:
w14:=w0,,cjp not i10 vupdat;
w15,,cjs xwread ;
rm:=w0:=w15,,cjp nupdat ;
carg1:
w14:=w0,,cjp i10 vupdat ;
w15,,cjs xwread ;
rm:=w0:=w15,,cjp nupdat ;
blp10:
zdw--w4,s,cjp blp03 ;
nop
;; bgw. branch if greater. format a.
bgwa:
w7:=w4 xor zdw,, ;
w7,s, ;
zdw,w4,s,cjp not b0 blp11 ;
zdw--w4,s,cjp not b0 blp15 ;
w0,,cjp vupdat ;
blp02:
w10+w0,,cjp not acy vupdat ;
blp15:
w14:=w0,,cjs xwread ;
rm:=w0:=w15,,cjp nupdat ;
blp11:
zdw--w4,s,cjp blp02 ;
nop
.p!0026 m3503
;; rc3503 microprogram.
;; branch and continue instruction.
;; bew. branch if equal. format a.
;; w0:= if w=operand then b else w0+2
bewa:
zdw-w4,s, ;
blp04:
w10+w0,,cjp not zro vupdat ;
bd:=w14:=w0,h r ,cjs ywread;
rm:=w0:=w15,,cjp nupdat ;
nop
nop
;; bew. branch if equal. format b&c.
bewb:
zdw-w4,s, ;
blp05:
w10+w0,,cjp zro carg1 ;
w14:=w0,,cjp not i10 vupdat;
bd:=w14,h r ,cjs ywread ;
rm:=w0:=w15,,cjp nupdat ;
nop
nop
.p!0027 m3503
;; rc3503 microprogram.
;; branch and continue instructions.
;; branch if less. blw. format a.
;; w0:= if w<operand then b else w0+2.
blwa:
w7:=w4 xor zdw,, ;
w7,s, ;
zdw,w4,s,cjp not b0 blp13 ;
w4--zdw,s,cjp b0 blp15 ;
w0,,cjp vupdat ;
w4,,cjp blp02 ;
blp13:
w4--zdw,s,cjp blp02 ;
nop
;; blw. branch if less. format b&c.
blwb:
w7:=w4 xor zdw,, ;
w7,s, ;
zdw,w4,s,cjp not b0 blp12 ;
w4--zdw,s,cjp b0 carg1 ;
w4,,cjp blp01 ;
blp12:
w4--zdw,s,cjp blp03 ;
nop
nop
;; bgb. branch if greater than byte. format a.
;; a(0:7):=0;
;; a(8:15):= if ea(15)=0 then operand(0:7) else operand(8:15);
bgba:
w0,,cjs boper ;
zdw-w4,s,cjp bgwa ;
nop
nop
;; bgb. branch if greater than byte. format b&c.
bgbb:
w0,,cjs boper ;
zdw-w4,s,cjp bgwb ;
nop
nop
;; subroutine to get the byte operand.
;; call: w4=operand.
;; rtn: w4(8:15):= if ea(15)=0 then w4(0:7) else w4(8:15);
;; w4(0:7):= 0;
boper:
1 and w3,s, ;
w4,,cjp not zro bopbl ;
bopal:
w4:=swp,, ;
bopbl:
w4:=0ff and w4,,crtn ;
nop
nop
.p!0028 m3503
;; rc3503 microprogram.
;; branch and continue instruction.
;; branch if equal to byte. beb. format a.
;; a(0:7):=0;
;; a(8:15):= if ea(15)=0 then operand(0:7) else operand(8:15);
;; w0:= if w=a then b else w0+2.
beba:
w0,,cjs boper ;
zdw-w4,s,cjp blp04 ;
nop
nop
;; beb. branch if equal to byte. format b&c.
bebb:
w0,,cjs boper ;
zdw-w4,s,cjp blp05 ;
nop
nop
;; blb. branch if less than byte. format a.
;; a(0:7):=0;
;; a(8:15):= if ea(15)=0 then operand(0:7) else operand(8:15);
;; w0:= if w<a then belse w0+2;
blba:
w0,,cjs boper ;
w4-zdw,s,cjp blwa ;
nop
nop
;; blb. branch if less than byte. format b&c.
blbb:
w0,,cjs boper ;
zdw-w4,s,cjp blwb ;
nop
nop
.p!0029 m3503
;; rc3503 microprogram.
;; branch and continue instructions.
;; bsz. branch if all selected bits are zero. format a.
;; a:=w and operand;
;; w0:= if a=0 then b else w0+2;
bsza:
zdw and w4,s,cjp blp04 ;
; bsz. branch if all selected bits are zero. format b&c.
nop
nop
bszb:
zdw and w4,s,cjp blp05 ;
nop
nop
;; bop. branch if odd parity. format a.
;; a:= w and operand;
;; w0:= if odd a then b else w0+2;
bopa:
w4:=zdw and w4,, ;
w4,s, ;
w10+w0,,cjv 3 xpeven ;
xbopa:
bd:=w14:=w0,h r ,cjs ywread;
rm:=w0:=w15,,cjp nupdat ;
nop
nop
;; bop. branch if odd parity. format b&c
bopb:
w4:=zdw and w4,, ;
w4,s, ;
w10+w0,,cjv 3 peven ;
bopc:
w14:=w0,,cjp not i10 vupdat;
bd:=w14,h r ,cjs ywread ;
rm:=w0:=w15,,cjp nupdat ;
nop
nop
.p!0030 m3503
;; routine to write into memory (word).
;; w14=address. w15=data. (w14-17 bitslice registers).
wwrite:
bf:=0c0,w0+q,, ;
; 8.306 --> modul select register.
bd:=w14,h , ;
; load address(w14) out on the back plane bus.
bfm:=0c1,w0+q,h , ;
; set modul select to data mode.
bd:=w15,h w ,crtn ;
; return from subroutine.
;; routine to write into memory (byte).
bwrite:
bf:=0c0,w0+q,, ;
; load 8.306 into modul select register.
bd:=w14,h , ;
; load address(w14) out onto the back plane bus.
bf:=0c1,w0+q,h b , ;
; set modul select to data mode.
bd:=w15,h w b ,crtn ;
nop
nop
nop
nop
;; return from subroutine.
.p!0031 m3503
;; rc3503 microprogram.
;; write control/word. x=0.
wxcx0:
w5:=1f and q,s, ;
; test if ir(11:15)=0.
w3:=w12,,cjp not zro wxcx1 ;
w5:=w1,, ;
wxcx1:
bf:=w5,w3:=w5 and w3,,cjp not i10 wwc;
w0,,cjp wcc0 ;
nop
nop
;; write control/word. x<>0.
wxcxn:
w5:=1f and q,s, ;
w3:=w12,,cjp not zro wxcx2 ;
w5:=w1,, ;
wxcx2:
bf:=w5,w3:=w5 and w3,,cjp not i10 wwc;
w0,,cjp wccx ;
nop
nop
;; rc3503 microprogram.
;; write block of bytes/words.
wbxx:
w5:=1f and q,s, ;
; test if ir(11:15)=0.
w3:=w12,,cjp not zro wbx1 ;
w5:=w1,, ;
wbx1:
w3:=w5 and w3,,cjp not i10 wbb;
w0,,cjp wbww ;
nop
nop
;; read status/word.
rxc:
w5:=1f and q,s, ;
w3:=w12,,cjp not zro rxc1 ;
w5:=w1,, ;
rxc1:
bf:=w5,w3:=w5 and w3,,cjp not i10 rwc;
w0,,cjp rsc ;
nop
nop
.p!0032 m3503
;; rc3503 microprogram.
;; read block of bytes/word.
rbx:
w5:=1f and q,s, ;
; test if ir(11:15)=0.
w3:=w12,,cjp not zro rbx1 ;
w5:=w1,, ;
rbx1:
bf:=w5,w3:=w5 and w3,,cjp not i10 rbb;
w0,,cjp rbw ;
nop
nop
nop
nop
;; rc3503 microprogram.
;; routine to set devno/head bits(w3+devno) and
;; transmit the contents of w4 to the device.
;; call: w3= 0 read data.
;; 100 write data.
;; 200 read status.
;; 300 write control.
;; w4= transmit data.
;; w5= device number.
xhead:
bf:=w9+w5,,cjp not st2 xhead;
; set modul selext:= 400+device number.
bd:=w3,h w , ;
xwait:
bf:=w5,, ;
bd:=w4,h w ,crtn ;
;; rc3503 microprogram.
;; routine to set timer and wait upon
;; timeout or data in ready.
;; if eoi or timeout then zero flag=0
w0,i ,push timer ;
w0,i ,twb st5 timot ;
wdal:
,i s,crtn st3 ;
timot:
0++,i s,crtn ;
.p!0033 m3503
;; read word and compare.
;; w7:=x;
;; w1:= data in;
;; if w<>a and eoi=0 then begin ir(current level):=0; w0:=w0-2 end;
;; enable:=1;
rwc:
w3:=0+w3,, ;
w4:=zd1,,1 ;
w7:=zdx,,cjs xhead ;
,s,cjs wdair ;
zdw-w7,s,cjp not zro eupdat;
w0,,cjp rbbl ;
nop
nop
nop
;; read block of bytes.
;; if x(15)=0 then st(x)(0:7):=data in(8:15);
;; else st(x):=data in(8:15);
;; x:=x+1;
;; if w<>x and eoi=0 then begin ir(current level):=0; w0:=w0-2 end;
;; enable:=1;
rbb:
w3:=0+w3,, ;
; "read data" frame to reg 3
w4:=zd1,,1 ;
; read w1 to reg 4
w7:=zdx,,cjs xhead ;
; read x-reg to reg 7, jump xhead
w14:=w7,,cjs wdain ;
; wait data in ready, jump wdain
bf:=w8+w1,, ;
bd:=w12 and w1,h w , ;
w15:=bd,h w ,cjs bwrite ;
; write byte into mem, incr x-reg
zdx:=w7:=++w7,,cjp xrbb ;
; jump if eoi to eupdat
rbbl:
bf:=w8+w1,,cjp zro eupdat ;
; prepare iors signals for clear itr
bd:=w12 and w1,h w ,cjp bupdat;
; clear itr-f/f, jump bupdat
.p!0034 m3503
;; rc3503 microprogram.
;; read block of words.
;; st(x):=data in;
;; x:=x+2;
;; if w<>x and eoi=0 then begin ir(current level):=0; w0:=w0-2 end;
;; enable:=1;
rbw:
w3:=0+w3,, ;
w4:=zd1,,1 ;
w7:=zdx,,cjs xhead ;
w14:=w7,,cjs wdain ;
bf:=w8+w1,, ;
bd:=w12 and w1,h w , ;
w15:=bd,w ,cjs wwrite ;
zdx:=w7:=w10+w7,,cjp xrbb ;
;; write word and compare.
;; data out:= w1;
;; w<>x then begin ir(current level):=0; w0:=w0-2 end;
;; enable:=1;
wwc:
w3:=40+w3,, ;
w4:=zd1,,1 ;
w7:=zdx,,cjs xhead ;
wwcl:
w7-zdw,s,cjp rbbl ;
; compare x and w reg
.p!0035 m3503
;; rc3503 microprogram.
;; write block of bytes.
;; data out(8:15):= if x(15)=0 then st(x)(0:7) else st(x)(8:15);
;; x:=x+1;
;; if w<>x then begin ir(current level):=0; w0:=w0-2 end;
;; enable:= 1;
wbb:
w3:=40+w3,, ;
; "write data" frame to reg 3
w14:=zdx,,cjs xbread ;
; read byte from mem
w4:=w15,,cjs xhead ;
; move byte to reg 17, jump xhead
zdx:=w7:=++w14,,cjp wwcl ;
; incr. x reg, jump to wwcl
;; write block of words.
;; data out:= st(x);
;; x:=x+2;
;; if w<>x then begin ir(current level):=0; w0:=w0-2 end;
;; enable:=1.
wbww:
w3:=40+w3,, ;
w14:=zdx,,cjs xwread ;
w4:=w15,,cjs xhead ;
zdx:=w14:=w10+w14,, ;
w14-zdw,s,cjp rbbl ;
.p!0036 m3503
;; rc3503 microprogram.
;; write control. x<>0.
;; control:= w1;
;; enable:=1;
wccx:
w3:=0c0+w3,, ;
w4:=zd1,,1 ;
w0,,cjs xhead ;
wccl:
led:=4,w6:=4,, ;
ir:=w0,,cjp fetch ;
;; write control. x=0.
;; control:=w1;
;; enable:=1; ir(current level):=0;
wcc0:
w3:=0c0+w3,, ;
w4:=zd1,,1 ;
w0,,cjs lhead ;
bf:=w8+w1,, ;
bd:=w12 and w1,h w ,cjp wccl;
;; rc3503 microprogram.
;; read status and compare.
;; w6:=x
;; w1:=status.
;; if w<>w6 and eoi=0 then begin ir(current):=0;w0:=w0-2 end;
;; enable:=1;
rsc:
w3:=80+w3,, ;
w4:=zd1,,1 ;
w7:=zdx,,cjs xhead ;
,s,cjs wdair ;
rscl:
,,cjp not zro eupdat ;
w7-zdw,s, ;
bf:=w8+w1,,cjp zro eupdat ;
bd:=w12 and w1,h w ,cjp bupdat;
nop
.p!0037 m3503
;; rc3503 microprogram.
;; update w0 routine.
;; sync interrupt.
update:
ir:=w10+w0,,cjp fetch ;
fetch,w0,,cjp ;
nupdat:
w0:=zd0,, ;
qupdat:
ir:=zm0:=w0,,cjp fetch ;
fetch,w0,,cjp ;
;; bupdat. w0:=w0-2; enable;
bupdat:
led:=4,w6:=4,, ;
; set enable in reg 6, enable, sync-itr
ir:=rm:=w0:=w0-w10,,cjp fetch;
; decr w0 (-2), jump fetch
eupdat:
led:=4,w6:=4,, ;
ir:=w0,,cjp fetch ;
;; subroutine to update w13 with highest priority level number.
ginta:
ra:=w1,, ;
gint1:
w13:=rd,, ;
ra:=w13,,crtn ;
cupdat:
ir:=w0,,cjp fetch ;
w0,,cjp fetch ;
cogll:
zdw:=w4,,cjp not i10 cupdat;
w4:=zdx+w10,, ;
zdx:=w4,,cjp cupdat ;
wdain:
w15:=waits,, ;
rc:=w15,,ldct ;
wdasp:
w0,,rpct wdasp ;
w0,i ,push timer ;
w0,i ,twb st5 timot ;
w0,i ,cjp wdal ;
vupdat:
ir:=zm0:=w0:=w10+w0,,cjp fetch;
w0,,cjp fetch ;
.p!0038 m3503
;; rc3503 microprogram.
;; interlevel store (ist). format c.
istc:
w7:=zdw,, ;
w14:=w0,, ;
w14:=w14-w10,,cjs wread ;
ra:=w3:=w15,,cjp istx ;
;; interlevel load (ild). format c.
ildc:
w14:=w0,, ;
w14:=w14-w10,,cjs wread ;
ra:=w3:=w15,,cjp ildx ;
;; instruction to set the module select.
mseta:
w4,,cjp msetc ;
msetb:
w4,,cjp msetc ;
.p!0039 m3503
;; routine to read from memory(word).
;; w14=address.w15:=data.
wread:
bf:=0c0,w14,, ;
; load 8.300 into modul select.
xwread:
bd:=w14,h r , ;
; load address register.
ywread:
w15:=bd,h w s, ;
; read answer,v-jump on lpe/rpe status
w15,h ,crtn not pty ;
w15:=bd,h w , ;
w2:=,,cjv 3 sparw ;
;; routine to read from memory (byte).
bread:
bf:=0c0,w0+q,, ;
; load 8.300 into modul select register.
xbread:
bd:=w14,h r , ;
; load address register.
bf:=0c1,w15+q,h b , ;
; select data mode.
w15:=bd,h w b s, ;
; read answer, v-jump on lpe/rpe status
w2:=,,cjv 3 bypar ;
wdair:
w15:=waits,, ;
rc:=w15,,ldct ;
wdai1:
w0,,rpct wdai1 ;
w0,i ,push timer ;
w0,i ,twb st5 timxx ;
w15:=bd,h i ,1 ;
zd1:=w15,i ,crtn st3 1 ;
zz1:=,i ,1 ;
timxx:
0++,i s,crtn ;
;; write control timer loop.
lhead:
w15:=wctim,, ;
w0,,cjs xhead ;
rc:=w15,,ldct ;
wdao1:
w0,,rpct wdao1 ;
w0,,crtn ;
.p!0040 m3503
;; routine to write into the w-register.
;; w14=address.w15=data.
wwreg:
ra:=w14,, ;
; load working register address register.
rd:=w15,h , ;
; write into working register.
ra:=w13,,crtn ;
; restore current level and return.
;; routine to read from the w-register.
;; w14=address. w15:=data.
rwreg:
ra:=w14,, ;
; load working register address.
w15:=rd,h , ;
; read from working register.
ra:=w13,,crtn ;
; restore current level and return.
;; routine to read from memory module. the module number is send
;; from the debug'er.
;; call: w14=offset address,w07=module number.
;; ret : w15=data.
dbread:
ba:=w7,, ;
bfm:=0c0,w14,, ;
bd:=w14,h r , ;
bwrd:
,h ,cjp not st2 bwrd ;
w15:=bd,h w s, ;
; read answer, v-jump on lpe/rpe status
ba:=w2:=,,cjv 3 sparw ;
;; routine to write into memory module.
;; call: w14=offset addr.,w07=module no,w15=data.
dbwrit:
ba:=w7,, ;
bfm:=0c0,w14,, ;
bd:=w14,h , ;
bfm:=0c1,w14,h , ;
bd:=w15,h w , ;
ba:=,,crtn ;
.p!0041 m3503
;; rc3503 microprogram.
;; procedure to receive one byte from the debug microprocessor.
;; w3(8:15):= cdi;
;; w3(0:7) := 0;
;; w4(0:7):= cdi;
;; w4(8:15):= 0;
gbyte:
w3:=,, ;
glp1:
w3,,cjp cr glp1 ;
w3:=cd,, ;
w3:=0ff and w3,, ;
w3,, ;
w4:=swp,, ;
w0,,crtn ;
;; routine to send w3(8:15) to the debug microprocessor(m).
prbyt:
w14:=fi5,, ;
w15:=w3,,cjp wwreg ;
;; rtn cs00,ar00,br00,nonf,addz,rsoa,cb,waw,bs5,bd0,doxx,0
;; routine to send w3(0:7) to the debug microprocessor.
plbyt:
w14:=fi4,, ;
w3,, ;
w15:=swp,,cjp wwreg ;
;; rtn cs00,ar00,br00,nonf,addz,rsoa,cb,waw,bs5,bd0,doxx,0
;; routine to get word from fifo.
;; call: w14= fix.
;; return: w14(0:7)=fix-1 and w14(8:15)=fix.
gword:
w14,,cjs rwreg ;
w3:=0ff and w15,, ;
w14:=w14--,,cjs rwreg ;
w15:=0ff and w15,, ;
w15,, ;
w14:=swp+w3,,crtn ;
.p!0042 m3503
;; rc3503 microprogram.
;; debug routine. get mem.
;; transfer a word from l-mem to m.
getm:
w14:=fi3,, ;
w14,,cjs gword ;
; fetch module no from fi3-fi2
w7:=w14,, ;
; save module no in reg 7
w14:=fi1,, ;
w14,,cjs gword ;
; fetch offset addr from fi1-fi0
w0,,cjs dbread ;
; read word from mem
w3:=w15,,cjs prbyt ;
; put right byte into fifo fi5
w0,,cjp plbyt ;
; put left byte into fifo fi4
;; rtn cs00,ar00,br00,nonf,addz,rsoa,cb,waw,bs5,bd0,doxx,0
; return
;; debug routine. put mem.
;; transfer a word from m to l-mem.
putm:
w14:=fi5,, ;
w14,,cjs gword ;
; fetch module no from fifo fi5-fi4
w7:=w14,, ;
; module to reg 7
w14:=fi3,, ;
w14,,cjs gword ;
; fetch offset addr from fifo fi3-fi2
w4:=w14,, ;
; save addr in reg 4
w14:=fi1,, ;
w14,,cjs gword ;
; fetch data from fifo fi1-fi0
w15:=w14,, ;
; move data to reg 17
w14:=w4,,cjp dbwrit ;
; move addr to reg 16
;; rtn cs00,ar00,br00,nonf,addz,rsoa,cb,waw,bs5,bd0,doxx,0
; return
.p!0043 m3503
;; rc3503 microprogram.
;; debug routine. get reg.
;; transfer a word from l-reg to m.
getr:
w14:=fi1,, ;
w14,,cjs gword ;
; fetch w-reg addr from fifo fi1-fi0
w4+w14,,cjs rwreg ;
; read w-reg
w3:=w15,,cjs prbyt ;
; put right byte into fifo fi5
w0,,cjp plbyt ;
; put left byte into fifo fi4
;; rtn cs00,ar00,br00,nonf,addz,rsoa,cb,waw,bs5,bd0,doxx,0
; return
;; debug routine. put reg.
;; transfer a word from m to l-reg.
putr:
w14:=fi3,, ;
w14,,cjs gword ;
; fetch w-reg addr from fifo fi3-fi2
w4:=w14,, ;
; save w-reg addr in reg 4
w14:=fi1,, ;
w14,,cjs gword ;
; fetch write data from fifo fi1-fi0
w15:=w14,, ;
; move write data to reg 17
w14:=w4,,cjp wwreg ;
; w-reg addr to reg 16, write into w-reg
;; rtn cs00,ar00,br00,nonf,addz,rsoa,cb,waw,bs5,bd0,doxx,0
; return
rdat:
w0,,cjs fifos ;
; circulate fifo
ccr,w0,,cjp tsrun ;
; clear cr f/f, jump tsrun
.p!0044 m3503
;; rc3503 microprogram.
;; debug routine. read data.
;; w((w2)+copy):= w3; received byte.
;; copy means start of the image of the microprocessor ram
;; in the w-register array.
rdadr:
w14:=fi1,, ;
w14,,cjs rwreg ;
; fetch lsb addr from fifo
w2:=<w15,, ;
; shift addr one step left
w2:=<w2+w2,, ;
; one step more
w14:=w14--,,cjs rwreg ;
; fetch data from fifo
w3:=0ff and w15,, ;
; mask and save in reg 3
w14:=1f8 and w2,, ;
; mask for max cells 3f
w14:=84+w14,, ;
; add base+offset
w15:=w3,,cjp wwreg ;
; reg 3 to reg 17, write data into image
;; rtn cs00,ar00,br00,ldbf,addz,rsoa,cb,waw,bs5,bd0,doxx,0
.p!0045 m3503
;; rc3503 microprogram
;; debug routine. get level.
;; transfer current level to m.
getl:
cd:=w3:=w1,, ;
; current level to cdo-reg
w0,,crtn ;
; return
;; test the state of run/stop.
tsrun:
w0,,cjp not c7 dupdat ;
w0,,cjp fetch ;
;; routine to
;; input level number and
;; output register offset.
gloff:
w0,,cjs gbyte ;
; read wanted level from cdo-reg
w14:=w3,,cjs rwreg ;
; fetch offset from table
w3:=w15,,cjs prbyt ;
; put right byte into fifo fi5
w0,,cjs plbyt ;
; put left byte into fifo fi4
ccr,w0,,cjp tsrun ;
; clear cr f/f, jump tsrun
.p!0046 m3503
;; rc3503 microprogram.
;; debug fifo administration.
;; fi5 (top of fifo) - fi4 - fi3 - fi2 - fi1 - fi0 (input to fifo)
;; when called:
;; cdi->fi0->fi1->fi2->fi3->fi4->fi5->cdo
fifos:
w14:=fi5,, ;
; fi5 addr to reg 16
w14,,cjs rwreg ;
; "read fifo" result in reg 17
cd:=w15,, ;
; reg 17 to cdo-reg
w14:=fi4,, ;
; fi4 addr to reg 16
w14,,cjs rwreg ;
; "read fifo" (fi4)
w14:=++w14,,cjs wwreg ;
; "write fifo" in fi5
w14:=w14-w10,,cjs rwreg ;
; "read fifo" (fi3)
w14:=++w14,,cjs wwreg ;
; "write fifo" in fi4
w14:=w14-w10,,cjs rwreg ;
; "read fifo" (fi2)
w14:=++w14,,cjs wwreg ;
; "write fifo" in fi3
w14:=w14-w10,,cjs rwreg ;
; "read fifo" (fi1)
w14:=++w14,,cjs wwreg ;
; "write fifo" in fi2
w14:=w14-w10,,cjs rwreg ;
; "read fifo" (fi0)
w14:=++w14,,cjs wwreg ;
; "write fifo" in fi1
w14:=fi0,, ;
; fi0 addr to reg 16
w15:=cd,,cjp wwreg ;
; "write fifo" cdi to fi0
;; rtn cs00,ar00,br00,nonf,addz,rsoa,cb,waw,bs5,bd0,doxx,0
; return
.p!0047 m3503
;; rc3503 microprogram.
;; debug routine. set timer level.
;; itr(w(copy)):=1;
sett:
w14:=84,, ;
; addr to rtc level (image)
setl:
w0,,cjs rwreg ;
; read from image
w14:=7f and w15,, ;
; mask for max 127 levels
w14,,cjs sitrn ;
; set level (reg 16)
ccr,w4,,cjp tsrun ;
; clear cr f/f , jump tsrun
seto:
w14:=8c,, ;
; addr to tto level (image)
w0,,cjp setl ;
; jump setl
seti:
w14:=94,, ;
; addr to tti level (image)
w0,,cjp setl ;
; jump setl
;; set version number and cpu no.
setver:
w14:=fi5,, ;
; fi5 addr to reg 16
w15:=cpuve,, ;
; cpu-type and m-prog. ver to reg 17
w0,,cjs wwreg ;
; write number to fi5
w0,,cjp lclear ;
; jump lclear
.p!0048 m3503
;; rc3503 microprogram.
;; routine to move autoload from prom mem to ram
;; starting from h.fe00.
;; w5=prom addr.; w7=ram addr.
auctl:
w5:=4,, ;
; 4 to reg 5 (rom start addr)
w7:=aucon,, ;
; 8.777 to reg 7
w7:=--w7,, ;
; 8.177000 to reg 7
aurep:
ba:=10,w14:=w5,, ;
; reg 5 to reg 16, sel prom
w14,,cjs wread ;
; read word (byte) from prom
ba:=0,w14:=w7,, ;
; reg 7 to reg 16, sel ram
w14,,cjs bwrite ;
; write byte into ram
w5:=w10+w5,, ;
; incr. prom addr +2 - to reg 5
w7:=++w7,s, ;
; incr. ram addr +1 - to reg 7
w0,,cjp not zro aurep ;
; jump to aurep if not finish with move
ir:=w0,,cjp pfetch ;
; jump to fetch
lclear:
w14:=80,, ;
; 1f (level 31) to reg 16
; set interrupt level 31
lcrep:
w14:=w14--,s, ;
; decr. level (reg 16)
w14,,cjp zro set32 ;
; jump to set31 if level decremented to zero
w14,,cjs citrn ;
; clear level (level no in reg 16)
int,w0,,cjp lcrep ;
; jump lcrep
set32:
w14:=fie,, ;
w15:=,,cjs wwreg ;
w14:=1f,, ;
,,cjs sitrn ;
.p!0049 m3503
;; rc3503 micro program
;; prepare level 1f to start in autoload code
;; placed in area fe00 to ffff.
set31:
w15:=aucon,, ;
; 8.777 to reg 17
w15:=--w15,, ;
; 8.177000 to reg 17
w14:=17a,, ;
; 8.572 to reg 16
w0,,cjs wwreg ;
; write hex fe00 into w2 level 1f
w15:=33,, ;
; 8.63 to reg 17
w15:=--w15,, ;
; 8.177714 to reg 17
w14:=178,, ;
; 8.570 to reg 16
w0,,cjs wwreg ;
; write hex ffcc into w0 on level 1f
w15:=,, ;
; zero to reg 17
w14:=17b,, ;
; 8.573 to reg 16
w0,,cjs wwreg ;
; write zero into w3 on level 1f
w0,,cjp auctl ;
; jump to auctl
.p!0050 m3503
;; rc3503 microprogram
;; generation of w-reg offset table
uptab:
w4:=0,, ;
; zero to reg 4
w7:=80,, ;
; hex 80 to reg 7 (last addr)
w5:=0,, ;
; zero to reg 5
up20:
w14:=w4,, ;
; reg 4 to reg 16 (addr)
w15:=w7,,cjs wwreg ;
; reg 7 to reg 17 (data) , write offset
w4:=++w4,, ;
; incr reg 4
w5:=++w5,, ;
; incr reg 5
w7:=8+w7,, ;
; incr. reg 7 with 8 (to next level)
w5-80,s, ;
; is it last level ?
w0,,cjp not zro up20 ;
; no jump to up20
w0,,cjp setver ;
; jump to setver
.p!0051 m3503
;; rc3503 microprogram.
;; decoder for test command.
;; =01 xmt 7.5 intr to 8085.
;; =02 working register address test.
;; =03 working register data test.
;; =04 memory address test.
;; =05 memory data test.
tscom:
w14:=fi0,, ;
; addr fi0 to reg 16
w0,,cjs rwreg ;
; read fi0 result in reg 17
w15:=7 and w15,, ;
; and read value (test number) with 7
w15 xor 1,s, ;
; exor with 1 - is it test 1 ?
w0,,cjp zro tes01 ;
; yes - jump to tes01
w15 xor 2,s, ;
; exor with 2 - is it test 2 ?
w0,,cjp zro tes02 ;
; yes - jump to tes02
w15 xor 3,s, ;
; exor with 3 - is it test 3 ?
w0,,cjp zro tes03 ;
; yes - jump to tes03
w15 xor 4,s, ;
; exor with 4 - is it test 4 ?
w0,,cjp zro tes04 ;
; yes - jump to test 4
w15 xor 5,s, ;
; exor with 5 - is it test 5 ?
w0,,cjp zro tes05 ;
; yes - jump to tes05
w0,,cjp dupdat ;
; not used test number - jump to dupdat
.p!0052 m3503
;; rc3503 microprogram.
;; tes01.xmit 7.5 intr to 8085.
tes01:
led:=6,w0,, ;
; send itr to 8085 (rst 7.5)
ccr,w0,,cjp tsrun ;
; clear cr f/f, jump to tsrun
;; working address register test.
;; (addr):=addr.
;; if test=ok then (fi5)=0 else (fi5)<>0 and (fi3,fi4)=addr a
tes02:
w14:=fi5,, ;
; fi5 addr to reg 16
ts020:
w15:=w14,,cjs wwreg ;
; write addr on addr
w14:=w14--,s, ;
; decr. addr
w14,,cjp not zro ts020 ;
; jump if addr<>0 to ts020
w15:=w14,,cjs wwreg ;
; write in addr 0
ts021:
w14,,cjs rwreg ;
; start check-read from addr 0
w14-w15,s, ;
; sub addr- read
w14,,cjp not zro te02 ;
; jump if result <>0 to te02
w14:=++w14,, ;
; incr addr
fi5-w14,s, ;
; is it last addr ?
w14,,cjp not zro ts021 ;
; jump if it isen't to ts021
w14:=fi5,, ;
; fi5 addr to reg 16
w15:=,,cjs wwreg ;
; zero to fi5
ccr,w0,,cjp tsrun ;
; clear cr f/f, jump to tsrun
.p!0053 m3503
;; rc3503 microprogram.
;; working address register test. (cont.)
;; (addr):=addr.
;; if test=ok then (fi5)=0 else (fi5)<>0 and (fi3,fi4)=addr a
te02:
w3:=w14,, ;
; save addr in reg 3
w4:=w15,, ;
; save read data in reg 4
w14:=fi5,, ;
; fi5 addr to reg 16
w15:=w14,,cjs wwreg ;
; write "addr" into fi5 a value <>0
w14:=w14--,, ;
; fi4 addr to reg 16
w15:=w3,,cjs wwreg ;
; write addr 8:15 into fi4
w14:=w14--,, ;
; fi3 addr to reg 16
w3,, ;
; load swap reg
w15:=swp,,cjs wwreg ;
; write addr 0:7 into fi3
w14:=w14--,, ;
; fi2 addr to reg 16
w15:=w4,,cjs wwreg ;
; write read 8:15 into fi2
w14:=w14--,, ;
; fi1 addr to reg 16
w4,, ;
; load swap
w15:=swp,,cjs wwreg ;
; write read 0:7 into fi1
ccr,w0,,cjp tsrun ;
; clear cr f/f, jump tsrun
.p!0054 m3503
;; rc3503 microprogram.
;; working register data test.
;; when called: (fi1,fi2)= data constant.
;; return:
;; if test=ok then (fi5)=0 else (fi5)<>0
;; and (fi3,fi4)=addr. and (fi1,fi2)=wanted data.
tes03:
w14:=fi2,, ;
; fi2 addr to reg 16
w14,,cjs gword ;
; read fi1 and fi2, result in reg 16 (testpat)
w7:=w14,, ;
; save pattern in reg 7
w14:=,, ;
; zero to reg 16 (addr)
w15:=w7,, ;
; pattern to reg 17
ts031:
w14,,cjs wwreg ;
; write pattern
w15:=--w15,, ;
; complement test pattern
w14:=++w14,, ;
; incr. addr
bf:=fi5,fi5-w14,s, ;
; compare with max addr
w14,,cjp not zro ts031 ;
; jump if not max to ts031
w14:=,, ;
; zero to reg 16
.p!0055 m3503
;; rc3503 microprogram.
;; working register data test. (cont.)
;; when called: (fi1,fi2)= data constant.
;; return:
;; if test=ok then (fi5)=0 else (fi5)<>0
;; and (fi3,fi4)=addr. and (fi1,fi2)=wanted data.
ts032:
w14,,cjs rwreg ;
; read value
w7-w15,s, ;
; is read = wanted ?
w15:=w7,,cjp not zro te02 ;
; jump if it isen't to te02
w7:=--w7,, ;
; complement wanted value
w14:=++w14,, ;
; incr. addr
bf:=fi5,fi5-w14,s, ;
; compare with max addr
w14,,cjp not zro ts032 ;
; jump if not max to ts032
w14:=fi5,, ;
; fi5 addr to reg 16
w15:=,,cjs wwreg ;
; zero to fi5 (test ok)
ccr,w0,,cjp tsrun ;
; clear cr f/f, jump tsrun
.p!0056 m3503
;; rc3503 microprogram.
;; memory address register test.
;; call: (fi1,fi2)= modul no.
;; if test=ok then (fi5)=0 else (fi5)<>0
;; and (fi3,fi4)=addr and (fi1,fi2)=wanted data.
tes04:
w14:=fi2,, ;
; fi2 addr to reg 16
w14,,cjs gword ;
; read fi1 and fi2, result in reg17 (modul number)
w7:=w14,, ;
; save modul number in reg 7
w14:=,, ;
; zero to reg 16 (addr)
ts041:
w15:=w14,,cjs dbwrit ;
; write addr on addr
w14:=w10+w14,, ;
; incr. addr
w14,s, ;
; is offset = 0 (finish with module)
w0,,cjp not zro ts041 ;
; if not jump to ts041
ts042:
w14,,cjs dbread ;
; read from mem. starting in cell 0
w14-w15,s, ;
; is read = wanted ?
w14,,cjp not zro te02 ;
; if not jump to te02 (error)
w14:=w10+w14,s, ;
; incr. addr
w14,,cjp not zro ts042 ;
; is offset = 0 (finish with module) if not jump to ts042
w14:=fi5,, ;
; fi5 addr to reg 16
w15:=,,cjs wwreg ;
; write zero into fi5 (test ok)
ccr,w14,,cjp tsrun ;
; clear cr f/f, jump to tsrun
.p!0057 m3503
;; rc3503 microprogram.
;; memory data test.
;; call: (fi1,fi2)=modul no. and (fi3,fi4)=data constant.
;; if test=ok then (fi5)=0 else (fi5)<>0
;; and (fi3,fi4)=addr and (fi1,fi2)=wanted data.
tes05:
w14:=fi2,, ;
; fi2 addr to reg 16
w14,,cjs gword ;
; read fi1 and fi2, result in reg 16,(modul no.)
w7:=w14,, ;
; save modul number in reg 7
w14:=fi4,, ;
; fi4 addr to reg 16
w14,,cjs gword ;
; read fi3 and fi4, result in reg 16, (testpattern)
w13:=w14,, ;
; save test pattern in reg 15
w14:=,, ;
; zero to reg 16 (addr)
w15:=w13,, ;
; test pattern to reg 17
ts051:
w14,,cjs dbwrit ;
; write pattern. (starting in cell 0)
w14:=w10+w14,s, ;
; incr. addr
w15:=--w15,, ;
; complement test pattern
w14,,cjp not zro ts051 ;
; is offset =0, if not jump to ts051
w14:=,, ;
; zero to reg 16 (addr)
.p!0058 m3503
;; rc3503 microprogram.
;; memory data test. (cont.)
;; call: (fi1,fi2)=modul no. and (fi3,fi4)=data constant.
;; if test=ok then (fi5)=0 else (fi5)<>0
;; and (fi3,fi4)=addr and (fi1,fi2)=wanted data.
ts052:
w14,,cjs dbread ;
; read mem
w15-w13,s, ;
; is read = wanted ?
w15:=w13,,cjp not zro te02 ;
; if not move wanted to reg 17 and jump to te02
w13:=--w13,, ;
; complement test pattern
w14:=w10+w14,s, ;
; is offset = 0?
w14,,cjp not zro ts052 ;
; if not jump ts052
w14:=fi5,, ;
; fi5 addr to reg 16
w15:=,,cjs wwreg ;
; zero to fi5 (test ok)
ccr,w14,,cjp tsrun ;
; clear cr f/f, jump tsrun
.p!0059 m3503
;; rc3503 microprogram.
;; routine to test that the level in cdi exist.
;; if level(cdi) exist then cdo<>0 else cdo=0
tslev:
w14:=cd,, ;
; level under test to reg 16
w14:=7f and w14,, ;
; mask for max 127 levels
w3:=w14,,cjs sitrn ;
; set level, save level no in reg 3
tsl03:
ir:=w0,, ;
; send sync-itr puls
int,w0,, ;
; dummy (delay)
w14:=int,, ;
; read inta answer to reg 16
w4:= equ w14,, ;
; >:reg16 to reg4
w14-w3,s, ;
; exist level ? (reg 16 = reg 3)
w0,,cjp not zro tsl02 ;
; if not jump to tsl02
cd:=0ff,w0,, ;
; load cdo reg with *ff (level exist)
ccr,w0,,cjp tsrun ;
;clear cr f/f, jump to tsrun
tsl02:
w4+w3,s, ;
;is it a higher level ?
w0,,cjp not acy tsl01 ;
;if yes jump to tsl01
cd:=0,w0,, ;
; load cdo-reg with zero (level exist not)
ccr,w0,,cjp tsrun ;
; clear cr f/f, jump to tsrun
tsl01:
w14,,cjs citrn ;
; clear the higher level
w14,,cjp tsl03 ;
; jump tsl03
.p!0060 m3503
;; rc3503 microprogram.
;; parity error routine.
;; (fi4,5)= module no.
;; (fi2,3)=address.
pxer1:
w4:=w14,,crtn not pty ;
w14:=fif,, ;
w14,,cjs wwreg ;
w14:=fie,, ;
w14,,cjs rwreg ;
w15 and w15,s, ;
w0,,cjp not zro pxer2 ;
w14:=fib,, ;
; addr fi5 to reg 16
w15:=,,cjs wwreg ;
; zero to reg 17, write zero into fi5
w14:=fia,, ;
; addr fi4 to reg 16
w15:=,,cjs wwreg ;
; zero to reg 17, write zero into fi4
w14:=fid,, ;
; addr fi3 to reg 16
w15:=w4,,cjs wwreg ;
; mem addr 8:15 to reg 17, write it into fi3
w14:=fic,, ;
; addr fi2 to reg 16
w15:=w4,, ;
; mem addr 0:7 to reg 17
w15:=swp,,cjs wwreg ;
; swap reg 17, mem addr 0:7 into fi2
w14:=fie,, ;
w15:=w2,,cjs wwreg ;
led:=6,w0,, ;
; send itr to 8085
pxer2:
w14:=fif,, ;
w14,,cjs rwreg ;
w14:=w4,,crtn ;
.p!0061 m3503
;; rc3503 microprogram.
;; parity error routine.
;; (fi4,5)= module no.
;; (fi2,3)= address.
wrreq:
w14:=fia,, ;
w14,,cjs rwreg ;
w14:=fi4,, ;
w14,,cjs wwreg ;
w14:=fib,, ;
w14,,cjs rwreg ;
w14:=fi5,, ;
w14,,cjs wwreg ;
w14:=fic,, ;
w14,,cjs rwreg ;
w14:=fi2,, ;
w14,,cjs wwreg ;
w14:=fid,, ;
w14,,cjs rwreg ;
w14:=fi3,, ;
w14,,cjs wwreg ;
w14:=fie,, ;
w14,,cjs rwreg ;
w2:=w15,, ;
w15:=,,cjs wwreg ;
w2:=<w2,, ;
; shift reg 2 < 1 parity error info
w2:=6 and w2,, ;
; mask with 6
w2:=perro+w2,, ;
; add parity base command
cd:=w2,, ;
; load cdo reg with parity information
ccr,w0,, ;
; clear cr f/f
w0,,cjp dupdat ;
; jump dupdat
.p!0062 m3503
xrbb:
++w7,,cjp not zro pupdat ;
w7-zdw,s, ;
w0,,cjp not zro bupdat ;
pupdat:
w14:=w1,,cjs sitrn ;
w0,,cjp eupdat ;
pxerf:
w0,,cjs pxer1 ;
w0,,cjp fetrd ;
;; instruction to transfer a word
;; from memory with module select m(s) to memory module select m(d)
;; before execution of this instruction the following working
;; registers had to be set.
;; w1(0:7) source module select;w1(8:15) destinatin module select.
;; w2 source address.
;; w3 destination address.
msetc:
w7:=zd1,,1 ;
w7:=swp,, ;
w14:=zd2,,2 ;
w14,,cjs dbread ;
w7:=zd1,,1 ;
w14:=zd3,,3 ;
w14,,cjs dbwrit ;
w0,,cjp nupdat ;
.p!0063 m3503
;; rc3503 microprogram.
;; fetch routine .
pfetch:
ra:=178,w13:=178,, ;
w1:=1f,, ;
led:=4,w6:=4,, ;
ir:=w0,,cjp fetch ;
.p!0064 m3503
;; rc3503 micro program
;; condition vector map.
.k=380
vec30:
w0,w0:=++w0,,cjp nupdat ;
led:=cd,w0+q,, ;
vec31:
led:=4,w6:=4,, ;
w0:=rd,,cjp qupdat ;
vec32:
led:=5,w6:=5,, ;
w0:=rd,,cjp qupdat ;
vec33:
w14:=w3,,cjs sitrn ;
w0:=rd,,cjp qupdat ;
vec40:
w7:=>c>w7,,rpct vec40 ;
zdw:=w4:=w7,,cjp nupdat ;
rr01:
w7:=>c>w7,,rpct rr01 ;
zdw:=w4:=w7,,cjp nupdat ;
rr02:
w7:=>w7,,rpct rr02 ;
zdw:=w4:=w7,,cjp nupdat ;
rr03:
w7:=>c>w7,,rpct rr03 ;
zdw:=w4:=w7,,cjp nupdat ;
.p!0065 m3503
;; rc3503 microprogram
;; this routine controls the enable/disable interrupt
;; flag in accordance to the value of ir(9:10).
;; ir(9:10)= 00 do nothing
;; ir(9:10)= 01 enable interrupt system
;; ir(9:10)= 10 disable interrupt system
;; ir(9:10)= 11 set level specified by q(11:15).
upitr:
w0:=rd,,cjp qupdat ;
; jump vec30
w0,,cjp vec31 ;
; jump vec31
w0,,cjp vec32 ;
; jump vec32
w0,,cjp vec33 ;
; jump vec 33
;; routine to shift right b01 the number of times
;; specified in the n-counter (am2910).
;; the specified operation is controlled by ir(9:10)
;; ir(9:10)= 00 rotate right
;; ir(9:10)= 01 logical shift right
;; ir(9:10)= 10 no carry shift right
;; ir(9:10)= 11 arithmetic shift right
rright:
w0,,cjp vec40 ;
; jump vec 40
w0,,cjp rr01 ;
; jump rr01
w0,,cjp rr02 ;
; jump rr02
w0,,cjp rr03 ;
; jump rr03
.p!0066 m3503
;; rc3503 microprogram
;; routine to shift left b01 the number of times
;; specified in the n-counter.
;; called by jump vector "rleft".
;; the specified operation is controlled by ir(9:10).
;; ir(9:10)= 00 rotate left.
;; ir(9:10)= 01 logical shift left.
;; ir(9:10)= 10 no carry shift left.
;; ir(9:10)= 11 dummy.
vec21:
w7:=<c<w7,,rpct vec21 ;
; ir(9:10)=00. b07:=b07 shift left n-times.
zdw:=w4:=w7,,cjp nupdat ;
; b07---> w(current level).
rl01:
w7:=<c<w7,,rpct rl01 ;
; ir(9:10)=01. b07:=b07 shift left n-times.
zdw:=w4:=w7,,cjp nupdat ;
; b07---> w(current level).
rl02:
w7:=<w7,,rpct rl02 ;
; ir(9:10)=10. b07:=b07 shift left n-times.
zdw:=w4:=w7,,cjp nupdat ;
; b07---> w(current level).
updw0:
w0,,cjp vupdat ;
; ir(9:10)=11. b0---> w0(current level).
nop
rleft:
w0,,cjp vec21 ;
; jump vec21
w0,,cjp rl01 ;
; jump rl01
w0,,cjp rl02 ;
; jump rl02
w0,,cjp updw0 ;
; jump updw0
.p!0067 m3503
;; rc3503 microprogram.
;; debug routine.
;; condition vector map,depending upon cs(0:1).
;; cs(0:1)= 11 goto grup3
;; cs(0:1)= 10 goto grup2
;; cs(0:1)= 01 goto grup1
;; cs(0:1)= 00 goto grup0.
dmap:
w0,,cjv 5 grup0 ;
; jump grup0
w0,,cjv 5 grup1 ;
; jump grup1
w0,,cjv 5 grup2 ;
; jump grup2
w0,,cjv 5 grup3 ;
; jump grup3
.p!0068 m3503
;; rc3503 microprogram.
vec13:
ccr,w0,,cjp tsrun ;
; clear cr f/f, jump tsrun
nop
vec14:
w0,,cjs getm ;
; load fifo with wanted word
ccr,w0,,cjp tsrun ;
; clear cr f/f, jump tsrun
vec15:
w0,,cjs getl ;
; load current level into cdo reg
ccr,w0,,cjp tsrun ;
; clear cr f/f, jump tsrun
vec16:
w0,,cjs getr ;
; load fifo with wanted w-reg contents
ccr,w0,,cjp tsrun ;
; clear cr f/f, jump tsrun
vec17:
ccr,w0,,cjs rdadr ;
w0,,cjp tsrun ;
vec18:
w0,,cjs putm ;
; write into mem cell in question
ccr,w0,,cjp dupdat ;
; clear cr f/f, jump dupdat
vec19:
ccr,w0,,cjp ;
; clear cr f/f, jump init
nop
vec20:
w0,,cjs putr ;
; write into w-reg in question
ccr,w0,,cjp dupdat ;
; clear cr f/f, jump dupdat
.p!0069 m3503
;; rc3503 microprogram
;; grup3 vector jump (test af cs(2:3))
;; cs(2:3)= 00
;; cs(2:3)= 01 get memory (getm).
;; cs(2:3)= 10 get level (getl).
;; cs(2:3)= 11 get register (getr).
grup3:
w0,,cjp wrreq ;
; jump vec13
w0,,cjp vec14 ;
; jump vec14
w0,,cjp vec15 ;
; jump vec15
w0,,cjp vec16 ;
; jump vec16
;; grup2 vector jump (test af cs(2:3)).
;; cs(2:3)= 00 read address (rdadr).
;; cs(2:3)= 01 put memory (putm).
;; cs(2:3)= 10 autoload (init).
;; cs(2:3)= 11 put register (putr).
grup2:
w0,,cjp vec17 ;
; jump vec17
w0,,cjp vec18 ;
; jump vec18
w0,,cjp vec19 ;
; jump vec19
w0,,cjp vec20 ;
; jump vec20
.p!0070 m3503
;; rc3503 microprogram.
vec05:
w0,,cjp rdat ;
; jump rdat
nop
vec06:
ccr,w0,,cjp fetcd ;
; clear cr f/f, jump fetcd
nop
vec07:
w0,,cjp gloff ;
; jump gloff
nop
vec08:
ccr,w0,,cjp dupdat ;
; clear cr f/f, jump dupdat
nop
;; grup0. vector jump (test af cs(2:3)).
;; cs(2:3)= 00 read data (rdat).
;; cs(2:3)= 01 exec next instruction (fetcd).
;; cs(2:3)= 10 dummy
;; cs(2:3)= 11 dummy
grup0:
w0,,cjp vec05 ;
; jump vec05
w0,,cjp vec06 ;
; jump vec06
w0,,cjp vec07 ;
; jump vec07
w0,,cjp vec08 ;
; jump vec08
.p!0071 m3503
;; rc3503 microprogram
;; map45. jump vector cs(4:5).
;; cs(4:5)= 00 set timer and console level (settc).
;; cs(4:5)= 01 set timer level (sett).
;; cs(4:5)= 10 set console level (setc).
;; cs(4:5)= 11 jump vector dmap.
map45:
w0,,cjp seti ;
; jump seti
w0,,cjp sett ;
; jump sett
w0,,cjp seto ;
; jump seto
w0,,cjv 4 dmap ;
; jump dmap (debug map)
;; parity error test for read byte.
;; left parity is don't care
;; 00 parity ok
;; 01 error
;; 10 parity ok
;; 11 error
bypar:
w0,,crtn ;
; return no error
w0,,cjp pxer1 ;
; jump to error routine
w0,,crtn ;
; return no error
w0,,cjp pxer1 ;
; jump to error routine
.p!0072 m3503
;; rc3503 microprogram.
;; vector table to test parity for bop format a.
;; 00 odd+odd continue
;; 01 even+odd branch
;; 10 odd+even branch
;; 11 even+even continue
xpeven:
ir:=zm0:=w0:=w10+w0,,cjp fetch;
w0,,cjp xbopa ;
w0,,cjp xbopa ;
ir:=zm0:=w0:=w10+w0,,cjp fetch;
;; rc3503 microprogram.
;; vector table to test parity.
;; 00 odd+odd --> even; continue.
;; 01 even+odd --> odd ; branch.
;; 10 odd+even --> odd ; branch.
;; 11 even+even--> even; continue.
peven:
w0,,cjp bopc ;
; jump bopc
w0,,cjp carg1 ;
; jump carg1
w0,,cjp carg1 ;
; jump carg1
w0,,cjp bopc ;
; jump bopc
;; vector table to test cs(0:1).
;; 00 jump gloff
;; 01 jump tsrun
;; 10 jump init
;; 11 jump tsrun
xgl00:
w0,,cjp gloff ;
; jump gloff
w0,,cjp tsrun ;
; jump tsrun
w0,,cjp ;
; jump init
w0,,cjp tsrun ;
; jump tsrun
.p!0073 m3503
;; rc3503 microprogram
;; vector table grup1. test of cs(2:3).
;; cs(2:3)= 00 dummy (return to test run f/f)
;; 01 dummy (return to test run f/f)
;; 10 level exist test
;; 11 tscom
grup1:
ccr,w0,,cjp tsrun ;
; clear cr f/f , jump tsrun
ccr,w0,,cjp tsrun ;
; clear cr f/f , jump tsrun
w0,,cjp tslev ;
; jump tslev
w0,,cjp tscom ;
; jump tscom
;; vector table to test parity.
;; 00 w2=w2 no parity error
;; 01 w2=1 right parity error
;; 10 w2=2 left parity error
;; 11 w2=0 left/right parity error
sparf:
rm:=w0:=w10+w0,,jmap 0 ;
; return no parity error
w2:=++w2,,cjp pxerf ;
; 1 to reg 2
w2:=w10,,cjp pxerf ;
; 2 to reg 2
w2:=w10++w2,,cjp pxerf ;
; 3 to reg 2
sparw:
w2,,crtn ;
w2:=++w2,,cjp pxer1 ;
w2:=w10,,cjp pxer1 ;
w2:=w10++w2,,cjp pxer1 ;
.p!0074 m3503
;; rc3503 microprogram.
fetch:
int,w6 and w11,s,cjp not cr debug;
fetca:
int-w1,s,cjp not zro disab ;
int,w0,,cjp zro disab ;
ra:=int,w1:=int,, ;
w13:=rd,, ;
ra:=w13,, ;
disab:
c:=rd,w0:=rd,, ;
bf:=0c0,w0,h , ;
bd:=w14:=w0,h r , ;
ir:=bd,q:=bd,h w s, ;
led:=w6,w2:=,,cjv 3 sparf ;
.p!0075 m3503
.mapk 200
;; table pro layout.
;; ic23,25.
;; address calculation jump table.escape=0.
.addr fax0,18
.addr rxc ; read status/word.
.addr wxcx0 ; write control/word.
.addr ild ; interlevel load.
.addr ist ; interlevel store.
.addr shiti ; shift/rotate,x=0.
.addr update ; dummy.
.addr bx001 ; format b,x=0,i=0.
.addr cx001 ; format c,x=0,i=0.
.addr fax0,18 ; format a,x=0.
.addr rbx ; read block of bytes/word.
.addr wbxx ; write block of bytes/word.
.addr ild ; interlevel load.
.addr ist ; interlevel store.
.addr shiti ; shift/rotate,x=0.
.addr update ; dummy.
.addr bx0i1 ; format b,x=0,i=1.
.addr cx0i1 ; format c,x=0,i=1.
.addr faxn,18 ; format a,x<>0.
.addr rxc ; read status/word.
.addr wxcxn ; write control/word,x<>0.
.addr ild ; interlevel load.
.addr ist ; interlevel store.
.addr shitx ; shift/rotate,x<>0.
.addr update ; dummy.
.addr bxn01 ; format b,x<>0,i=0.
.addr cxn01 ; format c,x<>0,i=0.
.addr faxn,18 ; format a,x<>0.
.addr rbx ; read block of bytes/word.
.addr wbxx ; write block of bytes/word.
.addr ild ; interlevel load.
.addr ist ; interlevel store.
.addr shitx ; shift/rotate,x<>0.
.addr update ; dummy.
.addr bxni1 ; format b,x<>0,i=1.
.addr cxni1 ; format c,x<>0,i=1.
.p!0076 m3503
;; address calculation map cont'd.
.addr faxn,18 ; format a,x<>0.
.addr rxc ; read status/word.
.addr wxcxn ; write control/word,x<>0.
.addr ild ; interlevel load.
.addr ist ; interlevel store.
.addr shitx ; shift/rotate,x<>0.
.addr update ; dummy.
.addr bxn01 ; format b,x<>0,i=0.
.addr cxn01 ; format c,x<>0,i=0.
.addr faxn,18 ; format a,x<>0.
.addr rbx ; read block of bytes/word.
.addr wbxx ; write block of bytes/word.
.addr ild ; interlevel load.
.addr ist ; interlevel store.
.addr shitx ; shift/rotate,x<>0.
.addr update ; dummy.
.addr bxni1 ; format b,x<>0,i=1.
.addr cxni1 ; format c,x<>0,i=1.
.addr faxn,18 ; format a,x<>0.
.addr rxc ; read status/word.
.addr wxcxn ; write control/word,x<>0.
.addr ild ; interlevel load.
.addr ist ; interlevel store.
.addr shitx ; shift/rotate,x<>0.
.addr update ; dummy.
.addr bxn01 ; format b,x<>0,i=0.
.addr cxn01 ; format c,x<>0,i=0.
.addr faxn,18 ; format a,x<>0.
.addr rbx ; read block of bytes/word.
.addr wbxx ; write block of bytes/word.
.addr ild ; interlevel load.
.addr ist ; interlevel store.
.addr shitx ; shift/rotate,x<>0.
.addr update ; dummy.
.addr bxni1 ; format b,x<>0,i=1.
.addr cxni1 ; format c,x<>0,i=1.
.p!0077 m3503
;; format a instruction jump map. escape=1.
;; ic 23,25.
.addr ldr1 ; ldr. load register.
.addr ldc1 ; ldc. load complement.
.addr ldi1 ; ldi. load indirect.
.addr str1 ; str. store register.
.addr sti1 ; sti. store indirect.
.addr xsrai ; xsr. exchange store and register.
.addr lba ; ldb. load byte.
.addr stba ; stb. store byte.
.addr adda ; add. add integer word.
.addr suba ; sub. subtract.
.addr anda ; and. logical and.
.addr lora ; logical or.
.addr xora ; xor. exlusive or.
.addr lce1 ; lce. load clear enable.
.addr mseta ; dummy.
.addr rsw1 ; rsw. read switches.
.addr bgwa ; bgw. branch if greater.
.addr bewa ; bew. branch if equal.
.addr blwa ; blw. branch if less.
.addr bgba ; bgb. branch if greater byte.
.addr beba ; beb. branch if equal byte.
.addr blba ; blb. branch if less byte.
.addr bsza ; bsz. branch if selected bits are zero.
.addr bopa ; bop. branch if selected bits has odd parity.
.addr update,8
.p!0078 m3503
;; format a instruction jump map. escape=1.
;; ic 23,25.
.addr ldr1 ; ldr. load register.
.addr ldc1 ; ldc. load complement.
.addr ldi1 ; ldi. load indirect.
.addr str1 ; str. store register.
.addr sti1 ; sti. store indirect.
.addr xsrai ; xsr. exchange store and register.
.addr lba ; ldb. load byte.
.addr stba ; stb. store byte.
.addr adda ; add. add integer word.
.addr suba ; sub. subtract.
.addr anda ; and. logical and.
.addr lora ; logical or.
.addr xora ; xor. exlusive or.
.addr lce1 ; lce. load clear enable.
.addr mseta ; dummy.
.addr rsw1 ; rsw. read switches.
.addr bgwa ; bgw. branch if greater.
.addr bewa ; bew. branch if equal.
.addr blwa ; blw. branch if less.
.addr bgba ; bgb. branch if greater byte.
.addr beba ; beb. branch if equal byte.
.addr blba ; blb. branch if less byte.
.addr bsza ; bsz. branch if selected bits are zero.
.addr bopa ; bop. branch if selected bits has odd parity.
.addr update,8
.p!0079 m3503
;; format a instruction jump map. escape=1.
;; ic 23,25.
.addr ldr1 ; ldr. load register.
.addr ldc1 ; ldc. load complement.
.addr ldi1 ; ldi. load indirect.
.addr str1 ; str. store register.
.addr sti1 ; sti. store indirect.
.addr xsrai ; xsr. exchange store and register.
.addr lba ; ldb. load byte.
.addr stba ; stb. store byte.
.addr adda ; add. add integer word.
.addr suba ; sub. subtract.
.addr anda ; and. logical and.
.addr lora ; logical or.
.addr xora ; xor. exlusive or.
.addr lce1 ; lce. load clear enable.
.addr mseta ; dummy.
.addr rsw1 ; rsw. read switches.
.addr bgwa ; bgw. branch if greater.
.addr bewa ; bew. branch if equal.
.addr blwa ; blw. branch if less.
.addr bgba ; bgb. branch if greater byte.
.addr beba ; beb. branch if equal byte.
.addr blba ; blb. branch if less byte.
.addr bsza ; bsz. branch if selected bits are zero.
.addr bopa ; bop. branch if selected bits has odd parity.
.addr update,8
.p!0080 m3503
;; format a instruction jump map. escape=1.
;; ic 23,25.
.addr ldr1 ; ldr. load register.
.addr ldc1 ; ldc. load complement.
.addr ldi1 ; ldi. load indirect.
.addr str1 ; str. store register.
.addr sti1 ; sti. store indirect.
.addr xsrai ; xsr. exchange store and register.
.addr lba ; ldb. load byte.
.addr stba ; stb. store byte.
.addr adda ; add. add integer word.
.addr suba ; sub. subtract.
.addr anda ; and. logical and.
.addr lora ; logical or.
.addr xora ; xor. exlusive or.
.addr lce1 ; lce. load clear enable.
.addr mseta ; dummy.
.addr rsw1 ; rsw. read switches.
.addr bgwa ; bgw. branch if greater.
.addr bewa ; bew. branch if equal.
.addr blwa ; blw. branch if less.
.addr bgba ; bgb. branch if greater byte.
.addr beba ; beb. branch if equal byte.
.addr blba ; blb. branch if less byte.
.addr bsza ; bsz. branch if selected bits are zero.
.addr bopa ; bop. branch if selected bits has odd parity.
.addr update,8
.p!0081 m3503
;; format a instruction jump map. escape=1.
;; ic 23,25.
.addr ldr1 ; ldr. load register.
.addr ldc1 ; ldc. load complement.
.addr ldi1 ; ldi. load indirect.
.addr str1 ; str. store register.
.addr sti1 ; sti. store indirect.
.addr xsrai ; xsr. exchange store and register.
.addr lba ; ldb. load byte.
.addr stba ; stb. store byte.
.addr adda ; add. add integer word.
.addr suba ; sub. subtract.
.addr anda ; and. logical and.
.addr lora ; logical or.
.addr xora ; xor. exlusive or.
.addr lce1 ; lce. load clear enable.
.addr mseta ; dummy.
.addr rsw1 ; rsw. read switches.
.addr bgwa ; bgw. branch if greater.
.addr bewa ; bew. branch if equal.
.addr blwa ; blw. branch if less.
.addr bgba ; bgb. branch if greater byte.
.addr beba ; beb. branch if equal byte.
.addr blba ; blb. branch if less byte.
.addr bsza ; bsz. branch if selected bits are zero.
.addr bopa ; bop. branch if selected bits has odd parity.
.addr update,8
.p!0082 m3503
;; format a instruction jump map. escape=1.
;; ic 23,25.
.addr ldr1 ; ldr. load register.
.addr ldc1 ; ldc. load complement.
.addr ldi1 ; ldi. load indirect.
.addr str1 ; str. store register.
.addr sti1 ; sti. store indirect.
.addr xsrai ; xsr. exchange store and register.
.addr lba ; ldb. load byte.
.addr stba ; stb. store byte.
.addr adda ; add. add integer word.
.addr suba ; sub. subtract.
.addr anda ; and. logical and.
.addr lora ; logical or.
.addr xora ; xor. exlusive or.
.addr lce1 ; lce. load clear enable.
.addr mseta ; dummy.
.addr rsw1 ; rsw. read switches.
.addr bgwa ; bgw. branch if greater.
.addr bewa ; bew. branch if equal.
.addr blwa ; blw. branch if less.
.addr bgba ; bgb. branch if greater byte.
.addr beba ; beb. branch if equal byte.
.addr blba ; blb. branch if less byte.
.addr bsza ; bsz. branch if selected bits are zero.
.addr bopa ; bop. branch if selected bits has odd parity.
.addr update,8
.p!0083 m3503
;; format a instruction jump map. escape=1.
;; ic 23,25.
.addr ldr1 ; ldr. load register.
.addr ldc1 ; ldc. load complement.
.addr ldi1 ; ldi. load indirect.
.addr str1 ; str. store register.
.addr sti1 ; sti. store indirect.
.addr xsrai ; xsr. exchange store and register.
.addr lba ; ldb. load byte.
.addr stba ; stb. store byte.
.addr adda ; add. add integer word.
.addr suba ; sub. subtract.
.addr anda ; and. logical and.
.addr lora ; logical or.
.addr xora ; xor. exlusive or.
.addr lce1 ; lce. load clear enable.
.addr mseta ; dummy.
.addr rsw1 ; rsw. read switches.
.addr bgwa ; bgw. branch if greater.
.addr bewa ; bew. branch if equal.
.addr blwa ; blw. branch if less.
.addr bgba ; bgb. branch if greater byte.
.addr beba ; beb. branch if equal byte.
.addr blba ; blb. branch if less byte.
.addr bsza ; bsz. branch if selected bits are zero.
.addr bopa ; bop. branch if selected bits has odd parity.
.addr update,8
.p!0084 m3503
;; format a instruction jump map. escape=1.
;; ic 23,25.
.addr ldr1 ; ldr. load register.
.addr ldc1 ; ldc. load complement.
.addr ldi1 ; ldi. load indirect.
.addr str1 ; str. store register.
.addr sti1 ; sti. store indirect.
.addr xsrai ; xsr. exchange store and register.
.addr lba ; ldb. load byte.
.addr stba ; stb. store byte.
.addr adda ; add. add integer word.
.addr suba ; sub. subtract.
.addr anda ; and. logical and.
.addr lora ; logical or.
.addr xora ; xor. exlusive or.
.addr lce1 ; lce. load clear enable.
.addr mseta ; dummy.
.addr rsw1 ; rsw. read switches.
.addr bgwa ; bgw. branch if greater.
.addr bewa ; bew. branch if equal.
.addr blwa ; blw. branch if less.
.addr bgba ; bgb. branch if greater byte.
.addr beba ; beb. branch if equal byte.
.addr blba ; blb. branch if less byte.
.addr bsza ; bsz. branch if selected bits are zero.
.addr bopa ; bop. branch if selected bits has odd parity.
.addr update,8
.p!0085 m3503
;; format b instruction jump map. escape=0.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr strix ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrbx ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0086 m3503
;; format b instruction jump map. escape=0.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr strix ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrbx ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0087 m3503
;; format b instruction jump map. escape=0.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr strix ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrbx ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0088 m3503
;; format b instruction jump map. escape=0.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr strix ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrbx ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0089 m3503
;; format b instruction jump map. escape=0.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr strix ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrbx ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0090 m3503
;; format b instruction jump map. escape=0.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr strix ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrbx ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0091 m3503
;; format b instruction jump map. escape=0.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr strix ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrbx ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0092 m3503
;; format b instruction jump map. escape=0.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr strix ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrbx ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0093 m3503
;; format b instruction jump map. escape=1.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr stri0 ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrb0 ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0094 m3503
;; format b instruction jump map. escape=1.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr stri0 ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrb0 ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0095 m3503
;; format b instruction jump map. escape=1.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr stri0 ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrb0 ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0096 m3503
;; format b instruction jump map. escape=1.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr stri0 ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrb0 ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0097 m3503
;; format b instruction jump map. escape=1.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr stri0 ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrb0 ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0098 m3503
;; format b instruction jump map. escape=1.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr stri0 ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrb0 ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0099 m3503
;; format b instruction jump map. escape=1.
;; ic 22,18
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr stri0 ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrb0 ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
.p!0100 m3503
;; format b instruction jump map. escape=1.
;; ic 23,25.
.addr ldr23 ; ldr. load register.
.addr ldc23 ; ldc. load complement.
.addr ldi23 ; ldi. load indirect.
.addr stri0 ; str. store register.
.addr sti23 ; sti. store indirect.
.addr xsrb0 ; xsr. exchange store and register.
.addr ldbb ; ldb. load byte.
.addr stbb ; stb. store byte.
.addr addb ; add. add integer word.
.addr subb ; sub. subtract.
.addr andb ; and. logical and.
.addr lorb ; logical or.
.addr xorb ; xor. exlusive or.
.addr lce23 ; lce. load clear enable.
.addr msetb ; dummy.
.addr rsw23 ; rsw. read switches.
.addr bgwb ; bgw. branch if greater.
.addr bewb ; bew. branch if equal.
.addr blwb ; blw. branch if less.
.addr bgbb ; bgb. branch if greater byte.
.addr bebb ; beb. branch if equal byte.
.addr blbb ; blb. branch if less byte.
.addr bszb ; bsz. branch if selected bits are zero.
.addr bopb ; bop. branch if selected bits has odd parity.
.addr update
.addr update
.addr ildc
.addr istc
.addr update,4
!\f
!rc35mass 81 06 09 15 49 13 page 1
!
! 76 blocksread
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