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Length: 5376 (0x1500)
Types: TextFileVerbose
Names: »lmitxt003«
└─⟦2c55ea56f⟧ Bits:30001844 SW-save af projekt 1000, Alarm-system
└─⟦093e2ad1c⟧
└─⟦this⟧ »lmitxt003«
;;
;; begin lmitxt003
;;
;
dumpregs: ;
;; time: 46x = 10.1 us
;; entry: ra = register address
;; exit: ir=300, w0,1,2,5,6 undefined
;
ir:=300,,, ;
w2:=rdx,s, ;
w1:=rd,,cjp b0 dumpregs1 ; return if dummyregs or i/o mode
w5:=rdw,, ;
dumplmp8= dumplm + 8 ;
w5:=w5+dumplmp8,, ; address of dumpib
w6:=zdx,,cjs cwrite21 ; dump ib, ic
w5:=w5-4,, ;
w1:=rd0,, ;
w2:=zd,,cjs cwrite21 ; dump lu, sf
w5:=w5-4,, ;
w2:=zd0,, ;
w1:=zdw,,cjs cwrite21 ; dump lm, ps
dumpregs1: ;
rdx:=7ff,,,crtn ; indicate dummyregs; return
.p ;
loadregs: ;
;; entry: w43=nbd=~process description
;; exit: w0= ra, w1,2,5,6 undefined
;; ra=register address
;; w7=nbd~.level
;; ir=300
;
w5:=w3+level,, ;
w6:=w4,,cjs creadbyte1 ;
w0:=w1,,push 2 ;
ra:=w0:=w0++w0,,rfct ; ra:=w0:=register address
w7:=w1,,cjs dumpregs ; w7:=nbd~.level; dumpregs(ra)
rdw:=w5:=w3,, ; pb, gf := nbd
w5:=w5+dumplm,, ;
zdx:=w6:=w4,,cjs cread21 ;
w5:=w5+4,, ;
zd0:=w2,, ;
zdw:=w1,,cjs cread21 ; load lm, ps
w5:=w5+4,, ;
rd0:=w1,, ; load lu, lf
zd:=w2,,cjs cread21 ;
rdx:=w2,, ; load ib, ic; now dr is cleared
rd:=w1,,crtn ; return
.p ;
;; usage of the registerset with base ramonitor:
;; zd0,zd1=zd0,zdw: ~actq(0)
;; zd2=zdx: n
;; zd3=zd: m
;; rd0: k
;; rd1=rdw: nxt
;; rd2,rd3=rdx,rd: dummy loop counter
;;
;; the active queue array is declared as
;; var actq: array(m..n) of addr,
;; where n>=0 and either
;; m < 0 and m <= k < 0 or else
;; m = 0 and k = -1.
;; if n=-1 then dummy looping is performed.
;; k may be changed by the time slice scheduler. if the time slice
;; scheduler is not a level 0 process then it must interrupt level 1
;; after having changed k.
;; k defines the priority sequence amongst the active queues as follows:
;; n, n-1, - - - , 0, k, -1, -2, - - - (not k) - - - , m.
;; nxt is used for scanning the active queues. it is reset to the value
;; n before starting scheduling. nxt=m-1 means dummy looping.
.p ;
dummyregs: ;dummyregs: (* from fetch when sib(0) *)
reg xor 7,s, ;
ra:=ramonitor,,, ;
q:=rd0,, ; q:=k
w0:=rd1,, ; w0:=w7:=nxt
ir:=c:=300,w7:=w0,, ;
zdx++,s,cjp not zro dci ; if reg<>7 then goto dummy clear
zd--w0,s,cjp zro sch20 ; if n=-1 then goto dummy loop
w0,s,cjp zro sch20 ; if nxt=m-1 then goto dummy loop
w0-q,s,cjp not b0 sch1 ; if nxt>=0 then goto ok
w0++,s,cjp not acy sch1 ; if nxt<k then goto ok
w0:=w0++,,cjp b0 sch1 ; w0:=w0+1; if nxt<-1 then goto ok
w0:=q,, ; w0:=k
sch1: ;ok:
w0:=<w0+w0,, ;
w6:=zd0,, ; w65:=~actq(w0)
w5:=zdw+w0,,cjs cread21 ; w21:=cread21(w65)
w2,s, ;
,,cjp not b1 sch10 ; if -,nill(w21) goto startlevel;
rdw:=w7--,,cjp sfetch ; nxt:=nxt-1; goto sfetch
;
sch10: ;; start level 0
;
,,cjs cread65 ; w65:=~first
w4:=w6,, ; nbd:=~first
w3:=w5,,cjs loadregs ; loadregs(nbd)
,,cjp sfetch ; goto sfetch
.p ;
sch20: ;; dummy loop counter
;
q:=rd++,s, ;
rd:=q,,cjp not acy sfetch ;
q:=rdx++,, ;
rdx:=q,,cjp sfetch ; goto sfetch
;
dci: ;; dummy clear interrupt
ra:=radummy,,, ;
rd0:=lev,, ;
w0:=rdw,, ;
rdw:=w0++,,cjp dci1 ;
;
;
.instruction sched ;
;; this instruction is executed on level 1 and it starts the
;; scheduling
;
ra:=ramonitor,,, ;
q:=zd2,, ; level1.nxt:=level1.n
rd1:=q,, ;
ra:=7,,, ;
,,cjs dumpregs ; dumpregs(0)
dci1: ;
,,cjs clear ; clear
ra:=reg,,cjp fetch0 ; goto fetch
;
;
.instruction cstdr ;
,,cjs readlucq ; nbd:=~process description
w3:=q,,cjs readlucq ;
w4:=q,,cjs loadregs ; loadregs(nbd)
w0:=w7,,cjs setlint ; setlint(nbd~.level)
ra:=reg,,cjp fetch0 ; goto fetch
.p ;
«eof»