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Names: »listhc01«
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Micro asm.: micasm01 version date.810804.1418
Source file: tcgorder010 version date.820426.1254
Object file: hcorder01 version date.820428.0906
*load: m2901
; -----------------------------------------------
; generel abrivations:
;
; msw = most significant word.
; lsw = least significant word.
; msh = most significant halfword.
; lsh = least significant halfword.
; mso = most significant octet.
; ino = intermidiate octet.
; lso = least significant octet.
; msb = most significatnt bit.
; lsb = least significatnt bit.
;
; C(<number>) = contents of memory location <number>,
; <number> can in this case also
; be a register.
;
; dot notation examples:
; wrk0.msh.lsb = bit 11 inwrk0 register.
; wrk0.lso.msb = bit 16 in wrk0 register.
;
; octet = 8 bits.
; halfword = 12 bits.
; word = 24 bit.
;
; the words is numbered so bit 0 is the most
; significant bit ( sign bit) and bit 23 is
; the least significant bit ( one bit).
; note: this is completely oposite from
; the normal rc8000 notation, but is
; due to some numbering facts in the bits
; bitslices.
; ------------------------------------------------
; -----------------------------------------
; 19810505:
; temporary the iccn bus is skipped
; with the skip construction 'iccnx',
; or 'iccn'.
; procedures only used by the iccn bus logic
; is also skipped.
; channel bus logic inserted.
; 810722/1600:
; status/interupt level fetch is changed,
; in module 'ansin'.
; only checked for rh2901.
; instead for two call of hlfwrd move
; subroutines the extraction of the interupt
; level is performed on the spot.
; constant 'hlfwdm1' declered for this
; purpose.
; 810722/1607:
; all occurences of the word octet is
; changed to octet.
; 810722/1645:
; the set disable/enable module is changed
; so halfword move subroutines is not called.
; 810722/1650:
; sobroutines 'hwmrtl' and 'hwmltr' is skipped
; with the controlwords 'hlfwds'.
; 810722/1650:
; return form interupt module is changed so
; half word move is not called, new entry
; in set level module.
; level is noe in intrupt level register
; and not in wrk0.
; 810723/1230:
; error corrected: interupt bit in intreg cleared
; in set disable module.
; error corrected: answer interupt calls set disable
; for exit
; module for control of interupt of lower level.
; 810730/1100:
; only relewant for hc2901.
; generel wait with x modification after fetch of
; instruction is deleted from the fetch routines.
; the generel wait logic is skipped out with
; the control word gewax.
; 810730/1130:
; only in rh8000.
; clock before and after evry channel output
; opration.
; 810730/1200:
; the subroutine entry for init orf wrk
; registers is changed so it continues
; directly to generel wait.
; init of wrk registers is introduced
; as seperate code in the init 2901
; sequence.
; 810803/1500:
; init from prom instead from local dma
; insertet in hc8000 text.
; 810805/1200:
; generel get instruction inserted
; to recieve level from external
; interupt devices. am9519.
; introduced as register 100,
; bu schould be changed to register
; 94. therefor the generel get instruction
; with effective address 94 schould only
; be allowed in monitor mode.
; 810807/1406:
; disarming of charakter interupt controler
; after interupt and arm after generel get 94.
;
; 810810/1749:
; no prefetch module changed so the subroutine
; call of ge03w0 is removed. this can be done
; in the rh2901 because the 2903 never sends
; a uneven instruction address.
; 810810/1750:
; all iccn bus logic and definition is now removed.
; the definition and the version up to this date
; can be found in the file 'ticcnbus'.
; 810814/1750:
; channel input/output logic changed, so it now
; accepts negative length buffers.
; 810824/0930:
; entry for external interupt fetch with a
; generel get instruction (gg 94) is inserted.
; 810824/0930:
; all generel get (gg) and generel put (gp)
; instrcution is allowed in rh8000, but
; their function is different.
; 810827/1500:
; dump of ic after evry instruction fetch
; introduced. gp 64 gives the address at which
; the dump schould start. gp 64 with the contents
; zero stops the dump.
; only in rh8000.
; 810903/1130:
; in rh8000 the start stop reset furnction send
; from hc8000 is changed so start after stop
; is a specific operation, and not mixed in with
; start interupt.
;NEXT
;--------------------------------------------------------
; ------------------------------------------------------
; project to be made in the future.
;
; 001: thre entry jump table schould be removed,
; and the hc2903 schould jump direcly to
; funtions mudoules wanted.
; before doing this subroutines and things
; which differ in length schoul be moved to
; the back of the program, so the rh and the hc
; version get the same entry addrress if possible.
; if that is not possible it dosent matter.
;
; 002: if it is decided to keep the entry jump table
; then some call of cl2903 schoud be moved up
; to the table.
;
; 003: it schould be tried to ballance the time
; from call of a memory acces to the acces
; is finished, so their is as little waste time
; as possible.
;
; 004: change of the interupt signal from the
; timer so it comes in as a seperate
; condition from the charakter device interupt.
; 005: check for parity error schould be performed
; after memory data out and memory data in
; the time out function in the memory data out
; and memory data in schould also be finishd.
;PROJECT:
;------------------------------------------------------
; -----------------------------------------
; helping logical table.
; after the operation
; sub(op1,op2) op1 - op2
;
; cjmp(neg,l) . op1 < op2
; cjmp(neg,l) not. op1 >= op2
; cjmp(zero,l) . op1=op2
; cjmp(zero,l) not. op1 <> op2
*const: metimo,200 ; no. of micro instructions before
; memory timeout.
*const: butimo,200 ; no of micro instructions before
*const: intimo,100 ; no. of micro instrcutions before
; time out for wait for
; pause signal in the amd9519
; interupt controler.
*const: sendto,4095 ; no of mic. instr. before sender
; reciever has send timeout.
*const: intsta,6 ; least significant bit in status reg that
; contains the interupt bits.
*const: rc80le,3 ; interupt from rc8000 level,
; same as timer interupt level.
*const: timele,3 ; timer interupt level - (1+3).
*const: chifil,4 ; channel input finis
; interupt level. ( 8)
*const: chisil,5 ; channel input start
; interupt level (9).
*const: chofil,6 ; channel output finis
; interupt level (10).
*const: lodmle,7 ; local dma interupt level.
*const: chdele,8 ; charakter device interupt level -(1+3).
*const: intno,9 ; no of allowed interupt bits
; in the interupt register.
*const: hlfwrd,11 ; halfword,
; no of bits - 1 in a half word.
*const: hfwdm1,10 ; halfword - 1,
; no of bits - 2 in halfword.
*const: octet,7 ; no of bits - 1 in a data octet.
*const: dyreno,7 ; number of allowed dynamic registers
; to be transferred to hc2903 - 1.
; power on logic starts microprogram in address 0
0000 e01ini/:jmp(init) ; program should start with a jump
; for hardware reasons
; also entry address of init from hc2903.
0001 jmp(dmain) ; entry micro program address 1.
0002 jmp(choint) ; address 2,
; channel out interupt.
0003 cont ; not used address 3.
0004 jmp(chiint) ; address 4,
; channel in interupt.
; entry address in hc2901 from hc2903
e01dob/: ; data out function jump table base.
0005 e01dom/:jmp(dowrme) ; write data word direct to memory.
0006 e01do0/:jmp(dontus) ; own dma start
0007 e01do1/:jmp(dochst) ; channel output start
0010 e01do2/:jmp(dontus) ; own dma reset.
0011 e01do3/:jmp(dochre) ; channel output reset.
0012 e01do4/:jmp(dochde) ; write external char device.
0013 e01do5/:jmp(dontus) ; data out not used.
0014 e01do6/:jmp(dontus) ; data out not used.
0015 e01do7/:jmp(dontus) ; data out not used.
e01dib/: ; data in functon jump table base.
0016 e01dim/:jmp(direme) ; read data word direct form memory.
0017 e01di0/:jmp(dintus) ; data in not used.
0020 e01di1/:jmp(dichst) ; channel input start.
0021 e01di2/:jmp(dintus) ; data in not used.
0022 e01di3/:jmp(dichre) ; channel input reset.
0023 e01di4/:jmp(dichde) ; read external chararcter device.
0024 e01di5/:jmp(dintus) ; data in not used.
0025 e01di6/:jmp(dintus) ; data in not used.
0026 e01di7/:jmp(dontus) ; data out not used.
0027 e01inp/:jmp(npref0) ; get instr with no prefetch
0030 e01ip/: jmp(prftc0) ; get instr with prefetch
0031 e01gmw/:jmp(rem0) ; get data word from memory.
0032 e01pmw/:jmp(wrm0) ; put data word to memory.
0033 e01gdw/:jmp(drem0) ; get double data word from memory.
0034 e01pdw/:jmp(dwrm0) ; put double data word to memory.
0035 e01rtc/:jmp(gng100) ; gg(100) get real time clock.
0036 e01rtr/:jmp(geng64) ; gg test register with no wait.
0037 e01wtr/:jmp(genp64) ; gp test register.
0040 e01rtw/:jmp(geng66) ; gg test register with wait.
; rh8000: wait start by rc8000, and send
; interupt register to hc2903.
0041 e01drd/:jmp(sadyre) ; entry save dynamic registers.
0042 e01sel/:jmp(stenle) ; entry set enable level.
0043 e01sdl/:jmp(stdile) ; entry set disable level.
0044 e01drr/:jmp(redyre) ; entry reestablish dynamic registers.
0045 e01rin/:jmp(rtrnpr) ; entry return to next process.
0046 e01aci/:jmp(ansin) ; entry answer and clear interupt.
0047 e01is1/:jmp(intser) ; entry goto interupt service 1.
0050 e01skn/:jmp(sknin0) ; entry skip next instruction and fetch.
0051 e01cil/:jmp(geng94) ; entry gg (94) get interupt level from
; amd9511 interupt controler,
; not on rh8000.
; init of wrk1, wrk2 and q reg before entr&ering
; generel wait loop.
; standard init of wrk registers is
; wrk0 = 0, but presently expected.
; wrk1 = 1.
; wrk2 = 8.
; q = 2.
; use of the working registers schold be
; done in the following order wrk0,wrk1,wrk2,q.
gewwri:
0052 iniwrk: mzero(wrk0) ; wrk0 := 0.
0053 moinc(wrk1,wrk0) ; wrk1 := 1.
0054 moinc(q,wrk1) ; q := 2.
0055 move(wrk2,q) sl ; wrk2 := 4.
0056 move(wrk2,wrk2) sl ; wrk2 := 8.
gewait: ; generel wait loop.
;===================
0057 cjmp(chioin,gewai1) not; if charakter interupt then goto
; gewwai1, this is done because
; the hc2903 cpu or the channel bus
; otherwise could delay the timer
; interupt. ( not used yet).
0060 cjvt(vect) and(wrk1,hc2903) noload noint opinde;
; hc2903 schould be addressed as source
; because this allowes the the clocking
; of the hc2903 data buffer into the
; vector prom, the hc2903 register no
; is equivalent with the register no
; of the internal register intreg so
; because intreg(0) tells if an
; interupt schold be send to the hc2903
; the alu operation will result in
; zero if no interupt an not zero if
; interupt, this is used in fetch
; and in prefetch.
0061 cjmp(chioin,gewait) ; if no interupt from char device then
; goto generel wait .
; if char device interupt then
0062 gewai1: moinc(wrk1,q) ; wrk1 := divice 1 + read bit.
0063 jsb(rechd0) ; call subroutine read char device
; special device 0 to 7.
; if sign bit set in the data word read
0064 cjmp(neg,timein) ; then goto timer interupt.
; disArment of first interupt controler.
0065 mzero(wrk1) ; wrk1 := 0.
0066 move(wrk0,q) ; wrk0 := const(2).
0067 lcpu(3) ; for 0 to 3 do
0070 move(wrk1,wrk1) sraq ; wrk1.msb := q.lsb.
0071 move(wrk1,wrk1) sraq ; wrk1.msb := q.lsb.
0072 rep move(q,wrk0) ; q := const(2).
; end.
0073 moinc(wrk0,wrk2) sl ; wrk0 := const(9) shift 1,
; control device no of first
; interupt controler.
0074 or(wrk1,wrk0) ; wrk1 := dataword + device address.
0075 jsb(wrchde) ; call subtroutine write charakter
; device.
0076 lcpu('chdele) ; counter := cha device interupt level.
0077 modec(wrk1,q) ; wrk1 := 1.
0100 jmp(clcint) ; goto calculate interupt .
; initialize.
; -----------
init:
0101 mzero(intreg) ; init of wrk registers.
; interupt bit register := 0.
0102 moinc(wrk1,intreg) ; wrk1 := intreg+1 ( 1).
0103 moinc(q,wrk1) ; q := wrk1 + 1 ( 2).
0104 move(wrk2,q) sl ; wrk2 := q*2 ( 4).
0105 move(wrk2,wrk2) sl ; wrk2 := wrk2*2 ( 8).
0106 mzero(intlev) ; clear current interupt level.
0107 mzero(intlim) ; clear disable level and
; enable level.
0110 mzero(dichwc) ; clear data in channel word counter.
0111 mzero(dochwc) ; clear data out channel word counter.
; init of channel interupt.
0112 cont firech ; clock finis read channel.
0113 cont fiwrch ; ckock finis write channel.
0114 cont clchii ; clear channel input interupt.
0115 cont clchoi ; clear channel output interupt.
;*skip: oldint
0116 move(lmem,wrk2) ; local dma memory address := 8.
0117 move(lwco,wrk2) sl ; local dma word counter := 16 ( 8 words.)
0120 lcpu(5) ;
0121 rep move(lwco,lwco) sl; lwco := 1 (segm ) * 256 (words)
; * 2 halfwords (lwco = 512)
0122 init7: cjmp(reldma,init7) not; wait for signal from local dma.
0123 init6: jsb(ipldma) ; call subroutne input local dma.
0124 cjmp(zero,init7) not; if lat word in memeory counter
; then goto continue init.
0125 jsb(waitst) ; call subroutine wait for test register.
; reset of first interupt controler.
0126 moinc(wrk1,wrk2) sl ; wrk1 := 9 shift 1.
0127 jsb(wrchde) ; goto write charakter device.
0130 init5: move(meaddr,wrk2) ; send address of word 8 to memory.
0131 init2: cjmp(re2903,init2) not; nb: for sync of memory,
; wait for hc2903 ready.
0132 init4: cjmp(rememo,init4) not; wait for ready of memory.
0133 move(hc2903,medata) ; send memory data to hc2903.
0134 jmp(gewwri) cl2903 ; goto generel wait
; and clock hc2903.
;*page: XX tcgorder01
; generel subroutine section
; --------------------------
; subroutine get a word from hc2903 to wrk0.
; ==========================================
0135 ge03w0: cjmp(re2903,ge03w0) not; wait until ready.
0136 rtn move(wrk0,hc2903) ; move word from hc2903 to wrk0.
; subroutine get a word from hc2903
; ==================================
; to wrk0 and memory address register,
; ===================================
; usualy called as : jmp(ge03a0) cl2903
0137 ge03a0: cjmp(re2903,ge03a0) not; wait loop until hc2903 is ready.
0140 rtn move(meaddr,hc2903) opramf; return from subroutine and
; move the word recieved from hc2903
; to the memory address register
; and start
; memory read cycle, and open for
; internal registers so the address
; also is moved to wrk0, ( does
; only function because the value
; the value of reg.address = the value
; of reg.wrk0 mod 16).
; subroutine divide wrk0 with 8 , 4 or 2.
;========================================
; entry call:
; q(23) = 0.
; their is no reasonto use divide by 2,
; as a subroutine call.
0141 divw08: move(wrk0,wrk0) sr ; wrk0 := wrk0 / 2.
0142 divw04: move(wrk0,wrk0) sr ; wrk0 := wrk0 / 2.
0143 divw02: rtn move(wrk0,wrk0) sr; wrk0 := wrk0 / 2.
; end of generel subroutine section.
; ----------------------------------
;*page: XX
; read memory section.
; --------------------
; read data word from memory to hc2903.
; ------------------------------------
0144 rem0: jsb(ge03a0) cl2903 ; clock the hc2903, and call subroutine
; to get address of data word to
; to memory and wrk0 (not used here).
0145 cont ; nb: sync of memory.
0146 rlt2: cjmp(rememo,rlt2) not ; wait until memory ready
0147 move(hc2903,medata) cl2903; move data from memory to hc2903.
0150 jmp(gewait) ; goto wait cyclus.
; read double word from memory to hc2903.
; ---------------------------------------
; to get address of data word with
; control of address 66.
0151 drem0/: jsb(ge03a0) cl2903 ; clock hc2903, and call subroutine
; to get address of data word to memory
; and start memory read cycle.
0152 negadd(wrk0,q) ; wrk0 := address of second data word
; ( wrk0 - 2).
0153 drlt2: cjmp(rememo,drlt2) not; wait for first address fecth is ready.
0154 move(hc2903,medata) cl2903; hc2903 := memory'first data word,
; and clock hc2903.
0155 move(meaddr,wrk0) ; memory'address := second word address.
0156 drlt4: cjmp(re2903,drlt4) not; wait forhc2903.
0157 drlt3: cjmp(rememo,drlt3) not; wait for memory address cycle.
0160 move(hc2903,medata) cl2903; hc2903 := memory'second data word,
; clock hc2903.
0161 jmp(gewait) ; clock hc2903, goto wait cycle.
; end of read memory section
; --------------------------
; write memory section
; ---------------------
; write to memory from hc2903.
; ----------------------------
0162 wrm0/: jsb(ge03a0) cl2903 ; clock hc2903, and call subroutine
; to get address of data word to
; memeory address register and
; to wrk0.
0163 cont cl2903; clock ready for data word.
0164 wlt3: cjmp(re2903,wlt3) not ; wait for memory data word.
0165 wlt2: cjmp(rememo,wlt2) not ; wait for memory ready
0166 move(medata,hc2903) cl2903; memory := hc2903.data, clock ready
; the hc2903.
0167 cont ; sync of memory
0170 wlt4: cjmp(rememo,wlt4) not ; wait for memory write cycle.
0171 jmp(gewait) ; goto wait cyclus.
; write double word to memory from hc2903.
; ----------------------------------------
0172 dwrm0/: jsb(ge03a0) cl2903 ; clock hc2903, and call subroutine to get
; to get address of data word to
; memory address register and wrk0.
0173 negadd(wrk0,q) cl2903; wrk0 := wrk0 - 2, ( calc. of
; next memory addrs., clock hc2903 ready
; for recieve data word.
0174 dwlt3: cjmp(re2903,dwlt3) not; wait for ready hc2903.
0175 dwlt5: cjmp(rememo,dwlt5) not; wait for memory ready.
0176 move(medata,hc2903) cl2903; memory := hc2903'data.
; clock hc2903 ready.
0177 cont ; nessecary fo sync of
; memory.
0200 dwlt4: cjmp(rememo,dwlt4) not; wait for memory ready.
0201 move(meaddr,wrk0) ; memory'address := calculated
; next address.
0202 jmp(wlt3) ; goto last of write single word
; to memory for continuation.
; end of write memory section.
; ----------------------------
;*page: XX
; fetch instruction section.
; --------------------------
; after one of the fetch entries
; contains pir ( prefetched instruction)
; the next instrcution and ic the address of the next
; after pir.
; fetch instruction with no prefetch.
; -----------------------------------
; subroutine send interupt to hc2903.
; -----------------------------------
sndint:
0203 rtn intr03 ; return and set interupt bit to
; hc2903.
0204 npref0/:and(wrk1,intreg) noload; temporary test entry.
0205 nprftc/:cjsb(zero,sndint) not cl2903; normal no prefetch entry:
; if intreg(23) = 1
; (i.e. interupt bit set
; then call subroutine send interupt,
; clock hc2903 ready to accept data.
0206 npref1: cjmp(re2903,npref1) not; wait for ic from hc2903.
0207 move(meaddr,hc2903) opramf; move the address to memory and start
; memory addres cycle, and open for
; internal registers so the address
; also is moved to
; to work 0. (does only function because
; the value off reg.addrs = the value
; of reg.wrk0 mod 16 ).
0210 sknin1: move(ic,q) ; entry from skip next,
; sync. of memory, ic := 2 .
; ( prepered for calculation of
; next next instr in prefetch logic.)
0211 npref2: cjmp(rememo,npref2) not; wait for memory address cycle.
0212 move(hc2903,medata) cl2903; move memory data word to hc2903,
; and clock hc2903.
0213 add(wrk0,q) opexde ; wrk0 := wrk0 + 2, wrk0 is now
; pointing to next instruction,
; open also to extern registers
; which will cause a move of
; wrk0 to memory address register
; and start memory read cycle.
0214 add(ic,wrk0) ; calculate address of next instr.
0215 npref3: cjmp(rememo,npref3) not; wait for memory ready.
0216 move(pir,medata) ; move prefetched instruction to
; prefetch register from memory.
0217 jmp(gewait) ; goto wait cycle.
; skip next instrcution.
; entry for skip instructions.
; ============================
0220 sknin0/:and(wrk1,intreg) noload; temporary test entry:
0221 sknins/:cjsb(zero,sndint) not ; if bit(23) intreg = 1 then goto
; send interupt to hc2903.
0222 move(wrk0,ic) opexde ; move address of next instr to wrk0,
; open also
; the external registers which will
; cause a move of wrk0 to the memory
; address register and start a read
; cycle.
0223 jmp(sknin1) ; continue in fetch next instruction
; with no prefetch.
; get prefetched instruction.
; ----------------------------
0224 prftc0/:and(wrk1,intreg) noload; temporary test entry:
0225 prftch/:cjsb(zero,sndint) not ; normal entry for prefetch next
; instruction:
; if intreg(23)<>0 (i.e.
; interupt set) then call subroutine
; set interupt.
0226 move(hc2903,pir) cl2903; move prefetched instrcution to
; hc2903 and clock ready.
0227 move(meaddr,ic) ; move address of next prefetched
; instruction
; to memory.
0230 add(ic,q) ; calculate address of next instruction
; to be prefetched.
0231 prftc1: cjmp(rememo,prftc1) not; wait for memory address cycle.
0232 move(pir,medata) ; move prefetched instruction from memory
; to prefetch register.
0233 jmp(gewait) ; goto wait cycle.
; end fetch instruction section
; -----------------------------
; write data in testregister. Startaddress by hardware.
; -----------------------------------------------------
0234 genp64: jsb(ge03w0) cl2903 ; call subroutine to get word to wrk0,
; and clock hc2903.
0235 move(tstreg,wrk0) cl2903; testregister:= wrk0 (hc290.data)
0236 jmp(gewait) ; goto generel wait.
; Wait manual test and read testreg.
geng66:
0237 jsb(waitst) ; call subroutine wait test register.
geng64: ; entry generel get with no wait.
0240 lab5: move(hc2903,tstreg) cl2903; move test register to hc2903,
; clock hc2903 ready.
0241 jmp(gewait) ; goto generel wait.
; subroutine wait manuel signal from test register.
; -------------------------------------------------
0242 waitst: cjmp(tstrdy,waitst) not; wait for test register in read mode.
0243 waits1: cjmp(tstrdy,waits1) ; wait for test register in write mode.
0244 rtn ; return from subroutine.
; get real time clock, genereal get 100.
;---------------------------------------
; real time clock is not fixed yet. 800505
; real time clock is there for used for different test
; purposes.
0245 gng100: move(hc2903,intreg) cl2903; move contents of real time clock
0246 jmp(gewait) ; to hc2901, goto generel wait.
; get interupt level from external interupt device.
; generel get 94.
; -------------------------------------------------
; when an internal interupt is detected the
; true level can be optaind with gg 94.
; see: advanced micro device 9519 for
; detailed and complete description.
geng94:
; arm first interupt controler.
; create data word for arming.
0247 move(wrk0,q) ; wrk0 := const(2).
0250 move(q,wrk1) ; q := const(1).
0251 lcpu(3) ; for 0 to 3 do begin
0252 move(wrk1,wrk1) sraq ; wrk1.msb := q.lsb.
0253 move(wrk1,wrk1) sraq ; wrk1.msb := q.lsb.
0254 rep move(q,wrk0) ; q := cost(2).
; end.
0255 moinc(wrk0,wrk2) sl ; wrk0 := const(9) shift 1,
; device address of first
; interupt controler.
0256 or(wrk1,wrk0) ; wrk1 := data word + device address.
0257 jsb(wrchde) ; write charakter device for disarment
; of interupt controler.
0260 modec(wrk1,q) ; wrk1 := const(1).
0261 move(extreg,wrk1) oprama opdirz trnbus readch;
; start read device 0, without selecting of
; timer device.
0262 push move(extreg,wrk1) oprama opdirz trnbus readch clexde;
; push next micro instr and start read
; device 0, send iack puls to interupt
; controler.
0263 loop(wainle) move(extreg,wrk1) oprama opdirz trnbus readch clexde;
; repeat read and sen iack pulse to
; interupt controler until pause signal
; from the interupt controler is finished.
0264 move(extreg,wrk1) oprama opdirz clexde trnbus readch;
; read response level from interupt controler.
; amd9519 interupt controler
; to answer.
; read level from external device bus.
; into mso of wrk1.
0265 mzero(q) ; clear q register.
0266 lcpu(7) ; for 0 to 7 do
0267 rep move(wrk1,wrk1) slaq; q.lsb := wrk1.msb.
0270 move(hc2903,q) cl2903 ; send data word to hc2903.
0271 jmp(gewwri) ; goto generel wait.
;*page: XX
; set interupt bit in interupt register.
; ------------------------------------
; call :
; wrk1 = std init 1.
; wrk2 = std init 2.
; q = std init 2.
timein: ; timer interupt.
0272 add(wrk1,q,wrk1) ; wrk1 := 2 shift 1 + 1.
0273 jsb(rechd0) ; call subroutine read char device no 0
; to 7.
0274 modec(wrk1,q) ; wrk1 := 1.
0275 ldct(timele) ; load counter with timer interupt
; level.
0276 clcint: jsb(clcin1) ; push address of next micro instr.
0277 clcin1: move(wrk2,wrk2) sl ; wrk2 := wrk2 * 2, ( interupt bit).
0300 rep inc(wrk1) ; wrk1 := wrk1 + 1 ( interupt no ).
enin03: ; entry for interupt bit 0, interupt 3,
; or entry with initialised interupt
; values in wrk1 (interupt no) and
; wrk2 ( the interupt bit in the
; interupt register).
0301 add(wrk1,q) ; wrk1 := wrk1 + q ( the first inetrupt
; no is infact level 3).
; entry intrs1:
; entry when wrk2 and wrk1 is defined.
0302 intrs1: or(intreg,wrk2) ; set interupt bit in interupt register.
0303 sub(wrk1,intlev) noload; if interupt no > current interupt
0304 cjmp(neg,gewwri) not ; level then goto generel wait.
0305 intsr2: move(intlev,wrk1) ; interupt level := interupt no as
; new level.
0306 modec(wrk0,q) ; wrk0 := 1 ( bit 23).
0307 or(intreg,wrk0) ; intreg(23) := 1 ( interupt schold
; be send to hc2903).
0310 jmp(gewwri) ; goto general wait.
; answer interupt cause and clear interupt bit
;=============================================
; in interupt register, continue in interupt
; service.
; interupt cause is current level.
; call:
; wrk0,wrk1,kwr2,q = std. reg. init.
0311 ansin/: move(hc2903,intlev) cl2903; send level to hc2903, and clock
; hc2903 ready to recieve data.
0312 negadd(intlev,q) ; justifi intlev because the
0313 dec(intlev) ; first interupt bit corrospond
; with intlev 3.
0314 ansin3: andinv(intreg,wrk2) ; clear interupt bit.
0315 move(wrk2,wrk2) sl ; wrk2 := wrk2 * 2 (next interupt bit).
0316 dec(intlev) ; intlev := intlev - 1.
0317 cjmp(neg,ansin3) not ; if interupt level > 0 then got ansin3.
0320 jsb(ge03a0) ; call subroutine to get address
; of status and interupt limit
; initialisation and start memory
; ready cycle.
0321 jmp(intse4) ; continue in interupt service 4.
; interupt service.
;==================
0322 intser/:jsb(ge03a0) cl2903 ; call subroutine to get address to wrk0
; and memory address register and start
; memory read cycle, ( wrk0 := inf )
0323 intse4: move(wrk2,wrk0) ; wrk2 := wrk0 ( inf ).
; this mic. instr is nessecary for memory
; syncronitation.
0324 andinv(intreg,wrk1) ; clear possible interupt bit in
; interupt register.
0325 moinv(wrk0,wrk1) sr ; start make bit in last halfword.
; wrk0 := -1 ( all bits) shift -1.
0326 lcpu(hfwdm1) ; load counter with no of bits in
; a halfword minus 1 ( first shift
; made when negating wrk1 into wrk0).
0327 rep move(wrk0,wrk0) sr; repeat until counter = 0 do
; wrk0 := wrk0 shift -1.
; counter := counter -1.
; end.
0330 intse1: cjmp(rememo,intse1) not; wait for memory ready cycle.
0331 move(hc2903,medata) cl2903; send status/intlim to
; hc2903 data register
; and clock hc2903.
0332 move(intlim,medata) ; intlim := status/intlim.
0333 add(meaddr,q,wrk2) ; send wrk2 + 2 (inf + 2)
; to memory address
; and start memory read cycle.
0334 and(intlim,wrk0) ; intlev := intlev(12:23),
; only last 12 bits contain
; interupt limit.
0335 move(intlev,intlim) ; interupt level := interupt limit.
0336 negadd(wrk2,q) ; nessecary for sunc of memory,
; wrk2 (inf) := wrk2 - 2.
0337 dec(wrk2) ; wrk2 := wrk2 -1.
; ( totaly inf := inf - 3).
0340 intsw2: cjmp(re2903,intsw2) not; wait for hc2903.
0341 intse2: cjmp(rememo,intse2) not; wait for memory ready.
0342 move(hc2903,medata) cl2903; send reg. dump. addr to hc2903,
; and clock hc2903 ready
0343 move(wrk1,medata) ; wrk1 := reg. dump. addrs.
0344 jsb(dmp8w) ; call subroutine to dump 8 words from
; hc2903 to memory, first word addresed by
; by wrk1.
0345 move(meaddr,wrk2) ; sedn addres of new ic to memory.
0346 intsw3: cjmp(re2903,intsw3) not; wait for hc2903 ready.
; ness. sync. of mem.
0347 intse3: cjmp(rememo,intse3) not; wait for memory ready.
0350 move(hc2903,medata) cl2903; send new ic to hc2903,
; and clock hc2903 ready.
0351 jmp(stdil3) ; continue in set disable level
; entry 3, for control of
; possible interupts with
; lover level.
; set current interupt level.
; -----------------------------
; entry select interupt enable level.
; disable level and enable level is in intlim register.
; current level is intlev register.
; entry call:
; wrk1 := 1.
; q := 2.
0352 stenle/:moinv(intlev,wrk1) sr cl2903; intlev := -1 (allbits) shift -1,
; clock hc2903 ready.
0353 lcpu('hfwdm1) ; load counter with no of
; bits in a halfword minus 1, and
; push next micro instr address.
0354 rep move(intlev,intlev) sr; intlev := intlev(0:11), all bits
; in rigth halfword.
0355 and(intlev,intlim) ; interupt level := enable level.
0356 jmp(stdil1) ; goto set disable level entry 1.
0357 stdile/:move(intlev,intlim) sr cl2903; intlev := interupt limit,
; clock hc2903 ready.
0360 lcpu('hfwdm1) ; load counter with no of bits
; in half word and push next address.
0361 rep move(intlev,intlev) sr; interupt limit := interupt limit(0:11).
; ( disable level).
stdil1:
stdil2: ; entry from return from interupt.
0362 andinv(intreg,wrk1) ; clear possible interupt bit.
stdil3: ; entry from answer interupt.
0363 move(wrk1,q) ; wrk1 := q (2).
0364 move(wrk2,wrk1) sl ; wrk2 := wrk1*2 (4).
0365 lcpu('intno) ; load counter with max no of interupt
; allowed.
0366 inc(wrk1) ; wrk1 := next interupt no.
0367 move(wrk2,wrk2) sl ; wrk2 := next interupt bit.
0370 and(intreg,wrk2) noload; if interupt bit is set then
0371 cjmpp(zero,intsr2) not; pop counter and goto intse2 ( entry
; in interupt routine.
0372 sub(wrk1,intlev) noload; if interupt no > new level then
0373 twb(neg,gewwri) not ; pop counter and continue in next
; micro instr, else invistigate
; next interupt bit while not all interupt
; is examinied.
0374 jmp(gewwri) ; goto generel wait.
; entry function restore 8 dynamic registers to hc2903.
; -----------------------------------------------------
0375 redyre/:jsb(ge03w0) cl2903 ; get address of first dynamic register.
; into w0.
0376 jsb(lodyre) ; call subroutine load dynamic registers.
0377 jmp(gewait) ; goto generel wait.
; subroutine load 8 registers.
; ----------------------------
0400 lodyre: ldct('dyreno) ; load counter with no of dynamic register
; entry load any number of registers,
; from hc2901 to hc2903.
0401 lonore: jsb(lonor1) ; push address of next micro instr.
0402 lonor1: move(meaddr,wrk0) ; send wrk0 to memory address regsiter and
; start memory read cycle.
0403 add(wrk0,q) ; memory address pointer := memory
; address pointer + 2.
0404 redyr1: cjmp(re2903,redyr1) not; wait until hc2903 is ready.
0405 redyr2: cjmp(rememo,redyr2) not; wait for memory ready.
0406 rep move(hc2903,medata) cl2903; move word from memory to hc2903,
; clock hc2903 ready, repeat loop.
0407 rtn ; return from subroutine.
; entry function return from interupt select next process registers.
; ------------------------------------------------------------------
0410 rtrnpr/:jsb(ge03a0) cl2903 ; get address of system table
; register dump addressfrom hc2903
; to memory and start read cycle.
0411 cont ; sync of memory.
0412 rtnnp2: cjmp(rememo,rtnnp2) not; wait for memory ready.
0413 move(hc2903,medata) cl2903; send reg dump address to hc2903.
0414 move(wrk0,medata) ; get register dump address to wrk0.
0415 jsb(lodyre) ; call subroutine load dynamic registers.
0416 rtnnp3: cjmp(re2903,rtnnp3) not; wait for hc2903 to recieve address
; of process definition registers.
0417 move(wrk0,hc2903) ; move address of register definition
; registers to wrk0.
0420 ldct(3) ; load counter with number of process
; definition registers.
0421 jsb(lonore) ; call subroutine load nomber of
; registers.
0422 move(meaddr,wrk0) ; send wrk0 to memory address.
0423 moinv(intlev,wrk1) sr ; intlev := -1 ( all bits) shift -1.
0424 lcpu('hfwdm1) ; load counter with no of bits in
; a halfword minus 1, and push
; next address.
0425 rep move(intlev,intlev) sr; intlev := intlev(0:11)
; all last 12 bit set.
0426 rtnnp4: cjmp(rememo,rtnnp4) not; wait for memory ready.
0427 move(intlim,medata) ; load interupt limit.
; set enable level.
0430 and(intlev,intlim) ; intlev := intlim(12:23).
; last halfword of interupt limit.
0431 jmp(stdil1) ; goto set disable level entry 1.
; entry functionsave 8 dynamic registers.
; ---------------------------------------
0432 sadyre/:jsb(ge03w0) cl2903 ; get address whereto the registers
; is to be written.
0433 move(wrk1,wrk0) cl2903; wrk1 := wrk0, clock hc2903 to continue.
0434 jsb(dmp8w) ; call subruotine to dump 8 words
; from hc2903 .
0435 jmp(gewwri) ; goto generel wait with init.
; subroutine dump 8 words from hc2903 to memory.
; entry wrk1 := address.
; entry q := 2.
0436 dmp8w: lcpu('dyreno) ; load counter with number of
; registers to be saved, and clock hc2903
; ready to accept 1. data word.
; repeat:
0437 move(meaddr,wrk1) ; send address of data word to be
; dumped to memory address register
; and start memory write cycle.
; of dumped word to memory address
; and start memory write cycle.
0440 dmp8w1: cjmp(re2903,dmp8w1) not; wait until hc2903 ready to send data
; word.
0441 dmp8w2: cjmp(rememo,dmp8w2) not; wait for memory write cycle.
0442 move(medata,hc2903) cl2903; send data word from hc2903 to memory,
; and clock hc2903 ready to accept
; next data word.
0443 cont ; sync. of memory.
0444 dmp8w3: cjmp(rememo,dmp8w3) not; wait for memory ready.
0445 rep add(wrk1,q) ; increase memory address pointer
; by to and repeat loop.
0446 rtn ; return from subroutine.
; data in and data out section.
; -----------------------------
; time out and other exceptions to hc2903.
; =========================================
; time out from data in and data out.
; -----------------------------------
0447 iotmo0: cont cl2903 ; clock hc2903 for dummy address.
0450 iotmw0: cjmp(re2903,iotmw0) not; wait for hc2903 ready.
0451 iotmo1: cont cl2903 ; send dummy data word to hc2903.
0452 iotmw1: cjmp(re2903,iotmw1) not; wait for hc2903 ready.
0453 iotmo2: move(hc2903,q) cl2903; send status bit 2 ( time out )
; to hc2903
0454 jmp(gewwri) ; goto general wait.
; entry for not used data in and dataout instructions.
dintus: ; data in functions not used.
dontus: ; data out functions not used.
; bus comunication error in data in and data out.
; -----------------------------------------------
0455 bucoe0: cont cl2903 ; clock hc2903 and wait.
0456 bucow0: cjmp(re2903,bucow0) not; wait for ready.
0457 bucoe1: cont cl2903 ; clock hc2903 for dummy data word.
0460 bucow1: cjmp(re2903,bucow1) not; wait for ready.
0461 bucoe2: cont cl2903 ; clock hc2903 for data word recieve.
0462 bucow2: cjmp(re2903,bucow2) not; wait for hc2903 to accept status word.
0463 bucoer: move(hc2903,wrk1) cl2903; send a one or what ever the
; contents of wrk1 is as status word
; to hc2903 and clock
; the hc2903 ( the bus communication
; error bit).
0464 jmp(gewwri) ; goto general wait with init.
; normal answer from data in and data out.
; ----------------------------------------
0465 noran0: cont cl2903 ; clock hc2901 for dummy addrs.
0466 noraw0: cjmp(re2903,noraw0) not; wait for hc2903 ready to send addrs.
0467 noran1: cont cl2903 ; clock hc2903 , for dummy
; address word.
0470 noraw1: cjmp(re2903,noraw1) not; wait for hc2903to send data.
0471 noran2: cont cl2903 ; return data word to hc2901 and wait.
0472 noraw2: cjmp(re2903,noraw2) not; wait for hc2901 to accept data word
; and be ready to accept status bits.
0473 norans: mzero(hc2903) cl2903 ; send a zero to hc2903 indicating
; that no exceptions bit are set.
0474 jmp(gewwri) ; goto generel wait with init.
; subroutine wait for hc2903.
0475 wa0300: cjmp(re2903,wa0300) not; wait for hc2903
0476 cont cl2903 ; clock hc2903
0477 wa0301: cjmp(re2903,wa0301) not; wait for hc2903
0500 rtn ; return form subroutine.
; subroutine get device block address.
; ------------------------------------
; call w0 = divice no*8.
; wrk2 = 8.
0501 gedvbl: move(meaddr,wrk2) ; start memeory read cycle in word 8.
0502 gedvb1: cjmp(rememo,gedvb1) not; wait for memory ready.
0503 move(wrk1,medata) ; get device base.
0504 add(wrk0,wrk1) ; wrk0 := wrk0 ( device no * 8) +
; device address base.
0505 rtn modec(wrk1,q) ; wrk1 := 1, return .
; subroutine write character device, no 0 to 7.
; ==================================
; wrk1 = data octet shift 16 + device address shift 1 + 0.
;
0506 wrchd0: cjmp(chiosy,wrchd0) not; wait for char io clock tom go
; low.
0507 wrchd7: cjmp(chiosy,wrchd7) ; wait for char io clock to go
; high. (now it is syncroniced
; with the data bus clock pulse).
0510 sync ; wait for syncr.
0511 move(extreg,wrk1) writch sltiml; sync
0512 move(extreg,wrk1) writch sltiml; send data and address to
0513 move(extreg,wrk1) writch sltiml; char io bus register and
0514 move(extreg,wrk1) writch sltiml; set clok external device signal
0515 move(extreg,wrk1) writch sltiml; (valid memory address in
; motorola
0516 move(extreg,wrk1) writch sltiml;
; terminology) 4 times,
; clear the
0517 rtn move(extreg,wrk1) writch sltiml; return after a addressing
; sending the addres out
; on the bus with out clocking
; the external device.
; read bit and return
; from subroutine.
; subroutine read character divice, for dev. no 0. to 7.
; =================================
; wrk1 = data octet shift 16 + divice address shift 1 + 1.
;
0520 rechd0: cjmp(chiosy,rechd0) not; wait for char io clock to go low.
0521 rechd7: cjmp(chiosy,rechd7) ; wait for char io clock to go high.
0522 sync ; wait for syncronation.
0523 move(extreg,wrk1) opdirz oprama sltiml trnbus; sync. and start signal.
0524 move(extreg,wrk1) opdirz oprama sltiml trnbus
; send divice and read bit to
; char io bus and clock the bus,
; open for direct and zero input to
; the alu, and open for wrk1 as des
; destination, four times.
0525 move(extreg,wrk1) opdirz oprama sltiml trnbus;
0526 move(extreg,wrk1) opdirz oprama sltiml trnbus;
0527 move(extreg,wrk1) opdirz oprama sltiml trnbus;
0530 rtn move(extreg,wrk1) noload sltiml trnbus;
; return from subroutine.
; subroutine write character device.
; ==================================
; wrk1 = data octet shift 16 + device address shift 1 + 0.
;
0531 wrchde: cjmp(chiosy,wrchde) not; wait for char io clock tom go
; low.
0532 wrchd1: cjmp(chiosy,wrchd1) ; wait for char io clock to go
; high. (now it is syncroniced
; with the data bus clock pulse).
0533 sync ; wait for sync.
0534 move(extreg,wrk1) writch; sync. and start signal.
0535 move(extreg,wrk1) clexde writch; send data and address to
0536 move(extreg,wrk1) clexde writch; char io bus register and
0537 move(extreg,wrk1) clexde writch; set clok external device signal
0540 move(extreg,wrk1) clexde writch; (valid memory address in motorola
0541 move(extreg,wrk1) clexde writch; terminology) 4 times , clear the
; read bit .
0542 rtn move(extreg,wrk1) writch; sync addressing of external
; bus and return.
; subroutine read character divice.
; =================================
; wrk1 = data octet shift 16 + divice address shift 1 + 1.
;
0543 rechde: cjmp(chiosy,rechde) not; wait for char io clock to go low.
0544 rechd1: cjmp(chiosy,rechd1) ; wait for char io clock to go high.
0545 sync ; wait for syncronation.
0546 move(extreg,wrk1) opdirz oprama readch trnbus; sync. and start
; signal.
0547 move(extreg,wrk1) clexde opdirz oprama readch trnbus
;send divice and read bit to
; char io bus and clock the bus,
; open for direct and zero input to
; the alu, and open for wrk1 as des
; destination, four times.
0550 move(extreg,wrk1) clexde opdirz oprama readch trnbus;
0551 move(extreg,wrk1) clexde opdirz oprama readch trnbus;
0552 move(extreg,wrk1) clexde opdirz oprama readch trnbus
0553 rtn move(extreg,wrk1) noload readch trnbus;
; retrun from subroutine.
; data out, write data word in own memory.
; ----------------------------------------------
0554 dowrme: jsb(ge03a0) cl2903 ; clock hc2903 and call subroutine to get
; get address of memory word.
0555 cont cl2903 ; clock hc2903 to accept data word.
0556 dowmw3: cjmp(re2903,dowmw3) not; wait for hc2903 ready sen data word.
0557 dowmw2: cjmp(rememo,dowmw2) not; wait for memory ready.
0560 move(medata,hc2903) ; move data word to memory data register.
0561 lcpu('metimo) ; load counter and pusch next micro instr.
; into micro stack.
0562 twb(rememo,iotmo2) ; repeat
; if counter = 0 then goto iotmo1.
; micro counter := micro counter.
; until memory ready.
0563 jmp(noraw1) ; goto normal answer, ( wait for data
; ready).
; data in, read data word from memory.
; ----------------------------------------
0564 direme: jsb(ge03a0) cl2903 ; clock hc2903, and call subroutine
; to get word from hc2903 to memory
; address register and clock memory.
0565 lcpu('metimo) ; load micro counter with
; 200 and push next micro instr to
; micro stack.
0566 twb(rememo,iotmo0) ; wait for memory ready 200 cycles.
; if not memory ready then goto iotmo0.
0567 jsb(wa0300) ; call subroutine to accept dummy
; data word and wait ready.
0570 move(hc2903,medata) cl2903; move data word to hc2903, and clock
; hc2903.
0571 jmp(noraw2) ; goto normal answer with 1 wait.
; data out, write external character device.
; --------------------------------------------
; entry gendo4.
0572 dochde: jsb(ge03w0) cl2903 ; clock hc2903, and call subroutine
; to device no into wrk0.
; if dev no < 8 ).
0573 jsb(divw08) ; call subroutine to divide wrk0 by 8
; to get rigth address.
0574 move(wrk1,wrk0) sl ; wrk1 := wrk0 shift 1 ( bit 0 = 0 signifi
; write function ).
0575 negadd(wrk2,wrk0) ; wrk2 := dev no - 8. (result used to
; test which dev write routine to
; be used).
0576 jsb(ge03w0) cl2903 ; call subroutine to get data word into
; wrk0.
0577 lcpu('octet) ; load counter with length of data
; octet.
0600 rep move(wrk0,wrk0) sraq; q(0..8) := wrk0(16.23) ( shift data
; octet into q reg as the most significant
; octet).
0601 or(wrk1,q,wrk1) ; wrk1 := q ( data) or wrk1 ( device addrs
; addrs +device funtion).
0602 move(wrk2,wrk2) ; if wrk2 < 0 then goto
0603 cjmp(neg,dochd1) ; dochd1.
0604 jsb(wrchde) ; call subroutine write char. devices.
; dev no from 8 , 9 , 10 ......
0605 jmp(noran2) ; goto send normal answer, with 1 wait.
0606 dochd1: jsb(wrchd0) ; call subroutine write char devices,
; dev. no from 0 to 7.
0607 jmp(noran2) ; goto normal answer, with 1 wait.
; data in, read external character device.
; ----------------------------------------
; entry gendi4.
0610 dichde: jsb(ge03w0) cl2903 ; clock the hc2903, and call subroutine
; to get divice no into wrk0.
0611 jsb(divw08) ; call subroutine to divide address
; by 8 to get rigth device address.
0612 negadd(wrk2,wrk0) ; wrk2 := dev no - 8 ( used to
; find out which read routine to be
; used).
0613 move(wrk0,wrk0) sl ; wrk0 := device address shift 1.
0614 or(wrk1,wrk0) ; wrk1 := device address shift 1 + 1
; (signifieng the read bit).
0615 move(wrk2,wrk2) ; if wrk2 < 0 then goto
0616 cjmp(neg,dichd1) ; dichd1.
0617 jsb(rechde) ; call subroutine read char device.
0620 dichd2: mzero(q) ; q reg := 0.
0621 lcpu('octet) ; load counter with octet length.
0622 rep move(wrk1,wrk1) slaq; q(16.23) := data octet.
0623 jsb(wa0300) ; call subroutine to accept dummy
; word.
0624 move(hc2903,q) cl2903 ; send data octet to hc2903, and
; clock hc2903 ready.
0625 jsb(noraw2) ; goto normal answer with 1 wait.
0626 dichd1: jsb(rechd0) ; call subroutine read char dev
; dev no 0 to 7.
0627 jmp(dichd2) ; goto send data word back to hc2903.
; section channel input output.
; =============================
; data out, channal reset.
0630 dochre: mzero(dochwc) ; reset data out word counter.
0631 jmp(noran0) ; goto normal answer.
; NOTE: after the resetting it
; is possibly that
; a data out finis interupt
; will be given.
; data out, channel start.
; ------------------------
dochst/:
0632 move(dochwc,dochwc) cl2903; clock hc2903 ready to recieve
; address,
; if word counter <> 0 then
0633 cjmp(zero,bucow0) not ; then goto bus cummunication error.
0634 dochw1: cjmp(re2903,dochw1) not; wait for hc2903 ready to sned address.
0635 move(wrk0,hc2903) cl2903; wrk0 := address, clock hc2903 ready
; to recieve data word.
0636 dochw2: cjmp(re2903,dochw2) not; wait for hc2903 to revieve data word.
0637 move(dochwc,hc2903) cl2903; get data word form hc2903, clock
; hc2903 ready to accept not used
; data word.
0640 negadd(dochwc,q) noload; if word counter < 2 then
0641 cjmp(neg,dochs3) ; then goto dochs3, ( send message).
0642 jsb(gedvbl) ; call subroutine to get device block
; address.
0643 add(wrk0,q) ; divice block address := device
; block address + 2.
0644 move(meaddr,wrk0) ; send adrress of word counter to
; memory and start read cycle.
0645 dochs1: cjmp(rememo,dochs1) not; wait for memory ready.
0646 move(dochad,medata) ; get channel block address.
0647 sub(dochad,wrk2) noload; if address of data block < 8
0650 cjmp(neg,bucow2) ; then goto bus communication error.
0651 move(chdata,dochwc) ; send channel output word counter
; to channal data buffer as first
; word.
0652 add(dochwc,q) ; data out channel word counter :=
; data out channel word counter +2,
; (after a subtraction by 2 in start of
; channel input interupt fetch, docchwc
; contain the number of bytes left to send,
; i.e. dochwc gives the no of bytes which
; their is not recieved a interupt answer
; for, that includes the first control word.)
0653 jmp(noraw2) ; goto normal answer 1.
dochs3: ; entry word counte < 2.
; only word counter is send.
0654 cont stwrch ; clock start write channel.
0655 move(chdata,dochwc) ; send word counter.
0656 cont fiwrch ; clcok finis write channel.
0657 jmp(noraw2) ; goto to normal answer.
; entry interupt from channel output buffer.
; ------------------------------------------
0660 choint: cont clchoi ; clear channel output interupt.
0661 negadd(dochwc,q) ; channel word counter := channel word
; counter -2.
0662 cjmp(neg,dochni) ; if word counter < 0
; then goto answer message▶16◀▶16◀▶16◀▶16◀
; with no interrupt
0663 move(dochwc,dochwc) ; if data out channel word counter = 0 then
0664 cjmp(zero,dochfi) ; send channel output finis interupt
; to hc2903.
0665 move(meaddr,dochad) ; send channel output block address
; to memory and start read cycle.
0666 add(dochad,q,dochad) ; block address counter :=
; block address counter + 2.
0667 docht1: cjmp(rememo,docht1) not; wait for memory ready.
0670 move(chdata,medata) ; send memory data word to channel
; data word.
0671 jmp(gewait) ; goto generel wait.
0672 dochni: mzero(dochwc) ; reset data word couter, and goto
0673 jmp(gewait) ; general wait without interrupt.
dochfi: ; data out channel finis interuot.
; --------------------------------
0674 mzero(dochwc) ; reset data word counter.
0675 ldct('chofil) ; load mic. counterwith channel output
; finis interupt level.
0676 jmp(clcint) ; goto calculate and set interupt.
; data in, channel reset.
; -----------------------
0677 dichre/:mzero(dichwc) ; reset data in word counter.
0700 jmp(noran0) ; goto normal answer.
; if given in the middle of in input
; input operation the output opration
; from the other computer is migth
; not finis.
; data in, channel start
; ----------------------
dichst/:
0701 jsb(ge03w0) cl2903 ; get device address from hc2903.
0702 cont strech cl2903 ; clock start reading of channel,
; clock hc2903 ready to get recieve
; not used data word.
0703 move(dichwc,chdata) ; get first data word.
0704 cont firech ; click finis reading of channel.
0705 negadd(dichwc,q) noload; if data word < 2 then
0706 cjmp(neg,dichs3) ; then goto dichs3, ( message arrived).
0707 jsb(gedvbl) ; call subroutine to get divice block
; address, and clock hc2903 ready to recieve dummy
; data word.
0710 add(wrk0,q) ; device block address + 2 to get
; data block address, ( word counter is
; not used).
0711 move(meaddr,wrk0) ; send address of data block address to memory
; memory and start read cycle.
0712 dichs1: cjmp(re2903,dichs1) not; wait for accept not used data word.
0713 move(hc2903,dichwc) cl2903; send word counter to hc2903,
; ( goes to the data in instruction
; w register), and clock hc2903 ready.
0714 dichs2: cjmp(rememo,dichs2) not; wait for memory ready.
0715 move(dichad,medata) ; get channel block address.
0716 negadd(dichwc,q) noload; if data in channel word counter < 2
0717 cjmp(neg,dichei) ; goto data in channel error in start.
0720 jmp(noraw2) ; else goto normal answer.
dichs3: ; message word revieved through channel.
0721 cjmp(re2903,dichs3) not; wait for acccepting not used
; data word.
0722 move(hc2903,dichwc) cl2903; send message word to
; hc2903 and clock data word ready
; from input.
0723 mzero(dichwc) ; reset data channel input word counter.
0724 jmp(noraw2) ; goto normal answer 2.
dichei: ; error at start of data in instruction.
0725 mzero(dichwc) ; clear data in word counter.
0726 jmp(bucow2) ; goto bus communication error.
; entry: interupt from channel input buffer.
; ------------------------------------------
0727 chiint: cont clchii ; clear channel input interupt.
0730 move(dichwc,dichwc) ; data in word counter = 0 then
0731 cjmp(zero,dichsi) ; goto data in channel interupt start.
0732 move(meaddr,dichad) ; send data block address to memory
; and start read cycle.
0733 cont strech ; clock start reading of channel.
0734 move(wrk0,chdata) ; sync of memory, get channel data to
; wrk0 ( schold all clock ready in rh8000).
0735 cont firech ; clock finis reading of channel.
0736 chiin1: cjmp(rememo,chiin1) not; wait for memory ready.
0737 move(medata,wrk0) ; send channel data to memory.
0740 chiin2: cjmp(rememo,chiin2) not; wait for memory ready.
0741 negadd(dichwc,q) ; decrease word counter with 2.
0742 cjmp(zero,dichfi) ; if word counter = 0 then
; goto data in channel interupt finis.
0743 add(dichad,q) ; increase data in channel block address
; with 2.
0744 jmp(gewait) ; goto generel wait.
dichfi: ; data in channel input finis transport interupt.
; -----------------------------------------------
0745 ldct('chifil) ; load counter with channel input finis
; level.
0746 jmp(clcint) ; goto calcuæate and set interupt bit.
dichsi: ; data in channel input start transport interupt.
; -----------------------------------------------
0747 ldct('chisil) ; load counter with channel input start
; interupt level.
0750 jmp(clcint) ; goto calculate interupt.
; local dma interupt service.
;----------------------------
dmain: ; select from status if it is
; input or output.
0751 jsb(ipldma) ; goto input dma from local dma.
; if local memory counter <> 0 then
0752 cjmp(zero,gewait) not; then generel wait else
0753 ldct('lodmle) ; load counter with local dma interupt
; level.
0754 jmp(clcint) ; goto clock interupt.
; subroutine input local dma.
; ----------------------------
0755 ipldma: move(meaddr,lmem) ; addrs:= local dma memory addres reg.
; clock memory.
0756 move(wrk0,dmada) set(14); wrk0:= dma data, clock dma control
0757 ipldm1: cjmp(rememo,ipldm1) not; loop while memory not rteady
0760 move(medata,wrk0) ; memory := wrk0.
0761 add(lmem,q) ; local dam mem addrs :=+2.
0762 dmain2: cjmp(rememo,dmain2) not; wait memory ready
0763 rtn negadd(lwco,q) ; return from subroutine, decrease local
; dma word counter with 2.
;*page: XX
;*page: XX
*end:
e01di0 \r reff. to address 0015 0017 spec. 258
e01di1 \r reff. to address 0016 0020 spec. 259
e01di2 \r reff. to address 0017 0021 spec. 260
e01do0 \r reff. to address 0006 0006 spec. 234
e01do1 \r reff. to address 0007 0007 spec. 239
e01do2 \r reff. to address 0008 0010 spec. 241
e01do3 \r reff. to address 0009 0011 spec. 246
e01do4 \r reff. to address 0010 0012 spec. 251
e01do5 \r reff. to address 0011 0013 spec. 253
e01do6 \r reff. to address 0012 0014 spec. 254
e01do7 \r reff. to address 0013 0015 spec. 255
e01di3 \r reff. to address 0018 0022 spec. 261
e01di4 \r reff. to address 0019 0023 spec. 263
e01di5 \r reff. to address 0020 0024 spec. 268
e01di6 \r reff. to address 0021 0025 spec. 269
e01di7 \r reff. to address 0022 0026 spec. 270
e01pdw \r reff. to address 0028 0034 spec. 276
e01rtc \r reff. to address 0029 0035 spec. 277
e01aci \r reff. to address 0038 0046 spec. 288
prftch \r reff. to address 0149 0225 spec. 836
e01rtr \r reff. to address 0030 0036 spec. 278
e01rtw \r reff. to address 0032 0040 spec. 280
nprftc \r reff. to address 0133 0205 spec. 779
e01sdl \r reff. to address 0035 0043 spec. 285
e01cil \r reff. to address 0041 0051 spec. 291
e01dib \r reff. to address 0014 0016 spec. 256
e01dob \r reff. to address 0005 0005 spec. 231
e01dim \r reff. to address 0014 0016 spec. 257
e01dom \r reff. to address 0005 0005 spec. 232
e01is1 \r reff. to address 0039 0047 spec. 289
e01wtr \r reff. to address 0031 0037 spec. 279
e01gmw \r reff. to address 0025 0031 spec. 273
redyre \r reff. to address 0253 0375 spec. 1228
dwrm0 \r reff. to address 0122 0172 spec. 732
sadyre \r reff. to address 0282 0432 spec. 1290
stdile \r reff. to address 0239 0357 spec. 1200
dichre \r reff. to address 0447 0677 spec. 1728
wrm0 \r reff. to address 0114 0162 spec. 694
stenle \r reff. to address 0234 0352 spec. 1191
rtrnpr \r reff. to address 0264 0410 spec. 1249
e01pmw \r reff. to address 0026 0032 spec. 274
e01ip \r reff. to address 0024 0030 spec. 272
e01rin \r reff. to address 0037 0045 spec. 287
e01sel \r reff. to address 0034 0042 spec. 284
ansin \r reff. to address 0201 0311 spec. 1086
e01skn \r reff. to address 0040 0050 spec. 290
e01drd \r reff. to address 0033 0041 spec. 283
e01drr \r reff. to address 0036 0044 spec. 286
e01gdw \r reff. to address 0027 0033 spec. 275
sknin0 \r reff. to address 0144 0220 spec. 820
drem0 \r reff. to address 0105 0151 spec. 662
e01ini \r reff. to address 0000 0000 spec. 210
e01inp \r reff. to address 0023 0027 spec. 271
dochst \r reff. to address 0410 0632 spec. 1639
dichst \r reff. to address 0449 0701 spec. 1736
sknins \r reff. to address 0145 0221 spec. 821
intser \r reff. to address 0210 0322 spec. 1106
npref0 \r reff. to address 0132 0204 spec. 778
prftc0 \r reff. to address 0148 0224 spec. 835
name spec. instr. octal
dichst 1736 449 701 1 193
dichre 1728 447 677 1 191
dochst 1639 410 632 1 154
sadyre 1290 282 432 1 26
rtrnpr 1249 264 410 1 8
redyre 1228 253 375 0 253
stdile 1200 239 357 0 239
stenle 1191 234 352 0 234
intser 1106 210 322 0 210
ansin 1086 201 311 0 201
prftch 836 149 225 0 149
prftc0 835 148 224 0 148
sknins 821 145 221 0 145
sknin0 820 144 220 0 144
nprftc 779 133 205 0 133
npref0 778 132 204 0 132
dwrm0 732 122 172 0 122
wrm0 694 114 162 0 114
drem0 662 105 151 0 105
e01cil 291 41 51 0 41
e01skn 290 40 50 0 40
e01is1 289 39 47 0 39
e01aci 288 38 46 0 38
e01rin 287 37 45 0 37
e01drr 286 36 44 0 36
e01sdl 285 35 43 0 35
e01sel 284 34 42 0 34
e01drd 283 33 41 0 33
e01rtw 280 32 40 0 32
e01wtr 279 31 37 0 31
e01rtr 278 30 36 0 30
e01rtc 277 29 35 0 29
e01pdw 276 28 34 0 28
e01gdw 275 27 33 0 27
e01pmw 274 26 32 0 26
e01gmw 273 25 31 0 25
e01ip 272 24 30 0 24
e01inp 271 23 27 0 23
e01di7 270 22 26 0 22
e01di6 269 21 25 0 21
e01di5 268 20 24 0 20
e01di4 263 19 23 0 19
e01di3 261 18 22 0 18
e01di2 260 17 21 0 17
e01di1 259 16 20 0 16
e01di0 258 15 17 0 15
e01dim 257 14 16 0 14
e01dib 256 14 16 0 14
e01do7 255 13 15 0 13
e01do6 254 12 14 0 12
e01do5 253 11 13 0 11
e01do4 251 10 12 0 10
e01do3 246 9 11 0 9
e01do2 241 8 10 0 8
e01do1 239 7 7 0 7
e01do0 234 6 6 0 6
e01dom 232 5 5 0 5
e01dob 231 5 5 0 5
e01ini 210 0 0 0 0
MIC. ASM. OK!
LAST INSTR. ADDRS.: 500 OCTAL INSTR. ADDRS.: 764 TRANSLATOR BLOCKS: 103
▶EOF◀