DataMuseum.dk

Presents historical artifacts from the history of:

RC4000/8000/9000

This is an automatic "excavation" of a thematic subset of
artifacts from Datamuseum.dk's BitArchive.

See our Wiki for more about RC4000/8000/9000

Excavated with: AutoArchaeologist - Free & Open Source Software.


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⟦468bc313c⟧ TextFile

    Length: 2304 (0x900)
    Types: TextFile
    Names: »ticcndir«

Derivation

└─⟦667bb35d6⟧ Bits:30007480 RC8000 Dump tape fra HCØ.
    └─⟦4334b4c0b⟧ 
        └─⟦this⟧ »ticcndir« 

TextFile

*name:  iccnch,30,3                ;                        
*name:  icmas,30,9                 ; iccn dma master memory address.
*name:  icwoco,30,10               ; iccn word counter.
*name:  icsla,30,11                ; iccn dma slave memory address.
*name:  icdev,30,12                ; iccn dma reciever 
                                   ; dev. no<12 + send dev. no.
*name:  icbiba,30,15               ; iccn bus informaiton block address.
                                   ; --   -   -           -     -
*name:  iccnid,30,20               ; source: device number of this system
                                   ;         as functioning in 
                                   ;         the iccn bus system,
                                   ;          does  not function on rh8000,
                                   ;          only on hc8000.
*name:  iccn,30,21                 ; dest:   write iccn register.
                                   ; source: read iccn register.
          ; iccn bus control
          ; implemented as specials but is acutally
          ; unused source in alufunction.
*name:  burqst,16,24,1,regsrc      ; ask for iccn bus request.
*name:  burels,16,25,1,regsrc      ; release iccn bus ( i.e not master on bus any
                                   ; more).
*name:  slctst,16,26,1,regsrc      ; set iccn bus device select logic.
*name:  slctcl,16,27,1,regsrc      ; clear iccn bus device select logic.
*name:  sendst,16,28,1,regsrc      ; set iccn bus send control logic.
*name:  sendcl,16,29,1,regsrc      ; clear iccn bus send control logic.
*name:  recvst,16,30,1,regsrc      ; set iccn bus recieve control.
*name:  recvcl,16,31,1,regsrc      ; clear iccn bus recieve control.
*name:  icsic,40,8,0,cndslc        ; iccn sender input control
*name:  icric,40,9,0,cndslc        ; iccn receive input control
*name:  nabrqi,40,10,0,cndslc      ; -, iccn bus request init
*name:  icmabu,40,12,0,cndslc      ; wait until master on bus.
▶EOF◀