⟦46f39f58b⟧

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;;
;; begin lmitxt001c
;;
;; rev: 810107 hlv
auto:
  cjp c7 k
  sic:=autodisp
  racom8085zd0=racom8085-7
  ra:=racom8085zd0, loop
  rd:=version

racom8085m4=racom8085-4
  w0:=racom8085m4, loop       ; clear the registers 3eb thru 3ff
  w1:=0, push 14
  ra:=w0, w0:=w0++
  rd:=, rfct

  push 3e7
  ra:=w1, w1:=w1++
  rd:=slu:=7ff, rfct     ; set -1 into the registers 0 thru 3e7

  ir:=ra:=reg:=firstreg, loop ; sync itr
  zd1:=             ; firstreg.ps:=0
  zd2:=slb:= lubase, loop
  sib:= autobase,loop               ;
  rd2:= sib
  lev:=startlevel, loop
  w0:= lev,cjs setlint
  cjp fetch
.p
mma:;proc mma; (*sel. mem-addr*)
  bfm:= 0c0,h,crtn; msel:= base+addrsel; return;

mma1:;proc seladdr1;
  bfm:= 0c0,errd:= w1,h,crtn; msel:= ba+seladdr; errd:= w1; return;

mma5:;proc seladdr5;
  bfm:= 0c0,errd:= w5,h,crtn; msel:= ba+seladdr; errd:= w5; return;

mmaq:;proc seladdrq;
  bfm:= 0c0,errd:= q++,h,crtn; msel:= ba+seladdr; errd:= q+1; return;

mmd:;proc mmd; (*sel. mem-data*)
  bfm:= 0c1,h,crtn; msel:= base+datasel; return;

thmmd:;proc thseldata;
  bfm:= 0c1,h,crtn not pty; msel:= ba+seldata; if not pty then return
  h,cjpp herror           ;                    else goto herror;

.p
stopmode:
  cjp not cr mreqq; if mreq then goto mreqq;
  ir:=ra:=radummy        
  q:= zd,s
  cjp zro exec ; if stopmode=0 then goto fetch
  cjp b0 stopmode1 ; jump if breakpoint-mode
  zd:=q-- , cjp exec ; countmode
stopmode1: ;; breakpoint mode
  sib-zd0, s
  cjp not zro exec
  sic-zd1,s
exec:; from mreqq with zro=false
  ra:=reg, cjp zro fetch
  ba:= errb:= sib,s,cjs mma; ba:= sib; seladdr;
  c:= bd:= errd:= sic,r,cjp fetch0; xbus:= sic; goto fetch0;
.p
setslice: ;;
  ra:=reg                  ;
setslice1:
  sic:=rd
  slu:=zd                  ;
setslice2:
  slb:=zd2                 ;
  sib:=rd2, crtn                 ;
;; entries into fetch:

fetch1: ;; from fetch with zro=false
  lev:=lev xor w0
  rd:=sic
  ;; no savings of the regs
  ;; set reg and ra according to lev:
  reg:=c: lev clr 700 ; cry:=external interrupt
  bus:= lev and lev, cjp cry fetch3
  ra:=swp,reg:=swp, cjp fetch4;
fetch3:
  reg:=reg++reg, push 1
  ra:=reg:=reg++reg, rfct
fetch4: ;; zro means test stopmode, mreqq, and level shift
  slu:=zd, cjs setslice2 ; set slb, sib
  sic:= rd
execnext: ;; no test on stopmode, mreqq, or level shift
  ba:= errb:= sib,s,cjs mma; ba:= sib; seladdr;
  bd:= c:= errd:= sic,r,cjp b0 dummyr10; xbus:= sic; read; if sib(0) goto dummyregs;
  w7:= bd,w s,cjp not cry fetch7; w7:= waitmem; if odd(sic) goto fetch7
  cjp fetch5                    ;               else goto fetch5;
.p
  ;; logical testsequence in fetch:
  ;;    1.  mreqq
  ;;    2.  stopmode
  ;;    3.  level shift
  ;;    4.  mcb, dummy regs
  ;; the actual test sequence may because of convenience differ from
  ;; this scheme. the logical testsequence must, however, as a
  ;; general rule be as outlined above.

sfetch:
  ra:=reg, cjs setslice1

.instruction mnoop

fetch:; time without interrupt: 9,5x = 2,06uS
  zd:= slu; lu:= slu;
  ba:= errb:= sib,s,cjp not c7 stopmode; ba:= sib; if -,run goto stopmode;
  bfm:=0c0,h; msel:= ba+seladdr;
  bd:= c:= errd:= sic,r,cjp not cr mreqq; xbus:= sic; read; if -,cr goto mreqq;
fetch0:; (* from exec with readmem started *)
  int,h,cjp b0 dummyregs; if sib(0) goto dummyregs; (* nasty bp *)
  w0:= int xor lev,h s,cjp not cry fetch6; x:= int xor lev; if odd(sic) goto fetch6;
  w7:= bd,w s,cjp not zro fetch1; w7:= waitmem; if x<>0 goto fetch1;
fetch5:;(* from execnext *)
  ir:= w7,h,cjs pty perror; ir:= w7; if pty then perror;
  rd:= sic,sic:= sic++,jmap 8; ic:= sic; sic:= sic+1; goto map(ir);

fetch6:
  w7:= bd,w s,cjp not zro fetch1; w7:= waitmem; if x<>0 goto fetch1;
fetch7:;(* from execnext *)
  ir:= swp,h,cjs pty perror; ir:= swap(w7); if pty then perror;
  rd:= sic, sic:= sic++,jmap 8; ic:= sic; sic:= sic+1; goto map(ir);
.p
;; procedure terror
;; return if no pty error or puerrmask.b1 (*supp. pty err*)
;;
;; entry: errb, errd, stat(pty)= def.;
;; exit : ra= regs, stat= undf;
;;
;; procedure perror
;; return if puerrmask.b1 (*supp. pty err*)
;;
;; entry: errb, errd: def.;
;; exit : ra= regs, stat= undf;
;;
terror:;proc terror;
  h,crtn not pty; if not pty then return;
perror:;proc perror;
  ra:= puerrmsk,h
  rd,h s; if puerrmask.b1 then
  ra:= reg,h,crtn b1;   return
  h,cjp herror; else goto herror;
;; procedure tberror
;;
;; entry: "wx:= bd,w s b,cjs tberror
;;
tberror:;proc tberror;
  bd, b,crtn not pty; if not pty then return;
  h,cjv 3 tberror10; case parity of
.loc
tberror10:;
  crtn; no pty: return;
  cjp tberror20; r-pty: goto rptyerr;
  crtn; l-pty: return;
tberror20:; lr-pty:
  q:= 52; q:= r-pty error;
  cjpp debugmess; goto debugmess;
;; procedure therror
;; return if no pty error
;;
;; entry: errb, errd, stat(pty)= def.;
;; exit : all unch;
;;
therror:;proc therror;
  h,crtn not pty; if not pty then return;
.p
;;
;; procedure herror
;; unconditional pty error
;;
;; entry: errb, errd= def.;
;; exit : to fetch;
;;
herror:;proc herror;
  q:= 56,h; 01010lr0: q:= memory error;
  bd, w ; define left and right parity error
  cjv 3 ptyerror1; w5:= (d+1) - 1;
  .loc
ptyerror1:
  q:= q-2; remove both left and right parity error
  q:= q-2; remove left parity error
  q:= q-2; remove right parity error

     ;;send mess to debug console
  ;;q,errb,errd=message
debugmess:
  ra:=racom8085, loop
  rd1:=q, loop
  rd2:=errb, loop
  rd:=errd
  led:=6
sendmess1:
  cjp cr k
  cjs mrequest
  cjp c7 sendmess1 ; wait while run-mode
  cjp sfetch

.p
;;
.instruction mxept
;;
  cjs readlucq
  cjp xept
;;
;; procedure undefined-instruction
;;
.instruction
;;
;; procedure xept(error); (* unconditional program exception *)
;;
;; entry: q= error;
;; exit : (* p.t. n.a *) q= stat= undf, ra= regs;
;;
  q:= undefins; error:= undefined instruction;
xept:;proc xept;
  ;; o b s : changes ir
  ra:= reg,cjs setslice; p.t. no return;
  ir:=300, w2:= spb, loop
  w1:= excode--, loop
  w1:= w1+rd1, loop; d:= pr+excode-1;
  w3:= q,cjs writenext; writenext(spb,d,error);
  w1:= w1+4, loop; d:= pr+exic-1;
  w3:=rdx, cjs writenext; writenext(spb,d,ib);
  w3:= rd,call writenext; writenext(spb,d,ic);
  w5:= w1-8; d:= pr+exadr-1;
  w6:= spb,call readnext; readnext(spb,d);
  sib:= bd,w s; sib:= waitmem;
  rdx:=sib, call readnextt; ib:=sib; readnextt(spb,d);
  sic:= bd,w s, cjs terror; test parity; sic:= waitmem;
  w5:= w5+maxstackrel;
  cjs readnext; readnext(pb,pr+maxstack);
  w3:= bd,w s,cjs terror; lm:= waitmem; testparity;
  zd0:= w3;
  w0:=,cjs setpswait; setpswait((..));
  cjp fetch; goto fetch
.p
;;
;; procedure tstack
;;
;; entry: exit: slu, lm;
;;
tstack:;proc tstack;
  zd0-slu,s
  crtn acy
;;
;; stack overflow
;;
stackerror:
  q:= stackovf; error:= stack overflow;
  cjp xept; goto exception;
.p
swap:
  q:=swp and w4
  swp, q:=q+w0
  w0:=swp and w5, crtn

shiftcom:
  w3, cjs swap
  w1, w3:=q, cjs swap
  w2, w1:=q, cjs swap
  w0, w2:=q, crtn

mrqterror:
  zd0:=w2, crtn not pty ; zd0:=the read data
  ccr, cjp herror ;

mreqq:
  rd:=sic, cjs mrequest
  cjp fetch

mrequest:
  ir:=300
  ra:=racom8085
  w2:=zd0
  w1:=zd1
  w3:=zd2
  w4:=0ff
  w5:=swp, cjv 6 mrq5

.loc

mrq5:
  cjp mrq7a; disp:=2; tti interrupt
  c:=w5:=w5--w5, cjp mrq7; disp:=0; timer interrupt
  c:=w5:=0, cjp mrq7; disp:=1; tto interrupt
  cjv 5 mreq ; normal request

mreq:                              ;012345
   vect 4,mrq1;xx0011
   vect 4,mrq2;xx0111
   vect 4,mrq3;xx1011
   vect 4,mrq4;xx1111
 
mrq1:
  cd, cjp putgetdata;000011 putgetdata
  cjp k ;010011
  w2:=w2-w2, cjp mrq14;100011 read data
  jmp,mrq9;110011 write request
  
mrq2:
  ccr,w0--w0,s,cjpp exec;000111 execute
  jmp,k;010111
  jmp,mrq21;100111 putmem
  jmp,mrq19;110111 getmem
 
mrq3:
  w2:=cd and w4, jmp,getregaddr;001011 get register address
  w0:= w0--w0,  jmp mrq10;011011 test level  o b s
  ccr, reset;101011 autoload
  w0:=reg,jmp,getlev   ;111011 get lev
  
mrq4:
  ccr,w0--w0,s,cjpp mrq8;001111 execute on curr. level
  bus:= w3,cjp selftest;011111 selfdiagnostic test
  ra:=w1, jmp,mrq23;101111 putreg
  ra:=w3, jmp,mrq22;111111 getreg
  
mrq7a: ;;set tti interrupt
  c:=w5:=1 ; disp:=2
mrq7:     ;;set timer interrupt or console interrupt
  w6:=w6-w6, cjs readnext
  w3:=bd, w s, cjs getbyte
  cjs pty mrqterror
  w0:=w3, cjs setlint ; set interrupt
  cjp mrq10

mrq8:; execute on curr. level:
  ra:= reg,cjp execnext; ra:= reg; goto execnext;

mrq9:     ;;write request
;; rd1, rd2, rd3 : message
;; zd3 : data byte

  w0:=rdw, s ; w021:=message
  w2:=rdx
  w1:=rd, cjp zro mrq9a ; jump if no message
  led:=6 ; send interrupt
  rdw:=, cjp mrq10a ; send message
mrq9a: ;; send data byte
  w0:=zd
  w2:=swp; w02:=data byte
  zd:= , cjp mrq10a

putgetdata: ;; bus=data to be put
  w0:=swp and w5, cjs shiftcom
  w0:=swp, cjp mrq10a

getregaddr:
  w2:=w2+w2, push 1
  w2:=w2+w2, rfct

mrq22a:
  ra:=racom8085

mrq10a: ;;update the cyclic buffer
  zd0:=w2
  zd1:=w1
  zdx:=w3, cjp mrq10

getlev:
  c:=ir:= , push 2
  w0:=>w0, rfct

mrq10: ;; end session
  cd:=w0
  ccr, cjp setslice
  
mrq14:    ;;read data
  q:=w3 and 3f
  w3, w1:=q--
  w3:=swp and w4 , cjs writebnext
  cjp mrq10
.p
mrq19:    ;get mem
;;
;; due to the intel multibus memory data are read
;; as two bytes supplying
;; a zero value when no module is answering selection.
;;
  w6:= w1
  w5:= w3--,cjs readnext
  0,w5:= w5--,h
  bd,w4:= w4-w4,w s b;
  w2:= swp,h,cjs pty mrq19pty
  cjs readnext
  0,h
  w2:= w2 ior bd,w s b
  w4,s h,cjs pty mrq19pty
  cjp zro mrq10a
  zd0:= w2
  ccr,q:= w4,cjp debugmess
mrq19pty:
  bd,w b
  h,cjv 3 mrq19pty1
.loc
mrq19pty1:
  crtn
  w4:= 52,crtn
  crtn
  w4:= 52,crtn
  
mrq21:    ;;putmem
  w1:=w1--, cjs writenext
  cjp mrq10
  
mrq22:    ;;get reg
  w2:=rd, cjp mrq22a
  
mrq23:    ;;put reg
  rd:=w3, cjp mrq10
  
;;
;; end lmitxt001c
;;
▶EOF◀
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⟦46f39f58b⟧ TextFile

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