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Length: 10752 (0x2a00)
Types: TextFile
Names: »kkrht«
└─⟦621cfb9a2⟧ Bits:30002817 RC8000 Dump tape fra HCØ. Detaljer om "HC8000" projekt.
└─⟦0364f57e3⟧
└─⟦this⟧ »kkrht«
(kkrh=slang list.no xref.no;
)
\f
s. a60,b20,c60 w. ;
p. <:fpnames:> ;
k=h55 ;
0 ;
a16: a14 ;
al w3 x1 ;
wa. w3 a16. ;
jl w2 x3 ; start init
jl. b0. ;
a50: 0,r.20 ;
; start exekvering
b0: jl. w3 h25.-2 ; input next command
se w2 114 ; if not r(eset) then
jl. b1. ; goto b1
jl. w3 a22. ; else reset cpu1
jl. b0. ; goto input next command
b1: se w2 97 ; if not (st)a(rt)
jl. b2. ; goto b
jl. w3 a24. ; else start cpu1
jl. b0. ; goto input next command
b2: se w2 111 ; if not (st)o(p) then
jl. b3. ; goto b3
jl. w3 a23. ; else stop cpu1
jl. b0. ; goto input next command
b3: se w2 105 ; if interrupt then
jl. b4. ; goto b4
jl. w3 a21. ; else interrupt
jl. b0. ; goto input next command
b4: se w2 102 ; if not f(inis) then
jl. b0. ; goto input next command
al w0 0 ;
rs w0 100 ;
jl. w3 a20. ;
al w2 0 ;
jl. w3 h7. ;
b. j1 w. ;
;
;
;
a20: ; venteprocedure
rs. w3 j0. ;
al. w3 a6. ;
al. w1 a7. ;
jd 1<11+16;
al. w1 a8. ;
jd 1<11+18;
al. w2 a50. ;
j1: rl w0 x2 ;
jl. w3 h32.-2 ;
1<23+32<12 +8 ;
al w2 x2+2 ;
sh. w2 a50.+14;
jl. j1. ;
al w2 10 ;
jl. w3 h33.-2 ;
jl. (j0.) ;
j0: 0 ;
e. ;
b. j0 w. ;
a24: am 1<1 ; start
a23: am 1<1 ; stop
a22: am 1<1 ; reset
a21: al w0 a0 ; interrupt
wa. w0 a5. ;
rs. w3 j0. ;
al w3 8 ;
do w3 (0) ;
jl. w3 a20. ; goto vent
jl. (j0.) ;
j0: 0 ;
e. ;
c0=+1 ; c0>0 for test af ri-ordren
a0=20<3 ;
a5: 1<23 ;
a6: <:clock:>,0,0,0,0 ;
a7: 0,1,0,0,0,0 ;
a8: 0,r.10 ;
;
a11: ; start test
c. -c0 ;
al w2 0 ;
al w3 20 ;
al w0 0 ;
al w1 19 ;
ds w3 1194 ;
ds w1 1190 ;
ss w1 1194 ;
ds w1 1186 ;
rl. w1 -4 ;
jl. a12. ;
m. wait cpu1 ;
a12: ls w1 -18 ;
rs w1 1198 ;
rl w1 1196 ;
al w1 x1+1 ;
rs w1 1196 ;
gg w3 66 ;
jl. a11. ;
;
;
c27: ;
b. h20,i12 w. ;
z. ;
c. c0 ;
jl. c26. ;
c27: ;
rl. w1 a50. ;
al w1 x1+1 ;
rs. w1 a50. ;
ri 16 ;
b. h20,i12 w. ;
c26: al. w3 h0. ;#1 init cpu1
gp w3 26 ;#1 set inf register addr;
rl w3 8 ;#1 base of controller descr addr
al. w1 c27. ;#1
rs w1 x3+a0+0 ;#1 set start addr
ri 16 ;#1 return interrupt;
;;
; testoutput
; antal ri - i type - antal int - int level - di - tl - tl - tl
;
; interrupt 16: input finis
; 18: input request
; 20: output finis
;
;#1 system table: monitor mode
h. ;
0 ;
h0: ;
0,r.6 ;
w. ;
0 ; -5 monitor call service addr
i0: h6 ; -3 interrupt service addr
1<23+0 ; -1 status interrupt limit
i1: h3 ; +1 register dump addr
0 ; +3 exception service addr
0 ; +5 escape service addr
;#1 system table: user mode
i2: h4 ; -5 monitor call service addr
i3: h5 ; -3 interrupt - -
1<23 + 6 ; -1 status < 12 + interrupt limit
i5: h7 ; +1 register dump addr
0 ; +3 exception service addr
0 ; +5 escape service addr
;#1 monitor register dump addr
h3: 0 ; w0
0 ; w1
0 ; w2
0 ; w3
1<23 ; status monitor mode
i4: c27 ; ic start cpu1 process
0 ; cause
0 ; sb
8 ; cpa
0 ; base
8 ; lower write limit
8.3777 7777 ; upper write limit
0<12 + 6 ; interrupt limits
;#1 interrupt service cpu1
h4: am 1 ;#1 monitor call service addr
h5: am 1 ;#1 interrupt service addr (level 1)
h6: al w3 1 ;#1 interrupt service addr (level 2)
rs. w3 a50.+2 ;
rl. w1 a50.+4 ;
al w1 x1+1 ;
rs. w1 a50.+4 ;
sh w2 14 ;
jl. c27. ;
rs. w2 a50.+6 ;
rs. w2 i10. ;
jl. c27. ;
h7: 0 ; w0
0 ; w1
0 ; w2
0 ; w3
1<23 ; status
i6: h8 ; ic
0 ; cause
0 ; sb
8 ; cpa
0 ; base
8 ;
8.3777 7777 ; upper write limit
0<12+20 ;
h8: ;
al w2 0 ;
do. w2 (a2.) ; start HC8000
al. w3 a49. ; output addr
ws. w3 a40. ;
rl w1 8 ; w1:= base of controller table
rs w3 x1+a0+1<3+2;
jl. h12. ; goto wait
h14: rl. w2 a41. ; w2:=share count
rl. w0 x2+a40. ; w0:=length of next share
wa w3 0 ;
al w2 x2+2 ;
rs. w2 a41. ;
rl. w0 x2+a40. ;
sh w0 0 ; if no more to output then
jl. h9. ; goto wait
ds w3 x1+a0+1<3+2; buff:= length,addr
al w2 0 ;
rs. w2 i10. ;
do. w0 (a2.) ; send data transfer request
al w2 0 ;
rs. w2 a50.+10;
h15: rl. w2 a50.+10;
al w2 x2+1 ;
rs. w2 a50.+10;
rl. w2 i10. ;
se w2 20 ; wait for data tranfer completed
jl. h15. ;
al w3 0 ;
rx. w3 i10. ;
se w3 x2 ; if a new interrupt already is arrieved then
jl. h13. ; goto h13
h12: al w2 0 ;
rs. w2 a50.+12;
h11: rl. w2 a50.+12;
al w2 x2+1 ;
rs. w2 a50.+12;
sl. w2 (a3.) ; if time out then
jl. h8. ; goto restart on HC8000
rl. w2 i10. ;
se w2 18 ; wait for ready signal from hc
jl. h11. ;
al w2 0 ;
rs. w2 i10. ; clear interrupt signal
h13: al w3 40 ;
di. w3 (a2.) ;
rs. w3 a50.+8 ;
rl w3 x1+a0+1<3+2;
jl. h14. ;
h9: ;
rl. w2 i10.
sn w2 0
jl. -4
al w2 0
rs. w2 i10.
al w3 30
di. w3 (a2.)
rl. w2 i10.
sn w2 0
jl. -4
al w2 0
rs. w2 i10.
rl. w2 i10.
sn w2 0
jl. -4
di. w3 (a2.)
rs. w3 a50.+2
rl. w2 a50.+14;
al w2 x2+1 ;
rs. w2 a50.+14;
jl. h9. ;
i10: 0 ;
z. ;
a1: 0 ;
a2: 1<23+21<3+2.001 ;
a3: 100000 ;
a4: 0 ;
a9: 1<23+21<3+ 2.010 ; reset
a14: ; start init
rs. w2 a4. ; save return
rs. w1 a14. ; save fp base
rl w3 8 ; base of controller tabel
al w3 x3+a0 ;
rs. w3 a1. ; addr of contr. table for cpu1
al. w1 a11. ;
al w0 x1 ;
ds w1 x3+2 ;
ds w1 x3+10 ;
ds w1 x3+18 ;
ds w1 x3+26 ;
jd 1<11+28;
c. c0 ;
rl. w1 i0. ;
wa. w1 a14. ;
rs. w1 i0. ;
rl. w1 i1. ;
wa. w1 a14. ;
rs. w1 i1. ;
rl. w1 i2. ;
wa. w1 a14. ;
rs. w1 i2. ;
rl. w1 i3. ;
wa. w1 a14. ;
rs. w1 i3. ;
rl. w1 i4. ;
wa. w1 a14. ;
rs. w1 i4. ;
rl. w1 i5. ;
wa. w1 a14. ;
rs. w1 i5. ;
rl. w1 i6. ;
wa. w1 a14. ;
rs. w1 i6. ;
;
;
; rl. w1 i7.
; wa. w1 a14.
; rs. w1 i7.
z. ;
jl. (a4.) ; return
a40: 4,4,20,a46,0 ;
a41: 0 ;
a49: ;
2 ;
2 ;
a47: 1<23+0<3+2.001 ;
al w1 x1+1
al w1 x1+1
al w1 x1+1
al w1 x1+1
al w1 x1+1
al w1 x1+1
al w1 x1+1
al w1 x1+1
al w1 x1+1
al w1 x1+1
al w2 -17 ;
do. w2 (a47.)
dl. w1 a54.
wd. w1 a55.
ds. w1 a56.
al. w1 a60. ; halfwords
al w2 8 ; output addr
al. w3 a53. ;
ds w2 x3+2 ;
al w0 2.111 ;
la w0 6 ; w0:=output addr mod 8
rs w0 8 ; contr. table base
ls w3 -3 ;
ls w3 3 ;
wa. w3 a51. ;
al w2 20 ; exp. int level
rs w2 108 ; !!!!!!!!!
al w2 x3 ; device addr
al. w3 a52. ; return addr
do w1 x2 ;
jl. 0 ; wait interrupt
a52: al. w3 a48. ;
al w2 -219 ;
do. w2 (a47.) ;
a48: jl. 0 ;
a53: 0,0,0,0
a51: 1<23 + 0<3 + 2.001
-1
a54: -8000000
-1
a55: -98
0
a56:0
a60:
a46=k-a49-24 ;
e. ;
e. ;
e. ;
▶EOF◀