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Length: 15360 (0x3c00)
Types: TextFile
Names: »t2903dir«
└─⟦00964e8f7⟧ Bits:30007478 RC8000 Dump tape fra HCØ.
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└─⟦this⟧ »t2903dir«
; directives and names to 2903.
; masks
*mask: aludes,(11:15) ; alu function from alu bit 8 to both
; bit 5 , mir(11) to mir(15)
; jump addrs codes
; use full sekvens mask.
; type = 12.
; bit(1:4) in instr. format is the sekvens kontrol,
; bit(5) in instr. format is condition enable.
*name: cjsb,12,1,0 ; conditional jump to subroutine
*name: jsb,12,1,1 ; jump to subroutine
*name: cjmp,12,3,0 ; conditional jump addrs.
*name: jmp,12,3,1 ; jump addrs unconditional.
*name: cjsrp,12,5,0 ; conditional jump to subroutine conditional addrs.
; from sekvenser reg. or direct.
*name: cjmrd,12,7,0 ; jump to addrs. conditional
; from secvenser register or direct.
*name: rpct,12,9,0 ; repeat direct and derease counter until
; counter = 0.
*name: cjmpp,12,11,0 ; conditional: if pass then
; pop stack and jump to direct addrs. else
; continue.
*name: twb,12,15,0 ; tree way branch
; jump sekvens codes.
*name: jmpz,14,0,0 ; jump to addrs. zero,
; clear stack.
*name: jmap,14,2,0 ; jump to addrs. given by map prom
*name: push,14,4,1 ; pusch micro program instr. counter to
; stack and continue.
*name: cjvec,14,6,0 ;if pass then go to address given
; by vector prom otherwise next micro
; instr.
*name: cjv1,14,6,0 ; jump to addrs. given by vektor1 prom
*name: cjv2,14,6,2 ; jmp to addrs. given by vector 2 prom.
*name: jvec,14,6,1 ; jump vector.
*name: rep,14,8,0 ; if counter <> 0 then goto first in stack
; else pop stack and continue.
*name: crtn,14,10,0 ; conditional: if pass then
; jump to first in stack and pop stack
; else continue.
*name: rtn,14,10,3 ; return: jump to first in stack
; and pop stack.
*name: loop,14,13,0 ; conditional loop:
; if pass then pop sctak and continue
; else jump to first in stack.
*name: pop,14,13,3 ; pop stack and continue.
*name: cont,14,14,0 ; continue to next micro instr.
; type 15 load counter types.
*name: ldct,15,12,0 ; load counter whit addrs. field and continue.
*name: clcpu,15,4,0 ; push micro program counter to stack
; if pass then load counter whit addrs. field
; else hold counter.
*name: lcpu,15,4,1 ; push micro program counter to stack
; load counter with address field.
; type 16 is load counter from internal alu reg.
*name: ldctre,16,12,5,0 ; load counter from register addressed.
*name: pushre,16,4,5,1 ; pusch mic. program instr. counter to
; stack and load counter with contents of
; the internal register pointed out by
; the argument.
*name: cpshre,16,4,5,0 ; pusch mic. program instr. counter
; into the stack and
; if(condition pass then load counter
; with internal alu register pointed
; out by the instr address field) else
; hold counter
; type 16. load micro sekvenser counter with contents of
; internal bus.
*name: ldctbu,16,12,6,0 ; load counter from bus
*name: pushbu,16,4,6,1 ;
*name: cpshbu,16,4,6,0 ;
; normal alu function codes
; code zero is not used
*name: sub,11,1,2 ; f = s minus r minus 1 plus carry = 1
*name: sub1,11,1,1 ; f = s minus r minus 1 plus carry (=0)
*name: subr,11,2,2 ; f = r minus s minus 1 plus carry (= 1).
*name: subr1,11,2,1 ; f = r minus s minus 1 plus carry (= 0).
*name: add,11,3,1 ; f = r plus s plus carry (= 0)
*name: add1,11,3,2 ; f = r plus s plus carry (= 1)
*name: moves,11,4,1 ; f = s plus carry (= 0)
*name: inc,11,4,2 ; f = s plus (carry = 1)
*name: invs,11,5,1 ; f = not(s) plus (carry = 0)
*name: invs1,11,5,2 ; f = not(s) plus (carry = 1)
*name: mover,11,6,1 ; f = r plus (carry = 0)
*name: incr,11,6,2 ; f = r plus (carry = 1)
*name: invr,11,7,1 ; f = not(r) plus (carry = 0)
*name: invr1,11,7,2 ; f = not(r) plus (carry = 1)
*name: mzero,11,8,1 ; f = low
*name: andinv,11,9,1 ; f = not(r) and s
*name: exnor,11,10,1 ; f = r exclusive nor s
*name: exor,11,11,1 ; f = r exclusive or s
*name: and,11,12,1 ; f = r and s
*name: nor,11,13,1 ; f = r nor s
*name: nand,11,14,1 ; f = r nand s
*name: or,11,15,1 ; f = r or s
; special functions
*name: unsmul,11,0,3 ; unsigned multiply
*name: mult2c,11,4,3 ; 2'complement multiply . bitpattern =/01010/
*name: sgnmgn,11,11,5 ; bitpattern = /01011/
; from 2's complement to sign magnitude.
*name: mult2l,11,12,5 ; 2'complement multiply, last cycle, bitpattern = /01100/
*name: slnorm,11,16,4 ; bitpattern = /10000/
; single length normalize.
*name: dlnorm,11,20,3 ; bitpattern = /10100/
; double length normalize.
*name: div1st,11,20,3 ; bitpattern = /10100/
; first divide operation. same as dlnorm.
*name: div2c,11,24,5 ; bitpattern = /11000/
; 2' complement divide.
*name: div2cr,11,28,5 ; bitpattern = /11100/
; 2' complement divide corectio and remainder.
*name: incone,11,8,3 ; increment by 1
*name: inctwo,11,8,4 ; increment by 2
; the nonaddressable q-register.
*name: q,30,-1 ; the negative value to
; destingues from the others .
; use of the indexd w and w_pre registers
*name: windex,30,-2 ;
*name: wreg,30,-2 ;
*name: wpre,30,-3 ;
; internal registers
; the working register is interchanged
; cause of a hard_ware bug.
;; note: it is important that the 4 working registers
;; have the fixed adresses in the register ram, otherwise
;; will the wreg and wpre register selection
;; logic not function.
*name: w3,30,0 ; the 3 reg.
*name: x3,30,0 ; schould be removed.
*name: w2,30,1 ; then w2 reg.
*name: x2,30,1 ; the w2 used as index reg.
*name: w1,30,2 ; the w2 reg.
*name: x1,30,2 ; the w2 used as index register
*name: w0,30,3 ; the w3 reg.
*name: status,30,4 ; the status register.
*name: ex,30,4 ; the exeption register.
*name: ic,30,5 ; the instruction counter.
*name: cause,30,6 ; the cause register.
*name: addrs,30,7 ; storage address buffer.
*name: wrk1,30,10 ; working locaition 1 for micro program
*name: r8,30,8
*name: wrk2,30,11 ; working locaition 2 for micro program.
*name: base,30,9 ; the base register
*name: cpa,30,8 ; the common protected area register
*name: inf,30,12 ; information register.
*name: uplim,30,13 ; the upper limit register.
*name: lowlim,30,14 ; the lower limit register.
*name: wrk0,30,15 ; micro program wroking register no 0.
; external registers.
*name: hc2901,30,16 ; dest: write hc2901
; source: read hc2901
;
;
; set conditions select
; type is 40
; format is <name>/40/<value>/<mask_kind>/<mask or std. mask no.>
;
*name: lseq,40,1,2,5 ; less or equal
*name: great,40,0,2,5 ; greather than '>'
*name: less,40,3,2,5 ; less then '<'
*name: greq,40,2,2,5 ; greather than or equal '>='
*name: equal,40,5,2,5 ; equal '='
*name: nequal,40,4,2,5 ; not equal '<>'
; normal cond bits
*name: zero,40,5,2,5 ; zero
*name: nzero,40,4,2,5 ; not zero
*name: over,40,7,2,5 ; overflow
*name: nover,40,6,2,5 ; not overflow
*name: cxorz,40,9,2,5 ; carry xor (+) zero
*name: candz,40,8,2,5 ; carry and (*) zero
*name: carry,40,11,2,5 ; carry
*name: ncarry,40,10,2,5 ; not carry
*name: ncxorz,40,13,2,5 ; not carry xor (+) zero
*name: candnz,40,12,2,5 ; carry and not z
*name: neg,40,15,2,5 ; negative
*name: notneg,40,14,2,5 ; not negative
; for hc2901 ready
*name: re2901,40,15,2,5 ; hc2901 ready
;
;
;
;
; specials
;
;
;
;
;
; set condition kind
*name: csmy,16,1,2,33 ; set condition to my bits
*name: cms,16,2,2,33 ; set condition to m bits
*name: cs2901,16,3,2,33 ; set condition to hc2901
; sign extend bits8 to 6 high
; bit 5 for the slices ther schould
; be extende thrugh = 0
; bit 5 for slices wwhit no extend = 1.
*name: signex,16,29,1,aludes ; bitpatern /11101/ = 29
; generel alu dest control bit 8 to both bits 5
; in alu function.
*name: noload,16,24,1,aludes ; bitpattern = /11000/ = 24
*name: rgtaol,16,3,1,aludes ; bitpattern = /00011/ = 3
; shift rigth alu output logaritm, hold q
; - -- - - -
*name: srgt,16,3,1,aludes ; shift rigth.
*name: lftaol,16,19,1,aludes ; bitpattern = /100ll/ = 19
; shift left alu output logaritm, hold q.
; - -- - - -
*name: slft,16,19,1,aludes ; shift left.
*name: lftqil,16,27,1,aludes ; bitpattern = /11011/ = 27
; sift left q-reg input logarithm, hold ram
; - -- - - -
*name: rgtqil,16,11,1,aludes ; bitpattern = /01011/ = 11
; shift rigth q-reg output logarithm, hold ram
; - -- - - -
*name: rgtaql,16,7,1,aludes ; bitpattern = /00111/ = 7
; shift rigth alu output q_reg input logical.
; - -- - - -
*name: lftaql,16,23,1,aludes ; bitpattern = /10111/ = 23
; shift left alu output q_reg input logical.
; - -- - - -
*name: rgtaoa,16,0,1,aludes ; bitpattern = /00000/ = 0
; shift rigth alu output aritmetric, hold q.
; - -- - - -
*name: lftaoa,16,16,1,aludes ; bitpattern = /10000/ = 16
; shift left alu output aritmetric, hold q.
; - -- - - -
*name: onlyq,16,12,1,aludes ; bitpattern = /01100/ = 12
; only load q reg, hold other internal registers
; hold and write my and m .
*name: holdmy,16,1,2,3 ; hold writing the my regs.
*name: openm,16,7,2,38 ; open for wring in m.
*name: setint,16,0,2,40 ; select the interupt bit.
; set half word moves
*name: hmlr,16,1,2,36 ; move left half word to right
*name: hmrl,16,0,2,36 ; move right half word to left
*name: nothm,16,3,2,36 ; no half word move
; set shift control in 2904
; both the alu and q reg is shifted either
; seperate or in conection
*name: shinz,16,0,2,37 ; shift seperat whit zero input
*name: shin1,16,1,2,37 ; shift seperate whit one input
*name: dshinz,16,6,2,37 ; shift double whit zero input
*name: dshin1,16,3,2,37 ; shift double whit 1 input
*name: dshln,16,15,2,37 ; shift alu output and q whit link
; or resetting bit 27.
; clock the hc2901 register by setting bit 26
*name: clwr01,16,1,2,23 ; set the write hc2901 bit.
*name: clre01,16,1,2,22 ; set the read hc2901 bit.
*name: nclk01,16,0,2,23 ; inhippit the clocking of the
; hc2901, allthough it migth is
; referenced through the
; destination field.
; set or clear selected bit or bits
; selected from the argument.
*name: set,16,-1,3,1 ; set one bit
*name: clear,16,0,3,1 ; clear one bit
*name: setall,16,-1,3,2 ; set all bit from arg1 to arg2
*name: clall,16,0,3,2 ; clear all bit from arg1 to arg2
; in internal register stack pointed
; out by b_addrs field.
*save: m2903
*end:
▶EOF◀