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Names: »listrh01«
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Micro asm.: micasm01 version date.810804.1418
Source file: tcgorder010 version date.820426.1254
Object file: rhorder01 version date.820428.0915
*load: m2901
; -----------------------------------------------
; generel abrivations:
;
; msw = most significant word.
; lsw = least significant word.
; msh = most significant halfword.
; lsh = least significant halfword.
; mso = most significant octet.
; ino = intermidiate octet.
; lso = least significant octet.
; msb = most significatnt bit.
; lsb = least significatnt bit.
;
; C(<number>) = contents of memory location <number>,
; <number> can in this case also
; be a register.
;
; dot notation examples:
; wrk0.msh.lsb = bit 11 inwrk0 register.
; wrk0.lso.msb = bit 16 in wrk0 register.
;
; octet = 8 bits.
; halfword = 12 bits.
; word = 24 bit.
;
; the words is numbered so bit 0 is the most
; significant bit ( sign bit) and bit 23 is
; the least significant bit ( one bit).
; note: this is completely oposite from
; the normal rc8000 notation, but is
; due to some numbering facts in the bits
; bitslices.
; ------------------------------------------------
; -----------------------------------------
; 19810505:
; temporary the iccn bus is skipped
; with the skip construction 'iccnx',
; or 'iccn'.
; procedures only used by the iccn bus logic
; is also skipped.
; channel bus logic inserted.
; 810722/1600:
; status/interupt level fetch is changed,
; in module 'ansin'.
; only checked for rh2901.
; instead for two call of hlfwrd move
; subroutines the extraction of the interupt
; level is performed on the spot.
; constant 'hlfwdm1' declered for this
; purpose.
; 810722/1607:
; all occurences of the word octet is
; changed to octet.
; 810722/1645:
; the set disable/enable module is changed
; so halfword move subroutines is not called.
; 810722/1650:
; sobroutines 'hwmrtl' and 'hwmltr' is skipped
; with the controlwords 'hlfwds'.
; 810722/1650:
; return form interupt module is changed so
; half word move is not called, new entry
; in set level module.
; level is noe in intrupt level register
; and not in wrk0.
; 810723/1230:
; error corrected: interupt bit in intreg cleared
; in set disable module.
; error corrected: answer interupt calls set disable
; for exit
; module for control of interupt of lower level.
; 810730/1100:
; only relewant for hc2901.
; generel wait with x modification after fetch of
; instruction is deleted from the fetch routines.
; the generel wait logic is skipped out with
; the control word gewax.
; 810730/1130:
; only in rh8000.
; clock before and after evry channel output
; opration.
; 810730/1200:
; the subroutine entry for init orf wrk
; registers is changed so it continues
; directly to generel wait.
; init of wrk registers is introduced
; as seperate code in the init 2901
; sequence.
; 810803/1500:
; init from prom instead from local dma
; insertet in hc8000 text.
; 810805/1200:
; generel get instruction inserted
; to recieve level from external
; interupt devices. am9519.
; introduced as register 100,
; bu schould be changed to register
; 94. therefor the generel get instruction
; with effective address 94 schould only
; be allowed in monitor mode.
; 810807/1406:
; disarming of charakter interupt controler
; after interupt and arm after generel get 94.
;
; 810810/1749:
; no prefetch module changed so the subroutine
; call of ge03w0 is removed. this can be done
; in the rh2901 because the 2903 never sends
; a uneven instruction address.
; 810810/1750:
; all iccn bus logic and definition is now removed.
; the definition and the version up to this date
; can be found in the file 'ticcnbus'.
; 810814/1750:
; channel input/output logic changed, so it now
; accepts negative length buffers.
; 810824/0930:
; entry for external interupt fetch with a
; generel get instruction (gg 94) is inserted.
; 810824/0930:
; all generel get (gg) and generel put (gp)
; instrcution is allowed in rh8000, but
; their function is different.
; 810827/1500:
; dump of ic after evry instruction fetch
; introduced. gp 64 gives the address at which
; the dump schould start. gp 64 with the contents
; zero stops the dump.
; only in rh8000.
; 810903/1130:
; in rh8000 the start stop reset furnction send
; from hc8000 is changed so start after stop
; is a specific operation, and not mixed in with
; start interupt.
;NEXT
;--------------------------------------------------------
; ------------------------------------------------------
; project to be made in the future.
;
; 001: thre entry jump table schould be removed,
; and the hc2903 schould jump direcly to
; funtions mudoules wanted.
; before doing this subroutines and things
; which differ in length schoul be moved to
; the back of the program, so the rh and the hc
; version get the same entry addrress if possible.
; if that is not possible it dosent matter.
;
; 002: if it is decided to keep the entry jump table
; then some call of cl2903 schoud be moved up
; to the table.
;
; 003: it schould be tried to ballance the time
; from call of a memory acces to the acces
; is finished, so their is as little waste time
; as possible.
;
; 004: change of the interupt signal from the
; timer so it comes in as a seperate
; condition from the charakter device interupt.
; 005: check for parity error schould be performed
; after memory data out and memory data in
; the time out function in the memory data out
; and memory data in schould also be finishd.
;PROJECT:
;------------------------------------------------------
; -----------------------------------------
; helping logical table.
; after the operation
; sub(op1,op2) op1 - op2
;
; cjmp(neg,l) . op1 < op2
; cjmp(neg,l) not. op1 >= op2
; cjmp(zero,l) . op1=op2
; cjmp(zero,l) not. op1 <> op2
*const: metimo,200 ; no. of micro instructions before
; memory timeout.
*const: butimo,200 ; no of micro instructions before
*const: intimo,100 ; no. of micro instrcutions before
; time out for wait for
; pause signal in the amd9519
; interupt controler.
*const: sendto,4095 ; no of mic. instr. before sender
; reciever has send timeout.
*const: intsta,6 ; least significant bit in status reg that
; contains the interupt bits.
*const: rc80le,3 ; interupt from rc8000 level,
; same as timer interupt level.
*const: timele,3 ; timer interupt level - (1+3).
*const: chifil,4 ; channel input finis
; interupt level. ( 8)
*const: chisil,5 ; channel input start
; interupt level (9).
*const: chofil,6 ; channel output finis
; interupt level (10).
*const: lodmle,7 ; local dma interupt level.
*const: chdele,8 ; charakter device interupt level -(1+3).
*const: intno,9 ; no of allowed interupt bits
; in the interupt register.
*const: hlfwrd,11 ; halfword,
; no of bits - 1 in a half word.
*const: hfwdm1,10 ; halfword - 1,
; no of bits - 2 in halfword.
*const: octet,7 ; no of bits - 1 in a data octet.
*const: dyreno,7 ; number of allowed dynamic registers
; to be transferred to hc2903 - 1.
; power on logic starts microprogram in address 0
0000 e01ini/:jmp(init) ; program should start with a jump
; for hardware reasons
; also entry address of init from hc2903.
0001 jmp(choint) ; address 1
; channel out interupt.
0002 jmp(chiint) ; address 2
; channel in interupt.
0003 reset: cont set(14) ; power reset
0004 jmp(rc80in) ; address 4
; interupt from rc8000.
; entry address in hc2901 from hc2903
e01dob/: ; data out function jump table base.
0005 e01dom/:jmp(dowrme) ; write data word direct to memory.
0006 e01do0/:jmp(douni0) ; data out on unibus control 0.
0007 e01do1/:jmp(dochst) ; channel output start
0010 e01do2/:jmp(douni1) ; unibus reset.
0011 e01do3/:jmp(dochre) ; channel output reset.
0012 e01do4/:jmp(dontus) ; not used.
0013 e01do5/:jmp(dontus) ; data out not used.
0014 e01do6/:jmp(dontus) ; data out not used.
0015 e01do7/:jmp(dontus) ; data out not used.
e01dib/: ; data in functon jump table base.
0016 e01dim/:jmp(direme) ; read data word direct form memory.
0017 e01di0/:jmp(dintus) ; data in not used.
0020 e01di1/:jmp(dichst) ; channel input start.
0021 e01di2/:jmp(dintus) ; data in not used.
0022 e01di3/:jmp(dichre) ; channel input reset.
0023 e01di4/:jmp(dintus) ; data in not used.
0024 e01di5/:jmp(dintus) ; data in not used.
0025 e01di6/:jmp(dintus) ; data in not used.
0026 e01di7/:jmp(dontus) ; data out not used.
0027 e01inp/:jmp(npref0) ; get instr with no prefetch
0030 e01ip/: jmp(prftc0) ; get instr with prefetch
0031 e01gmw/:jmp(rem0) ; get data word from memory.
0032 e01pmw/:jmp(wrm0) ; put data word to memory.
0033 e01gdw/:jmp(drem0) ; get double data word from memory.
0034 e01pdw/:jmp(dwrm0) ; put double data word to memory.
0035 e01rtc/:jmp(gng100) ; gg(100) get real time clock.
0036 e01rtr/:jmp(geng64) ; gg test register with no wait.
0037 e01wtr/:jmp(genp64) ; gp test register.
0040 e01rtw/:jmp(geng66) ; gg test register with wait.
; rh8000: wait start by rc8000, and send
; interupt register to hc2903.
0041 e01drd/:jmp(sadyre) ; entry save dynamic registers.
0042 e01sel/:jmp(stenle) ; entry set enable level.
0043 e01sdl/:jmp(stdile) ; entry set disable level.
0044 e01drr/:jmp(redyre) ; entry reestablish dynamic registers.
0045 e01rin/:jmp(rtrnpr) ; entry return to next process.
0046 e01aci/:jmp(ansin) ; entry answer and clear interupt.
0047 e01is1/:jmp(intser) ; entry goto interupt service 1.
0050 e01skn/:jmp(sknin0) ; entry skip next instruction and fetch.
0051 e01cil/:jmp(geng94) ; entry gg (94) get interupt level from
; amd9511 interupt controler,
; not on rh8000.
; init of wrk1, wrk2 and q reg before entr&ering
; generel wait loop.
; standard init of wrk registers is
; wrk0 = 0, but presently expected.
; wrk1 = 1.
; wrk2 = 8.
; q = 2.
; use of the working registers schold be
; done in the following order wrk0,wrk1,wrk2,q.
gewwri:
0052 iniwrk: mzero(wrk0) ; wrk0 := 0.
0053 moinc(wrk1,wrk0) ; wrk1 := 1.
0054 moinc(q,wrk1) ; q := 2.
0055 move(wrk2,q) sl ; wrk2 := 4.
0056 move(wrk2,wrk2) sl ; wrk2 := 8.
gewait: ; generel wait loop.
;===================
0057 cjvt(vect) and(wrk1,hc2903) noload noint opinde;
; hc2903 schould be addressed as source
; because this allowes the the clocking
; of the hc2903 data buffer into the
; vector prom, the hc2903 register no
; is equivalent with the register no
; of the internal register intreg so
; because intreg(0) tells if an
; interupt schold be send to the hc2903
; the alu operation will result in
; zero if no interupt an not zero if
; interupt, this is used in fetch
; and in prefetch.
0060 jmp(gewait) ; goto generel wait.
; initialize.
; -----------
init:
0061 mzero(clrf80) ; clear flag bit signal from
; rc8000.
0062 cont init03 ; reset hc2903
0063 cont init03
0064 cont init03
; hc2903 now goes to init.
;. temp test.
0065 mzero(ictsad) ; clear instrcution test address.
0066 mzero(intreg) ; init of wrk registers.
; interupt bit register := 0.
0067 moinc(wrk1,intreg) ; wrk1 := intreg+1 ( 1).
0070 moinc(q,wrk1) ; q := wrk1 + 1 ( 2).
0071 move(wrk2,q) sl ; wrk2 := q*2 ( 4).
init6: ; wait for start by rc8000.
; only control word with address bit(21:22) = 00
; accepted as start.
0072 cjmp(re8000,init6) not; wait for data word from rc8000.
0073 move(wrk0,rc80cn) ; get control word form rc8000 into wrk0.
0074 mzero(clrf80) ; clear flag indicating that
; word was send from hc8000.
0075 and(wrk0,wrk2) noload ; if bit(21) <> 0 then
0076 cjmp(zero,init6) not ; goto wait for data word start.
0077 and(q,wrk0) noload ; if bit(22) <> 0 then
0100 cjmp(zero,init6) not ; goto wait for data word start.
0101 move(wrk2,wrk2) sl ; wrk2 := wrk2*2 ( 8).
0102 mzero(intlev) ; clear current interupt level.
0103 mzero(intlim) ; clear disable level and
; enable level.
0104 mzero(dichwc) ; clear data in channel word counter.
0105 mzero(dochwc) ; clear data out channel word counter.
; init of channel interupt.
0106 cont firech ; clock finis read channel.
0107 cont fiwrch ; ckock finis write channel.
0110 cont clchii ; clear channel input interupt.
0111 cont clchoi ; clear channel output interupt.
;*skip: oldint
0112 init5: move(wrk0,wrk2) opexde sl; send addrs or word 8 to memory.
; and load 8 shift 1 (i.e.16 ) to wrk0.
0113 move(wrk0,wrk0) sl ; wrk0 := 32.
0114 move(c66,wrk0) sl ; generate contant 66 in local dma
; addrs register. c66 := 64.
0115 move(wrk2,c66) sl ; wrk2 := c66( 64) * 2,
; ( wrk2 is now 128
; i.e. device 16*8).
0116 add(wrk2,wrk0) ; wrk2 := wrk2 + wrk0, ( i.e.
; wrk2 := 128 + 32 ( device 20 * 8)),
; now wrk2 points to the relative
; distance from device table 0 to
; device table 20.
0117 add(c66,q) ; c66 := c66 (64) + q (2).
0120 init3: cjmp(rememo,init3) not; wait for memory ready
; get word 8 from memory.
0121 add(wrk2,medata) ; wrk1 := word8 or memory
; ( device base) + wrk2
; (device no 20 * 8))
0122 move(meaddr,wrk2) ; move addrs of device table to memory.
0123 init2: cjmp(re2903,init2) not; nb: for sync of memory,
; wait for hc2903 ready.
0124 init4: cjmp(rememo,init4) not; wait for ready of memory.
0125 move(hc2903,medata) ; send memory data to hc2903.
0126 jmp(gewwri) cl2903 ; goto generel wait
; and clock hc2903.
;*page: XX tcgorder01
; generel subroutine section
; --------------------------
; subroutine get a word from hc2903 to wrk0.
; ==========================================
0127 ge03w0: cjmp(re2903,ge03w0) not; wait until ready.
0130 rtn move(wrk0,hc2903) ; move word from hc2903 to wrk0.
; subroutine get a word from hc2903
; ==================================
; to wrk0 and memory address register,
; ===================================
; usualy called as : jmp(ge03a0) cl2903
0131 ge03a0: cjmp(re2903,ge03a0) not; wait loop until hc2903 is ready.
0132 move(wrk0,hc2903) ; get word form hc2903.
0133 andinv(wrk0,wrk1) ; clear possibly bit ( 23).
0134 rtn move(meaddr,wrk0) ; send addrs to memory.
; the trick with word 66 is only
; performed in rh8000.
; subroutine get a word from hc2903
; =================================
; to wrk0 and control that if the word is
; equal to 66 then send 132 to memory address
; else send thw word to memory address register.
0135 ge03a6: cjmp(re2903,ge03a6) not; wait loop until hc2903 ready.
0136 move(wrk0,hc2903) ; get address to wrk0.
0137 andinv(wrk0,wrk1) ; clear bit(23) in address.
0140 ge03ad: sub(wrk0,c66) noload ; entry for read double word:
; if address of data word = 66 then
0141 crtn(zero) move(meaddr,wrk0) not; return and send address to
; memory , and clock memory read cycle.
0142 ge03aw: cjmp(rememo,ge03aw) not; else wait for memory.
0143 rtn add(wrk0,c66) noload opexde; send 132 to memory addrs register
; and start memory read cycle.
; end of generel subroutine section.
; ----------------------------------
;*page: XX
; read memory section.
; --------------------
; read data word from memory to hc2903.
; ------------------------------------
0144 rem0: jsb(ge03a6) cl2903 ; clock the hc2903, and call subroutine
; with control of address 66.
0145 rlt2: cjmp(rememo,rlt2) not ; wait until memory ready
0146 move(hc2903,medata) cl2903; move data from memory to hc2903.
0147 jmp(gewait) ; goto wait cyclus.
; read double word from memory to hc2903.
; ---------------------------------------
0150 drem0/: jsb(ge03a6) cl2903 ; clock hc2903, and call subroutine
; to get address of data word with
; control of address 66.
0151 negadd(wrk0,q) ; wrk0 := address of second data word
; ( wrk0 - 2).
0152 drlt2: cjmp(rememo,drlt2) not; wait for first address fecth is ready.
0153 move(hc2903,medata) cl2903; hc2903 := memory'first data word,
; and clock hc2903.
0154 jsb(ge03ad) ; call subroutine for control of
; address 66 and start memory read cycle.
0155 drlt4: cjmp(re2903,drlt4) not; wait forhc2903.
0156 drlt3: cjmp(rememo,drlt3) not; wait for memory address cycle.
0157 move(hc2903,medata) cl2903; hc2903 := memory'second data word,
; clock hc2903.
0160 jmp(gewait) ; clock hc2903, goto wait cycle.
; end of read memory section
; --------------------------
; write memory section
; ---------------------
; write to memory from hc2903.
; ----------------------------
0161 wrm0: jsb(ge03w0) cl2903 ; clock hc2903, and call subroutine
; to get address into wrk0.
0162 andinv(wrk0,wrk1) cl2903; clear bit(23) of address and
; clock hc2903 ready.
0163 wlt3: cjmp(re2903,wlt3) not ; wait for memory data word.
0164 move(medata,hc2903) cl2903; memory := hc2903.data, clock ready
; the hc2903.
0165 move(meaddr,wrk0) ; memory address reg. := address
; of data word.
0166 wlt4: cjmp(rememo,wlt4) not ; wait for memory write cycle.
0167 jmp(gewait) ; goto wait cyclus.
; write double word to memory from hc2903.
; ----------------------------------------
0170 dwrm0/: jsb(ge03w0) cl2903 ; clock hc2903, and call subroutine
; to get address into wrk0.
0171 andinv(wrk0,wrk1) cl2903; clock ready for recieve first data
; word.
0172 dwlt3: cjmp(re2903,dwlt3) not; wait for ready hc2903.
0173 move(medata,hc2903) cl2903; memory := hc2903'data.
; clock hc2903 ready.
0174 move(meaddr,wrk0) ; move address of data word to address re
; register and clock memory.
0175 negadd(wrk0,q) ; wrk0 := wrk0 - q, ( next address).
0176 dwlt4: cjmp(rememo,dwlt4) not; wait for memory ready.
0177 jmp(wlt3) ; goto last of write single word
; to memory for continuation.
; end of write memory section.
; ----------------------------
;*page: XX
; fetch instruction section.
; --------------------------
; after one of the fetch entries
; contains pir ( prefetched instruction)
; the next instrcution and ic the address of the next
; after pir.
; fetch instruction with no prefetch.
; -----------------------------------
; subroutine send interupt to hc2903.
; -----------------------------------
sndint:
0200 rtn intr03 ; return and set interupt bit to
; hc2903.
0201 npref0/:and(wrk1,intreg) noload; temporary test entry.
0202 nprftc/:cjsb(zero,sndint) not cl2903; normal no prefetch entry:
; if intreg(23) = 1
; (i.e. interupt bit set
; then call subroutine send interupt,
; clock hc2903 ready to accept data.
0203 npref1: cjmp(re2903,npref1) not; wait for ic from hc2903.
0204 move(meaddr,hc2903) opramf; move the address to memory and start
; memory addres cycle, and open for
; internal registers so the address
; also is moved to
; to work 0. (does only function because
; the value off reg.addrs = the value
; of reg.wrk0 mod 16 ).
0205 sknin1: move(ic,q) ; entry from skip next,
; sync. of memory, ic := 2 .
; ( prepered for calculation of
; next next instr in prefetch logic.)
0206 npref2: cjmp(rememo,npref2) not; wait for memory address cycle.
0207 move(hc2903,medata) cl2903; move memory data word to hc2903,
; and clock hc2903.
; jsb(ictst) . call subroutine for posible writing
; of instrcution counter out in
; in memory for test purposes.
0210 add(wrk0,q) opexde ; wrk0 := wrk0 + 2, wrk0 is now
; pointing to next instruction,
; open also to extern registers
; which will cause a move of
; wrk0 to memory address register
; and start memory read cycle.
0211 add(ic,wrk0) ; calculate address of next instr.
0212 npref3: cjmp(rememo,npref3) not; wait for memory ready.
0213 move(pir,medata) ; move prefetched instruction to
; prefetch register from memory.
0214 jmp(gewait) ; goto wait cycle.
; skip next instrcution.
; entry for skip instructions.
; ============================
0215 sknin0/:and(wrk1,intreg) noload; temporary test entry:
0216 sknins/:cjsb(zero,sndint) not ; if bit(23) intreg = 1 then goto
; send interupt to hc2903.
0217 move(wrk0,ic) opexde ; move address of next instr to wrk0,
; open also
; the external registers which will
; cause a move of wrk0 to the memory
; address register and start a read
; cycle.
0220 jmp(sknin1) ; continue in fetch next instruction
; with no prefetch.
; get prefetched instruction.
; ----------------------------
0221 prftc0/:and(wrk1,intreg) noload; temporary test entry:
0222 prftch/:cjsb(zero,sndint) not ; normal entry for prefetch next
; instruction:
; if intreg(23)<>0 (i.e.
; interupt set) then call subroutine
; set interupt.
0223 move(hc2903,pir) cl2903; move prefetched instrcution to
; hc2903 and clock ready.
0224 move(wrk0,ic) ; wrk0 := ic of instruction +2.
0225 sub(wrk0,q) ; wrk0 := wrk0 - 2.
; jsb(ictst) . call subroutine ic test.
0226 move(meaddr,ic) ; move address of next prefetched
; instruction
; to memory.
0227 add(ic,q) ; calculate address of next instruction
; to be prefetched.
0230 prftc1: cjmp(rememo,prftc1) not; wait for memory address cycle.
0231 move(pir,medata) ; move prefetched instruction from memory
; to prefetch register.
0232 jmp(gewait) ; goto wait cycle.
; end fetch instruction section
; -----------------------------
0233 ictst: move(ictsad,ictsad) ; if ic test address = 0 then
0234 crtn(zero) ; then return from subroutine.
0235 move(medata,wrk0) ; send wrk0 to memory.
0236 move(meaddr,ictsad) ; send instrcution test address to
; memory address register and start write cycle.
0237 add(ictsad,q) ; calc. next ic test address.
0240 ictsw1: cjmp(rememo,ictsw1) not; wait for memory ready.
0241 rtn ; retrun from subroutine.
; special functions in rh8000
; ----------------------------
; subroutine control address from rc8000
; --------------------------------------
; the 2 second last bit of the instrcution
; controls the function of the control address.
; inst(21:22) = 00 => start after init and
; give interupt.
; inst(21:22) = 01 => reset ( goto init).
; inst(21:22) = 10 => stop imidiatly ( micro tempi stop).
; inst(21:22) = 11 => start after stop ( micro tempi start).
0242 cnrc80: move(wrk0,rc80cn) ; get control bits into wrk0.
0243 mzero(clrf80) ; clear flag bit indicating
; word send from rc8000.
0244 move(wrk2,wrk2) sr ; wrk2 := 4.
0245 and(wrk0,wrk2) noload ; if control bits '1x' then
0246 cjmp(zero,cnrc82) not ; goto control ( '11' or '10').
0247 and(q,wrk0) noload ; if control bits is '01' then
0250 cjmp(zero,reset) not ; then goto reset
0251 rtn move(wrk2,wrk2) sl; else wrk2 := 8 , start.
0252 cnrc82: and(q,wrk0) noload ; if control bits '10' then
0253 cjmp(zero,gewwri) not ; goto generel wait with init else
0254 cnrc83: cjmp(re8000,cnrc83) not; wait until signal from rc8000.
0255 move(wrk0,rc80cn) ; get control bits into wrk0.
0256 mzero(clrf80) ; clear flag indicating word
; send from rc8000.
0257 and(wrk0,wrk2) noload ; if bit(21) <> 1 then
0260 cjmp(zero,cnrc83) ; then goto wait for start ( stop).
0261 and(q,wrk0) noload ; if bit(22) <> 1 then
0262 cjmp(zero,cnrc83) ; then goto wait for start ( stop).
0263 jmp(gewwri) ; else start met goto
; generel wait with init.
;*page: XX
; generel get 66
; --------------
; wait for start by rc8000, send intreg to hc2903.
0264 geng66: jmp(cnrc83) cl2903 ; goto wait signal from
; rc8000 and check control bits.
geng64: ; generel get 64.
; ---------------
; get test register.
0265 move(hc2903,intreg) cl2903; send interupt register to
; hc2903 and clock hc2903 ready.
0266 jmp(gewait) ; goto generel wait.
geng94: ; generel get 94.
; ---------------
; get interupt controler interupt.
0267 move(hc2903,intlev) cl2903; send interupt level to hc2903
; and clock hc2903 ready.
0270 jmp(gewait) ; goto generel wait.
gng100: ; generel get 100
; ---------------
; get real time clock.
0271 move(hc2903,intlim) cl2903; send interupt limit register
; to hc2903 and clokc hc2903 ready.
0272 jmp(gewait) ; goto generel wait.
genp64: ; generel put 64
; ---------------
; generel put test register.
0273 jsb(ge03w0) cl2903 ; get word from hc2903 to wrk0.
0274 move(ictsad,wrk0) ; move data word to
; ic test address register.
0275 jmp(gewait) ; goto generel wait.
; set interupt bit in interupt register.
; ------------------------------------
; call :
; wrk1 = std init 1.
; wrk2 = std init 2.
; q = std init 2.
rc80in: ; interupt from rc8000
; the interupt is clocked direct into address location 4.
0276 jsb(cnrc80) ; call subroutine to check control
; bit from rc8000.
0277 ldct(rc80le) ; load counter with interupt level
; from rc8000.
0300 clcint: jsb(clcin1) ; push address of next micro instr.
0301 clcin1: move(wrk2,wrk2) sl ; wrk2 := wrk2 * 2, ( interupt bit).
0302 rep inc(wrk1) ; wrk1 := wrk1 + 1 ( interupt no ).
enin03: ; entry for interupt bit 0, interupt 3,
; or entry with initialised interupt
; values in wrk1 (interupt no) and
; wrk2 ( the interupt bit in the
; interupt register).
0303 add(wrk1,q) ; wrk1 := wrk1 + q ( the first inetrupt
; no is infact level 3).
; entry intrs1:
; entry when wrk2 and wrk1 is defined.
0304 intrs1: or(intreg,wrk2) ; set interupt bit in interupt register.
0305 sub(wrk1,intlev) noload; if interupt no > current interupt
0306 cjmp(neg,gewwri) not ; level then goto generel wait.
0307 intsr2: move(intlev,wrk1) ; interupt level := interupt no as
; new level.
0310 modec(wrk0,q) ; wrk0 := 1 ( bit 23).
0311 or(intreg,wrk0) ; intreg(23) := 1 ( interupt schold
; be send to hc2903).
0312 jmp(gewwri) ; goto general wait.
; interupt service
; ================
; entry from monitor call and exeptions.
intser/:
0313 jmp(intse4) cl2903 ; goto intse4, clock hc2903 ready
; to recieve information register.
; answer interupt cause and clear interupt bit
;=============================================
; in interupt register, continue in interupt
; service.
; interupt cause is current level.
; call:
; wrk0,wrk1,kwr2,q = std. reg. init.
0314 ansin/: move(hc2903,intlev) cl2903; send level to hc2903, and clock
; hc2903 ready to recieve data.
0315 negadd(intlev,q) ; justifi intlev because the
0316 dec(intlev) ; first interupt bit corrospond
; with intlev 3.
0317 ansin3: andinv(intreg,wrk2) ; clear interupt bit.
0320 move(wrk2,wrk2) sl ; wrk2 := wrk2 * 2 (next interupt bit).
0321 dec(intlev) ; intlev := intlev - 1.
0322 cjmp(neg,ansin3) not ; if interupt level > 0 then got ansin3.
0323 intse4: andinv(intreg,wrk1) ; clear possible interupt bit
; in interupt register.
0324 cjmp(re2903,intse4) not; wait for hc2903 ready.
0325 move(wrk2,hc2903) ; get address of status and interupt
; limit initialisation.
0326 move(intlev,wrk2) ; remove possible last bit
0327 andinv(intlev,wrk1) ; in address.
0330 move(meaddr,intlev) ; send address to memory and
; start read cycle.
0331 moinv(wrk0,wrk1) sr ; start make bit in last halfword.
; wrk0 := -1 ( all bits) shift -1.
0332 lcpu(hfwdm1) ; load counter with no of bits in
; a halfword minus 1 ( first shift
; made when negating wrk1 into wrk0).
0333 rep move(wrk0,wrk0) sr; repeat until counter = 0 do
; wrk0 := wrk0 shift -1.
; counter := counter -1.
; end.
0334 intse1: cjmp(rememo,intse1) not; wait for memory ready cycle.
0335 move(hc2903,medata) cl2903; send status/intlim to
; hc2903 data register
; and clock hc2903.
0336 move(intlim,medata) ; intlim := status/intlim.
0337 add(meaddr,q,intlev) ; send inf+2 to memory address
; register and start read cycle.
0340 and(intlim,wrk0) ; intlev := intlev(12:23),
; only last 12 bits contain
; interupt limit.
0341 move(intlev,intlim) ; interupt level := interupt limit.
0342 negadd(wrk2,q) ; nessecary for sunc of memory,
; wrk2 (inf) := wrk2 - 2.
0343 dec(wrk2) ; wrk2 := wrk2 -1.
; ( totaly inf := inf - 3).
0344 andinv(wrk2,wrk1) ; clear bit(23) in address.
0345 intsw2: cjmp(re2903,intsw2) not; wait for hc2903.
0346 intse2: cjmp(rememo,intse2) not; wait for memory ready.
0347 move(hc2903,medata) cl2903; send reg. dump. addr to hc2903,
; and clock hc2903 ready
0350 move(wrk1,medata) ; wrk1 := reg. dump. addrs.
0351 jsb(dmp8w) ; call subroutine to dump 8 words from
; hc2903 to memory, first word addresed by
; by wrk1.
0352 move(meaddr,wrk2) ; sedn addres of new ic to memory.
0353 intsw3: cjmp(re2903,intsw3) not; wait for hc2903 ready.
; ness. sync. of mem.
0354 intse3: cjmp(rememo,intse3) not; wait for memory ready.
0355 move(hc2903,medata) cl2903; send new ic to hc2903,
; and clock hc2903 ready.
0356 jmp(stdil3) ; continue in set disable level
; entry 3, for control of
; possible interupts with
; lover level.
; set current interupt level.
; -----------------------------
; entry select interupt enable level.
; disable level and enable level is in intlim register.
; current level is intlev register.
; entry call:
; wrk1 := 1.
; q := 2.
0357 stenle/:moinv(intlev,wrk1) sr cl2903; intlev := -1 (allbits) shift -1,
; clock hc2903 ready.
0360 lcpu('hfwdm1) ; load counter with no of
; bits in a halfword minus 1, and
; push next micro instr address.
0361 rep move(intlev,intlev) sr; intlev := intlev(0:11), all bits
; in rigth halfword.
0362 and(intlev,intlim) ; interupt level := enable level.
0363 jmp(stdil1) ; goto set disable level entry 1.
0364 stdile/:move(intlev,intlim) sr cl2903; intlev := interupt limit,
; clock hc2903 ready.
0365 lcpu('hfwdm1) ; load counter with no of bits
; in half word and push next address.
0366 rep move(intlev,intlev) sr; interupt limit := interupt limit(0:11).
; ( disable level).
stdil1:
stdil2: ; entry from return from interupt.
0367 andinv(intreg,wrk1) ; clear possible interupt bit.
stdil3: ; entry from answer interupt.
0370 move(wrk1,q) ; wrk1 := q (2).
0371 move(wrk2,wrk1) sl ; wrk2 := wrk1*2 (4).
0372 lcpu('intno) ; load counter with max no of interupt
; allowed.
0373 inc(wrk1) ; wrk1 := next interupt no.
0374 move(wrk2,wrk2) sl ; wrk2 := next interupt bit.
0375 and(intreg,wrk2) noload; if interupt bit is set then
0376 cjmpp(zero,intsr2) not; pop counter and goto intse2 ( entry
; in interupt routine.
0377 sub(wrk1,intlev) noload; if interupt no > new level then
0400 twb(neg,gewwri) not ; pop counter and continue in next
; micro instr, else invistigate
; next interupt bit while not all interupt
; is examinied.
0401 jmp(gewwri) ; goto generel wait.
; entry function restore 8 dynamic registers to hc2903.
; -----------------------------------------------------
0402 redyre/:jsb(ge03w0) cl2903 ; get address of first dynamic register.
; into w0.
0403 jsb(lodyre) ; call subroutine load dynamic registers.
0404 jmp(gewait) ; goto generel wait.
; subroutine load 8 registers.
; ----------------------------
0405 lodyre: ldct('dyreno) ; load counter with no of dynamic register
; entry load any number of registers,
; from hc2901 to hc2903.
0406 lonore: jsb(lonor1) ; push address of next micro instr.
0407 lonor1: move(meaddr,wrk0) ; send wrk0 to memory address regsiter and
; start memory read cycle.
0410 add(wrk0,q) ; memory address pointer := memory
; address pointer + 2.
0411 redyr1: cjmp(re2903,redyr1) not; wait until hc2903 is ready.
0412 redyr2: cjmp(rememo,redyr2) not; wait for memory ready.
0413 rep move(hc2903,medata) cl2903; move word from memory to hc2903,
; clock hc2903 ready, repeat loop.
0414 rtn ; return from subroutine.
; entry function return from interupt select next process registers.
; ------------------------------------------------------------------
0415 rtrnpr/:jsb(ge03a0) cl2903 ; get address of system table
; register dump addressfrom hc2903
; to memory and start read cycle.
0416 rtnnp2: cjmp(rememo,rtnnp2) not; wait for memory ready.
0417 move(hc2903,medata) cl2903; send reg dump address to hc2903.
0420 move(wrk0,medata) ; get register dump address to wrk0.
0421 andinv(wrk0,wrk1) ; clear bit(23) in address.
0422 jsb(lodyre) ; call subroutine load dynamic registers.
0423 rtnnp3: cjmp(re2903,rtnnp3) not; wait for hc2903 to recieve address
; of process definition registers.
0424 move(wrk0,hc2903) ; move address of register definition
; registers to wrk0.
0425 andinv(wrk0,wrk1) ; clear bit(23) of address.
0426 ldct(3) ; load counter with number of process
; definition registers.
0427 jsb(lonore) ; call subroutine load nomber of
; registers.
0430 move(meaddr,wrk0) ; send wrk0 to memory address.
0431 moinv(intlev,wrk1) sr ; intlev := -1 ( all bits) shift -1.
0432 lcpu('hfwdm1) ; load counter with no of bits in
; a halfword minus 1, and push
; next address.
0433 rep move(intlev,intlev) sr; intlev := intlev(0:11)
; all last 12 bit set.
0434 rtnnp4: cjmp(rememo,rtnnp4) not; wait for memory ready.
0435 move(intlim,medata) ; load interupt limit.
; set enable level.
0436 and(intlev,intlim) ; intlev := intlim(12:23).
; last halfword of interupt limit.
0437 jmp(stdil1) ; goto set disable level entry 1.
; entry functionsave 8 dynamic registers.
; ---------------------------------------
0440 sadyre/:jsb(ge03w0) cl2903 ; get address whereto the registers
; is to be written.
0441 move(wrk1,wrk0) cl2903; wrk1 := wrk0, clock hc2903 to continue.
0442 jsb(dmp8w) ; call subruotine to dump 8 words
; from hc2903 .
0443 jmp(gewwri) ; goto generel wait with init.
; subroutine dump 8 words from hc2903 to memory.
; entry wrk1 := address.
; entry q := 2.
0444 dmp8w: lcpu('dyreno) ; load counter with number of
; registers to be saved, and clock hc2903
; ready to accept 1. data word.
; repeat:
0445 dmp8w1: cjmp(re2903,dmp8w1) not; wait until hc2903 ready to send data
; word.
0446 move(medata,hc2903) cl2903; send data word from hc2903 to memory,
; and clock hc2903 ready to accept
; next data word.
0447 move(meaddr,wrk1) ; send address to memory
; address register and
; start memory write cycle.
0450 dmp8w3: cjmp(rememo,dmp8w3) not; wait for memory ready.
0451 rep add(wrk1,q) ; increase memory address pointer
; by to and repeat loop.
0452 rtn ; return from subroutine.
; data in and data out section.
; -----------------------------
; time out and other exceptions to hc2903.
; =========================================
; time out from data in and data out.
; -----------------------------------
0453 iotmo0: cont cl2903 ; clock hc2903 for dummy address.
0454 iotmw0: cjmp(re2903,iotmw0) not; wait for hc2903 ready.
0455 iotmo1: cont cl2903 ; send dummy data word to hc2903.
0456 iotmw1: cjmp(re2903,iotmw1) not; wait for hc2903 ready.
0457 iotmo2: move(hc2903,q) cl2903; send status bit 2 ( time out )
; to hc2903
0460 jmp(gewwri) ; goto general wait.
; entry for not used data in and dataout instructions.
dintus: ; data in functions not used.
dontus: ; data out functions not used.
; bus comunication error in data in and data out.
; -----------------------------------------------
0461 bucoe0: cont cl2903 ; clock hc2903 and wait.
0462 bucow0: cjmp(re2903,bucow0) not; wait for ready.
0463 bucoe1: cont cl2903 ; clock hc2903 for dummy data word.
0464 bucow1: cjmp(re2903,bucow1) not; wait for ready.
0465 bucoe2: cont cl2903 ; clock hc2903 for data word recieve.
0466 bucow2: cjmp(re2903,bucow2) not; wait for hc2903 to accept status word.
0467 bucoer: move(hc2903,wrk1) cl2903; send a one or what ever the
; contents of wrk1 is as status word
; to hc2903 and clock
; the hc2903 ( the bus communication
; error bit).
0470 jmp(gewwri) ; goto general wait with init.
; normal answer from data in and data out.
; ----------------------------------------
0471 noran0: cont cl2903 ; clock hc2901 for dummy addrs.
0472 noraw0: cjmp(re2903,noraw0) not; wait for hc2903 ready to send addrs.
0473 noran1: cont cl2903 ; clock hc2903 , for dummy
; address word.
0474 noraw1: cjmp(re2903,noraw1) not; wait for hc2903to send data.
0475 noran2: cont cl2903 ; return data word to hc2901 and wait.
0476 noraw2: cjmp(re2903,noraw2) not; wait for hc2901 to accept data word
; and be ready to accept status bits.
0477 norans: mzero(hc2903) cl2903 ; send a zero to hc2903 indicating
; that no exceptions bit are set.
0500 jmp(gewwri) ; goto generel wait with init.
; subroutine wait for hc2903.
0501 wa0300: cjmp(re2903,wa0300) not; wait for hc2903
0502 cont cl2903 ; clock hc2903
0503 wa0301: cjmp(re2903,wa0301) not; wait for hc2903
0504 rtn ; return form subroutine.
; subroutine get device block address.
; ------------------------------------
; call w0 = divice no*8.
; wrk2 = 8.
0505 gedvbl: move(meaddr,wrk2) ; start memeory read cycle in word 8.
0506 gedvb1: cjmp(rememo,gedvb1) not; wait for memory ready.
0507 move(wrk1,medata) ; get device base.
0510 add(wrk0,wrk1) ; wrk0 := wrk0 ( device no * 8) +
; device address base.
0511 rtn modec(wrk1,q) ; wrk1 := 1, return .
; data out unibus reset and start.
; --------------------------------
douni1: ; data out on unibus reset command.
0512 jsb(ge03w0) cl2903 ; get address from hc2903.
0513 or(wrk0,q) ; set reset control bit an address.
0514 jmp(dounix) ; continus in data out unibus start.
douni0: ; data out on unibus start command.
; ---------------------------------
0515 jsb(ge03w0) cl2903 ; get address from hc2903 into wrk0.
0516 dounix: move(wrk1,wrk1) sraq ; set sign bit in wrk1 by shifting
0517 move(wrk1,wrk1) sraq ; the contents of q register ( 2)
; into bit 23.
0520 or(wrk0,wrk1) ; set sign bit in address.
0521 move(wrk1,wrk1) slaq ; reestablish wrk1 and q.
0522 move(wrk1,wrk1) slaq ;
0523 jmp(dowmw3) cl2903 ; continue in data out
; write memory word.
; data out, write data word in own memory.
; ----------------------------------------------
0524 dowrme: jsb(ge03w0) cl2903 ; get address of memory word to
; wrk0.
0525 cont cl2903 ; clock hc2903 to accept data word.
0526 dowmw3: cjmp(re2903,dowmw3) not; wait for hc2903 ready sen data word.
0527 move(medata,hc2903) ; move data word to memory data register.
0530 move(meaddr,wrk0) ; move addrs of memory data word to
; memory address register and clock memory.
0531 lcpu('metimo) ; load counter and pusch next micro instr.
; into micro stack.
0532 twb(rememo,iotmo2) ; repeat
; if counter = 0 then goto iotmo1.
; micro counter := micro counter.
; until memory ready.
0533 jmp(noraw1) ; goto normal answer, ( wait for data
; ready).
; data in, read data word from memory.
; ----------------------------------------
0534 direme: jsb(ge03a0) cl2903 ; clock hc2903, and call subroutine
; to get word from hc2903 to memory
; address register and clock memory.
0535 lcpu('metimo) ; load micro counter with
; 200 and push next micro instr to
; micro stack.
0536 twb(rememo,iotmo0) ; wait for memory ready 200 cycles.
; if not memory ready then goto iotmo0.
0537 jsb(wa0300) ; call subroutine to accept dummy
; data word and wait ready.
0540 move(hc2903,medata) cl2903; move data word to hc2903, and clock
; hc2903.
0541 jmp(noraw2) ; goto normal answer with 1 wait.
; section channel input output.
; =============================
; data out, channal reset.
0542 dochre: mzero(dochwc) ; reset data out word counter.
0543 jmp(noran0) ; goto normal answer.
; NOTE: after the resetting it
; is possibly that
; a data out finis interupt
; will be given.
; data out, channel start.
; ------------------------
dochst/:
0544 move(dochwc,dochwc) cl2903; clock hc2903 ready to recieve
; address,
; if word counter <> 0 then
0545 cjmp(zero,bucow0) not ; then goto bus cummunication error.
0546 dochw1: cjmp(re2903,dochw1) not; wait for hc2903 ready to sned address.
0547 move(wrk0,hc2903) cl2903; wrk0 := address, clock hc2903 ready
; to recieve data word.
0550 dochw2: cjmp(re2903,dochw2) not; wait for hc2903 to revieve data word.
0551 move(dochwc,hc2903) cl2903; get data word form hc2903, clock
; hc2903 ready to accept not used
; data word.
0552 negadd(dochwc,q) noload; if word counter < 2 then
0553 cjmp(neg,dochs3) ; then goto dochs3, ( send message).
0554 jsb(gedvbl) ; call subroutine to get device block
; address.
0555 add(wrk0,q) ; divice block address := device
; block address + 2.
0556 move(meaddr,wrk0) ; send adrress of word counter to
; memory and start read cycle.
0557 dochs1: cjmp(rememo,dochs1) not; wait for memory ready.
0560 move(dochad,medata) ; get channel block address.
0561 sub(dochad,wrk2) noload; if address of data block < 8
0562 cjmp(neg,bucow2) ; then goto bus communication error.
0563 cont stwrch ; clock start write channel.
0564 move(chdata,dochwc) ; send channel output word counter
; to channal data buffer as first
; word.
0565 cont fiwrch ; clock finis write channel.
0566 add(dochwc,q) ; data out channel word counter :=
; data out channel word counter +2,
; (after a subtraction by 2 in start of
; channel input interupt fetch, docchwc
; contain the number of bytes left to send,
; i.e. dochwc gives the no of bytes which
; their is not recieved a interupt answer
; for, that includes the first control word.)
0567 jmp(noraw2) ; goto normal answer 1.
dochs3: ; entry word counte < 2.
; only word counter is send.
0570 cont stwrch ; clock start write channel.
0571 move(chdata,dochwc) ; send word counter.
0572 cont fiwrch ; clcok finis write channel.
0573 jmp(noraw2) ; goto to normal answer.
; entry interupt from channel output buffer.
; ------------------------------------------
0574 choint: cont clchoi ; clear channel output interupt.
0575 negadd(dochwc,q) ; channel word counter := channel word
; counter -2.
0576 cjmp(neg,dochni) ; if word counter < 0
; then goto answer message▶16◀▶16◀▶16◀▶16◀
; with no interrupt
0577 move(dochwc,dochwc) ; if data out channel word counter = 0 then
0600 cjmp(zero,dochfi) ; send channel output finis interupt
; to hc2903.
0601 move(meaddr,dochad) ; send channel output block address
; to memory and start read cycle.
0602 add(dochad,q,dochad) ; block address counter :=
; block address counter + 2.
0603 docht1: cjmp(rememo,docht1) not; wait for memory ready.
0604 cont stwrch ; clock start write channel.
0605 move(chdata,medata) ; send memory data word to channel
; data word.
0606 cont fiwrch ; finis write channel.
0607 jmp(gewait) ; goto generel wait.
0610 dochni: mzero(dochwc) ; reset data word couter, and goto
0611 jmp(gewait) ; general wait without interrupt.
dochfi: ; data out channel finis interuot.
; --------------------------------
0612 mzero(dochwc) ; reset data word counter.
0613 ldct('chofil) ; load mic. counterwith channel output
; finis interupt level.
0614 jmp(clcint) ; goto calculate and set interupt.
; data in, channel reset.
; -----------------------
0615 dichre/:mzero(dichwc) ; reset data in word counter.
0616 jmp(noran0) ; goto normal answer.
; if given in the middle of in input
; input operation the output opration
; from the other computer is migth
; not finis.
; data in, channel start
; ----------------------
dichst/:
0617 jsb(ge03w0) cl2903 ; get device address from hc2903.
0620 cont strech cl2903 ; clock start reading of channel,
; clock hc2903 ready to get recieve
; not used data word.
0621 move(dichwc,chdata) ; get first data word.
0622 cont firech ; click finis reading of channel.
0623 negadd(dichwc,q) noload; if data word < 2 then
0624 cjmp(neg,dichs3) ; then goto dichs3, ( message arrived).
0625 jsb(gedvbl) ; call subroutine to get divice block
; address, and clock hc2903 ready to recieve dummy
; data word.
0626 add(wrk0,q) ; device block address + 2 to get
; data block address, ( word counter is
; not used).
0627 move(meaddr,wrk0) ; send address of data block address to memory
; memory and start read cycle.
0630 dichs1: cjmp(re2903,dichs1) not; wait for accept not used data word.
0631 move(hc2903,dichwc) cl2903; send word counter to hc2903,
; ( goes to the data in instruction
; w register), and clock hc2903 ready.
0632 dichs2: cjmp(rememo,dichs2) not; wait for memory ready.
0633 move(dichad,medata) ; get channel block address.
0634 negadd(dichwc,q) noload; if data in channel word counter < 2
0635 cjmp(neg,dichei) ; goto data in channel error in start.
0636 jmp(noraw2) ; else goto normal answer.
dichs3: ; message word revieved through channel.
0637 cjmp(re2903,dichs3) not; wait for acccepting not used
; data word.
0640 move(hc2903,dichwc) cl2903; send message word to
; hc2903 and clock data word ready
; from input.
0641 mzero(dichwc) ; reset data channel input word counter.
0642 jmp(noraw2) ; goto normal answer 2.
dichei: ; error at start of data in instruction.
0643 mzero(dichwc) ; clear data in word counter.
0644 jmp(bucow2) ; goto bus communication error.
; entry: interupt from channel input buffer.
; ------------------------------------------
0645 chiint: cont clchii ; clear channel input interupt.
0646 move(dichwc,dichwc) ; data in word counter = 0 then
0647 cjmp(zero,dichsi) ; goto data in channel interupt start.
0650 cont strech ; clock start reading of channel
0651 move(medata,chdata) ; send channel data to memory
0652 cont firech ; clock finis reading of channel.
0653 move(meaddr,dichad) ; send channel data in data block
; address to memory and start
; write cycle.
0654 chiin2: cjmp(rememo,chiin2) not; wait for memory ready.
0655 negadd(dichwc,q) ; decrease word counter with 2.
0656 cjmp(zero,dichfi) ; if word counter = 0 then
; goto data in channel interupt finis.
0657 add(dichad,q) ; increase data in channel block address
; with 2.
0660 jmp(gewait) ; goto generel wait.
dichfi: ; data in channel input finis transport interupt.
; -----------------------------------------------
0661 ldct('chifil) ; load counter with channel input finis
; level.
0662 jmp(clcint) ; goto calcuæate and set interupt bit.
dichsi: ; data in channel input start transport interupt.
; -----------------------------------------------
0663 ldct('chisil) ; load counter with channel input start
; interupt level.
0664 jmp(clcint) ; goto calculate interupt.
;*page: XX
;*page: XX
*end:
e01di0 \r reff. to address 0015 0017 spec. 258
e01di1 \r reff. to address 0016 0020 spec. 259
e01di2 \r reff. to address 0017 0021 spec. 260
e01do0 \r reff. to address 0006 0006 spec. 237
e01do1 \r reff. to address 0007 0007 spec. 239
e01do2 \r reff. to address 0008 0010 spec. 244
e01do3 \r reff. to address 0009 0011 spec. 246
e01do4 \r reff. to address 0010 0012 spec. 248
e01do5 \r reff. to address 0011 0013 spec. 253
e01do6 \r reff. to address 0012 0014 spec. 254
e01do7 \r reff. to address 0013 0015 spec. 255
e01di3 \r reff. to address 0018 0022 spec. 261
e01di4 \r reff. to address 0019 0023 spec. 266
e01di5 \r reff. to address 0020 0024 spec. 268
e01di6 \r reff. to address 0021 0025 spec. 269
e01di7 \r reff. to address 0022 0026 spec. 270
e01pdw \r reff. to address 0028 0034 spec. 276
e01rtc \r reff. to address 0029 0035 spec. 277
e01aci \r reff. to address 0038 0046 spec. 288
prftch \r reff. to address 0146 0222 spec. 836
e01rtr \r reff. to address 0030 0036 spec. 278
e01rtw \r reff. to address 0032 0040 spec. 280
nprftc \r reff. to address 0130 0202 spec. 779
e01sdl \r reff. to address 0035 0043 spec. 285
e01cil \r reff. to address 0041 0051 spec. 291
e01dib \r reff. to address 0014 0016 spec. 256
e01dob \r reff. to address 0005 0005 spec. 231
e01dim \r reff. to address 0014 0016 spec. 257
e01dom \r reff. to address 0005 0005 spec. 232
e01is1 \r reff. to address 0039 0047 spec. 289
e01wtr \r reff. to address 0031 0037 spec. 279
e01gmw \r reff. to address 0025 0031 spec. 273
redyre \r reff. to address 0258 0402 spec. 1228
dwrm0 \r reff. to address 0120 0170 spec. 725
sadyre \r reff. to address 0288 0440 spec. 1290
dichre \r reff. to address 0397 0615 spec. 1728
stdile \r reff. to address 0244 0364 spec. 1200
stenle \r reff. to address 0239 0357 spec. 1191
rtrnpr \r reff. to address 0269 0415 spec. 1249
e01pmw \r reff. to address 0026 0032 spec. 274
e01ip \r reff. to address 0024 0030 spec. 272
e01rin \r reff. to address 0037 0045 spec. 287
e01sel \r reff. to address 0034 0042 spec. 284
ansin \r reff. to address 0204 0314 spec. 1086
e01skn \r reff. to address 0040 0050 spec. 290
e01drd \r reff. to address 0033 0041 spec. 283
e01drr \r reff. to address 0036 0044 spec. 286
e01gdw \r reff. to address 0027 0033 spec. 275
sknin0 \r reff. to address 0141 0215 spec. 820
drem0 \r reff. to address 0104 0150 spec. 657
e01ini \r reff. to address 0000 0000 spec. 210
e01inp \r reff. to address 0023 0027 spec. 271
dochst \r reff. to address 0356 0544 spec. 1639
dichst \r reff. to address 0399 0617 spec. 1736
sknins \r reff. to address 0142 0216 spec. 821
intser \r reff. to address 0203 0313 spec. 1072
npref0 \r reff. to address 0129 0201 spec. 778
prftc0 \r reff. to address 0145 0221 spec. 835
name spec. instr. octal
dichst 1736 399 617 1 143
dichre 1728 397 615 1 141
dochst 1639 356 544 1 100
sadyre 1290 288 440 1 32
rtrnpr 1249 269 415 1 13
redyre 1228 258 402 1 2
stdile 1200 244 364 0 244
stenle 1191 239 357 0 239
ansin 1086 204 314 0 204
intser 1072 203 313 0 203
prftch 836 146 222 0 146
prftc0 835 145 221 0 145
sknins 821 142 216 0 142
sknin0 820 141 215 0 141
nprftc 779 130 202 0 130
npref0 778 129 201 0 129
dwrm0 725 120 170 0 120
drem0 657 104 150 0 104
e01cil 291 41 51 0 41
e01skn 290 40 50 0 40
e01is1 289 39 47 0 39
e01aci 288 38 46 0 38
e01rin 287 37 45 0 37
e01drr 286 36 44 0 36
e01sdl 285 35 43 0 35
e01sel 284 34 42 0 34
e01drd 283 33 41 0 33
e01rtw 280 32 40 0 32
e01wtr 279 31 37 0 31
e01rtr 278 30 36 0 30
e01rtc 277 29 35 0 29
e01pdw 276 28 34 0 28
e01gdw 275 27 33 0 27
e01pmw 274 26 32 0 26
e01gmw 273 25 31 0 25
e01ip 272 24 30 0 24
e01inp 271 23 27 0 23
e01di7 270 22 26 0 22
e01di6 269 21 25 0 21
e01di5 268 20 24 0 20
e01di4 266 19 23 0 19
e01di3 261 18 22 0 18
e01di2 260 17 21 0 17
e01di1 259 16 20 0 16
e01di0 258 15 17 0 15
e01dim 257 14 16 0 14
e01dib 256 14 16 0 14
e01do7 255 13 15 0 13
e01do6 254 12 14 0 12
e01do5 253 11 13 0 11
e01do4 248 10 12 0 10
e01do3 246 9 11 0 9
e01do2 244 8 10 0 8
e01do1 239 7 7 0 7
e01do0 237 6 6 0 6
e01dom 232 5 5 0 5
e01dob 231 5 5 0 5
e01ini 210 0 0 0 0
MIC. ASM. OK!
LAST INSTR. ADDRS.: 437 OCTAL INSTR. ADDRS.: 665 TRANSLATOR BLOCKS: 103
▶EOF◀