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Names: »listrh03«
└─⟦667bb35d6⟧ Bits:30007480 RC8000 Dump tape fra HCØ.
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Micro asm.: micasm03 version date.810603.1340
Source file: tcgorder030 version date.811013.1005
Object file: rhorder03 version date.0811013.1014
;*page: XXXX micasm03
*load: m2903
; ----------------------------
; skipped is code 'finalx'
; skipped is code 'rhtest'
; 810810/1710:
; auto load interupt removed.
; skipped by code 'autoin'
; 810810/1700:
; fetch 8000 instr: from register repaired.
; 810810/1730:
; clearing of last bit in ic removed from jl
; instrcution and inserted in noprefetch module
; now ic can never be negative.
; also corrected in rh2901.
; 810817/2000:
; gg 94 introduced, get interupt level
; from amd9511 interupt controler.
; 810817/2000:
; gg with address >= 200 defined as
; user programmed instructions. (i.e
; instrcution which can be used from a
; user program and gives a result which
; is defines by a user.
; 810817/2000:
; gg 200 = reverse bits in register selected.
; 810818/0900:
; gg 201 = count register 1 and skip if zero.
; gg 202 = count register 2 and skip if zero.
; the skip is performed when the selected register
; reach or pass zero.
; the count can be both positive
; and negative depending on the sign of the
; contents of the selected working register.
; 810819/1100:
; fetch changed so address after jump vector
; is contained in wrk1, and wrk1 is subtracted
; the address register at external interupt.
; 810825/2000:
; all instruction code mnemonics changed
; so when in doubt they are prefixed with a
; letter r or a letter s signifing from which
; mux the operand is entering the alu.
;NEXT.
; ------------------------------------------------------------
; WHAT SCHOULD BE DONE:
; 001: if you define that yuo never double store
; overlabing registers and memory(8)
; or double load some check could be removed.
; 002: if you define that registers that contain
; HC8000 instr:s, never continue in memory(8)
; some check in module regins can be removed.
; 003: if you define that the word which is stored
; by a store 8000 instr: never is used by
; as the absolute next 8000 instr:, then
; some check can be removed in the store module.
; 004: the increment of the instruction counter could be
; much earlyer in most instrcution. fx. in the
; same moment you call get op, if you insure that
; the increment is removed from exeption.
; NEXT WHAT.
; --------------------------------------------------------------
; -------------------------------------------------------------
; micro 8000 instr: description.
;
; only one format.
; mir(0) is msb.
; mir(47) is lsb.
;
; mir(0) = -, cc ccenable.
; mir(1:4) = amd2910 micro program sequencer 8000 instr:.
; mir(5) = -,( ce my)
; mir(6) = -,( ce M)
; mir(7:10) = amd2904 condition select.
; mir(11:20) = amd2903 bitslice 8000 instr:.
; mir(14) is intruction bit 5 for msh.
; mir(15) is 8000 instr: bit 5 for lsh.
; mir(21:22) = amd2904 carry control.
; mir(23) = -,(amd2904 enable)
; mir(24) = -,(ea)
; mir(25) = hc8000 working register select.
; mir(26) = -,(Oeb)
; mir(27) = -,(write hc2901)
; mir(28:31) = source register address ( a address to amd2903).
; mir(32:35) = disitnation register address.
; mir(26:27) = jump address, imidiate operand.
*const: e01inp,23 ; entry get intr. with no prefetc
*const: e01ip,24 ; entry in hc2901 instr. with prefetch.
; - -- - -
*const: e01gmw,25 ; entry in hc2901 get memory word.
*const: e01pmw,26 ; entry in hc2901 put memory word.
*const: e01gdw,27 ; entry in hc2901 get double memory word.
*const: e01pdw,28 ; entry in hc2901 put double memory word.
*const: e01rtc,29 ; gg(100) , generel get real time clock.
*const: e01rtr,30 ; generel get test register ( 64)
*const: e01wtr,31 ; generel put testregister ( 64)
*const: e01rtw,32 ; generel get test register with wait
; (66).
*const: e01dom,13 ; data out memory word.
*const: e01dob,5 ; data out function jump table.
*const: e01dim,22 ; data in memory word.
*const: e01dib,14 ; data in function jumb table.
*const: e01drd,33 ; dynamic registers dump
*const: e01drr,36 ; dynamic registers restore.
*const: e01rin,37 ; return from interupt.
*const: e01aci,38 ; get and clear interupt or exeption.
*const: e01ini,0 ; initialize.
*const: e01sdl,35 ; set interupt disable level.
*const: e01sel,34 ; set interupt enable level.
*const: e01is1,39 ; interupt service entry 1.
*const: e01skn,40 ; entry skip next instr and fetch.
*const: e01cil,41 ; gg (94) get interupt level from
; amd9511 charakter interupt level
; controler.
*const: montop,256 ; the higest monitor operation is set to
*const: autoin,6 ; cause no of auto load. (interupt 3
*const: disbit,8 ; position of diable bit in
; the status register bit(20).
; system table error).
; a fixed valus of 512.
*origo: 0
0000 jmp(init) ; goto init.
; address calculations.
; =====================
0001 nomodi/"0:jmap ; no modifiers
0002 relati/"8:jmap add(addrs,ic) ; relative
0003 relax1/"9:jmp(relati) add(addrs,x1) ; reletive and x1
0004 relax2/"10:jmp(relati) add(addrs,x2) ; relative and x2
0005 relax3/"11:jmp(relati) add(addrs,x3) ; relative and x3
0006 onlyx1/"1:jmap add(addrs,x1) ; only x1
0007 onlyx2/"2:jmap add(addrs,x2) ; only x2
0010 onlyx3/"3:jmap add(addrs,x3) ; only x3
0011 iomodi/"4:jsb(getop) ; only indirect
0012 jmap mover(addrs,wrk0) ;
0013 inlyx1/"5:jsb(getop) add(addrs,x1) ; indirect and x1.
0014 jmap mover(addrs,wrk0) ;
0015 inlyx2/"6:jsb(getop) add(addrs,x2) ; indirect and x2.
0016 jmap mover(addrs,wrk0) ;
0017 inlyx3/"7:jsb(getop) add(addrs,x3) ; indirect and x3.
0020 jmap mover(addrs,wrk0) ;
0021 ielati/"12:jsb(getop) add(addrs,ic) ; indirect and relative
0022 jmap mover(addrs,wrk0) ;
0023 ielax1/"13:jmp(ielati) add(addrs,x1) ; indirect and relative and x1
0024 ielax2/"14:jmp(ielati) add(addrs,x2) ; indirect and relative and x2
0025 ielax3/"15:jmp(ielati) add(addrs,x3) ; indirect and relative and x3
▶01◀
; new initialize.
; ---------------
0026 init: mzero(base) nothm csmy shinz ; base := 0, reset half word
; move logic, set normal condition
; select logic, set shift in
; zero.
0027 invr(cpa,base) srgt ; cpa := max integer.
0030 invr(status,cpa) ; status(1:23) := 0,
; status(0) := 1 ( monitor mode).
0031 mover(uplim,cpa) ; uppper limit := max integer
; schould be memory sixe.
0032 mover(lowlim,8) ; lower limit := 8.
0033 cjvec(neg) ; if lowerlimit is negative then
; jump vector prom, (this is not
; the case because 8 is put into
; lower limit, so next micro
; HC8000 instr: is allways performed
; next but it cause the interupt
; bit to be cleared).
0034 invr(hc2901,'e01ini) ; clock hc2901 in no address.
0035 init1: cjmp(re2901,init1) invs(ic,hc2901); wait for hc2901 ready,
; ic := hc2901.
0036 jmp(nopfic) ; goto nopfic ( fetch instr with
; no prefetch.
; entry get 8000 instr: with no prefetch
; ---------------------------------------
0037 nopfne: inctwo(ic) ; ic:=ic+2.
0040 nopfic: andinv(ic,1) ; clear possible last bit
; in 8000 instr: pointer.
0041 sub(ic,8) noload ; if ic < 8 then
0042 cjmp(less,regins) mzero(addrs) ; goto regins, addrs := 0.
0043 npref2: invr(hc2901,'e01inp) ;
0044 jsb(chlicp) mover(wrk0,ic) ; wrk0 := ic, call subroutine
; check limit and cpa.
0045 fetch1: cjmp(re2901,fetch1) clre01 ; wait until hc2901 is ready.
0046 jmp(fetch2) invs(hc2901,wrk0) ; send address of next instr to
; the hc2901, goto fetch2.
; entry skip next 8000 instr: and fetch.
; --------------------------------------
0047 sknini: inctwo(ic) ; ic := ic + 2.
0050 sknins: sub(ic,10) noload ; if ic < 10 then
0051 cjmp(less,regins) mzero(addrs) ; goto regins, addrs := 0.
0052 invr(hc2901,'e01skn) ; clock hc2901 in skip next.
0053 jmp(fetch2) ; continue in wait instrcution.
; entry fetch 8000 instr: with prefetch
; --------------------------------------
0054 pfneic: inctwo(ic) ; ic := ic + 2.
0055 pficin: sub(ic,10) noload ; if ic < 10 then
0056 cjmp(less,regins) mzero(addrs) ; goto regins, addrs := 0.
; if the previous 8000 instr: was
; taken from w3, then the prefetch
; function wil not work, so the next
; is taken without prefetch,
; this check is ofcource not performed
; in the getting of w3 because
; the 8000 instr: in w3 could be a
; jump to an 8000 instr: in w0.
; hold condition from previous
; HC8000 instr: to next.
0057 ftcam: invr(hc2901,'e01ip) ; clock hc2901 in entry get
; instrcution with no prefetch.
; also entry from 'am' anstruction.
0060 fetch2: mover(wrk2,3) ; init wrk2 with 3.
0061 fetch3: cjmp(re2901,fetch3) invs(wrk1,hc2901) signex ;
; wait for hc2901 to send instrcution
; move instrcution with sign extension
; to wrk1 so wrk1 now contain
; the instrcutions displacement field.
0062 mover(q,wrk1) clre01 ; extra clock of read so their is time
; to clock the vector and the mapping
; prom with the instrcution field
; and the address mofifier field,
; move the diaplacement field to
; the q register with a move out
; of the amd2903 r bus, so the
; it is certain that the birectional
; bus db is notclocked
; from any output the amd2903.
0063 jvec add(addrs,addrs,q)▶16◀▶16◀▶16◀▶16◀ clre01 nothm shinz csmy;
; addrs := addrs + displacement field,
; clock the hc2901
; read bit,
; get instr from register.
; if previous 8000 instr: was taken from w3,
; then will the prefetch not work so
; the next is taken witout prefetch,
; this check is of course not performed in
; the getting of w3 bacause the 8000 instr: in w3 could be
; a jump to 8000 instr: in w0 ( e.x dummy lowrk0 the monitor).
; registers is numbered:
; w0 = 0
; w1 = 2
; w2 = 4
; w3 = 6
; negative value = program exeption.
; 8 = get next from memory with no prefetch.
0064 regins: sub(ic,4) noload ; if ic < 4 then
0065 cjmp(less,insw01) holdmy ; goto get w0 or w1 or negative
; address, hold condition.
0066 cjmp(equal,regin1) mover(wrk0,w2); if ic =4 then wrk0:=w2,
; goto regin1.
0067 sub(ic,6) noload ; if ic = 8 then
0070 cjmp(equal,regin1) mover(wrk0,w3); wrk0 := w3, goto regin1.
; else
0071 jmp(npref2) ; goto noprefetch (location 8).
0072 insw01: sub(ic,0) noload ; if ic > 0 then
0073 cjmp(great,regin1) mover(wrk0,w1) holdmy;wrk0 := w1 ,
; hold condition , goto regins.
0074 insw0m: cjmp(notneg,regin1) mover(wrk0,w0); else wrk0 := w0, goto regin1.
0075 jmp(prgex0) mzero(cause) ; else goto program exeption, causec:=.0.
0076 regin1: mover(wrk1,wrk0) signex ; wrk1 := signextend ( 8000 instr:)
; ( address field of 8000 instr:).
0077 add(addrs,wrk1) ; addrs := addrs + wrk1.
0100 mover(wrk2,3) ; init wrk2 to constant 3,
; used in aritmetric instructions to
; speed up calculations).
0101 invs(q,wrk0) ; send 8000 instr: through amd2903's
; r bus, and there by out on the the
; bidirectional db-bus, this will send
; the 8000 instr: out to address the
; vector 8000 instr: prom and the
; map address modifier prom.
0102 jvec invs(q,wrk0) ; jump vector, repeat addressing
; of vector prom and map prom.
; interupt, exeption and escape control section.
; ----------------------------------------------
; subroutine perform limit check with wrk0 register
; -------------------------------------------------
; and return wrk0 register with added base if limit
; is not violated else if wrk0 < cpa then just wrk0,
; last instr subtract 8 from wrk0 with noload.
; ----------------------------------------------
0103 chlicp: add(wrk0,base) ; wrk0 := wrk0 + base,
; ( wrk0 contains address to be
; be investigated)
0104 chlic1: sub(wrk0,uplim) noload ; if wrk0 >= upper limit then
0105 cjmp(greq,prgex2) sub(wrk0,lowlim) noload; goto program exeption, with 2
; wait for hc2901.
0106 crtn(greq) ; if q >= lower limit then return
; where wrk0 = wrk0+base.
0107 sub(addrs,cpa) noload ; if addrs < cpa then
0110 crtn(less) mover(wrk0,addrs)▶16◀▶16◀ ; return and wrk0 := addrs with no
; base.
0111 jmp(prgex2) ; else goto program exeption, with 2
; wait for hc2901.
; subroutine dump dynamic registers.
; ----------------------------------
dudyre:
0112 invr(hc2901,'e01drd) ; call function dynamic register dump in
; hc2901.
0113 dudyr1: cjmp(re2901,dudyr1) clre01 ; wait for hc2901 ready.
0114 invs(hc2901,wrk1) ; sen regdump addrs to hc2901.
0115 dudyr2: cjmp(re2901,dudyr2) clre01 ; wait for hc2901 ready.
0116 dudyen: invs(hc2901,w0) ; send w0 to reg dump.
0117 dudyr3: cjmp(re2901,dudyr3) clre01 ; wait for hc2901 ready.
0120 invs(hc2901,w1) ; send w1 to reg dump.
0121 dudyr4: cjmp(re2901,dudyr4) clre01 ; wait for hc2901 ready.
0122 invs(hc2901,w2) ; send w2 to reg dump.
0123 dudyr5: cjmp(re2901,dudyr5) clre01 ; wait for hc2901 ready.
0124 invs(hc2901,w3) ; send w3 to reg dump.
0125 dudyr6: cjmp(re2901,dudyr6) clre01 ; wait for hc2901 ready.
0126 invs(hc2901,status) ; send status to reg dum.
0127 dudyr7: cjmp(re2901,dudyr7) clre01 ; wait for hc2901 ready.
0130 invs(hc2901,ic) ; sen ic to reg dump.
0131 dudyr8: cjmp(re2901,dudyr8) clre01 ; wait for hc2901 ready.
0132 invs(hc2901,cause) ; send cause to reg dump.
0133 dudyr9: cjmp(re2901,dudyr9) clre01 ; wait for hc2901 ready.
0134 invs(hc2901,addrs) ; send addrs to reg dump.
0135 dudy10: cjmp(re2901,dudy10) clre01 ; wait for hc2901 ready.
0136 rtn add(wrk1,16) ; return from subroutine,
; wrk1 := wrk1 + 16,
; ( wrk1 = reg. dump address).
; subroutine reestablish dynamic registers.
; -----------------------------------------
redyre:
0137 invr(hc2901,'e01drr) ; call function dunamic register reestablish
; in hc2901.
0140 redyaw: cjmp(re2901,redyaw) clre01 ; wait for hc2901 ready to accept address
; of dump block.
0141 invs(hc2901,wrk0) ; send reg dump addrs to hc2901.
redyen: ; entry dum dynamic registers.
0142 redyr1: cjmp(re2901,redyr1) clre01 invs(w0,hc2901); wait for hc2901 ready,
; reestablish w0.
0143 cont clwr01 ; clock ready to hc2901.
0144 redyr2: cjmp(re2901,redyr2) clre01 invs(w1,hc2901); wait for hc2901,
; reestablish w1.
0145 cont clwr01 ; cont clock write ready to hc2901.
0146 redyr3: cjmp(re2901,redyr3) clre01 invs(w2,hc2901); wair for hc2901 ready,
; reestablish w2.
0147 cont clwr01 ; cont clock write ready to hc2901.
0150 redyr4: cjmp(re2901,redyr4) clre01 invs(w3,hc2901); wait for hc2901 ready,
; reestablish w3.
0151 cont clwr01 ; cont clock write ready to hc2901.
0152 redyr5: cjmp(re2901,redyr5) clre01 invs(status,hc2901); wait for hc2901 ready,
; reestablish status.
0153 cont clwr01 ; cont clock write ready to hc2901.
0154 redyr6: cjmp(re2901,redyr6) clre01 invs(ic,hc2901); wait for hc2901 ready,
; reestablish ic.
0155 cont clwr01 ; cont clock write ready to hc2901.
0156 redyr7: cjmp(re2901,redyr7) clre01 invs(cause,hc2901); wait for hc2901 ready,
; reestablish cause.
0157 cont clwr01 ; cont clock write ready to hc2901.
0160 redyr8: cjmp(re2901,redyr8) clre01 invs(addrs,hc2901); wait for hc2901 ready,
; reestablish hc2901.
0161 rtn ; return from subroutine
;
; exeption
; ---------
; program exeption.
; -----------------
; ( se also entry prgex1 prgex2 prgex3).
0162 prgexp/:jmp(expt) mzero(cause) ; goto exeption service, cause := 0.
; integer exeption.
; -----------------
0163 intexp/:mover(cause,2) ; cause := 2.
0164 jmp(expt) ; goto exeption service.
; floating point exeption.
; ------------------------
0165 flpexp/:mover(cause,4) ; cause := 4.
0166 jmp(expt) ; goto exeption service.
; program exeption whwn double load is clocked.
0167 prgex3: cjmp(re2901,prgex2) clre01 ; wait for hc2901 is ready.
0170 cont clwr01 invr(hc2901,8) ; clear write ready to hc2901.
; entry for program exeption
; when read memory word is clocked.
0171 prgex2: cjmp(re2901,prgex2) clre01 ; wait for hc2901 is ready.
0172 cont clwr01 invr(hc2901,8) ; clear write ready to hc2901.
0173 prgex1: cjmp(re2901,prgex1) mzero(cause) clre01; wait for hc201 is ready.
; exeption.
; ---------
prgex0: ; entry when cause is zero.
0174 expt/: invr(hc2901,'e01gmw) ; call get word from memory with
; no limit check in hc2901.
0175 inctwo(ic) ; ic := ic + 2.
0176 add(inf,4) ; inf := inf + 4.
0177 expt1: cjmp(re2901,expt1) clre01 ; wait for hc2901 is ready.
0200 invs(hc2901,inf) ; send address of reg. dump to hc2901.
0201 sub(inf,4) ; inf := inf - 4.
0202 expt2: cjmp(re2901,expt2) clre01 invs(wrk1,hc2901); get reg dump addrs to wrk1.
; wrk1 := register dum address.
0203 cjmp(zero,intser) ; if regdump address = 0 then goto
; interupt service.
; entry for dump registers from escape routine
; after control of register dump address <> 0.
; wrk1 = register dump address <> 0.
extp3:
dmpreg:
0204 add(wrk1,base) ; reg dump addrs := reg dump addrs + base.
0205 sub(wrk1,lowlim) noload ; if reg dump addrs + base <
; lower limit then
0206 cjmp(less,stbe1) ; then goto syetm table error.
0207 add(wrk1,14) ; reg dump addrs := reg dump addrs + 14.
0210 sub(wrk1,uplim) noload ; if reg dump addrs >= upper limit then
0211 cjmp(greq,stbe1) ; goto system table error.
0212 sub(wrk1,14) ; reg dump addrs := reg dump addrs - 14.
0213 jsb(dudyre) ; call sub routine to dump dynamic registers.
0214 mover(w0,ic) ; w0 := old ic.
; w1 is not initialized acording to
; the the rc8000 family refference
; manual.
0215 mover(w2,addrs) ; w2 := addrs.
0216 and(cause,63) ; cause := cause(18..23).
0217 mover(ic,wrk1) ; new ic := reg dump addrs + 16,
; ( reg. dump. address is increased
; with 16 in subroutine dump dynamic
; registers).
0220 jmp(nopfic) mover(w3,cause) ; w3 := cause, goto next 8000 instr:
; with no prefetch.
stbe1: ; system table error from exeption.
0221 mover(cause,6) ; cause := 6.
0222 sub(wrk1,base) ; reg dump addr := reg dump addr - base.
0223 jmp(intser) mover(addrs,wrk1) ; addrs := reg dump addrs ,
; goto interupt service.
; external interupt.
; ------------------
; this address is reached after an 'jvec' micro 8000 instr:
; in the fetch next 8000 instr: section and the interupt is
; set from the hc2901.
0224 extint/:invr(hc2901,'e01aci) ; clock hc2901 in address answer
; and clear interupt.
; the answer is given as an exact interupt
; interupt no.
0225 mzero(base) ; base := 0.
0226 sub(addrs,wrk1) ; reestablish addrs register as before
; fetch instrcution. (i.e. if after am
; then address register is unchanged).
0227 extin1: cjmp(re2901,extin1) clre01 invs(cause,hc2901); wait for hc2901 to be
; to be ready , cause := interupt no * 2.
0230 jmp(intse3) mover(cause,cause) slft; cause := cause * 2, continue
; interupt service entry 3.
intser/: ; common interupt service routine.
; --------------------------------
0231 invr(hc2901,'e01is1) ; call function in hc2901 for starting
; interupt service 1.
0232 intse1: mzero(base) ; base := 0, (disabling memory
; relocation).
0233 intse2: cjmp(re2901,intse2) clre01 ; wait for hc2901 ready.
0234 intse3: invs(hc2901,inf) ; send information register to hc2901.
0235 mover(lowlim,8) ; lower limit := 8.
0236 invr(uplim,base) srgt ; lower limit := max integer ( schould be
; size of memory).
; this diables the limit check.
0237 intse4: cjmp(re2901,intse4) clre01 invs(wrk2,hc2901); wait for hc2901 ready,
; get system table status and interupt
; initialization.
0240 mover(lowlim,8) clwr01 ; lower limit := const(8).
; clear write ready to hc2901.
0241 intse6: cjmp(re2901,intse6) clre01 invs(wrk1,hc2901); wait for hc2901 ready,
; get system table reg dump addrs.
0242 jsb(dudyen) ; call subroutine dump dynamic
; registers, in entry 1 with
; no init clock of hc2901.
0243 mover(w1,wrk1) clwr01 ; sync of hc2901 with a clear of the
; sync bit to hc2901,
; w1 := reg dump address + 16,
; ( reg. dump address is increassed
; by 16 in subroutine dump dynamic
; registers).
0244 ints19: cjmp(re2901,ints19) clre01 invs(ic,hc2901); wait for hc2901 ready,
; get new ic address from system table.
0245 mover(status,wrk2) ; status := system table status initialistion
0246 andinv(status,4095) ; status := system table status and
; intlim initialiation (0..11).
0247 sub(inf,12) ; inf := inf - 12.
0250 or(inf,1) ; inf(23) := 1.
0251 jmp(nopfic) mover(w2,cause) ; w2 := cause, goto fetch next
; HC8000 instr: with no prefetch.
; carry and owerflow control section.
; -----------------------------------
0252 ccowc: cjmp(over,ccowc1) holdmy ; if overflow then goto ccowc1,
; hold control.
0253 cjmp(ncarry,pfneic) ; if not carry then goto nexin.
0254 or(ex,1) ; ex(carry) := 1.
0255 jmp(pfneic) ; ex(carry) := 1, goto pfneic.
0256 ccowc1: or(ex,2) holdmy ; ex(overflow) := 1, hold condition
; control.
0257 cjmp(ncarry,ccowc2) ; ex(overflow) := 1, if not carry
; then goto ccowc2.
0260 or(ex,1) ; ex(carry) := 1.
0261 ccowc2: and(status,16) noload ; if status(integer mask) = 0 then
0262 cjmp(zero,pfneic) ; goto pfneic.
0263 jmp(intexp) ; goto integer exeption.
; subroutine get operand
; -----------------------
; call: address of operand in reg. 'addrs'.
; return: operand in reg. 'wrk0'.
; destroyed: none.
; condition select is expected to b 'csmy'
0264 getop: sub(addrs,8) noload ;
0265 cjmp(less,regget) mover(wrk0,addrs); wrk0 := addrs.
0266 getop1: invr(hc2901,'e01gmw) ; call function in hc2901 get operand
; get opreand without limit control.
0267 jsb(chlic1) add(wrk0,base) ; wrk0:= wrk0 + base , call subroutine
; to perform limit check and cpa
; limit check.
0270 getop2: andinv(wrk0,1) ; remove possible last bit in address.
0271 getop4: cjmp(re2901,getop4) clre01 ; wait for hc2901 to accept address.
0272 invs(hc2901,wrk0) ;send daddress to hc2901, and clock
; write bit.
0273 getop3: cjmp(re2901,getop3) invs(wrk0,hc2901); wait for hc2901 to sned data,
; inver data into wrk0 from hc2901
; buffer register.
0274 rtn mover(wrk0,wrk0) shinz nothm csmy; return from subroutine,
; prepere for negative or zero test
; data.
; subroutine load from internal reg.
; ----------------------------------
0275 regget: cjmp(neg,prgexp) mover(wrk0,wrk0) srgt; if addres if negative then goto
; program exeption, shift wrk0 rigth 1,
; so wrk0 points to exact register no.
0276 regge1: add(wrk0,'regge2) ; microsekvens counter := address
0277 ldctre(wrk0) ; shift -1 + mic. instr addres
; regge1.
0300 cjmrd(neg,prgexp) ; jump in micro. program to
; to address indexd by regge1 +
; addrs // 2.
0301 regge2: rtn mover(wrk0,w0) ; wrk0 := w0.
0302 rtn mover(wrk0,w1) ; wrk0 := w1.
0303 rtn mover(wrk0,w2) ; wrk0 := w2.
0304 rtn mover(wrk0,w3) ; wrk0 := w3.
; subroutine get double word from memory with
; write protection check.
; -------------------------------------------
0305 getdo1: sub(addrs,8) noload ; if addrs < 8 then
0306 cjmp(less,regget) mover(wrk0,addrs); wrk0 := address, goto regget.
0307 getdo3: invr(hc2901,'e01gdw) ; send entry to hc2901.
0310 add(wrk0,base) ; wrk0 := addrs + base.
0311 sub(wrk0,uplim) noload ; if wrk0 >= upper limit then
0312 cjmp(greq,prgex3) sub(wrk0,lowlim) noload; goto program exeption
; with 3 wait for hc2901.
0313 cjmp(greq,getop2) sub(addrs,cpa) noload; if wrk0 >= lower limit
; then goto getop2.
0314 cjmp(less,getop2) mover(wrk0,addrs); if addrs < cpa then goto getop2.
0315 jmp(prgex3) ; else goto program exeption
; with 3 wait for hc2901.
; second entry in get double word from memory
; with protection check.
; -------------------------------------------
0316 getdo2: mover(wrk1,addrs) ; wrk1 := addrs.
0317 andinv(wrk1,1) ; wrk1.lsb := 0.
; (remove possible uneven address.)
0320 sub(wrk1,2) ; wrk1 := wrk1 - 2.
0321 cjmp(neg,getdo4) mover(wrk0,w3) ; if new address < 0 then
; data word in register w3)
; goto getdo4,
0322 sub(wrk1,6) noload ; if address < 6 then
0323 cjmp(less,regge1) mover(wrk0,wrk1) srgt holdmy; wrk0 := address shift -1,
; hold condition, goto regge1.
0324 cjmp(great,getop3) clwr01 ; if address > 6 then
; clock write hc2901 and goto
; wait for last operand in
; getop3.
; else
0325 jmp(regge1) ; if address = 6 then
; (previus was memory(8))
; goto regget ( clock of
; write ready was done in
; just previus micro insteuction.
0326 getdo4: rtn mover(addrs,6) ; addrs := 6 , and return from
; subroutine.
; subroutine putoperand.
; ----------------------
; call: address in reg. 'addrs'
; operand in reg. 'q'.
; destroyed: wrk0.
0327 putop: sub(addrs,8) noload ; if addrs < 8 then
0330 cjmp(less,regput) mover(wrk0,addrs); then goto put register.
0331 add(wrk0,base) ; wrk0 := addr+ base.
0332 sub(wrk0,uplim) noload ; if wrk0 >= uppper limit then
0333 cjmp(greq,prgexp) sub(wrk0,lowlim) noload; goto program exeption
; else if wrk0 < lower limit then
0334 cjmp(less,prgexp) ; then goto program exeption.
0335 invr(hc2901,'e01pmw) ; call function put operand
; protected.
0336 andinv(wrk0,1) ; remove possible uneven address
; bit in address.
0337 putop1: cjmp(re2901,putop1) clre01 ;
0340 invs(hc2901,wrk0) ; send fysical address to hc2901.
0341 putop2: cjmp(re2901,putop2) clre01 ;
0342 invs(hc2901,q) ; send data word to hc2901.
0343 putop3: cjmp(re2901,putop3) clre01 ; wait for hc2901 ready.
0344 inctwo(ic) ; ic := ic + 2 ( next 8000 instr:).
0345 sub(ic,wrk0) noload ; if next ic <> from just used physical
0346 cjmp(nzero,pficin) ; then goto prefetch next instr else
0347 jmp(nopfic) ; goto get 8000 instr: with no prefetch.
0350 regput: cjmp(neg,intexp) mover(wrk0,wrk0) srgt; if the effective address is
; negative then goto intexp,
; shift wrk1 1 rigth so wrk1
; contains absolute register no.
0351 add(wrk0,'regpu0) ;
0352 ldctre(wrk0)
0353 cjmrd(neg,intexp) ;
0354 regpu0: jmp(pfneic) moves(w0, q)
0355 regpu1: jmp(pfneic) moves(w1,q)
0356 regpu2: jmp(pfneic) moves(w2,q)
0357 regpu3: jmp(pfneic) moves(w3,q)
;*page: XXX
; address handling
; ----------------
; HC8000 instr: next address, modify: 'am', numeric code 9.
; ------------------------------------------------------
0360 am/'9: sub(ic,8) noload ; if ic >= 10 (i.e ic + 2) then
0361 cjmp(greq,ftcam) inctwo(ic) ; goto fetch 8000 instr: after
; address modify (entry in
; prefetch 8000 instr:),
; ic := ic + 2.
0362 jmp(regins) ; else goto regins ( 8000 instr: in
; register or location 8).
; HC8000 instr: address, load: 'al', numeric code 11.
; --------------------------------------------------
0363 al/'11: jmp(pfneic) mover(wreg,addrs) ; w_reg(index) := addrs,
; goto pfneic
; HC8000 instr: address complemented, load: 'ac', numeric code 33.
; --------------------------------------------------------------
0364 ac/'33: andinv(ex,3) ; ex(carry) := ex(overflow) := 0.
0365 jmp(ccowc) invr1(wreg,addrs) ; w_reg(index) := not(addrs)+1,
; goto ccowc.
;*page: XXX
; register transfer.
; ------------------
; HC8000 instr: half register, load: 'hl', numreic code 3.
; -------------------------------------------------------
0366 hl/'3: jsb(getop) ; wrk0 := core(addrs),
0367 and(addrs,1) noload ; if addrs(23) = 0 ( addrs even) then
0370 cjmp(zero,hl1) ; goto hl1,
0371 mover(wrk0,wrk0) hmrl ; wrk0(0:11) := wrk0(12:23)
0372 hl1: mover(wreg,wrk0) hmlr ; w_reg(index,12:23) := wrk0(0:11),
0373 cont nothm csmy ; reset half word move logic
0374 jmp(pficin) inctwo(ic) ; goto pfneic, ic := ic +2.
; HC8000 instr: half register, store: 'hs', numeric code 26.
; --------------------------------------------------------
0375 hs/'26: jsb(getop) moves(q,wreg) ; wrk0( := core(addrs), q := w_reg(index)
0376 hsnoen: and(addrs,1) noload ; normalisze single and double entry:
; if addrs(23) = 0 ( addrs even) then
0377 cjmp(zero,hs1) moves(wrk1,q) ; goto hs1, wrk1 := q,
0400 mover(wrk1,wrk1) hmrl ; wrk1(12:23) := wrk1(0:11),
0401 mover(wrk0,wrk1) hmlr ; wrk0(12:23) := wrk1(0:11).
0402 mover(q,wrk0) nothm csmy shinz ; q:=wrk0, reset half word move
; logic.
0403 jmp(putop) ; goto putop.
0404 hs1: mover(wrk0,wrk1) hmrl ; wrk0(0:11):= wrk1(12:23)
0405 mover(q,wrk0) nothm csmy shinz ; q:=wrk0, reset half word
; move logic.
0406 jmp(putop) ; goto putop.
; HC8000 instr: register, load: 'rl', numeric code 20.
; ---------------------------------------------------
0407 rl/'20: jsb(getop) ; wrk0 := core(addrs)
0410 jmp(pfneic) mover(wreg,wrk0) ; w_reg(index) := wrk0, goto pfneic
; HC8000 instr: register, store: 'rs', numeric code 23.
; ---------------------------------------------------
0411 rs/'23: jmp(putop) moves(q,wreg) ;q := w_reg(index), goto putop.
; HC8000 instr: register and memory word, exchange: 'rx', numeric code 25.
; ----------------------------------------------------------------------
0412 rx/'25: jsb(getop) moves(q,wreg) ; q := w_reg(index) call subroutine get operand from memory
0413 jmp(putop) mover(wreg,wrk0) ; w_reg(index) := wrk0,
; goto putop, (addrs(core) := q)
; HC8000 instr: double register, load: 'dl', numeric code 54.
; ---------------------------------------------------------
0414 dl/'54: jsb(getdo1) ;
0415 jsb(getdo2) mover(wreg,wrk0) ;
0416 jmp(pfneic) mover(wpre,wrk0) ;move word previus to address
; to register previus to selected
; register, goto get nest prefetched
; instruction.
; HC8000 instr: double register, store: 'ds', numeric code 55.
; -----------------------------------------------------------
0417 ds/'55: sub(addrs,8) noload ; if addrs >= 8 then
0420 cjmp(greq,ds4) mover(wrk1,addrs); goto ds4, wrk1 := addrs.
0421 cjmp(neg,prgexp) ; if addrs is negative then goto
; program exeption.
0422 andinv(wrk1,1) ; remove possible last bit in address.
0423 add(wrk1,'ds7) ; add mic. address
; of first load sentence to no of reg.
0424 ldctre(wrk1) ; load mic sekvens counter with
; counter with addrs + addres of
; first instr. of load reg.
; instr.
0425 cjmrd(neg,intexp) moves(q,wreg) ; jump indexed by counter to
; to micro. instr based by ds7,
; q := wreg(index).
0426 ds7: moves(w0,q) ; w0 := q.
0427 jmp(regpu3) moves(q,wpre) ; q := wreg(index-1) , goto reg put 3.
0430 moves(w1,q) ; w1 := q.
0431 jmp(regpu0) moves(q,wpre) ; q := wreg(index-1) , goto reg put w0.
0432 moves(w2,q) ; w2 := q.
0433 jmp(regpu1) moves(q,wpre) ; q := wreg(index-1) , goto reg put w1.
0434 moves(w3,q) ; w3 := q.
0435 jmp(regpu2) moves(q,wpre) ; q := wreg(index-1) , goto reg put w2.
0436 ds4: andinv(wrk1,1) ; remove possible last bit in address.
0437 add(wrk1,base) ; wrk1 := wrk1 ( addrs) + base.
0440 sub(wrk1,uplim) noload ; if wrk1 => uplim then
0441 cjmp(greq,prgexp) mover(wrk2,wrk1); goto program exeption.
0442 sub(wrk2,2) ; wrk2 := wrk2 - 2.
0443 sub(wrk2,lowlim) noload ; if wrk2 < lowlimt then
0444 cjmp(less,prgexp) ; goto program exeption.
0445 invr(hc2901,'e01pdw) ; clock the hc2901 with the
; entry address put double word
; unprotected.
0446 ds1: cjmp(re2901,ds1) clre01 ; wait for the hc2901 to be ready
; to recieve first storage address.
0447 invs(hc2901,wrk1) ; hc2901 := wrk1.
0450 moves(q,wreg) ; move wreg(index) to q register.
0451 ds2: cjmp(re2901,ds2) clre01 ; wait for the hc2901 to be ready
; to recieve first data word.
0452 invs(hc2901,q) ; hc2901 := q.
0453 moves(q,wpre) ; move wreg(index-1) to q register.
0454 ds3: cjmp(re2901,ds3) clre01 ; wait for the hc2901 to be
; ready for recieving the next
; data word.
0455 invs(hc2901,q) ; hc2901 := q.
0456 inctwo(ic) ; ic := ic + 2.
0457 ds6: cjmp(re2901,ds6) clre01 ; wait for hc2901 ready.
0460 sub(wrk1,ic) noload ; if wrk1 = next ic then goto
0461 cjmp(equal,nopfic) sub(wrk2,ic) noload; goto nopfic
; if addrs = next ic then
0462 cjmp(equal,nopfic) ; goto nopfic.
0463 jmp(pficin) ; else goto nexti2.
; HC8000 instr: exeption register, load: 'xl', numeric code 16.
; -----------------------------------------------------------
0464 xl/'16: jsb(getop) ; call getop,
0465 and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) then
0466 cjmp(nzero,xl1) ; goto xl1.
0467 mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
0470 xl1: and(wrk0,7) csmy nothm csmy shinz; wrk0:= wrk0(21:23) reset move
; half word logic.
0471 jmp(pfneic) or(ex,wrk0) ; ex := ex or wrk0,
; goto pfneic.
; HC8000 instr: exeption register, store: 'xs', numeric code 27.
; ------------------------------------------------------------
0472 xs/'27: and(q,ex,7) ; q:= ex, (i.e. status(21:23)).
0473 jsb(getop) ; call getop.
0474 and(addrs,1) noload ; if addrs(23) = 1 ( addrs odd ) then
0475 cjmp(zero,xs1) moves(wrk1,q) ; goto xs1, wrk1 := q.
0476 mover(wrk1,wrk1) hmrl ; wrk1(0:11) := wrk1(12:23).
0477 mover(wrk0,wrk1) hmlr ; wrk0(12:23) := wrk(0:11).
0500 jmp(putop) mover(q,wrk0) ; q:=wrk0, goto putop.
0501 xs1: mover(wrk0,wrk1) hmrl ; wrk0(0:11) := wrk1(wrk1(12:23)
0502 cont csmy nothm shinz ; clear half word move logic.
0503 jmp(putop) mover(q,wrk0) ; q:=wrk0, reset half word move
; logic, goto putop.
; integer halfword arithmetic
; ---------------------------
; HC8000 instr: integer byte, load (zero extension): 'bz', numeric code 19.
; ------------------------------------------------------------------------
0504 bz/'19: jsb(getop) ; call getop.
0505 and(addrs,1) noload ; if addrs(23) = 0 (addrs even) then
0506 cjmp(zero,bz1)mzero(wreg) ; goto bz1, reset selected working
; register.
0507 mover(wrk0,wrk0) hmrl ; wrk0(0:11) := wrk0(12:23).
0510 bz1: mover(wreg,wrk0) hmlr ; w_regg(index,12:23):=wrk0(0:11).
0511 cont csmy nothm csmy shinz ; reset half word move control
0512 jmp(pficin) inctwo(ic) ; goto pfneic, ic := ic + 2.
; HC8000 instr: integer byte, load (sign extension): 'bl', numeric code 2.
; ----------------------------------------------------------------------
0513 bl/'2: jsb(getop) ; call getop.
0514 and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) then
0515 cjmp(nzero,bl1) inctwo(ic) ; goto bl1, ic := ic + 2.
0516 mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
0517 cont csmy nothm csmy shinz ; reset half word move control
0520 bl1: jmp(pficin) mover(wreg,wrk0) signex; w_reg(index)
; := signextend(wrk0(12:23)),
; goto pfneic.
; HC8000 instr: integer byte, add: 'ba', numeric code 18.
; -----------------------------------------------------
ba/'18: ; ex(carry):=ex(overflow):=0.
0521 jsb(getop) andinv(ex,wrk2) ; call getop
0522 and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) the
0523 cjmp(nzero,ba1) ; goto ba1.
0524 mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
0525 cont csmy nothm csmy shinz ; reset half word move control
0526 ba1: mover(wrk0,wrk0) signex ; signextend(wrk0(12:23)).
0527 jmp(ccowc) add(wreg,wrk0) ; w_reg(index) := w_reg(index)
; + wrk0, goto ccowc.
; HC8000 instr: integer byte subtract: 'bs', numeric code 17.
; ---------------------------------------------------------
bs/'17: ; ex(carry):=ex(overflow):=0.
0530 jsb(getop) andinv(ex,wrk2) ; call getop.
0531 and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) then
0532 cjmp(nzero,bs1) ; goto bs1.
0533 mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
0534 cont csmy nothm csmy shinz ; reset half word mov control
0535 bs1: mover(wrk0,wrk0) signex ; signextend(wrk0(12:23)).
0536 jmp(ccowc) sub(wreg,wrk0) ; w_reg(index):=w_reg(index)
; - wrk0, goto ccowc.
; integer word arithmetic
; ------------------------
; HC8000 instr: integer word, add: 'wa', numeric code 7.
; ----------------------------------------------------
wa/'7: ; ex(carry):=ex(overflow):=0.
0537 jsb(getop) andinv(ex,wrk2) ; call subroutine get operand from memory.
0540 jmp(ccowc) add(wreg,wrk0) ; w_reg(index) := w_reg(index) +
; wrk0, goto ccowc.
; HC8000 instr: integer word, subtract: 'ws', numeric code 8.
; ---------------------------------------------------------
ws/'8: ; ex(carry):=ex(overflow):=0.
0541 jsb(getop) andinv(ex,wrk2) ; call subroutine get operand from memory.
0542 jmp(ccowc) sub(wreg,wrk0) ; w_reg(index) := w_reg(index) -
; wrk0, goto ccowc.
; HC8000 instr: integer word, multiply: 'wm', numeric code 10.
; ----------------------------------------------------------
0543 wm/'10: jsb(getop) moves(q,wreg) ; call getop, q := wreg(index).
0544 lcpu(22) mzero(wrk2) ; push next micro instr to stack
; mic. sekv. counter := 23,
; wrk2 := 0.
0545 rep mult2c(wrk2,wrk0) dshinz ;
0546 mult2l(wrk2,wrk0) ;
0547 mover(wpre,wrk2) nothm csmy shinz; wreg(index) := wrk2.
0550 jmp(pfneic) moves(wreg,q) ; goto pfneic, wreg(index-1) := q.
; ========
; division
; ========
; division moved to en program until final version.
; integer double word arithmetic.
; -------------------------------
; removed until final
;*onlyin: final
; HC8000 instr: integer double word, add: 'aa', numeric code 56.
; ------------------------------------------------------------
aa/'56: ; ex(carry):=ex(overflow):=0.
0551 jsb(getdo1) andinv(ex,wrk2) ; call subroutine get operand from memory.
0552 add(wreg,wrk0) ; w_reg(index) := w_reg(index) +
; wrk0.
0553 cjmp(carry,aa1) ; if carry then goto aa1.
0554 jsb(getdo2) ; call(getd2o).
0555 jmp(ccowc) add(wpre,wrk0) ; w_reg(index-1):=w_reg(index-1)
; + wrk0, goto ccowc.
0556 aa1: jsb(getdo2) ; call(getdo2).
0557 jmp(ccowc) add1(wpre,wrk0) ; w_reg(index-1):=w_reg(index-1)
; + wrk0 + 1, goto ccowc.
; HC8000 instr: integer double word, subtract: 'ss', numeric code 57.
; -----------------------------------------------------------------
ss/'57: ; ex(carry):=ex(overflow):=.
0560 jsb(getdo1) andinv(ex,wrk2) ; call(getdo1).
0561 sub(wreg,wrk0) ; w_reg(index) := w_reg(index) -
; wrk0.
0562 cjmp(carry,ss1) ; if carry then goto ss1.
0563 jsb(getdo2) ; call(getdo2).
0564 jmp(ccowc) sub(wpre,wrk0) ; w_reg(index-1):=w_reg(index-1)
; - wrk0, goto ccowc.
0565 ss1: jsb(getdo2) ; call(getdo2).
0566 jmp(ccowc) sub1(wpre,wrk0) ; w_reg(index-1):=w_reg(index-1)
; - wrk0 + 1, goto ccowc.
;*until: final
; logical operation.
; ------------------
; HC8000 instr: logical and: 'la', numeric code 4.
; ----------------------------------------------
0567 la/'4: jsb(getop) ; call subroutine get operand from memory.
0570 jmp(pfneic) and(wreg,wrk0) ; w_reg(index):=w_reg(index)
; and wrk0, goto pfneic.
; HC8000 instr: logical or: 'lo', numeric code 5.
; ---------------------------------------------
0571 lo/'5: jsb(getop) ; call subroutine get operand from memory.
0572 jmp(pfneic) or(wreg,wrk0) ; w_reg(index) := w_reg(index) or
; wrk0, goto pfneic.
; HC8000 instr: logical exclusive or: 'lx', numeric code 6.
; -------------------------------------------------------
0573 lx/'6: jsb(getop) ; call subroutine get operand from memory.
0574 jmp(pfneic) exor(wreg,wrk0) ; w_reg(index) := w_reg(index) exor
; wrk0, goto pfneic.
;*page: XXX
; shift operations.
; -----------------
;
;*skip: ashift .
; HC8000 instr: aritmetically shift single: 'as', numeric code 36.
; --------------------------------------------------------------
0575 as/'36: andinv(ex,3) ; ex(carry):=ex(overflow):=0.
0576 sub(addrs,0) noload ; if addrs > 0 then
0577 cjmp(great,as1) moves(q,wreg) holdmy; goto as2, q:=w_reg(index), hold condition.
0600 cjmp(less,as2) moves(wrk1,q) ; if addrs < 0 then goto as2, wrk1:=q.
0601 jmp(pfneic) ; if addrs = 0 then goto pfneic..
0602 as1: sub(addrs,24) noload ; if addrs < 24 then
0603 cjmp(less,as4) moves(wrk1,q) ; goto as4, wrk1:=q.
0604 mover(addrs,24) ; addrs := 24.
0605 as4: sub(addrs,1) ; addrs := addrs - 1.
0606 pushre(addrs) ; counter := addrs,
0607 twb(over,as5) mover(wrk1,wrk1) slft; wrk1:= leftshift_1(wrk1),wrk1(0):=0.
0610 as6: rpct(as6) mover(wrk1,wrk1) slft ; repeat this while counter <> 0
; (wrk := left_shift_1(wrk1) ,wrk(0):=0,
; decrease (counter) ).
0611 mover(wreg,wrk1) ; w_reg(index):=wrk1.
0612 or(ex,2) ; ex(overflow) := 1.
0613 and(status,16) noload ; if integer mask = 1 then
0614 cjmp(zero,pfneic) ; goto pfneic.
0615 jmp(intexp) ; goto integer exeption.
0616 as2: cjmp(neg,as3) invr(wrk2,addrs) ; if q (i.e wreg) < 0 then
; goto as3, wrk2 := abs(addrs).
0617 sub(wrk2,23) noload ; if wrk2 > 23 then
0620 cjmp(great,pfneic) mzero(wreg) ; goto pfneic, w_reg(index) :=0.
0621 sub(wrk1,1) ; wrk2 := wrk2 - 1.
0622 pushre(wrk2) ; counter := wrk2.
; push next mic.instr addres.
0623 rep mover(wrk1,wrk1) slft shinz ;
0624 jmp(pfneic) mover(wreg,wrk1) ; w_reg(index) := wrk1, goto nein
0625 as3: sub(addrs,23) noload ; if addrs > 23 then
0626 cjmp(great,pfneic) ;
0627 sub(addrs,1) ; addrs := addrs - 1.
0630 pushre(addrs) ; counter := addrs.
; push next mic. instr. address.
0631 rep mover(wrk1,wrk1) shin1 srgt ;
0632 as5: jmp(pfneic) mover(wreg,wrk1) ;
; HC8000 instr: arithmetically shift double: 'ad', numeric code 37.
; ---------------------------------------------------------------
0633 ad/'37: andinv(ex,3) ; ex(carry) := ex(overflow):=0.
0634 sub(addrs,0) noload ; if addrs > 0 then
0635 cjmp(great,ad1) holdmy moves(q,wpre); goto ad2, q:= wreg(index-1).
0636 cjmp(less,ad2) moves(wrk1,q) ; else if addrs < 0 then goto ad2,
; wrk1 := q.
0637 jmp(pficin) inctwo(ic) ; goto pficin, ic := ic + 2.
0640 ad1: sub(addrs,48) noload
0641 cjmp(less,ad4) moves(wrk1,q) ; goto ad4, wrk1 := q.
0642 mover(addrs,48) ; addrs := 48.
0643 ad4: moves(q,wreg) dshinz ; q := wreg(index).
0644 sub(addrs,1) ; addrs := addrs - 1.
0645 pushre(addrs) ; micro sekvens counter := addrs.
; push next micro instr. addrs.
; to micro sekvenser stack.
0646 twb(over,ad3) mover(wrk1,wrk1) lftaql; repeat
; double shift wrk1 and q
; with zero input,
; mic. sekvens counter :=
; mic. sekvens counter -1.
; if mi. sekvens counter = 0 then
; goto ad5.
; until overflow.
0647 push ; if owerflow then
0650 rep mover(wrk1,wrk1) lftaql ; repeat double shift wrk1 and q
; with zero input,
; mic. secvens counter:=
; mic. sekvens counter - 1.
; until mic. sekvens counter = 0.
0651 mover(wreg,wrk1) ; wreg(index)
0652 mover(wpre,wrk1) ; wreg(index -1) := wrk1.
0653 moves(wreg,q) ; wreg(index) := q.
0654 or(ex,2) ; exeption(owerflow) := 1.
0655 and(status,16) noload ; if integer mask = 1 then
0656 cjmp(zero,pfneic) ; goto pfneic.
0657 jmp(intexp) ; goto intger exeption.
0660 ad3: moves(wreg,q) ; wreg(index) :=q.
0661 mover(wpre,wrk1) ; wreg(index-1) := wrk1.
0662 jmp(pfneic) ; goto pfneic.
0663 ad2: cjmp(neg,ad5) invr(wrk2,addrs) ; if q < 0 (i.e. wreg(index-1)) then
; goto ad5, wrk2 := abs(addrs).
0664 sub(wrk2,47) noload ; if wrk2 (i.e. abs(addrs)) > 47 then
0665 cjmp(great,ad6) mzero(wpre) ; goto ad6, wreg(index-1) := 0.
0666 moves(q,wreg) dshinz ; q := wreg(index)
0667 ad7: sub(wrk2,1) ; wrk2 := wrk2 - 1.
0670 pushre(wrk2) ; mic. sekvens counter := wrk2.
; push next mic. instr. address to
; to sekvens stack, set shift
; shift to double shift in zero.
0671 rep mover(wrk1,wrk1) rgtaql; repeat
; shift wrk1 and q rigth double
; with zero input from rigth.
; counter := counter - 1.
; until counter = 0.
0672 mover(wpre,wrk1) nothm csmy; wreg(index - 1) := wrk1,
;
0673 jmp(pfneic) moves(wreg,q) ; wreg(index) := q, goto pfneic.
0674 ad5: sub(wrk2,47) noload ; if q < 47 then
0675 cjmp(great,ad8) ; goto ad8.
0676 moves(q,wreg) dshin1 ; q := wreg, set shift logic
; to doubble shift with 1 input.
0677 jmp(ad7)
0700 ad6: jmp(pfneic) mzero(wreg) ; goto pfneic, wreg(index) := 0.
0701 ad8: invr(wpre,0) ;
0702 invr(wreg,0) ;
0703 jmp(pfneic)
;*until: ashift .
; HC8000 instr: logically shift single: 'ls', numeric code 38.
; ----------------------------------------------------------
0704 ls/'38: sub(addrs,0) noload ; if addrs > 0 then
0705 cjmp(great,ls1) moves(q,wreg) holdmy; goto ls1, q:=w_reg(index), hold
; condition bits.
0706 cjmp(less,ls2) moves(wrk1,q) ; if addrs < 0 then goto ls2, wrk1:=q.
0707 jmp(pficin) inctwo(ic) ; <* if addrs = 0 *> then goto
; goto pficin, ic := ic + 2.
0710 ls1: sub(addrs,23) noload ; if addrs > 23 then
0711 cjmp(great,pfneic) mzero(wreg) ; goto pfneic, w_reg(index):=0.
0712 sub(addrs,1) ; addrs := addrs - 1.
0713 pushre(addrs) ; counter := 0.
; push next mic. instr.
0714 rep mover(wrk1,wrk1) lftqil ; q_reg := q_reg shift left 1
; the opration with the
; wrk1 reg is dummy.
0715 jmp(pfneic) moves(wreg,q) ; w_reg(index):=q, goto pfneic.
0716 ls2: invr1(wrk2,addrs) ; wrk2:=abs(addrs)
0717 sub(wrk2,23) noload ; if addrs > 23 then
0720 cjmp(great,pfneic) mzero(wreg) ; goto pfneic, w_reg(index):=0.
0721 sub(wrk2,1) ; wrk2 := wrk2 - 1.
0722 pushre(wrk2) ; counter := wrk2.
; push next mic. instr. address.
0723 rep mover(wrk1,wrk1) srgt shinz ; shift rigth zero input
0724 jmp(pfneic) mover(wreg,wrk1) ; w_reg(index):= wrk1, goto prefn.
; HC8000 instr: logically shift double: 'ld', numeric code 39.
; ----------------------------------------------------------
;*onlyin: final
0725 ld/'39: sub(addrs,0) noload ; if addrs > 0 then
0726 cjmp(great,ld1) holdmy moves(q,wpre); goto ls1, hold condition bits,
; q := wreg(index - 1).
0727 cjmp(less,ld2) moves(wrk1,q) ; if addrs < 0 then goto ld2,
; wrk1 := q.
0730 jmp(pficin) inctwo(ic) ; ic := ic + 2, goto pficin.
0731 ld1: sub(addrs,47) noload ; if addrs > 47 then
0732 cjmp(great,ld3) mzero(wpre) ; goto ld3, wreg(index-1) := 0.
0733 moves(wrk1,q) ; wrk1 := q.
0734 moves(q,wreg) ; q := wreg(index).
0735 sub(addrs,1) ; addrs := addrs - 1.
0736 pushre(addrs) ; micro sekvenser counter := addrs.
; pusch next micro. instr addrs.
; to stack,
0737 rep mover(wrk1,wrk1) lftaql dshinz; shift wrk1 and q left with conection
; until counter = 0.
0740 mover(wpre,wrk1) nothm csmy shinz; wreg(index-1) := wrk1.
0741 jmp(pfneic) moves(wreg,q) ; w(index) := q, goto pficin.
0742 ld2: invr1(addrs,addrs) ; addrs := - addrs.
0743 sub(addrs,47) noload ; if addrs > 47 then
0744 cjmp(great,ld3) mzero(wpre) ; goto ld3, wreg(index-1) :=0.
0745 moves(q,wreg)
0746 sub(addrs,1) ; addrs := addrs -1 .
0747 pushre(addrs) ; micro sekvenser counter := 0.
; push address of the next
; micro instr into the stack,
0750 rep mover(wrk1,wrk1) rgtaql dshinz; repeat
; counter := counter -1,
; double shift wrk1 and q
; rigth with zero input,
; until counter = 0.
0751 mover(wpre,wrk1) nothm csmy shinz; wreg(index - 1) := wrk1.
0752 jmp(pfneic) moves(wreg,q) ; wreg(index) := q, goto pficin.
0753 ld3: jmp(pfneic) mzero(wreg) ; wreg(index) := 0, goto pfneic.
;*until: final
;*skip: norm
; HC8000 instr: normalize single: 'ns', numeric code 34.
; ----------------------------------------------------
0754 ns/'34: moves(q,wreg) ; q := wreg(index).
0755 cjmp(zero,ns2) mzero(wrk1) ; if wreg(index) = 0 then
; goto ns2, wrk1 := 0.
0756 ns1: cjmp(nover,ns1) slnorm(wrk1) ;
0757 moves(wreg,q) ; wreg(index) := q.
0760 jsb(getop) mover(q,wrk1) ; q := wrk1, call getop.
0761 jmp(hsnoen) ; goto hsnoen. (i.e. normalize
; entry in instr. half word
; store ).
0762 ns2: mover(q,-2048) ; q := -2048
0763 jsb(getop) ;
0764 jmp(hsnoen) ;
; HC8000 instr: normalize double: 'nd', numeric code 35.
; ------------------------------------------------------
0765 nd/'35: moves(q,wpre) dshinz ; q := wreg(index-1), set shift control
; to shift double with zero input.
0766 moves(wrk1,q) ; wrk1 := q.
0767 cjmp(zero,nd2) moves(q,wreg) ; if wrk1 (i.e. wreg(index-1)) = 0 then
; goto nd2, q := wreg(index).
0770 mzero(wrk2) ; wrk2 := 0.
0771 nd1: dlnorm(wrk1) ; double normalize wrk1 and q.
0772 cjmp(ncarry,nd1) incone(wrk2) ; if not carry then goto nd1,
; wrk2 := wrk2 + 1.
0773 moves(wpre,wrk1) ; wreg(index-1) := wrk1.
0774 jsb(getop) moves(wreg,q) ; wreg(index) := q, call getop.
0775 jmp(hsnoen) mover(q,wrk2) ; goto hsnoen ( i.e. entry inhalf
; word store) , q := wrk2.
0776 nd2: cjmp(nzero,nd1) mzero(wrk2) ; if q <(i.e. wreg(index)) <> 0 then
; goto nd1, wrk2 := 0.
0777 jsb(getop) ; call getop.
1000 mover(q,8.4000) ; q := -2048.
1001 jmp(hsnoen) ; goto hsnoen.
;*until: norm
;*page: XXX
; sequencing .
; -----------
; HC8000 instr: jump and select enable level: 'je', numeric code 15.
;-----------------------------------------------------------------
je/'15:
1002 invr(hc2901,'e01sel) ; closk hc2901 in function set enable level.
1003 andinv(status,'disbit) ; clear disable bit in status register.
1004 jmp(jd2) ; continue in jump disable 2.
; HC8000 instr: jump and select diable level: 'jd', numeric code 14.
;------------------------------------------------------------------
1005 jd/'14: add(addrs,'montop) noload ; if addrs >= -montop then
1006 cjmp(notneg,jd1) ; then goto jd1.
1007 mover(wrk0,-2048) signex ; wrk0 := -2048.
1010 sub(addrs,wrk0) noload ; if addrs < -2048 then
1011 cjmp(less,jd1) ; then goto jd1.
1012 mover(cause,addrs) ; cause := addrs.
1013 add(cause,2048) ; cause := cause + 2048.
1014 sub(inf,1) ; inf := inf -1.
1015 jmp(intser) inctwo(ic) ; ic := ic + 2, goto service interupt.
1016 jd1: invr(hc2901,'e01sdl) ; closk hc2901 in set diable level.
1017 or(status,'disbit) ; set disable bit in status register.
1020 jd2: cjmp(re2901,jd2) clre01 ; wait until hc2901 ready.
; HC8000 instr: jump with register link: 'jl', numeric code 13.
; -----------------------------------------------------------
1021 jl/'13: mover(wrk1,w0) ; save w_reg(0) in wrk1.
1022 mover(wreg,ic) ; move old ic to wreg(index).
1023 inctwo(wreg) ; w_reg(index) := wreg(index) + 2.
1024 mover(ic,addrs) ; get new ic form address.
1025 jmp(nopfic) mover(w0,wrk1) ; goto nopfne, w0 := originaaly w0.
; HC8000 instr: skip if register high: 'sh', numeric code 40.
;---------------------------------------------------------
1026 sh/'40: sub(wreg,addrs) noload ; if w_reg(index) <= addrs then
1027 cjmp(lseq,pficin) inctwo(ic) ; ic := ic + 2,goto pfnicin
1030 jmp(sknins) inctwo(ic) ; ic := ic + 2, goto sknins.
; HC8000 instr: skip if register low: 'sl', numeric code 41.
;----------------------------------------------------------
1031 sl/'41: sub(wreg,addrs) noload ; if w_reg(index) >= addrs then
1032 sl1: cjmp(greq,pficin) inctwo(ic) ; entry skip limit violation,
; ic := ic + 2, goto pficin.
1033 jmp(sknins) inctwo(ic) ; ic := ic + 2, goto sknins.
; HC8000 instr: skip if register equal: 'se', numeric code 42.
;----------------------------------------------------------
1034 se/'42: sub(wreg,addrs) noload ; if w_reg(index) <> addrs then
1035 se1: cjmp(nequal,pficin) inctwo(ic) ; ( entry from skip one),
; ic := ic + 2, goto pficin.
1036 jmp(sknins) inctwo(ic) ; ic := ic + 2, goto sknins.
; HC8000 instr: skip if register not equal: 'sn', numeric code 43.
;----------------------------------------------------------------
1037 sn/'43: sub(wreg,addrs) noload ; if w_reg(index) = addrs then
1040 cjmp(equal,pficin) inctwo(ic) ; ic := ic+2, goto pficin.
1041 jmp(sknins) inctwo(ic) ; ic := ic + 2, goto sknins,
; HC8000 instr: skip if register bits one: 'so', numeric code 44.
; -------------------------------------------------------------
1042 so/'44: and(q,wreg,addrs) ; q := w_reg(index) and addrs.
1043 jmp(se1) sub(q,addrs) noload ; if addrs <> q then
; condition test performed in skip equal.
; HC8000 instr: skip if register bits zero: 'sz', numeric code 45.
;----------------------------------------------------------------
1044 sz/'45: and(wreg,addrs) noload ; if w_reg(index) and addrs <> 0 then
1045 sz1: cjmp(nzero,pficin) inctwo(ic) ; ( entry from skip exeption)
; ic := ic + 2, goto pficin.
1046 jmp(sknins) inctwo(ic) ; ic := ic + 2, goto sknins.
; HC8000 instr: skip if no exeption: 'sx', numeric code 46.
; -------------------------------------------------------
1047 sx/'46: and(addrs,7) ; addrs := addrs and 7.
1050 jmp(sz1) and(addrs,ex) noload ; if (ex and addrs) <> 0 then
; skip test performed in skip zero.
; HC8000 instr: skip if no write protection: 'sp', numeric code 21.
; ---------------------------------------------------------
1051 sp/'21: sub(addrs,8) noload ; if sp < 8 then
1052 cjmp(less,sp1) add(q,addrs,base); goto sp1, q := addrs + base.
1053 sub(q,lowlim) noload ; if addrs + base < lower_limit then
1054 cjmp(less,pfneic) ; goto pfneic.
1055 jmp(sl1) sub(q,uplim) noload ; if addrs+base >=
; skip action performed in skil low.
1056 sp1: sub(addrs,0) noload ; if addrs < 0 then
1057 cjmp(less,pficin) inctwo(ic) ; ic := ic + 1, goto pficin.
1060 jmp(sknins) inctwo(ic) ; ic := ic + 2 , goto skins.
; escape and interupt sequencing.
; -------------------------------
; HC8000 instr: return from excape: 're', numeric code 22.
; ------------------------------------------------------
; escape pattern /.11.1./
1061 re/'22: mover(wrk0,addrs) ; wrk0 ( reg dump addrs) := addrs.
1062 add(wrk0,base) ; reg dump addrs := reg dump addrs + base.
1063 add(q,wrk0,14) ; q := addrs of last reg to be
; reestablished.
1064 sub(lowlim,wrk0) noload ; if lower limit > reg dump addrs then
1065 cjmp(great,re5) sub(q,uplim) noload; goto re5, if reg dump addrs
1066 cjmp(greq,re5) mover(wrk2,status); save monitor mode bit for
; preventing illegal setting of
; monitor mode in werk2.
1067 re7: jsb(redyre) mover(wrk1,ic) ; call reestablish dynamic registers,
; save old ic.
1070 re3: mover(wrk2,wrk2) ; if process previus was in monitor
1071 cjmp(neg,re4) mover(wrk2,status) slft; then goto re4 , else
1072 mover(status,wrk2) srgt ; clear monitor mode bit in status reg.
re4:
1073 jmp(nopfic) ; goto get next 8000 instr:.
1074 re5: mover(wrk0,addrs) ; wrk0 := reg dump addrs.
1075 sub(q,base) ; q := reg dump addrs + 14.
1076 mover(wrk2,status) ; save monitor mode bit.
1077 sub(wrk0,8) noload ; if reg dump addrs < 8 then
1100 cjmp(less,expt) sub(q,cpa) noload; goto re6, else if reg dumpadd + 14
1101 cjmp(less,re7) ; < cpa then goto re7 ( reestablish
; registers) else
1102 jmp(expt) ; goto exeption.
; HC8000 instr: return from interupt: 'ri', numeric code 12.
; --------------------------------------------------------
; escape pattern /111.1./
1103 ri/'12: mover(status,status) ; if not in monitor mode then
1104 cjmp(notneg,prgexp) ; then goto program exeption.
1105 invr(hc2901,'e01rin) ; clok hc2901 in entry
; return from interupt.
1106 add(inf,12) ; select new system table
; inf := inf + 12.
1107 add(q,inf,2) ; q := inf+2, calculate register dump
; address in new system table.
1110 ri1: cjmp(re2901,ri1) clre01 ; wait for hc2901 is ready.
1111 invs(hc2901,q) ; move addrs of system table regdump
; addrs to hc2901
1112 mover(wrk2,addrs) ; save old address in wrk2.
1113 mover(wrk1,ic) ; save old address in wrk1.
1114 ri2: cjmp(re2901,ri2) clre01 invs(wrk0,hc2901); wait for hc2901 is ready,
; get regdump addrs to wrk0.
1115 jsb(redyen) clwr01 ; call subroutine for reestablishing
; the dynamic registers from hc2901,
; clear write hc2901.
1116 add(wrk0,wrk2) ; reg dump addr := reg dump addr
; + old addrs
; ( reg dump addr is now addr of static
; registers, old addrs is the
; effective address of ri intruction).
1117 invs(hc2901,wrk0) ; send address of dynamic register dump to
; to hc2901.
1120 ri12: cjmp(re2901,ri12) clre01 invs(cpa,hc2901); wait for hc2901 ready,
; reestablish spa register.
1121 cont clwr01 ; clock hc2901 ready to accept next
; data word.
1122 ri14: cjmp(re2901,ri14) clre01 invs(base,hc2901); wait for hc2901 ready,
; reestablish base register.
1123 cont clwr01 ; clock hc2901 ready to accept next
; data word.
1124 ri15: cjmp(re2901,ri15) clre01 invs(lowlim,hc2901); wait for hc2901 ready,
; reestablish lower limit register.
1125 cont clwr01 ; clock hc2901 ready to accept next data
; word.
1126 ri16: cjmp(re2901,ri16) clre01 invs(uplim,hc2901); wait for hc2901 ready,
; reestablish upper limit register.
; set dump error count to 0.
1127 and(status,'disbit) noload ; if disable bit not set then
1130 cjmp(zero,nopfic) ; fetch next instr wih no prefetch.
1131 invr(hc2901,'e01sdl) ; else clock entry set disable level.
1132 ri17: cjmp(re2901,ri17) clre01 ; wait for hc2901 ready.
1133 jmp(nopfic) ; go to fetch next 8000 instr: with
; prefecth.
; monitor control
; ---------------
; HC8000 instr: general register, put: 'gp', numeric code 47.
; ---------------------------------------------------------
; escape pattern 2.1000001
1134 gp/'47: mover(status,status) ; if not in monitor mode
1135 cjmp(notneg,prgexp) moves(q,wreg); then goto program exeption,
; q := wreg(index).
1136 sub(addrs,26) noload ; if address = 26 then
1137 cjmp(equal,gp26) inctwo(ic) ; then goto generel put 26, ic := ic+2.
1140 sub(addrs,64) noload ; if addrs = 64 then
1141 cjmp(equal,gp64) ; goto generel put 64.
; else if no legal address then
1142 jmp(pficin) ; goto get next prefetched instruction.
1143 gp64: invr(hc2901,'e01wtr) ; clock hc2901 in write test
; register.
1144 gp3: cjmp(re2901,gp3) clre01 ; loop while hc2901 is not ready
1145 invs(hc2901,q) ; hc2901 := q and clock
1146 gp4: cjmp(re2901,gp4) clre01 ; loop until hc2901 is ready.
1147 jmp(pficin) ; goto pfneic.
1150 gp26: jmp(pficin) moves(inf,q) ; information register := q (
; selected working register), goto
; get next prefetched instrcution.
; HC8000 instr: general register, get: 'gg', numeric code 28.
; -----------------------------------------------------
; escape pattern: 2.000001
1151 gg/'28: moves(q,wreg) ; save wreg(index).
1152 sub(addrs,94) noload ; if address = 94 then
1153 cjmp(equal,gg94) ; then goto generel get 94 else
1154 sub(addrs,26) noload ; if addrs = 26 then
1155 cjmp(equal,pfneic) mover(wreg,inf); wreg(index) := infromation
; register, goto pfneic.
; else
1156 sub(addrs,100) noload ; if address = 100 then
1157 cjmp(equal,gg100) ; then goto generel get 100 else
1160 sub(addrs,200) noload ; if address > 200 then
1161 cjmp(greq,ggm200) ; then goto generel get more than 200
; else
1162 sub(addrs,64) noload ; if addres = 64 then
1163 cjmp(equal,gg64) ; then goto generel get 64 else
1164 sub(addrs,66) noload ; if addrs = 66 then
1165 cjmp(equal,gg66) ; then goto generel get 66
; else
1166 ggnle: jmp(pfneic) moves(wreg,q) ; if not legal then reestablish
; w reg(index) and goto pfneic
1167 gg100: invr(hc2901,'e01rtc) ; send addrs of real time clock to
; hc2901.
1170 jmp(gg4) ; goto gg4.
1171 gg64: invr(hc2901,'e01rtr) ; send0address of read test register
; with no wait to hc2901.
1172 jmp(gg4) ; goto gg4.
1173 gg66: invr(hc2901,'e01rtw) ; clock hc2901 in read test register
; with wait.
1174 jmp(gg4) ; goto wait word from hc2901.
gg94: ; generel get chrakter interupt level from
; amd9511 interupt controler.
1175 mover(status,status) ; if not in monitor mode then
1176 cjmp(notneg,ggnle) ; goto generel get no legal entry.
1177 invr(hc2901,'e01cil) ; else clock hc2901 in entry
; get charakter interupt level.
1200 gg4: cjmp(re2901,gg4) clre01 ; loop while hc2901 is not redy
1201 jmp(pfneic) invs(wreg,hc2901) ; w_reg(index) := hc2901, gpfneic.
ggm200: ; entry for generel get with addres greather and equal 200.
1202 sub(addrs,200) noload ; if address > 200 then
1203 cjmp(great,ggm202) ; then goto generel get more 202
; else
; generel get 200.
; reverse bit in word.
1204 moves(wrk0,q) dshinz ; wrk0 := q( selected working register),
; set shift condition in amd2904 to
; double shift with zero input.
1205 lcpu(23) ; load counter with length or word.
; for 0 to 23 do
; begin
1206 mover(wrk0,wrk0) rgtaql ; q.msb := wrk0.lsb, shift wrk0 rigth.
1207 rep mover(wrk1,wrk1) lftaql ; wrk1.lsb := q.msb . shift wrk1 left.
1210 mover(wreg,wrk1) shinz ; wreg(index) := wrk1 ( reversed word),
; set shift condition to singleshift
; and zero input.
1211 jmp(pficin) inctwo(ic) ; goto get next prefetched
; instrcution.
ggm202: ; entry for instruction greather than 200.
1212 sub(addrs,202) noload ; if address > 202 then
1213 cjmp(great,ggm204) ; goto continue with generel get instructions
; with address greather than 202.
; else gg 202 and 201.
1214 moves(wrk0,q) ; wrk0 := C(selected w register).
1215 cjmp(neg,gg2021) inctwo(ic) ; if c(wreg) negative then
; goto gg201 else
1216 sub(addrs,201) noload ; if address = 201 then
1217 cjmp(equal,gg2024) ; goto one decrement of wrk0.
1220 sub(wrk0,1) ; decrement wrk0 by 1.
1221 gg2024: sub(wrk0,1) ; decrement wrk0 by 1.
1222 cjmp(greq,pficin) moves(wreg,wrk0); if wrk0 >= 1 then goto
; get next instruction prefetched
; selected working register := wrk0.
1223 jmp(sknini) mzero(wreg) ; else goto get next instrcution
; with skip, reset seleted working
; register.
1224 gg2021: sub(addrs,202) noload ; if address = 202 then
1225 cjmp(equal,gg2023) inctwo(wrk0) ; goto gg2023 wrk0 :=
; wrk0 + 2.
1226 sub(wrk0,1) ; else wrk0 := wrk0+1.
1227 gg2023: cjmp(neg,pficin) mover(wreg,wrk0); if wrk0 < 0 then goto
; get next prefetched instruction
; selected working register := wrk0
1230 jmp(sknini) mzero(wreg) ; else goto get next skipped prefetched
; instruction, reset selected
; working register.
; HC8000 instr: data out: 'do', numeric code 1.
; -------------------------------------------
1231 do/'1: mover(wrk0,'e01dob) ; wrk0 := address of data out base block
; in hc2901.
1232 jmp(dioent) ; goto common data in data out entry.
; HC8000 instr: data in: 'di', numeric code 0.
; --------------------------------------------
1233 di/'29: mover(wrk0,'e01dib) ; wrk0 := entry in hc2901 for address
; block for data in.
dioent: ; common entry for data in and data out.
1234 andinv(ex,7) ; ex(21,23) := 0, clear bit 21 to
; 23 in ex register (i.e. status
; register.)
1235 cjmp(notneg,prgexp) mover(wrk1,addrs) slft; if status
; (same as ex) is not
; negative ( not monitor mode)
; then goto program exeption,
; wrk1 := addrs * 2 ( delete possible
; sign bit).
1236 cjmp(notneg,dimemo) mover(wrk1,wrk1) srgt; if addrs is not negative
; then goto dimemo ( memory word fetch),
1237 and(q,addrs,7) ; q := last 3 bits of
; effective address.
1240 add1(wrk0,q,wrk0) ; wrk0 := wrk0 + address of first
; data in function, in hc2901 + 1,
; ( add 1 because the first entry in
; hc2901 is used to direct memory
; access).
1241 andinv(wrk1,7) ; clear last 3 bits of device number.
; data in jump table.
1242 dimemo: invs(hc2901,wrk0) ; clock hc2901 in address e01gmw.
1243 diw1: cjmp(re2901,diw1) clre01 ; wait for ready.
1244 invs(hc2901,wrk1) ; hc2901 := divice number.
1245 moves(q,wreg) ; q := wreg(index).
1246 diw2: cjmp(re2901,diw2) clre01 ; wait for hc2901 ready.
1247 invs(hc2901,q) ; send contents of w reg to hc2901.
1250 diw3: cjmp(re2901,diw3) invs(wreg,hc2901); wait for hc2901,
; wreg(index) := hc2901.
1251 cont clwr01 ; clear write ready from hc2901.
1252 diw4: cjmp(re2901,diw4) invs(wrk1,hc2901); wait for hc2901, wrk1 := hc2901.
1253 and(wrk1,7) ; wrk1 := wrk1(21.23).
1254 jmp(pfneic) or(ex,wrk1) ; ex := wrk1.
; goto pfneic.
; jumptable to not finished 8000 instr:
; schould not be prommed.
1255 wd/'24: jmp(dowd) ; word divide.
1256 cf/'53: jmp(docf) ; convert floating to integer.
1257 ci/'32: jmp(doci) ; convert integer to floating.
1260 fa/'48: jmp(dofa) ; floating point add.
1261 fd/'52: jmp(dofd) ; floating point divide.
1262 fm/'50: jmp(dofm) ; floating point multiply.
1263 fs/'49: jmp(dofs) ; floating point subtract.
ggm204: ; entry next generel get instruction
; .
dowd:
docf:
doci:
dofa:
dofd:
dofm:
dofs:
1264 jmp(prgexp) ; goto program exeption.
; end of micro program
*end:
expt \r reff. to address 0124 0174 spec. 494
ad \r reff. to address 0411 0633 spec. 37
al \r reff. to address 0243 0363 spec. 11
rs \r reff. to address 0265 0411 spec. 23
bz \r reff. to address 0324 0504 spec. 19
bl \r reff. to address 0331 0513 spec. 2
re \r reff. to address 0561 1061 spec. 22
ri \r reff. to address 0579 1103 spec. 12
ss \r reff. to address 0368 0560 spec. 57
se \r reff. to address 0540 1034 spec. 42
cf \r reff. to address 0686 1256 spec. 53
prgexp \r reff. to address 0114 0162 spec. 474
so \r reff. to address 0546 1042 spec. 44
dl \r reff. to address 0268 0414 spec. 54
ielax1 \r reff. to address 0019 0023 spec. 13
ielax2 \r reff. to address 0020 0024 spec. 14
ielax3 \r reff. to address 0021 0025 spec. 15
wa \r reff. to address 0351 0537 spec. 7
ws \r reff. to address 0353 0541 spec. 8
wm \r reff. to address 0355 0543 spec. 10
xs \r reff. to address 0314 0472 spec. 27
ielati \r reff. to address 0017 0021 spec. 12
hl \r reff. to address 0246 0366 spec. 3
gp \r reff. to address 0604 1134 spec. 47
fd \r reff. to address 0689 1261 spec. 52
jd \r reff. to address 0517 1005 spec. 14
jl \r reff. to address 0529 1021 spec. 13
ld \r reff. to address 0469 0725 spec. 39
lx \r reff. to address 0379 0573 spec. 6
inlyx1 \r reff. to address 0011 0013 spec. 5
inlyx2 \r reff. to address 0013 0015 spec. 6
inlyx3 \r reff. to address 0015 0017 spec. 7
relax1 \r reff. to address 0003 0003 spec. 9
relax2 \r reff. to address 0004 0004 spec. 10
relax3 \r reff. to address 0005 0005 spec. 11
nd \r reff. to address 0501 0765 spec. 35
aa \r reff. to address 0361 0551 spec. 56
ac \r reff. to address 0244 0364 spec. 33
relati \r reff. to address 0002 0002 spec. 8
am \r reff. to address 0240 0360 spec. 9
as \r reff. to address 0381 0575 spec. 36
ba \r reff. to address 0337 0521 spec. 18
bs \r reff. to address 0344 0530 spec. 17
rx \r reff. to address 0266 0412 spec. 25
rl \r reff. to address 0263 0407 spec. 20
sp \r reff. to address 0553 1051 spec. 21
onlyx1 \r reff. to address 0006 0006 spec. 1
onlyx2 \r reff. to address 0007 0007 spec. 2
onlyx3 \r reff. to address 0008 0010 spec. 3
sh \r reff. to address 0534 1026 spec. 40
sl \r reff. to address 0537 1031 spec. 41
sn \r reff. to address 0543 1037 spec. 43
ds \r reff. to address 0271 0417 spec. 55
sz \r reff. to address 0548 1044 spec. 45
sx \r reff. to address 0551 1047 spec. 46
do \r reff. to address 0665 1231 spec. 1
di \r reff. to address 0667 1233 spec. 29
ci \r reff. to address 0687 1257 spec. 32
fa \r reff. to address 0688 1260 spec. 48
fs \r reff. to address 0691 1263 spec. 49
iomodi \r reff. to address 0009 0011 spec. 4
hs \r reff. to address 0253 0375 spec. 26
xl \r reff. to address 0308 0464 spec. 16
gg \r reff. to address 0617 1151 spec. 28
je \r reff. to address 0514 1002 spec. 15
flpexp \r reff. to address 0117 0165 spec. 481
wd \r reff. to address 0685 1255 spec. 24
fm \r reff. to address 0690 1262 spec. 50
nomodi \r reff. to address 0001 0001 spec. 0
intser \r reff. to address 0153 0231 spec. 568
la \r reff. to address 0375 0567 spec. 4
ls \r reff. to address 0452 0704 spec. 38
lo \r reff. to address 0377 0571 spec. 5
intexp \r reff. to address 0115 0163 spec. 477
extint \r reff. to address 0148 0224 spec. 553
ns \r reff. to address 0492 0754 spec. 34
name spec. instr. octal
intser 568 153 231 0 153
extint 553 148 224 0 148
expt 494 124 174 0 124
flpexp 481 117 165 0 117
intexp 477 115 163 0 115
prgexp 474 114 162 0 114
MAP ENTRIES
name spec. instr. octal
ss 57 368 560 1 112
aa 56 361 551 1 105
ds 55 271 417 1 15
dl 54 268 414 1 12
cf 53 686 1256 2 174
fd 52 689 1261 2 177
fm 50 690 1262 2 178
fs 49 691 1263 2 179
fa 48 688 1260 2 176
gp 47 604 1134 2 92
sx 46 551 1047 2 39
sz 45 548 1044 2 36
so 44 546 1042 2 34
sn 43 543 1037 2 31
se 42 540 1034 2 28
sl 41 537 1031 2 25
sh 40 534 1026 2 22
ld 39 469 725 1 213
ls 38 452 704 1 196
ad 37 411 633 1 155
as 36 381 575 1 125
nd 35 501 765 1 245
ns 34 492 754 1 236
ac 33 244 364 0 244
ci 32 687 1257 2 175
di 29 667 1233 2 155
gg 28 617 1151 2 105
xs 27 314 472 1 58
hs 26 253 375 0 253
rx 25 266 412 1 10
wd 24 685 1255 2 173
rs 23 265 411 1 9
re 22 561 1061 2 49
sp 21 553 1051 2 41
rl 20 263 407 1 7
bz 19 324 504 1 68
ba 18 337 521 1 81
bs 17 344 530 1 88
xl 16 308 464 1 52
je 15 514 1002 2 2
jd 14 517 1005 2 5
jl 13 529 1021 2 17
ri 12 579 1103 2 67
al 11 243 363 0 243
wm 10 355 543 1 99
am 9 240 360 0 240
ws 8 353 541 1 97
wa 7 351 537 1 95
lx 6 379 573 1 123
lo 5 377 571 1 121
la 4 375 567 1 119
hl 3 246 366 0 246
bl 2 331 513 1 75
do 1 665 1231 2 153
VECTOR ENTIES
name spec. instr. octal
ielax3 15 21 25 0 21
ielax2 14 20 24 0 20
ielax1 13 19 23 0 19
ielati 12 17 21 0 17
relax3 11 5 5 0 5
relax2 10 4 4 0 4
relax1 9 3 3 0 3
relati 8 2 2 0 2
inlyx3 7 15 17 0 15
inlyx2 6 13 15 0 13
inlyx1 5 11 13 0 11
iomodi 4 9 11 0 9
onlyx3 3 8 10 0 8
onlyx2 2 7 7 0 7
onlyx1 1 6 6 0 6
nomodi 0 1 1 0 1
MIC. ASM. OK!
LAST INSTR. ADDRS.: 693 OCTAL INSTR. ADDRS.: 1265 TRANSLATOR BLOCKS: 118
▶EOF◀