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└─⟦621cfb9a2⟧ Bits:30002817 RC8000 Dump tape fra HCØ. Detaljer om "HC8000" projekt.
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\f Micro asm.: micasm03 version date.830214.1123 Source file: t2903dir version date.830321.1045 1 ; directives and names to 2903. 2 ; masks before 2 47oev after 2oev before until 19oev 3 *mask: mcnden,5 ; condition enable. before until 19oev 4 *mask: aludes,(11:15) ; alu function from alu bit 8 to both 5 ; bit 5 , mir(11) to mir(15) before 2 47oev after 2oev before until 12oev before 2 47oev after 2oev before until 12oev before 2 47oev after 2oev before until 19oev 6 *mask: mhlfmo,23,42,43 ; halfword move mask. before 2 47oev after 2oev before until 12oev before 2 47oev after 2oev before until 12oev before 2 47oev after 2oev before until 19oev 7 *mask: mmym,23,40,41 ; select the M reg or the my reg 8 ; in the 2904 condition controler 9 ; 10 11 12 ; jump addrs codes 13 ; use full sekvens mask. 14 ; type = 12. 15 ; bit(1:4) in instr. format is the sekvens kontrol, 16 ; bit(5) in instr. format is condition enable. 17 *name: cjsb,12,1,0 ; conditional jump to subroutine 18 *name: jsb,12,1,1 ; jump to subroutine 19 *name: cjmp,12,3,0 ; conditional jump addrs. 20 *name: jmp,12,3,1 ; jump addrs unconditional. 21 22 *name: cjsrp,12,5,0 ; conditional jump to subroutine conditional addrs. 23 ; from sekvenser reg. or direct. 24 25 *name: cjmrd,12,7,0 ; jump to addrs. conditional 26 ; from secvenser register or direct. 27 *name: rpct,12,9,0 ; repeat direct and derease counter until 28 ; counter = 0. 29 *name: cjmpp,12,11,0 ; conditional: if pass then 30 ; pop stack and jump to direct addrs. else 31 ; continue. 32 *name: twb,12,15,0 ; tree way branch 33 34 ; jump sekvens codes. 35 *name: wait,17,3,0 ; wait until condition is true. 36 ; wait is translated into an 37 ; equivalent of: 38 ; labelx: cjmp(conditio,labelx) 39 *name: jmpz,14,0,0 ; jump to addrs. zero, 40 ; clear stack. 41 *name: jmap,14,2,0 ; jump to addrs. given by map prom 42 *name: push,14,4,1 ; pusch micro program instr. counter to 43 ; stack and continue. 44 *name: cjvec,14,6,0 ;if pass then go to address given 45 ; by vector prom otherwise next micro 46 ; instr. 47 *name: cjv1,14,6,0 ; jump to addrs. given by vektor1 prom 48 *name: cjv2,14,6,2 ; jmp to addrs. given by vector 2 prom. 49 50 *name: jvec,14,6,1 ; jump vector. 51 *name: rep,14,8,0 ; if counter <> 0 then goto first in stack 52 ; else pop stack and continue. 53 *name: crtn,14,10,0 ; conditional: if pass then 54 ; jump to first in stack and pop stack 55 ; else continue. 56 *name: rtn,14,10,3 ; return: jump to first in stack 57 ; and pop stack. 58 59 *name: loop,14,13,0 ; conditional loop: 60 ; if pass then pop sctak and continue 61 ; else jump to first in stack. 62 *name: pop,14,13,3 ; pop stack and continue. 63 *name: cont,14,14,0 ; continue to next micro instr. 64 65 66 67 68 ; type 15 load counter types. 69 70 *name: ldct,15,12,0 ; load counter whit addrs. field and continue. 71 *name: clcpu,15,4,0 ; push micro program counter to stack 72 ; if pass then load counter whit addrs. field 73 ; else hold counter. 74 75 *name: lcpu,15,4,1 ; push micro program counter to stack 76 ; load counter with address field. 77 ; type 16 is load counter from internal alu reg. 78 *name: ldctre,16,12,5,0 ; load counter from register addressed. 79 *name: pushre,16,4,5,1 ; pusch mic. program instr. counter to 80 ; stack and load counter with contents of 81 ; the internal register pointed out by 82 ; the argument. 83 *name: cpshre,16,4,5,0 ; pusch mic. program instr. counter 84 ; into the stack and 85 ; if(condition pass then load counter 86 ; with internal alu register pointed 87 ; out by the instr address field) else 88 89 ; hold counter 90 ; type 16. load micro sekvenser counter with contents of 91 ; internal bus. 92 *name: ldctbu,16,12,6,0 ; load counter from bus 93 *name: pushbu,16,4,6,1 ; 94 *name: cpshbu,16,4,6,0 ; 95 96 ; normal alu function codes 97 ; code zero is not used 98 *name: sub,11,1,2 ; f = s minus r minus 1 plus carry = 1 99 *name: sub1,11,1,1 ; f = s minus r minus 1 plus carry (=0) 100 *name: subr,11,2,2 ; f = r minus s minus 1 plus carry (= 1). 101 *name: subr1,11,2,1 ; f = r minus s minus 1 plus carry (= 0). 102 *name: add,11,3,1 ; f = r plus s plus carry (= 0) 103 *name: add1,11,3,2 ; f = r plus s plus carry (= 1) 104 *name: moves,11,4,1 ; f = s plus carry (= 0) 105 *name: inc,11,4,2 ; f = s plus (carry = 1) 106 *name: invs,11,5,1 ; f = not(s) plus (carry = 0) 107 *name: invs1,11,5,2 ; f = not(s) plus (carry = 1) 108 *name: mover,11,6,1 ; f = r plus (carry = 0) 109 *name: incr,11,6,2 ; f = r plus (carry = 1) 110 *name: invr,11,7,1 ; f = not(r) plus (carry = 0) 111 *name: invr1,11,7,2 ; f = not(r) plus (carry = 1) 112 *name: mzero,11,8,1 ; f = low 113 *name: andinv,11,9,1 ; f = not(r) and s 114 *name: exnor,11,10,1 ; f = r exclusive nor s 115 *name: exor,11,11,1 ; f = r exclusive or s 116 *name: and,11,12,1 ; f = r and s 117 *name: nor,11,13,1 ; f = r nor s 118 *name: nand,11,14,1 ; f = r nand s 119 *name: or,11,15,1 ; f = r or s 120 ; special functions 121 *name: unsmul,11,0,3 ; unsigned multiply 122 *name: mult2c,11,4,3 ; 2'complement multiply . bitpattern =/01010/ 123 *name: sgnmgn,11,11,5 ; bitpattern = /01011/ 124 ; from 2's complement to sign magnitude. 125 *name: mult2l,11,12,5 ; 2'complement multiply, last cycle, bitpattern = /01100/ 126 *name: slnorm,11,16,4 ; bitpattern = /10000/ 127 ; single length normalize. 128 *name: dlnorm,11,20,3 ; bitpattern = /10100/ 129 ; double length normalize. 130 *name: div1st,11,20,3 ; bitpattern = /10100/ 131 ; first divide operation. same as dlnorm. 132 *name: div2c,11,24,5 ; bitpattern = /11000/ 133 ; 2' complement divide. 134 *name: div2cr,11,28,5 ; bitpattern = /11100/ 135 ; 2' complement divide corectio and remainder. 136 *name: incone,11,8,3 ; increment by 1 137 *name: inctwo,11,8,4 ; increment by 2 138 ; the nonaddressable q-register. 139 *name: q,30,-1 ; the negative value to 140 ; destingues from the others . 141 ; use of the indexd w and w_pre registers 142 *name: windex,30,-2 ; 143 *name: wreg,30,-2 ; 144 *name: wpre,30,-3 ; 145 146 ; internal registers 147 ; the working register is interchanged 148 ; cause of a hard_ware bug. 149 ;; note: it is important that the 4 working registers 150 ;; have the fixed adresses in the register ram, otherwise 151 ;; will the wreg and wpre register selection 152 ;; logic not function. 153 *name: w3,30,0 ; the 3 reg. 154 *name: x3,30,0 ; schould be removed. 155 *name: w2,30,1 ; then w2 reg. 156 *name: x2,30,1 ; the w2 used as index reg. 157 *name: w1,30,2 ; the w2 reg. 158 *name: x1,30,2 ; the w2 used as index register 159 *name: w0,30,3 ; the w3 reg. 160 *name: status,30,4 ; the status register. 161 *name: ex,30,4 ; the exeption register. 162 *name: ic,30,5 ; the instruction counter. 163 *name: cause,30,6 ; the cause register. 164 *name: addrs,30,7 ; storage address buffer. 165 *name: wrk1,30,10 ; working locaition 1 for micro program 166 *name: wrk2,30,11 ; working locaition 2 for micro program. 167 *name: base,30,9 ; the base register 168 *name: cpa,30,8 ; the common protected area register 169 *name: inf,30,12 ; information register. 170 *name: uplim,30,13 ; the upper limit register. 171 *name: lowlim,30,14 ; the lower limit register. 172 *name: wrk0,30,15 ; micro program wroking register no 0. 173 ; external registers. 174 *name: hc2901,30,16 ; dest: write hc2901 175 ; source: read hc2901 176 ; 177 ; 178 ; set conditions select 179 ; type is 40 180 ; format is <name>/40/<value>/<mask_kind>/<mask or std. mask no.> 181 ; 182 *name: lseq,40,1,2,5 ; less or equal 183 *name: great,40,0,2,5 ; greather than '>' 184 *name: less,40,3,2,5 ; less then '<' 185 *name: greq,40,2,2,5 ; greather than or equal '>=' 186 *name: equal,40,5,2,5 ; equal '=' 187 *name: nequal,40,4,2,5 ; not equal '<>' 188 ; normal cond bits 189 *name: zero,40,5,2,5 ; zero 190 *name: nzero,40,4,2,5 ; not zero 191 *name: over,40,7,2,5 ; overflow 192 *name: nover,40,6,2,5 ; not overflow 193 *name: cxorz,40,9,2,5 ; carry xor (+) zero 194 *name: candz,40,8,2,5 ; carry and (*) zero 195 *name: carry,40,11,2,5 ; carry 196 *name: ncarry,40,10,2,5 ; not carry 197 *name: ncxorz,40,13,2,5 ; not carry xor (+) zero 198 *name: candnz,40,12,2,5 ; carry and not z 199 *name: neg,40,15,2,5 ; negative 200 *name: notneg,40,14,2,5 ; not negative 201 ; for hc2901 ready 202 *name: re2901,40,15,2,5 ; hc2901 ready 203 ; 204 ; 205 ; 206 ; 207 ; specials 208 ; 209 ; 210 ; 211 ; 212 ; 213 214 ; set condition kind 215 *name: csmy,16,1,1,mmym ; set condition to my bits 216 *name: csm,16,2,1,mmym ; set condition to M bits 217 *name: cs2901,16,3,1,mmym ; set condition to hc2901 218 ; sign extend bits8 to 6 high 219 ; bit 5 for the slices ther schould 220 ; be extende thrugh = 0 221 ; bit 5 for slices wwhit no extend = 1. 222 *name: signex,16,29,1,aludes ; bitpatern /11101/ = 29 223 224 ; generel alu dest control bit 8 to both bits 5 225 ; in alu function. 226 *name: noload,16,24,1,aludes ; bitpattern = /11000/ = 24 227 *name: rgtaol,16,3,1,aludes ; bitpattern = /00011/ = 3 228 ; shift rigth alu output logaritm, hold q 229 ; - -- - - - 230 *name: srgt,16,3,1,aludes ; shift rigth. 231 *name: lftaol,16,19,1,aludes ; bitpattern = /100ll/ = 19 232 ; shift left alu output logaritm, hold q. 233 ; - -- - - - 234 *name: slft,16,19,1,aludes ; shift left. 235 *name: lftqil,16,27,1,aludes ; bitpattern = /11011/ = 27 236 ; sift left q-reg input logarithm, hold ram 237 ; - -- - - - 238 *name: rgtqil,16,11,1,aludes ; bitpattern = /01011/ = 11 239 ; shift rigth q-reg output logarithm, hold ram 240 ; - -- - - - 241 *name: rgtaql,16,7,1,aludes ; bitpattern = /00111/ = 7 242 ; shift rigth alu output q_reg input logical. 243 ; - -- - - - 244 *name: lftaql,16,23,1,aludes ; bitpattern = /10111/ = 23 245 ; shift left alu output q_reg input logical. 246 ; - -- - - - 247 *name: rgtaoa,16,0,1,aludes ; bitpattern = /00000/ = 0 248 ; shift rigth alu output aritmetric, hold q. 249 ; - -- - - - 250 *name: lftaoa,16,16,1,aludes ; bitpattern = /10000/ = 16 251 ; shift left alu output aritmetric, hold q. 252 ; - -- - - - 253 *name: onlyq,16,12,1,aludes ; bitpattern = /01100/ = 12 254 ; only load q reg, hold other internal registers 255 ; hold and write my and m . 256 *name: hldcnd,16,1,1,mcnden ; hold writing the condition regs. 257 *name: openm,16,7,2,38 ; open for wring in m. 258 *name: setint,16,0,2,40 ; select the interupt bit. 259 ; set half word moves 260 ;*name: hmlr,16,1,2,36 261 *name: hmlr,16,1,1,mhlfmo ; move left half word to right 262 ;*name: hmrl,16,0,2,36 263 *name: hmrl,16,0,1,mhlfmo ; move right half word to left 264 ;*name: nothm,16,3,2,36 265 *name: nothm,16,3,1,mhlfmo ; no half word move 266 ; set shift control in 2904 267 ; both the alu and q reg is shifted either 268 ; seperate or in conection 269 *name: shinz,16,0,2,37 ; shift seperat whit zero input 270 *name: shin1,16,1,2,37 ; shift seperate whit one input 271 *name: dshinz,16,6,2,37 ; shift double whit zero input 272 *name: dshin1,16,3,2,37 ; shift double whit 1 input 273 *name: dshln,16,15,2,37 ; shift alu output and q whit link 274 *name: shslno,16,2,2,37 ; used in shift rigth in last 275 ; correction in single length 276 ; normalize. M(n) is left input 277 ; to q-reg. 278 *name: shdlno,16,5,2,37 ; used in shift rigth in last 279 ; correction in double length 280 ; normalize. M(n) is left input 281 ; to ram-shifter. 282 *name: slszm,16,2,2,37 ; shift ram left with zero input 283 ; and output to Mcarry. 284 *name: dlszm,16,7,2,37 ; shift ram and q left with 285 ; zero input and output to Mcarry. 286 *name: dlsmm,16,12,2,37 ; shift ram and q left with 287 ; Mcarry input and output to Mcarry. 288 ; or resetting bit 27. 289 ; clock the hc2901 register by setting bit 26 290 *name: clwr01,16,1,2,23 ; set the write hc2901 bit. 291 *name: clre01,16,1,2,22 ; set the read hc2901 bit. 292 *name: nclk01,16,0,2,23 ; inhippit the clocking of the 293 ; hc2901, allthough it migth is 294 ; referenced through the 295 ; destination field. 296 ; set or clear selected bit or bits 297 ; selected from the argument. 298 *name: set,16,-1,3,1 ; set one bit 299 *name: clear,16,0,3,1 ; clear one bit 300 *name: setall,16,-1,3,2 ; set all bit from arg1 to arg2 301 *name: clall,16,0,3,2 ; clear all bit from arg1 to arg2 302 ; in internal register stack pointed 303 ; out by b_addrs field. 304 *save: m2903 305 *end: MIC. ASM. OK! LAST INSTR. ADDRS.: 0 OCTAL INSTR. ADDRS.: 0 TRANSLATOR BLOCKS: 81 ▶EOF◀