DataMuseum.dk

Presents historical artifacts from the history of:

RC4000/8000/9000

This is an automatic "excavation" of a thematic subset of
artifacts from Datamuseum.dk's BitArchive.

See our Wiki for more about RC4000/8000/9000

Excavated with: AutoArchaeologist - Free & Open Source Software.


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⟦dff5f918f⟧ TextFile

    Length: 13056 (0x3300)
    Types: TextFile
    Names: »kkrhmload1t«

Derivation

└─⟦621cfb9a2⟧ Bits:30002817 RC8000 Dump tape fra HCØ.  Detaljer om "HC8000" projekt.
    └─⟦0364f57e3⟧ 
        └─⟦this⟧ »kkrhmload1t« 

TextFile

     (kkrhmload=slang list.no xref.no;
     )                 ;
\f


s.   a60,b20,c60 w.    ;
p.   <:fpnames:>       ;
     k=h55             ;
     0                 ;
a16: a14               ;
     al  w3  x1        ;
     wa. w3     a16.   ;
     jl  w2  x3        ;  start init
     jl.        b0.    ;
a50: 50,r.20           ;
                       ; start exekvering
b0:  jl. w3     h25.-2 ; input next command
     se  w2     114    ; if not r(eset) then
     jl.        b1.    ; goto b1
     jl. w3     a22.   ; else reset cpu1
     jl.        b0.    ; goto input next command
b1:  se  w2     97     ; if not (st)a(rt)
     jl.        b2.    ; goto b
     jl. w3     a24.   ; else start cpu1
     jl.        b0.    ; goto input next command
b2:  se  w2     111    ; if not (st)o(p) then
     jl.        b3.    ; goto b3
     jl. w3     a23.   ; else stop cpu1
     jl.        b0.    ; goto input next command
b3:  se  w2     105    ; if interrupt then
     jl.        b4.    ; goto b4
     jl. w3     a21.   ; else interrupt
     jl.        b0.    ; goto input next command
b4:  se  w2     102    ; if not f(inis) then
     jl.        b0.    ; goto input next command
     al  w0     0      ;
     rs  w0     100    ;
     jl. w3     a20.   ;
     al  w2     0      ;
     jl. w3     h7.    ;
b.   j1 w.             ;
                       ;
                       ;
                       ;
a20:                   ; venteprocedure
     rs. w3     j0.    ;
     al. w3     a6.    ;
     al. w1     a7.    ;
     jd         1<11+16;
     al. w1     a8.    ;
     jd         1<11+18;
     al. w2     a50.   ;
j1:  rl  w0  x2        ;
     jl. w3     h32.-2 ;
     1<23+32<12 +8     ;
     al  w2  x2+2      ;
     sh. w2     a50.+14;
     jl.        j1.    ;
     al  w2     10     ;
     jl. w3     h33.-2 ;
     jl.     (  j0.)   ;
j0:  0                 ;
e.                     ;
b.   j0 w.             ;
a24: am         1<1    ; start
a23: am         1<1    ; stop
a22: am         1<1    ; reset
a21: al  w0     a0     ; interrupt
     wa. w0     a5.    ;
     rs. w3     j0.    ;
     al  w3     8      ;
     do  w3  (  0)     ;
     jl. w3     a20.   ; goto vent
     jl.     (  j0.)   ;
j0:  0                 ;
e.                     ;


     c0=+1             ; c0>0 for test af ri-ordren
     a0=20<3           ;
a5:  1<23              ;
a6:  <:clock:>,0,0,0,0 ;
a7:  0,1,0,0,0,0       ;
a8:  0,r.10            ;
                       ;
a11:                   ;  start test
c.   -c0               ;
     al  w2     0      ;
     al  w3     20     ;
     al  w0     0      ;
     al  w1     19     ;
     ds  w3     1194   ;
     ds  w1     1190   ;
     ss  w1     1194   ;
     ds  w1     1186   ;
     rl. w1     -4     ;
     jl.        a12.   ;
m.   wait cpu1         ;
a12: ls  w1     -18    ;
     rs  w1     1198   ;
     rl  w1     1196   ;
     al  w1  x1+1      ;
     rs  w1     1196   ;
     gg  w3     66     ;
     jl.        a11.   ;
                       ;
                       ;
c27:                   ;
b.   h21,i12 w.        ;
z.                     ;
c.   c0                ;
     jl.        c26.   ;
c27:                   ;
     rl. w1     a50.   ;
     al  w1  x1+1      ;
     rs. w1     a50.   ;
     ri         16     ;


b.   h21,i12  w.       ;
c26: al. w3     h0.    ;#1   init cpu1
     gp  w3     26     ;#1   set inf register addr;
     rl  w3     8      ;#1   base of controller descr addr
     al. w1     c27.   ;#1
     rs  w1  x3+a0+0   ;#1    set start addr


     ri         16     ;#1    return interrupt;
     ;;
     ; testoutput
     ;  antal ri - i type - antal int - int level - di - tl - tl - tl
     ;
     ;  interrupt 16:  input finis
     ;            18:  input request
     ;            20:  output finis
     ;

     ;#1 system table: monitor mode
h.                     ;

     0                 ;
h0:                    ;
     0,r.6             ;
w.                     ;
     0                 ; -5  monitor call service addr
i0:  h6                ; -3  interrupt service addr
     1<23+0            ; -1  status  interrupt limit
i1:  h3                ; +1  register dump addr
     0                 ; +3  exception service addr
     0                 ; +5  escape service addr

                       ;#1 system table: user mode
i2:  h4                ; -5  monitor call service addr
i3:  h5                ; -3  interrupt       -      -
     1<23 + 6          ; -1  status < 12 + interrupt limit
i5:  h7                ; +1  register dump addr
     0                 ; +3  exception service addr
     0                 ; +5  escape service addr

                       ;#1  monitor register dump addr
h3:  0                 ;  w0
     0                 ;  w1
     0                 ;  w2
     0                 ;  w3
     1<23              ;  status       monitor mode
i4:  c27               ;  ic           start cpu1 process
     0                 ;  cause
     0                 ;  sb

     8                 ;  cpa
     0                 ;  base
     8                 ;  lower write limit
     8.3777 7777       ;  upper write limit
     0<12 + 6          ;  interrupt limits


                       ;#1 interrupt service cpu1
h4:  am         1      ;#1  monitor call service addr
h5:  am         1      ;#1  interrupt service addr (level 1)
h6:  al  w3     1      ;#1  interrupt service addr (level 2)
     rs. w3     a50.+2 ;
     rl. w1     a50.+4 ;
     al  w1  x1+1      ;
     rs. w1     a50.+4 ;
     sh  w2     14     ;
     jl.        c27.   ;
     rs. w2     a50.+6 ;
     al  w3     1      ;
     wa. w3     i10.   ;
     rs. w3     i10.   ;
     am         -14    ;
     rs. w2  x2+i10.   ;
     rl. w3     h8.    ;
     al  w3  x3+2      ;
     rs  w2  x3
     rs. w3     h8.
     jl.        c27.   ;
h7:  0                 ; w0
     0                 ; w1
     0                 ; w2
     0                 ; w3
     1<23              ; status
i6:  h8                ; ic
     0                 ; cause
     0                 ; sb
     8                 ; cpa
     0                 ; base
     8                 ;
     8.3777 7777       ; upper write limit
i9:  0<12+12           ;
h8:                    ;
    al. w3  h8.
    rs. w3  h8.
                       ;
jl. h21.
     al  w2     -1     ; start output section
     do. w2  (  a2.)   ; start HC8000
h9:  jl. w3     h20.   ; wait interrupt
     se  w2     18     ;
     jl.        h9.    ;
     di. w3  (  a2.)   ;
     rs. w3     a50.+8 ;
al  w3  1
ls  w3  22
al  w3  x1-1
sl  w3  0
jl. -4
     rl  w1     8      ;  w1:= base of controller table
     al  w3     4      ;
     al. w0     a49.   ;
     ds  w0  x1+a0+1<3+2; number of halfwords,addr
     do. w3  (  a2.)   ; send data transfer request
h10: jl. w3     h20.   ; wait interrupt
     sn  w2     0      ;
     jl.        h10.   ;
     sn  w2     18     ;
     jl.        h12.   ;
     se  w2     20     ;
     jl.        h10.   ;
     rs. w2     a10.   ;
     jl.        h10.   ;
h12: di. w3  (  a2.)   ;
     wa. w3     a50.+8 ;
     rs. w3     a50.+8 ;
     al  w2     0      ;
     rx. w2     a10.   ;
     se  w2     0      ;
     jl.        h21.   ;

h11: jl. w3     h20.   ; wait interrupt
     se  w2     20     ;
     jl.        h11.   ;
h21: rl  w1     8      ; w1:=controller table base
al w3 20;     rl. w3     a40.   ;
     al. w0     a45.   ;
     ds  w0  x1+a0+1<3+2;
     do. w3  (  a2.)   ; send data transfer request
h13: jl. w3     h20.   ; wait interrupt
     sn  w2     0      ;
     jl.        h13.   ;
     sn  w2     18     ;
     jl.        h16.   ;
     se  w2     20     ;
     jl.        h13.   ;
     rs. w2     a10.   ;
     jl.        h13.   ;
h16: di. w3  (  a2.)   ;
     wa. w3     a50.+8 ;
     rs. w3     a50.+8 ;
     al  w2     0      ;
     rx. w2     a10.   ;
     se  w2     0      ;
     jl.        h18.   ;

h19: jl. w3     h20.   ; wait interrupt
     se  w2     20     ;
     jl.        h19.   ;
h18: al  w2     -5     ;
     do. w2  (  a2.)   ;
h14: rl. w2     a50.+10;
     al  w2  x2+1      ;
     rs. w2     a50.+10;
     jl. w3     h20.   ; wait interupt
     sn  w2     0      ;
     jl.        h14.   ;
     rl. w0     a41.   ;
     wa. w0     a40.   ; addr for receiving mon copy
     rl. w3     a40.   ;
     rl  w1     8      ;
     ds  w0  x1+a0+2<3+2;
     di. w3  (  a9.)   ; input mon copy
h17: rl. w2     a50.+4 ;
     al  w2  x2+1      ;
     rs. w2     a50.+4 ;
     jl. w3     h20.   ; wait interrupt
     se  w2     16     ;
     jl.        h17.   ;
h15: jl. w3     h20.   ; wait interrupt
     se  w2     18     ;
     jl.        h15.   ;
     di. w3  (  a2.)   ;
     rs. w3     a50.+2 ;
     rl. w2     a50.+14;
     al  w2  x2+1      ;
     rs. w2     a50.+14;
     jl.        h15.   ;
                       ;
i10: 0,r.5             ;

     ;;
h20:                   ; wait interrupt
     rl. w2     i10.   ;
     sh  w2     0      ;
     jl.        h20.   ;
     al  w2  x2-1      ;
     rs. w2     i10.   ;
     al  w2     0      ;
     rx. w2     i10.+2 ;
     se  w2     0      ;
     jl      x3        ;
     rx. w2     i10.+4 ;
     se  w2     0      ;
     jl      x3        ;
     rx. w2     i10.+6 ;
     se  w2     0      ;
     jl      x3        ;
     jl.        h20.   ;
z.                     ;

a1:  0                 ;
a2:  1<23+21<3+2.001   ;
a3:  8000000           ;
a4:  0                 ;
a9:  1<23+22<3+ 2.001  ; 
a10:0
a14:                   ;  start init
     rs. w2     a4.    ; save return
     rs. w1     a14.   ;  save fp base
     rl  w3     8      ; base of controller tabel
     al  w3  x3+a0     ;
     rs. w3     a1.    ; addr of contr. table for cpu1
     al. w1     a11.   ;
     al  w0  x1        ;
     ds  w1  x3+2      ;
     ds  w1  x3+10     ;
     ds  w1  x3+18     ;
     ds  w1  x3+26     ;
     jd         1<11+28;
c.   c0                ;
     rl. w1     i0.    ;
     wa. w1     a14.   ;
     rs. w1     i0.    ;
     rl. w1     i1.    ;
     wa. w1     a14.   ;
     rs. w1     i1.    ;
     rl. w1     i2.    ;
     wa. w1     a14.   ;
     rs. w1     i2.    ;
     rl. w1     i3.    ;
     wa. w1     a14.   ;
     rs. w1     i3.    ;
     rl. w1     i4.    ;
     wa. w1     a14.   ;
     rs. w1     i4.    ;
     rl. w1     i5.    ;
     wa. w1     a14.   ;
     rs. w1     i5.    ;

     rl. w1     i6.    ;
     wa. w1     a14.   ;
     rs. w1     i6.    ;
                       ;
     rl. w1     a41.   ;
     wa. w1     a14.   ;
     rs. w1     a41.   ;
z.                     ;
b.   f10,g10 w.        ;
     al. w1     g0.    ;
     al. w3     g1.    ;
     jd         1<11+42; lookup(<:kkmon8004:>)
     se  w0     0      ; if not found then
     jl.        f5.    ; goto f5
     rl. w1     a41.   ; start of buf
     rl. w2     g0.    ; w:=monitor length
     ls  w2     9      ;
     wa. w2     a42.   ; +size of dummy area
     rs. w2     a40.   ;
     wa  w2     2      ;
     ds. w2     g4.    ; first and last addr
     al. w3     g1.    ;
     jd         1<11+52;
     jd         1<11+8 ; create and reserve(<:kkmon8004:>)
     se  w0     0      ; if error then
     jl.        f5.    ; goto f5
f1:  al. w3     g1.    ;
     al. w1     g2.    ;
     jd         1<11+16; input next share
     al. w1     g8.    ;
     jd         1<11+18;  wait for input finis
     se  w0     1      ; if error then
     jl.        f5.    ; goto f5
f3:  al. w3     g1.    ;
     jl.        f6.    ; goto remove process
f5:  al. w3     g1.    ;
     jd         1<11+4 ; if process exist then
     se  w0     0      ;
f6:  jd         1<11+64; remove process
     jl.        f7.    ; goto 
g0:  0,r.10            ; tail
g1:  <:cgaciatst:>,0,0 ;
g2:  3<12 + 0          ; input message
g3:  0                 ; first addr
g4:  0                 ; last addr
g5:  0,r.5             ; segment
g6:  0                 ; number of shares
g7:  1<23              ; message
g8:  0,r.8             ;
g9:  0                 ; share length
f7:                    ;
e.                     ;
     jl.     (  a4.)   ; return
a40: 0                 ;
a49: 1,1               ;
 1<23+22<3+2.001   ;
a46: 8000000           ;
a42: a48.              ;
     rl. w2     a46.   ;
     rs  w2     248    ;
     rs  w2     274    ;
     al  w3     18     ;
     rs  w3     108    ;
     al. w3     a43.   ;
     al  w2     -40    ;
     do. w2  (  a45.)  ;
     jl.        0      ;
     di. w0  (  a45.)  ;
     jl.        a43.   ;
a41: a48               ;
a43:                   ;

     jl.        a47.   ;
a45:
   -1
   -2
   -3
gg 66
al w2 1
rl w3  2
ls w3 16
gp w3 64
al  w2  x2+2
jl.-8
jl.-2
a48:
a47: 0,r.100           ;
e.                     ;
e.                     ;
e.                     ;
▶EOF◀