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└─⟦00964e8f7⟧ Bits:30007478 RC8000 Dump tape fra HCØ.
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└─⟦this⟧ »tcgorder032«
;*page: XXXX micasm03
*load: m2903
; ----------------------------
; skipped is code 'finalx'
; skipped is code 'rhtest'
; 810810/1710:
; auto load interupt removed.
; skipped by code 'autoin'
; 810810/1700:
; fetch 8000 instr: from register repaired.
; 810810/1730:
; clearing of last bit in ic removed from jl
; HC8000 instr: and inserted in noprefetch module
; now ic can never be negative.
; also corrected in rh2901.
; 810817/2000:
; gg 99 introduced, get interupt level
; from amd9511 interupt controler.
; 810817/2000:
; gg with address >= 200 defined as
; user programmed instructions. (i.e
; instrcution which can be used from a
; user program and gives a result which
; is defines by a user.
; 810817/2000:
; gg 200 = reverse bits in register selected.
;NEXT.
; ------------------------------------------------------------
; WHAT SCHOULD BE DONE:
; 001: if you define that yuo never double store
; overlabing registers and memory(8)
; or double load some check could be removed.
; 002: if you define that registers that contain
; HC8000 instr:s, never continue in memory(8)
; some check in module regins can be removed.
; 003: if you define that the word which is stored
; by a store 8000 instr: never is used by
; as the absolute next 8000 instr:, then
; some check can be removed in the store module.
; 004: the increment of the instruction counter could be
; much earlyer in most instrcution. fx. in the
; same moment you call get op, if you insure that
; the increment is removed from exeption.
; NEXT WHAT.
; --------------------------------------------------------------
; -------------------------------------------------------------
; micro 8000 instr: description.
;
; only one format.
; mir(0) is msb.
; mir(47) is lsb.
;
; mir(0) = -, cc ccenable.
; mir(1:4) = amd2910 micro program sequencer 8000 instr:.
; mir(5) = -,( ce my)
; mir(6) = -,( ce M)
; mir(7:10) = amd2904 condition select.
; mir(11:20) = amd2903 bitslice 8000 instr:.
; mir(14) is intruction bit 5 for msh.
; mir(15) is 8000 instr: bit 5 for lsh.
; mir(21:22) = amd2904 carry control.
; mir(23) = -,(amd2904 enable)
; mir(24) = -,(ea)
; mir(25) = hc8000 working register select.
; mir(26) = -,(Oeb)
; mir(27) = -,(write hc2901)
; mir(28:31) = source register address ( a address to amd2903).
; mir(32:35) = disitnation register address.
; mir(26:27) = jump address, imidiate operand.
*const: e01inp,23 ; entry get intr. with no prefetc
*const: e01ip,24 ; entry in hc2901 instr. with prefetch.
; - -- - -
*const: e01gmw,25 ; entry in hc2901 get memory word.
*const: e01pmw,26 ; entry in hc2901 put memory word.
*const: e01gdw,27 ; entry in hc2901 get double memory word.
*const: e01pdw,28 ; entry in hc2901 put double memory word.
*const: e01rtc,29 ; gg(100) , generel get real time clock.
*const: e01rtr,30 ; generel get test register ( 64)
*const: e01wtr,31 ; generel put testregister ( 64)
*const: e01rtw,32 ; generel get test register with wait
; (66).
*const: e01dom,13 ; data out memory word.
*const: e01dob,5 ; data out function jump table.
*const: e01dim,22 ; data in memory word.
*const: e01dib,14 ; data in function jumb table.
*const: e01drd,33 ; dynamic registers dump
*const: e01drr,36 ; dynamic registers restore.
*const: e01rin,37 ; return from interupt.
*const: e01aci,38 ; get and clear interupt or exeption.
*const: e01ini,0 ; initialize.
*const: e01sdl,35 ; set interupt disable level.
*const: e01sel,34 ; set interupt enable level.
*const: e01is1,39 ; interupt service entry 1.
*const: e01skn,40 ; entry skip next instr and fetch.
*const: e01cil,41 ; gg (94) get interupt level from
; amd9511 charakter interupt level
; controler.
*const: montop,256 ; the higest monitor operation is set to
*const: autoin,6 ; cause no of auto load. (interupt 3
*const: disbit,8 ; position of diable bit in
; the status register bit(20).
; system table error).
; a fixed valus of 512.
*origo: 0
jmp(init) ; goto init.
*notin: rhtest
; entries for mapping proms.
; --------------------------
jmp(ielax3) ;indirect relative and x3
jmp(ielax2) ; -do.- and x2.
jmp(ielax1) ; - do. - and x1.
jmp(ielati) ; - do. - no index reg.
jmp(relax3) ; relative and index reg 3.
jmp(relax2) ; - do. - 2
jmp(relax1) ; - do. - 1
jmp(relati) ; - do. - no index register.
jmp(inlyx3) ; indirect and index reg 3.
jmp(inlyx2) ; - do. - 2.
jmp(inlyx1) ; - do. - 1.
jmp(iomodi) ; - do. - no index reg.
jmp(onlyx3) ; direct addressing and index reg 3.
jmp(onlyx2) ; - do. - 2.
jmp(onlyx1) ; - do. - 1.
jmp(nomodi) ;
jmp(prgexp) ; HC8000 instr: 63. xx unass.
jmp(prgexp) ; HC8000 instr: 62. unassigned.
jmp(prgexp) ; HC8000 instr: 61. unassigned..
jmp(prgexp) ; HC8000 instr: 60. unassigned.
jmp(prgexp) ; HC8000 instr: 59. unassigned
jmp(prgexp) ; HC8000 instr: 58. unassigned.
jmp(ss) ; HC8000 instr: 57.
jmp(aa) ; HC8000 instr: 56.
jmp(ds) ; HC8000 instr: 55.
jmp(dl) ; HC8000 instr: 54.
jmp(prgexp) ; HC8000 instr: 53. cf.
jmp(prgexp) ; HC8000 instr: 52. fd.
jmp(prgexp) ; HC8000 instr: 51. unas.
jmp(prgexp) ; HC8000 instr: 50. fm.
jmp(prgexp) ; HC8000 instr: 49. prgexp.
jmp(prgexp) ; HC8000 instr: 48. fa.
jmp(gp) ; HC8000 instr: 47. unas.
jmp(sx) ; HC8000 instr: 46.
jmp(sz) ; HC8000 instr: 45.
jmp(so) ; HC8000 instr: 44.
jmp(sn) ; HC8000 instr: 43.
jmp(se) ; HC8000 instr: 42.
jmp(sl) ; HC8000 instr: 41.
jmp(sh) ; HC8000 instr: 40.
jmp(ld) ; HC8000 instr: 39.
jmp(ls) ; HC8000 instr: 38.
jmp(ad) ; HC8000 instr: 37.
jmp(as) ; HC8000 instr: 36.
jmp(nd) ; HC8000 instr: 35.
jmp(ns) ; HC8000 instr: 34.
jmp(ac) ; HC8000 instr: 33.
jmp(prgexp) ; HC8000 instr: 32. ci.
jmp(prgexp) ; HC8000 instr: 31. unas.
jmp(prgexp) ; HC8000 instr: 30. unas.
jmp(di) ; HC8000 instr: 29.
jmp(gg) ; HC8000 instr: 28.
jmp(xs) ; HC8000 instr: 27.
jmp(hs) ; HC8000 instr: 26.
jmp(rx) ; HC8000 instr: 25.
jmp(wd) ; HC8000 instr: 24.
jmp(rs) ; HC8000 instr: 23.
jmp(re) ; HC8000 instr: 22.
jmp(sp) ; HC8000 instr: 21.
jmp(rl) ; HC8000 instr: 20.
jmp(bz) ; HC8000 instr: 19. zl.
jmp(ba) ; HC8000 instr: 18. ea.
jmp(bs) ; HC8000 instr: 17. ea.
jmp(xl) ; HC8000 instr: 16.
jmp(je) ; HC8000 instr: 15.
jmp(jd) ; HC8000 instr: 14.
jmp(jl) ; HC8000 instr: 13.
jmp(ri) ; HC8000 instr: 12.
jmp(al) ; HC8000 instr: 11.
jmp(wm) ; HC8000 instr: 10.
jmp(am) ; HC8000 instr: 9.
jmp(ws) ; HC8000 instr: 8.
jmp(wa) ; HC8000 instr: 7.
jmp(lx) ; HC8000 instr: 6.
jmp(lo) ; HC8000 instr: 5.
jmp(la) ; HC8000 instr: 4.
jmp(hl) ; HC8000 instr: 3.
jmp(bl) ; HC8000 instr: 2. el.
jmp(do) ; HC8000 instr: 1.
jmp(prgexp) ; HC8000 instr: 00. unas.
; entry from vector prom with external interupt.
jmp(extint) ; goto external interupt.
*until: rhtest
; address calculations.
; =====================
nomodi/"0:jmap ; no modifiers
relati/"8:jmap add(addrs,ic); relative
relax1/"9:jmp(relati) add(addrs,x1); reletive and x1
relax2/"10:jmp(relati) add(addrs,x2); relative and x2
relax3/"11:jmp(relati) add(addrs,x3); relative and x3
onlyx1/"1:jmap add(addrs,x1); only x1
onlyx2/"2:jmap add(addrs,x2); only x2
onlyx3/"3:jmap add(addrs,x3); only x3
iomodi/"4:jsb(getop) ; only indirect
jmap mover(addrs,wrk0);
inlyx1/"5:jsb(getop) add(addrs,x1); indirect and x1.
jmap mover(addrs,wrk0);
inlyx2/"6:jsb(getop) add(addrs,x2); indirect and x2.
jmap mover(addrs,wrk0);
inlyx3/"7:jsb(getop) add(addrs,x3); indirect and x3.
jmap mover(addrs,wrk0);
ielati/"12:jsb(getop) add(addrs,ic); indirect and relative
jmap mover(addrs,wrk0);
ielax1/"13:jmp(ielati) add(addrs,x1); indirect and relative and x1
ielax2/"14:jmp(ielati) add(addrs,x2); indirect and relative and x2
ielax3/"15:jmp(ielati) add(addrs,x3); indirect and relative and x3
▶01◀
; new initialize.
; ---------------
init: mzero(base) nothm csmy shinz; base := 0, reset half word
; move logic, set normal condition
; select logic, set shift in
; zero.
invr(cpa,base) srgt ; cpa := max integer.
invr(status,cpa) ; status(1:23) := 0,
; status(0) := 1 ( monitor mode).
mover(uplim,cpa) ; uppper limit := max integer
; schould be memory sixe.
mover(lowlim,8) ; lower limit := 8.
cjvec(neg) ; if lowerlimit is negative then
; jump vector prom, (this is not
; the case because 8 is put into
; lower limit, so next micro
; HC8000 instr: is allways performed
; next but it cause the interupt
; bit to be cleared).
invr(hc2901,'e01ini) ; clock hc2901 in no address.
init1: cjmp(re2901,init1) invs(ic,hc2901); wait for hc2901 ready,
; ic := hc2901.
jmp(nopfic) ; goto nopfic ( fetch instr with
; no prefetch.
; entry get 8000 instr: with no prefetch
; ---------------------------------------
nopfne: inctwo(ic) ; ic:=ic+2.
nopfic: andinv(ic,1) ; clear possible last bit
; in 8000 instr: pointer.
sub(ic,8) noload ; if ic < 8 then
cjmp(less,regins) mzero(addrs); goto regins, addrs := 0.
npref2: invr(hc2901,'e01inp) ;
jsb(chlicp) mover(wrk0,ic); wrk0 := ic, call subroutine
; check limit and cpa.
fetch1: cjmp(re2901,fetch1) clre01; wait until hc2901 is ready.
jmp(fetch2) invs(hc2901,wrk0); send address of next instr to
; the hc2901, goto fetch2.
; entry skip next 8000 instr: and fetch.
; --------------------------------------
sknini: inctwo(ic) ; ic := ic + 2. ( not used).
sknins: sub(ic,10) noload ; if ic < 10 then
cjmp(less,regins) mzero(addrs); goto regins, addrs := 0.
invr(hc2901,'e01skn) ; clock hc2901 in skip next.
jmp(fetch2) ; continue in wait instrcution.
; entry fetch 8000 instr: with prefetch
; --------------------------------------
pfneic: inctwo(ic) ; ic := ic + 2.
pficin: sub(ic,10) noload ; if ic < 10 then
cjmp(less,regins) mzero(addrs); goto regins, addrs := 0.
; if the previous 8000 instr: was
; taken from w3, then the prefetch
; function wil not work, so the next
; is taken without prefetch,
; this check is ofcource not performed
; in the getting of w3 because
; the 8000 instr: in w3 could be a
; jump to an 8000 instr: in w0.
; hold condition from previous
; HC8000 instr: to next.
ftcam: invr(hc2901,'e01ip) ; clock hc2901 in entry get
; instrcution with no prefetch.
; also entry from 'am' anstruction.
fetch2: mover(wrk2,3) ; init wrk2 with 3.
fetch3: cjmp(re2901,fetch3) invs(wrk0,hc2901) signex
mover(q,wrk0) clre01
jvec add(addrs,addrs,q) clre01 nothm shinz csmy; addrs := addrs + q, clock the hc2901
; read bit,
; get instr from register.
; if previous 8000 instr: was taken from w3,
; then will the prefetch not work so
; the next is taken witout prefetch,
; this check is of course not performed in
; the getting of w3 bacause the 8000 instr: in w3 could be
; a jump to 8000 instr: in w0 ( e.x dummy lowrk0 the monitor).
; registers is numbered:
; w0 = 0
; w1 = 2
; w2 = 4
; w3 = 6
; negative value = program exeption.
; 8 = get next from memory with no prefetch.
regins: sub(ic,4) noload ; if ic < 4 then
cjmp(less,insw01) holdmy; goto get w0 or w1 or negative
; address, hold condition.
cjmp(equal,regin1) mover(wrk0,w2); if ic =4 then wrk0:=w2,
; goto regin1.
sub(ic,6) noload ; if ic = 8 then
cjmp(equal,regin1) mover(wrk0,w3); wrk0 := w3, goto regin1.
; else
jmp(npref2) ; goto noprefetch (location 8).
insw01: sub(ic,0) noload ; if ic > 0 then
cjmp(great,regin1) mover(wrk0,w1) holdmy;wrk0 := w1 ,
; hold condition , goto regins.
*test: biton
insw0m: cjmp(notneg,regin1) mover(wrk0,w0); else wrk0 := w0, goto regin1.
jmp(prgex0) mzero(cause); else goto program exeption, causec:=.0.
regin1: mover(wrk1,wrk0) signex; wrk1 := signextend ( 8000 instr:)
; ( address field of 8000 instr:).
add(addrs,wrk1) ; addrs := addrs + wrk1.
*test: biton
invs(q,wrk0) ; send 8000 instr: through amd2903's
; r bus, and there by out on the the
; bidirectional db-bus, this will send
; the 8000 instr: out to address the
; vector 8000 instr: prom and the
; map address modifier prom.
jvec invs(q,wrk0) ; jump vector, repeat addressing
; of vector prom and map prom.
*test: bitoff
; interupt, exeption and escape control section.
; ----------------------------------------------
; subroutine perform limit check with wrk0 register
; -------------------------------------------------
; and return wrk0 register with added base if limit
; is not violated else if wrk0 < cpa then just wrk0,
; last instr subtract 8 from wrk0 with noload.
; ----------------------------------------------
chlicp: add(wrk0,base) ; wrk0 := wrk0 + base,
; ( wrk0 contains address to be
; be investigated)
chlic1: sub(wrk0,uplim) noload; if wrk0 >= upper limit then
cjmp(greq,prgex2) sub(wrk0,lowlim) noload; goto program exeption, with 2
; wait for hc2901.
crtn(greq) ; if q >= lower limit then return
; where wrk0 = wrk0+base.
sub(addrs,cpa) noload ; if addrs < cpa then
crtn(less) mover(wrk0,addrs)▶16◀▶16◀; return and wrk0 := addrs with no
; base.
jmp(prgex2) ; else goto program exeption, with 2
; wait for hc2901.
; subroutine dump dynamic registers.
; ----------------------------------
dudyre:
invr(hc2901,'e01drd) ; call function dynamic register dump in
; hc2901.
dudyr1: cjmp(re2901,dudyr1) clre01; wait for hc2901 ready.
invs(hc2901,wrk1) ; sen regdump addrs to hc2901.
dudyr2: cjmp(re2901,dudyr2) clre01; wait for hc2901 ready.
dudyen: invs(hc2901,w0) ; send w0 to reg dump.
dudyr3: cjmp(re2901,dudyr3) clre01; wait for hc2901 ready.
invs(hc2901,w1) ; send w1 to reg dump.
dudyr4: cjmp(re2901,dudyr4) clre01; wait for hc2901 ready.
invs(hc2901,w2) ; send w2 to reg dump.
dudyr5: cjmp(re2901,dudyr5) clre01; wait for hc2901 ready.
invs(hc2901,w3) ; send w3 to reg dump.
dudyr6: cjmp(re2901,dudyr6) clre01; wait for hc2901 ready.
invs(hc2901,status) ; send status to reg dum.
dudyr7: cjmp(re2901,dudyr7) clre01; wait for hc2901 ready.
invs(hc2901,ic) ; sen ic to reg dump.
dudyr8: cjmp(re2901,dudyr8) clre01; wait for hc2901 ready.
invs(hc2901,cause) ; send cause to reg dump.
dudyr9: cjmp(re2901,dudyr9) clre01; wait for hc2901 ready.
invs(hc2901,addrs) ; send addrs to reg dump.
dudy10: cjmp(re2901,dudy10) clre01; wait for hc2901 ready.
rtn add(wrk1,16) ; return from subroutine,
; wrk1 := wrk1 + 16,
; ( wrk1 = reg. dump address).
; subroutine reestablish dynamic registers.
; -----------------------------------------
redyre:
invr(hc2901,'e01drr) ; call function dunamic register reestablish
; in hc2901.
redyaw: cjmp(re2901,redyaw) clre01; wait for hc2901 ready to accept address
; of dump block.
invs(hc2901,wrk0) ; send reg dump addrs to hc2901.
redyen: ; entry dum dynamic registers.
redyr1: cjmp(re2901,redyr1) clre01 invs(w0,hc2901); wait for hc2901 ready,
; reestablish w0.
cont clwr01 ; clock ready to hc2901.
redyr2: cjmp(re2901,redyr2) clre01 invs(w1,hc2901); wait for hc2901,
; reestablish w1.
cont clwr01 ; cont clock write ready to hc2901.
redyr3: cjmp(re2901,redyr3) clre01 invs(w2,hc2901); wair for hc2901 ready,
; reestablish w2.
cont clwr01 ; cont clock write ready to hc2901.
redyr4: cjmp(re2901,redyr4) clre01 invs(w3,hc2901); wait for hc2901 ready,
; reestablish w3.
cont clwr01 ; cont clock write ready to hc2901.
redyr5: cjmp(re2901,redyr5) clre01 invs(status,hc2901); wait for hc2901 ready,
; reestablish status.
cont clwr01 ; cont clock write ready to hc2901.
redyr6: cjmp(re2901,redyr6) clre01 invs(ic,hc2901); wait for hc2901 ready,
; reestablish ic.
cont clwr01 ; cont clock write ready to hc2901.
redyr7: cjmp(re2901,redyr7) clre01 invs(cause,hc2901); wait for hc2901 ready,
; reestablish cause.
cont clwr01 ; cont clock write ready to hc2901.
redyr8: cjmp(re2901,redyr8) clre01 invs(addrs,hc2901); wait for hc2901 ready,
; reestablish hc2901.
rtn ; return from subroutine
;
; exeption
; ---------
; program exeption.
; -----------------
; ( se also entry prgex1 prgex2 prgex3).
prgexp/:jmp(expt) mzero(cause); goto exeption service, cause := 0.
; integer exeption.
; -----------------
intexp/:mover(cause,2) ; cause := 2.
jmp(expt) ; goto exeption service.
; floating point exeption.
; ------------------------
flpexp/:mover(cause,4) ; cause := 4.
jmp(expt) ; goto exeption service.
; program exeption whwn double load is clocked.
prgex3: cjmp(re2901,prgex2) clre01; wait for hc2901 is ready.
cont clwr01 invr(hc2901,8); clear write ready to hc2901.
; entry for program exeption
; when read memory word is clocked.
prgex2: cjmp(re2901,prgex2) clre01; wait for hc2901 is ready.
cont clwr01 invr(hc2901,8); clear write ready to hc2901.
prgex1: cjmp(re2901,prgex1) mzero(cause) clre01; wait for hc201 is ready.
; exeption.
; ---------
prgex0: ; entry when cause is zero.
expt/: invr(hc2901,'e01gmw) ; call get word from memory with
; no limit check in hc2901.
inctwo(ic) ; ic := ic + 2.
*onlyin:finalx
mover(q,status) ; save status
mover(wrk0,'naameq) ; wrk0 := 0 or (14..15) ( after am and
; after escape in status shift 12).
mover(wrk1,-1) ; set all bit in wrk1.
mover(wrk1,wrk0) hmrl ; wrk1 := all bitaddrsut (2..3).
and(q,wrk1) nothm csmy shinz; saved status(2..3) := 0.
*until: finalx
add(inf,4) ; inf := inf + 4.
expt1: cjmp(re2901,expt1) clre01; wait for hc2901 is ready.
invs(hc2901,inf) ; send address of reg. dump to hc2901.
sub(inf,4) ; inf := inf - 4.
expt2: cjmp(re2901,expt2) clre01 invs(wrk1,hc2901); get reg dump addrs to wrk1.
; wrk1 := register dum address.
cjmp(zero,intser) ; if regdump address = 0 then goto
; interupt service.
; entry for dump registers from escape routine
; after control of register dump address <> 0.
; wrk1 = register dump address <> 0.
extp3:
dmpreg:
add(wrk1,base) ; reg dump addrs := reg dump addrs + base.
sub(wrk1,lowlim) noload; if reg dump addrs + base <
; lower limit then
cjmp(less,stbe1) ; then goto syetm table error.
add(wrk1,14) ; reg dump addrs := reg dump addrs + 14.
sub(wrk1,uplim) noload; if reg dump addrs >= upper limit then
cjmp(greq,stbe1) ; goto system table error.
sub(wrk1,14) ; reg dump addrs := reg dump addrs - 14.
jsb(dudyre) ; call sub routine to dump dynamic registers.
mover(w0,ic) ; w0 := old ic.
; w1 is not initialized acording to
; the the rc8000 family refference
; manual.
mover(w2,addrs) ; w2 := addrs.
and(cause,63) ; cause := cause(18..23).
mover(ic,wrk1) ; new ic := reg dump addrs + 16,
; ( reg. dump. address is increased
; with 16 in subroutine dump dynamic
; registers).
jmp(nopfic) mover(w3,cause); w3 := cause, goto next 8000 instr:
; with no prefetch.
stbe1: ; system table error from exeption.
mover(cause,6) ; cause := 6.
sub(wrk1,base) ; reg dump addr := reg dump addr - base.
jmp(intser) mover(addrs,wrk1); addrs := reg dump addrs ,
; goto interupt service.
; external interupt.
; ------------------
; this address is reached after an 'jvec' micro 8000 instr:
; in the fetch next 8000 instr: section and the interupt is
; set from the hc2901.
extint/:invr(hc2901,'e01aci) ; clock hc2901 in address answer
; and clear interupt.
; the answer is given as an exact interupt
; interupt no.
mzero(base) ; base := 0.
extin1: cjmp(re2901,extin1) clre01 invs(cause,hc2901); wait for hc2901 to be
; to be ready , cause := interupt no * 2.
jmp(intse3) mover(cause,cause) slft; cause := cause * 2, continue
; interupt service entry 3.
intser/: ; common interupt service routine.
; --------------------------------
invr(hc2901,'e01is1) ; call function in hc2901 for starting
; interupt service 1.
intse1: mzero(base) ; base := 0, (disabling memory
; relocation).
intse2: cjmp(re2901,intse2) clre01; wait for hc2901 ready.
intse3: invs(hc2901,inf) ; send information register to hc2901.
mover(lowlim,8) ; lower limit := 8.
invr(uplim,base) srgt ; lower limit := max integer ( schould be
; size of memory).
; this diables the limit check.
intse4: cjmp(re2901,intse4) clre01 invs(wrk2,hc2901); wait for hc2901 ready,
; get system table status and interupt
; initialization.
mover(lowlim,8) clwr01; lower limit := const(8).
; clear write ready to hc2901.
intse6: cjmp(re2901,intse6) clre01 invs(wrk1,hc2901); wait for hc2901 ready,
; get system table reg dump addrs.
jsb(dudyen) ; call subroutine dump dynamic
; registers, in entry 1 with
; no init clock of hc2901.
mover(w1,wrk1) clwr01; sync of hc2901 with a clear of the
; sync bit to hc2901,
; w1 := reg dump address + 16,
; ( reg. dump address is increassed
; by 16 in subroutine dump dynamic
; registers).
ints19: cjmp(re2901,ints19) clre01 invs(ic,hc2901); wait for hc2901 ready,
; get new ic address from system table.
mover(status,wrk2) ; status := system table status initialistion
andinv(status,4095) ; status := system table status and
; intlim initialiation (0..11).
sub(inf,12) ; inf := inf - 12.
or(inf,1) ; inf(23) := 1.
jmp(nopfic) mover(w2,cause); w2 := cause, goto fetch next
; HC8000 instr: with no prefetch.
*skip: autoin
sub(cause,'autoin) noload; if interupt cause = auto load
; interupt then goto
cjmp(nequal,nopfic) mover(w2,cause); w2 := cause,
; fetch 8000 instr: with no
; prefetch else
invr(hc2901,'e01ini) ; clock hc2901 in init address.
jmp(init) ; goto init.
*until: autoin
; carry and owerflow control section.
; -----------------------------------
ccowc: cjmp(over,ccowc1) holdmy; if overflow then goto ccowc1,
; hold control.
cjmp(ncarry,pfneic) ; if not carry then goto nexin.
or(ex,1) ; ex(carry) := 1.
jmp(pfneic) ; ex(carry) := 1, goto pfneic.
ccowc1: or(ex,2) holdmy ; ex(overflow) := 1, hold condition
; control.
cjmp(ncarry,ccowc2) ; ex(overflow) := 1, if not carry
; then goto ccowc2.
or(ex,1) ; ex(carry) := 1.
ccowc2: and(status,16) noload ; if status(integer mask) = 0 then
cjmp(zero,pfneic) ; goto pfneic.
jmp(intexp) ; goto integer exeption.
; subroutine get operand
; -----------------------
; call: address of operand in reg. 'addrs'.
; return: operand in reg. 'wrk0'.
; destroyed: none.
; condition select is expected to b 'csmy'
getop: sub(addrs,8) noload ;
cjmp(less,regget) mover(wrk0,addrs); wrk0 := addrs.
getop1: invr(hc2901,'e01gmw) ; call function in hc2901 get operand
; get opreand without limit control.
jsb(chlic1) add(wrk0,base); wrk0:= wrk0 + base , call subroutine
; to perform limit check and cpa
; limit check.
getop2: andinv(wrk0,1) ; remove possible last bit in address.
getop4: cjmp(re2901,getop4) clre01; wait for hc2901 to accept address.
invs(hc2901,wrk0) ;send daddress to hc2901, and clock
; write bit.
getop3: cjmp(re2901,getop3) invs(wrk0,hc2901); wait for hc2901 to sned data,
; inver data into wrk0 from hc2901
; buffer register.
rtn mover(wrk0,wrk0) shinz nothm csmy; return from subroutine,
; prepere for negative or zero test
; data.
; subroutine load from internal reg.
; ----------------------------------
regget: cjmp(neg,prgexp) mover(wrk0,wrk0) srgt; if addres if negative then goto
; program exeption, shift wrk0 rigth 1,
; so wrk0 points to exact register no.
regge1: add(wrk0,'regge2) ; microsekvens counter := address
ldctre(wrk0) ; shift -1 + mic. instr addres
; regge1.
cjmrd(neg,prgexp) ; jump in micro. program to
; to address indexd by regge1 +
; addrs // 2.
regge2: rtn mover(wrk0,w0) ; wrk0 := w0.
rtn mover(wrk0,w1) ; wrk0 := w1.
rtn mover(wrk0,w2) ; wrk0 := w2.
rtn mover(wrk0,w3) ; wrk0 := w3.
; subroutine get double word from memory with
; write protection check.
; -------------------------------------------
getdo1: sub(addrs,8) noload ; if addrs < 8 then
cjmp(less,regget) mover(wrk0,addrs); wrk0 := address, goto regget.
getdo3: invr(hc2901,'e01gdw) ; send entry to hc2901.
add(wrk0,base) ; wrk0 := addrs + base.
sub(wrk0,uplim) noload; if wrk0 >= upper limit then
cjmp(greq,prgex3) sub(wrk0,lowlim) noload; goto program exeption
; with 3 wait for hc2901.
cjmp(greq,getop2) sub(addrs,cpa) noload; if wrk0 >= lower limit
; then goto getop2.
cjmp(less,getop2) mover(wrk0,addrs); if addrs < cpa then goto getop2.
jmp(prgex3) ; else goto program exeption
; with 3 wait for hc2901.
; second entry in get double word from memory
; with protection check.
; -------------------------------------------
getdo2: mover(wrk1,addrs) ; wrk1 := addrs.
andinv(wrk1,1) ; wrk1.lsb := 0.
; (remove possible uneven address.)
sub(wrk1,2) ; wrk1 := wrk1 - 2.
cjmp(neg,getdo4) mover(wrk0,w3); if new address < 0 then
; data word in register w3)
; goto getdo4,
sub(wrk1,6) noload ; if address < 6 then
cjmp(less,regge1) mover(wrk0,wrk1) srgt holdmy; wrk0 := address shift -1,
; hold condition, goto regge1.
cjmp(great,getop3) clwr01; if address > 6 then
; clock write hc2901 and goto
; wait for last operand in
; getop3.
; else
jmp(regge1) ; if address = 6 then
; (previus was memory(8))
; goto regget ( clock of
; write ready was done in
; just previus micro insteuction.
getdo4: rtn mover(addrs,6) ; addrs := 6 , and return from
; subroutine.
; subroutine putoperand.
; ----------------------
; call: address in reg. 'addrs'
; operand in reg. 'q'.
; destroyed: wrk0.
putop: sub(addrs,8) noload ; if addrs < 8 then
cjmp(less,regput) mover(wrk0,addrs); then goto put register.
add(wrk0,base) ; wrk0 := addr+ base.
sub(wrk0,uplim) noload; if wrk0 >= uppper limit then
cjmp(greq,prgexp) sub(wrk0,lowlim) noload; goto program exeption
; else if wrk0 < lower limit then
cjmp(less,prgexp) ; then goto program exeption.
invr(hc2901,'e01pmw) ; call function put operand
; protected.
andinv(wrk0,1) ; remove possible uneven address
; bit in address.
putop1: cjmp(re2901,putop1) clre01;
invs(hc2901,wrk0) ; send fysical address to hc2901.
putop2: cjmp(re2901,putop2) clre01;
invs(hc2901,q) ; send data word to hc2901.
putop3: cjmp(re2901,putop3) clre01; wait for hc2901 ready.
inctwo(ic) ; ic := ic + 2 ( next 8000 instr:).
sub(ic,wrk0) noload ; if next ic <> from just used physical
cjmp(nzero,pficin) ; then goto prefetch next instr else
jmp(nopfic) ; goto get 8000 instr: with no prefetch.
regput: cjmp(neg,intexp) mover(wrk0,wrk0) srgt; if the effective address is
; negative then goto intexp,
; shift wrk1 1 rigth so wrk1
; contains absolute register no.
add(wrk0,'regpu0) ;
ldctre(wrk0)
cjmrd(neg,intexp) ;
regpu0: jmp(pfneic) moves(w0, q)
regpu1: jmp(pfneic) moves(w1,q)
regpu2: jmp(pfneic) moves(w2,q)
regpu3: jmp(pfneic) moves(w3,q)
;*page: XXX
; address handling
; ----------------
; HC8000 instr: next address, modify: 'am', numeric code 9.
; ------------------------------------------------------
am/'9: sub(ic,8) noload ; if ic >= 10 (i.e ic + 2) then
cjmp(greq,ftcam) inctwo(ic); goto fetch 8000 instr: after
; address modify (entry in
; prefetch 8000 instr:),
; ic := ic + 2.
jmp(regins) ; else goto regins ( 8000 instr: in
; register or location 8).
; HC8000 instr: address, load: 'al', numeric code 11.
; --------------------------------------------------
al/'11: jmp(pfneic) mover(wreg,addrs); w_reg(index) := addrs,
; goto pfneic
; HC8000 instr: address complemented, load: 'ac', numeric code 33.
; --------------------------------------------------------------
ac/'33: andinv(ex,3) ; ex(carry) := ex(overflow) := 0.
jmp(ccowc) invr1(wreg,addrs); w_reg(index) := not(addrs)+1,
; goto ccowc.
;*page: XXX
; register transfer.
; ------------------
; HC8000 instr: half register, load: 'hl', numreic code 3.
; -------------------------------------------------------
hl/'3: jsb(getop) ; wrk0 := core(addrs),
and(addrs,1) noload ; if addrs(23) = 0 ( addrs even) then
cjmp(zero,hl1) ; goto hl1,
mover(wrk0,wrk0) hmrl ; wrk0(0:11) := wrk0(12:23)
hl1: mover(wreg,wrk0) hmlr ; w_reg(index,12:23) := wrk0(0:11),
cont nothm csmy ; reset half word move logic
jmp(pficin) inctwo(ic) ; goto pfneic, ic := ic +2.
; HC8000 instr: half register, store: 'hs', numeric code 26.
; --------------------------------------------------------
hs/'26: jsb(getop) moves(q,wreg); wrk0( := core(addrs), q := w_reg(index)
hsnoen: and(addrs,1) noload ; normalisze single and double entry:
; if addrs(23) = 0 ( addrs even) then
cjmp(zero,hs1) moves(wrk1,q); goto hs1, wrk1 := q,
mover(wrk1,wrk1) hmrl ; wrk1(12:23) := wrk1(0:11),
mover(wrk0,wrk1) hmlr ; wrk0(12:23) := wrk1(0:11).
mover(q,wrk0) nothm csmy shinz; q:=wrk0, reset half word move
; logic.
jmp(putop) ; goto putop.
hs1: mover(wrk0,wrk1) hmrl ; wrk0(0:11):= wrk1(12:23)
mover(q,wrk0) nothm csmy shinz; q:=wrk0, reset half word
; move logic.
jmp(putop) ; goto putop.
; HC8000 instr: register, load: 'rl', numeric code 20.
; ---------------------------------------------------
rl/'20: jsb(getop) ; wrk0 := core(addrs)
jmp(pfneic) mover(wreg,wrk0); w_reg(index) := wrk0, goto pfneic
; HC8000 instr: register, store: 'rs', numeric code 23.
; ---------------------------------------------------
rs/'23: jmp(putop) moves(q,wreg);q := w_reg(index), goto putop.
; HC8000 instr: register and memory word, exchange: 'rx', numeric code 25.
; ----------------------------------------------------------------------
rx/'25: jsb(getop) moves(q,wreg); q := w_reg(index) call subroutine get operand from memory
jmp(putop) mover(wreg,wrk0); w_reg(index) := wrk0,
; goto putop, (addrs(core) := q)
; HC8000 instr: double register, load: 'dl', numeric code 54.
; ---------------------------------------------------------
dl/'54: jsb(getdo1) ;
jsb(getdo2) mover(wreg,wrk0);
jmp(pfneic) mover(wpre,wrk0);move word previus to address
; to register previus to selected
; register, goto get nest prefetched
; instruction.
; HC8000 instr: double register, store: 'ds', numeric code 55.
; -----------------------------------------------------------
ds/'55: sub(addrs,8) noload ; if addrs >= 8 then
cjmp(greq,ds4) mover(wrk1,addrs); goto ds4, wrk1 := addrs.
cjmp(neg,prgexp) ; if addrs is negative then goto
; program exeption.
andinv(wrk1,1) ; remove possible last bit in address.
add(wrk1,'ds7) ; add mic. address
; of first load sentence to no of reg.
ldctre(wrk1) ; load mic sekvens counter with
; counter with addrs + addres of
; first instr. of load reg.
; instr.
cjmrd(neg,intexp) moves(q,wreg); jump indexed by counter to
; to micro. instr based by ds7,
; q := wreg(index).
ds7: moves(w0,q) ; w0 := q.
jmp(regpu3) moves(q,wpre); q := wreg(index-1) , goto reg put 3.
moves(w1,q) ; w1 := q.
jmp(regpu0) moves(q,wpre); q := wreg(index-1) , goto reg put w0.
moves(w2,q) ; w2 := q.
jmp(regpu1) moves(q,wpre); q := wreg(index-1) , goto reg put w1.
moves(w3,q) ; w3 := q.
jmp(regpu2) moves(q,wpre); q := wreg(index-1) , goto reg put w2.
ds4: andinv(wrk1,1) ; remove possible last bit in address.
add(wrk1,base) ; wrk1 := wrk1 ( addrs) + base.
sub(wrk1,uplim) noload; if wrk1 => uplim then
cjmp(greq,prgexp) mover(wrk2,wrk1) ; goto program exeption.
sub(wrk2,2) ; wrk2 := wrk2 - 2.
sub(wrk2,lowlim) noload; if wrk2 < lowlimt then
cjmp(less,prgexp) ; goto program exeption.
invr(hc2901,'e01pdw) ; clock the hc2901 with the
; entry address put double word
; unprotected.
ds1: cjmp(re2901,ds1) clre01; wait for the hc2901 to be ready
; to recieve first storage address.
invs(hc2901,wrk1) ; hc2901 := wrk1.
moves(q,wreg) ; move wreg(index) to q register.
ds2: cjmp(re2901,ds2) clre01; wait for the hc2901 to be ready
; to recieve first data word.
invs(hc2901,q) ; hc2901 := q.
moves(q,wpre) ; move wreg(index-1) to q register.
ds3: cjmp(re2901,ds3) clre01; wait for the hc2901 to be
; ready for recieving the next
; data word.
invs(hc2901,q) ; hc2901 := q.
inctwo(ic) ; ic := ic + 2.
ds6: cjmp(re2901,ds6) clre01; wait for hc2901 ready.
sub(wrk1,ic) noload ; if wrk1 = next ic then goto
cjmp(equal,nopfic) sub(wrk2,ic) noload; goto nopfic
; if addrs = next ic then
cjmp(equal,nopfic) ; goto nopfic.
jmp(pficin) ; else goto nexti2.
; HC8000 instr: exeption register, load: 'xl', numeric code 16.
; -----------------------------------------------------------
xl/'16: jsb(getop) ; call getop,
and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) then
cjmp(nzero,xl1) ; goto xl1.
mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
xl1: and(wrk0,7) csmy nothm csmy shinz; wrk0:= wrk0(21:23) reset move
; half word logic.
jmp(pfneic) or(ex,wrk0); ex := ex or wrk0,
; goto pfneic.
; HC8000 instr: exeption register, store: 'xs', numeric code 27.
; ------------------------------------------------------------
xs/'27: and(q,ex,7) ; q:= ex, (i.e. status(21:23)).
jsb(getop) ; call getop.
and(addrs,1) noload ; if addrs(23) = 1 ( addrs odd ) then
cjmp(zero,xs1) moves(wrk1,q); goto xs1, wrk1 := q.
mover(wrk1,wrk1) hmrl ; wrk1(0:11) := wrk1(12:23).
mover(wrk0,wrk1) hmlr ; wrk0(12:23) := wrk(0:11).
jmp(putop) mover(q,wrk0); q:=wrk0, goto putop.
xs1: mover(wrk0,wrk1) hmrl ; wrk0(0:11) := wrk1(wrk1(12:23)
cont csmy nothm shinz ; clear half word move logic.
jmp(putop) mover(q,wrk0); q:=wrk0, reset half word move
; logic, goto putop.
; integer halfword arithmetic
; ---------------------------
; HC8000 instr: integer byte, load (zero extension): 'bz', numeric code 19.
; ------------------------------------------------------------------------
bz/'19: jsb(getop) ; call getop.
and(addrs,1) noload ; if addrs(23) = 0 (addrs even) then
cjmp(zero,bz1)mzero(wreg); goto bz1, reset selected working
; register.
mover(wrk0,wrk0) hmlr ; wrk0(0:11) := wrk0(12:23).
bz1: mover(wreg,wrk0) hmrl ; w_regg(index,12:23):=wrk0(0:11).
cont csmy nothm csmy shinz; reset half word move control
jmp(pficin) inctwo(ic) ; goto pfneic, ic := ic + 2.
; HC8000 instr: integer byte, load (sign extension): 'bl', numeric code 2.
; ----------------------------------------------------------------------
bl/'2: jsb(getop) ; call getop.
and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) then
cjmp(nzero,bl1) inctwo(ic) ; goto bl1, ic := ic + 2.
mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
cont csmy nothm csmy shinz; reset half word move control
bl1: jmp(pficin) mover(wreg,wrk0) signex; w_reg(index)
; := signextend(wrk0(12:23)),
; goto pfneic.
; HC8000 instr: integer byte, add: 'ba', numeric code 18.
; -----------------------------------------------------
ba/'18: ; ex(carry):=ex(overflow):=0.
jsb(getop) andinv(ex,wrk2); call getop
and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) the
cjmp(nzero,ba1) ; goto ba1.
mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
cont csmy nothm csmy shinz; reset half word move control
ba1: mover(wrk0,wrk0) signex; signextend(wrk0(12:23)).
jmp(ccowc) add(wreg,wrk0); w_reg(index) := w_reg(index)
; + wrk0, goto ccowc.
; HC8000 instr: integer byte subtract: 'bs', numeric code 17.
; ---------------------------------------------------------
bs/'17: ; ex(carry):=ex(overflow):=0.
jsb(getop) andinv(ex,wrk2); call getop.
and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) then
cjmp(nzero,bs1) ; goto bs1.
mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
cont csmy nothm csmy shinz; reset half word mov control
bs1: mover(wrk0,wrk0) signex; signextend(wrk0(12:23)).
jmp(ccowc) sub(wreg,wrk0); w_reg(index):=w_reg(index)
; - wrk0, goto ccowc.
; integer word arithmetic
; ------------------------
; HC8000 instr: integer word, add: 'wa', numeric code 7.
; ----------------------------------------------------
wa/'7: ; ex(carry):=ex(overflow):=0.
jsb(getop) andinv(ex,wrk2); call subroutine get operand from memory.
jmp(ccowc) add(wreg,wrk0); w_reg(index) := w_reg(index) +
; wrk0, goto ccowc.
; HC8000 instr: integer word, subtract: 'ws', numeric code 8.
; ---------------------------------------------------------
ws/'8: ; ex(carry):=ex(overflow):=0.
jsb(getop) andinv(ex,wrk2); call subroutine get operand from memory.
jmp(ccowc) sub(wreg,wrk0); w_reg(index) := w_reg(index) -
; wrk0, goto ccowc.
; HC8000 instr: integer word, multiply: 'wm', numeric code 10.
; ----------------------------------------------------------
wm/'10: jsb(getop) moves(q,wreg); call getop, q := wreg(index).
lcpu(22) mzero(wrk2) ; push next micro instr to stack
; mic. sekv. counter := 23,
; wrk2 := 0.
rep mult2c(wrk2,wrk0) dshinz;
mult2l(wrk2,wrk0) ;
mover(wpre,wrk2) nothm csmy shinz; wreg(index) := wrk2.
jmp(pfneic) moves(wreg,q); goto pfneic, wreg(index-1) := q.
; ========
; division
; ========
; division moved to en program until final version.
; integer double word arithmetic.
; -------------------------------
; removed until final
;*onlyin: final
; HC8000 instr: integer double word, add: 'aa', numeric code 56.
; ------------------------------------------------------------
aa/'56: ; ex(carry):=ex(overflow):=0.
jsb(getdo1) andinv(ex,wrk2); call subroutine get operand from memory.
add(wreg,wrk0) ; w_reg(index) := w_reg(index) +
; wrk0.
cjmp(carry,aa1) ; if carry then goto aa1.
jsb(getdo2) ; call(getd2o).
jmp(ccowc) add(wpre,wrk0); w_reg(index-1):=w_reg(index-1)
; + wrk0, goto ccowc.
aa1: jsb(getdo2) ; call(getdo2).
jmp(ccowc) add1(wpre,wrk0); w_reg(index-1):=w_reg(index-1)
; + wrk0 + 1, goto ccowc.
; HC8000 instr: integer double word, subtract: 'ss', numeric code 57.
; -----------------------------------------------------------------
ss/'57: ; ex(carry):=ex(overflow):=.
jsb(getdo1) andinv(ex,wrk2); call(getdo1).
sub(wreg,wrk0) ; w_reg(index) := w_reg(index) -
; wrk0.
cjmp(carry,ss1) ; if carry then goto ss1.
jsb(getdo2) ; call(getdo2).
jmp(ccowc) sub(wpre,wrk0); w_reg(index-1):=w_reg(index-1)
; - wrk0, goto ccowc.
ss1: jsb(getdo2) ; call(getdo2).
jmp(ccowc) sub1(wpre,wrk0); w_reg(index-1):=w_reg(index-1)
; - wrk0 + 1, goto ccowc.
;*until: final
; logical operation.
; ------------------
; HC8000 instr: logical and: 'la', numeric code 4.
; ----------------------------------------------
la/'4: jsb(getop) ; call subroutine get operand from memory.
jmp(pfneic) and(wreg,wrk0); w_reg(index):=w_reg(index)
; and wrk0, goto pfneic.
; HC8000 instr: logical or: 'lo', numeric code 5.
; ---------------------------------------------
lo/'5: jsb(getop) ; call subroutine get operand from memory.
jmp(pfneic) or(wreg,wrk0); w_reg(index) := w_reg(index) or
; wrk0, goto pfneic.
; HC8000 instr: logical exclusive or: 'lx', numeric code 6.
; -------------------------------------------------------
lx/'6: jsb(getop) ; call subroutine get operand from memory.
jmp(pfneic) exor(wreg,wrk0); w_reg(index) := w_reg(index) exor
; wrk0, goto pfneic.
;*page: XXX
; shift operations.
; -----------------
;
;*skip: ashift .
; HC8000 instr: aritmetically shift single: 'as', numeric code 36.
; --------------------------------------------------------------
as/'36: andinv(ex,3) ; ex(carry):=ex(overflow):=0.
sub(addrs,0) noload ; if addrs > 0 then
cjmp(great,as1) moves(q,wreg) holdmy; goto as2, q:=w_reg(index), hold condition.
cjmp(less,as2) moves(wrk1,q); if addrs < 0 then goto as2, wrk1:=q.
jmp(pfneic) ; if addrs = 0 then goto pfneic..
as1: sub(addrs,24) noload ; if addrs < 24 then
cjmp(less,as4) moves(wrk1,q); goto as4, wrk1:=q.
mover(addrs,24) ; addrs := 24.
as4: sub(addrs,1) ; addrs := addrs - 1.
pushre(addrs) ; counter := addrs,
twb(over,as5) mover(wrk1,wrk1) slft; wrk1:= leftshift_1(wrk1),wrk1(0):=0.
as6: rpct(as6) mover(wrk1,wrk1) slft; repeat this while counter <> 0
; (wrk := left_shift_1(wrk1) ,wrk(0):=0,
; decrease (counter) ).
mover(wreg,wrk1) ; w_reg(index):=wrk1.
or(ex,2) ; ex(overflow) := 1.
and(status,16) noload ; if integer mask = 1 then
cjmp(zero,pfneic) ; goto pfneic.
jmp(intexp) ; goto integer exeption.
as2: cjmp(neg,as3) invr(wrk2,addrs); if q (i.e wreg) < 0 then
; goto as3, wrk2 := abs(addrs).
sub(wrk2,23) noload ; if wrk2 > 23 then
cjmp(great,pfneic) mzero(wreg); goto pfneic, w_reg(index) :=0.
sub(wrk1,1) ; wrk2 := wrk2 - 1.
pushre(wrk2) ; counter := wrk2.
; push next mic.instr addres.
rep mover(wrk1,wrk1) slft shinz;
jmp(pfneic) mover(wreg,wrk1); w_reg(index) := wrk1, goto nein
as3: sub(addrs,23) noload ; if addrs > 23 then
cjmp(great,pfneic) ;
sub(addrs,1) ; addrs := addrs - 1.
pushre(addrs) ; counter := addrs.
; push next mic. instr. address.
rep mover(wrk1,wrk1) shin1 srgt;
as5: jmp(pfneic) mover(wreg,wrk1);
; HC8000 instr: arithmetically shift double: 'ad', numeric code 37.
; ---------------------------------------------------------------
ad/'37: andinv(ex,3) ; ex(carry) := ex(overflow):=0.
sub(addrs,0) noload ; if addrs > 0 then
cjmp(great,ad1) holdmy moves(q,wpre); goto ad2, q:= wreg(index-1).
cjmp(less,ad2) moves(wrk1,q); else if addrs < 0 then goto ad2,
; wrk1 := q.
jmp(pficin) inctwo(ic); goto pficin, ic := ic + 2.
ad1: sub(addrs,48) noload
cjmp(less,ad4) moves(wrk1,q); goto ad4, wrk1 := q.
mover(addrs,48) ; addrs := 48.
ad4: moves(q,wreg) dshinz ; q := wreg(index).
sub(addrs,1) ; addrs := addrs - 1.
pushre(addrs) ; micro sekvens counter := addrs.
; push next micro instr. addrs.
; to micro sekvenser stack.
twb(over,ad3) mover(wrk1,wrk1) lftaql; repeat
; double shift wrk1 and q
; with zero input,
; mic. sekvens counter :=
; mic. sekvens counter -1.
; if mi. sekvens counter = 0 then
; goto ad5.
; until overflow.
push ; if owerflow then
rep mover(wrk1,wrk1) lftaql; repeat double shift wrk1 and q
; with zero input,
; mic. secvens counter:=
; mic. sekvens counter - 1.
; until mic. sekvens counter = 0.
mover(wreg,wrk1) ; wreg(index)
mover(wpre,wrk1) ; wreg(index -1) := wrk1.
moves(wreg,q) ; wreg(index) := q.
or(ex,2) ; exeption(owerflow) := 1.
and(status,16) noload ; if integer mask = 1 then
cjmp(zero,pfneic) ; goto pfneic.
jmp(intexp) ; goto intger exeption.
ad3: moves(wreg,q) ; wreg(index) :=q.
mover(wpre,wrk1) ; wreg(index-1) := wrk1.
jmp(pfneic) ; goto pfneic.
ad2: cjmp(neg,ad5) invr(wrk2,addrs); if q < 0 (i.e. wreg(index-1)) then
; goto ad5, wrk2 := abs(addrs).
sub(wrk2,47) noload ; if wrk2 (i.e. abs(addrs)) > 47 then
cjmp(great,ad6) mzero(wpre); goto ad6, wreg(index-1) := 0.
moves(q,wreg) dshinz ; q := wreg(index)
ad7: sub(wrk2,1) ; wrk2 := wrk2 - 1.
pushre(wrk2) ; mic. sekvens counter := wrk2.
; push next mic. instr. address to
; to sekvens stack, set shift
; shift to double shift in zero.
rep mover(wrk1,wrk1) rgtaql; repeat
; shift wrk1 and q rigth double
; with zero input from rigth.
; counter := counter - 1.
; until counter = 0.
mover(wpre,wrk1) nothm csmy; wreg(index - 1) := wrk1,
;
jmp(pfneic) moves(wreg,q); wreg(index) := q, goto pfneic.
ad5: sub(wrk2,47) noload ; if q < 47 then
cjmp(great,ad8) ; goto ad8.
moves(q,wreg) dshin1 ; q := wreg, set shift logic
; to doubble shift with 1 input.
jmp(ad7)
ad6: jmp(pfneic) mzero(wreg); goto pfneic, wreg(index) := 0.
ad8: invr(wpre,0) ;
invr(wreg,0) ;
jmp(pfneic)
;*until: ashift .
; HC8000 instr: logically shift single: 'ls', numeric code 38.
; ----------------------------------------------------------
ls/'38: sub(addrs,0) noload ; if addrs > 0 then
cjmp(great,ls1) moves(q,wreg) holdmy; goto ls1, q:=w_reg(index), hold
; condition bits.
cjmp(less,ls2) moves(wrk1,q); if addrs < 0 then goto ls2, wrk1:=q.
jmp(pficin) inctwo(ic); <* if addrs = 0 *> then goto
; goto pficin, ic := ic + 2.
ls1: sub(addrs,23) noload ; if addrs > 23 then
cjmp(great,pfneic) mzero(wreg); goto pfneic, w_reg(index):=0.
sub(addrs,1) ; addrs := addrs - 1.
pushre(addrs) ; counter := 0.
; push next mic. instr.
rep mover(wrk1,wrk1) lftqil; q_reg := q_reg shift left 1
; the opration with the
; wrk1 reg is dummy.
jmp(pfneic) moves(wreg,q); w_reg(index):=q, goto pfneic.
ls2: invr1(wrk2,addrs) ; wrk2:=abs(addrs)
sub(wrk2,23) noload ; if addrs > 23 then
cjmp(great,pfneic) mzero(wreg); goto pfneic, w_reg(index):=0.
sub(wrk2,1) ; wrk2 := wrk2 - 1.
pushre(wrk2) ; counter := wrk2.
; push next mic. instr. address.
rep mover(wrk1,wrk1) srgt shinz; shift rigth zero input
jmp(pfneic) mover(wreg,wrk1); w_reg(index):= wrk1, goto prefn.
; HC8000 instr: logically shift double: 'ld', numeric code 39.
; ----------------------------------------------------------
;*onlyin: final
ld/'39: sub(addrs,0) noload ; if addrs > 0 then
cjmp(great,ld1) holdmy moves(q,wpre); goto ls1, hold condition bits,
; q := wreg(index - 1).
cjmp(less,ld2) moves(wrk1,q); if addrs < 0 then goto ld2,
; wrk1 := q.
jmp(pficin) inctwo(ic); ic := ic + 2, goto pficin.
ld1: sub(addrs,47) noload ; if addrs > 47 then
cjmp(great,ld3) mzero(wpre); goto ld3, wreg(index-1) := 0.
moves(wrk1,q) ; wrk1 := q.
moves(q,wreg) ; q := wreg(index).
sub(addrs,1) ; addrs := addrs - 1.
pushre(addrs) ; micro sekvenser counter := addrs.
; pusch next micro. instr addrs.
; to stack,
rep mover(wrk1,wrk1) lftaql dshinz; shift wrk1 and q left with conection
; until counter = 0.
mover(wpre,wrk1) nothm csmy shinz; wreg(index-1) := wrk1.
jmp(pfneic) moves(wreg,q); w(index) := q, goto pficin.
ld2: invr1(addrs,addrs) ; addrs := - addrs.
sub(addrs,47) noload ; if addrs > 47 then
cjmp(great,ld3) mzero(wpre); goto ld3, wreg(index-1) :=0.
moves(q,wreg)
sub(addrs,1) ; addrs := addrs -1 .
pushre(addrs) ; micro sekvenser counter := 0.
; push address of the next
; micro instr into the stack,
rep mover(wrk1,wrk1) rgtaql dshinz; repeat
; counter := counter -1,
; double shift wrk1 and q
; rigth with zero input,
; until counter = 0.
mover(wpre,wrk1) nothm csmy shinz; wreg(index - 1) := wrk1.
jmp(pfneic) moves(wreg,q); wreg(index) := q, goto pficin.
ld3: jmp(pfneic) mzero(wreg); wreg(index) := 0, goto pfneic.
;*until: final
;*skip: norm
; HC8000 instr: normalize single: 'ns', numeric code 34.
; ----------------------------------------------------
ns/'34: moves(q,wreg) ; q := wreg(index).
cjmp(zero,ns2) mzero(wrk1); if wreg(index) = 0 then
; goto ns2, wrk1 := 0.
ns1: cjmp(nover,ns1) slnorm(wrk1);
moves(wreg,q) ; wreg(index) := q.
jsb(getop) mover(q,wrk1); q := wrk1, call getop.
jmp(hsnoen) ; goto hsnoen. (i.e. normalize
; entry in instr. half word
; store ).
ns2: mover(q,-2048) ; q := -2048
jsb(getop) ;
jmp(hsnoen) ;
; HC8000 instr: normalize double: 'nd', numeric code 35.
; ------------------------------------------------------
nd/'35: moves(q,wpre) dshinz ; q := wreg(index-1), set shift control
; to shift double with zero input.
moves(wrk1,q) ; wrk1 := q.
cjmp(zero,nd2) moves(q,wreg); if wrk1 (i.e. wreg(index-1)) = 0 then
; goto nd2, q := wreg(index).
mzero(wrk2) ; wrk2 := 0.
nd1: dlnorm(wrk1) ; double normalize wrk1 and q.
cjmp(ncarry,nd1) incone(wrk2); if not carry then goto nd1,
; wrk2 := wrk2 + 1.
moves(wpre,wrk1) ; wreg(index-1) := wrk1.
jsb(getop) moves(wreg,q); wreg(index) := q, call getop.
jmp(hsnoen) mover(q,wrk2); goto hsnoen ( i.e. entry inhalf
; word store) , q := wrk2.
nd2: cjmp(nzero,nd1) mzero(wrk2); if q <(i.e. wreg(index)) <> 0 then
; goto nd1, wrk2 := 0.
jsb(getop) ; call getop.
mover(q,8.4000) ; q := -2048.
jmp(hsnoen) ; goto hsnoen.
;*until: norm
;*page: XXX
; sequencing .
; -----------
; HC8000 instr: jump and select enable level: 'je', numeric code 15.
;-----------------------------------------------------------------
je/'15:
invr(hc2901,'e01sel) ; closk hc2901 in function set enable level.
andinv(status,'disbit) ; clear disable bit in status register.
jmp(jd2) ; continue in jump disable 2.
; HC8000 instr: jump and select diable level: 'jd', numeric code 14.
;------------------------------------------------------------------
jd/'14: add(addrs,'montop) noload; if addrs >= -montop then
cjmp(notneg,jd1) ; then goto jd1.
mover(wrk0,-2048) signex; wrk0 := -2048.
sub(addrs,wrk0) noload; if addrs < -2048 then
cjmp(less,jd1) ; then goto jd1.
mover(cause,addrs) ; cause := addrs.
add(cause,2048) ; cause := cause + 2048.
sub(inf,1) ; inf := inf -1.
jmp(intser) inctwo(ic); ic := ic + 2, goto service interupt.
jd1: invr(hc2901,'e01sdl) ; closk hc2901 in set diable level.
or(status,'disbit) ; set disable bit in status register.
jd2: cjmp(re2901,jd2) clre01; wait until hc2901 ready.
; HC8000 instr: jump with register link: 'jl', numeric code 13.
; -----------------------------------------------------------
jl/'13: mover(wrk1,w0) ; save w_reg(0) in wrk1.
mover(wreg,ic) ; move old ic to wreg(index).
inctwo(wreg) ; w_reg(index) := wreg(index) + 2.
mover(ic,addrs) ; get new ic form address.
jmp(nopfic) mover(w0,wrk1); goto nopfne, w0 := originaaly w0.
; HC8000 instr: skip if register high: 'sh', numeric code 40.
;---------------------------------------------------------
sh/'40: sub(wreg,addrs) noload; if w_reg(index) <= addrs then
cjmp(lseq,pficin) inctwo(ic); ic := ic + 2,goto pfnicin
jmp(sknins) inctwo(ic); ic := ic + 2, goto sknins.
; HC8000 instr: skip if register low: 'sl', numeric code 41.
;----------------------------------------------------------
sl/'41: sub(wreg,addrs) noload; if w_reg(index) >= addrs then
sl1: cjmp(greq,pficin) inctwo(ic); entry skip limit violation,
; ic := ic + 2, goto pficin.
jmp(sknins) inctwo(ic); ic := ic + 2, goto sknins.
; HC8000 instr: skip if register equal: 'se', numeric code 42.
;----------------------------------------------------------
se/'42: sub(wreg,addrs) noload; if w_reg(index) <> addrs then
se1: cjmp(nequal,pficin) inctwo(ic); ( entry from skip one),
; ic := ic + 2, goto pficin.
jmp(sknins) inctwo(ic); ic := ic + 2, goto sknins.
; HC8000 instr: skip if register not equal: 'sn', numeric code 43.
;----------------------------------------------------------------
sn/'43: sub(wreg,addrs) noload; if w_reg(index) = addrs then
cjmp(equal,pficin) inctwo(ic); ic := ic+2, goto pficin.
jmp(sknins) inctwo(ic); ic := ic + 2, goto sknins,
; HC8000 instr: skip if register bits one: 'so', numeric code 44.
; -------------------------------------------------------------
so/'44: and(q,wreg,addrs) ; q := w_reg(index) and addrs.
jmp(se1) sub(q,addrs) noload; if addrs <> q then
; condition test performed in skip equal.
; HC8000 instr: skip if register bits zero: 'sz', numeric code 45.
;----------------------------------------------------------------
sz/'45: and(wreg,addrs) noload; if w_reg(index) and addrs <> 0 then
sz1: cjmp(nzero,pficin) inctwo(ic); ( entry from skip exeption)
; ic := ic + 2, goto pficin.
jmp(sknins) inctwo(ic); ic := ic + 2, goto sknins.
; HC8000 instr: skip if no exeption: 'sx', numeric code 46.
; -------------------------------------------------------
sx/'46: and(addrs,7) ; addrs := addrs and 7.
jmp(sz1) and(addrs,ex) noload; if (ex and addrs) <> 0 then
; skip test performed in skip zero.
; HC8000 instr: skip if no write protection: 'sp', opcode 21.
; ---------------------------------------------------------
sp/'21: sub(addrs,8) noload ; if sp < 8 then
cjmp(less,sp1) add(q,addrs,base); goto sp1, q := addrs + base.
sub(q,lowlim) noload ; if addrs + base < lower_limit then
cjmp(less,pfneic) ; goto pfneic.
jmp(sl1) sub(q,uplim) noload; if addrs+base >=
; skip action performed in skil low.
sp1: sub(addrs,0) noload ; if addrs < 0 then
cjmp(less,pficin) inctwo(ic); ic := ic + 1, goto pficin.
jmp(sknins) inctwo(ic); ic := ic + 2 , goto skins.
; escape and interupt sequencing.
; -------------------------------
; HC8000 instr: return from excape: 're', numeric code 22.
; ------------------------------------------------------
; escape pattern /.11.1./
re/'22: mover(wrk0,addrs) ; wrk0 ( reg dump addrs) := addrs.
add(wrk0,base) ; reg dump addrs := reg dump addrs + base.
add(q,wrk0,14) ; q := addrs of last reg to be
; reestablished.
sub(lowlim,wrk0) noload; if lower limit > reg dump addrs then
cjmp(great,re5) sub(q,uplim) noload; goto re5, if reg dump addrs
cjmp(greq,re5) mover(wrk2,status); save monitor mode bit for
; preventing illegal setting of
; monitor mode in werk2.
re7: jsb(redyre) mover(wrk1,ic); call reestablish dynamic registers,
; save old ic.
re3: mover(wrk2,wrk2) ; if process previus was in monitor
cjmp(neg,re4) mover(wrk2,status) slft; then goto re4 , else
mover(status,wrk2) srgt; clear monitor mode bit in status reg.
re4:
jmp(nopfic) ; goto get next 8000 instr:.
re5: mover(wrk0,addrs) ; wrk0 := reg dump addrs.
sub(q,base) ; q := reg dump addrs + 14.
mover(wrk2,status) ; save monitor mode bit.
sub(wrk0,8) noload ; if reg dump addrs < 8 then
cjmp(less,expt) sub(q,cpa) noload; goto re6, else if reg dumpadd + 14
cjmp(less,re7) ; < cpa then goto re7 ( reestablish
; registers) else
jmp(expt) ; goto exeption.
; HC8000 instr: return from interupt: 'ri', numeric code 12.
; --------------------------------------------------------
; escape pattern /111.1./
ri/'12: mover(status,status) ; if not in monitor mode then
cjmp(notneg,prgexp) ; then goto program exeption.
invr(hc2901,'e01rin) ; clok hc2901 in entry
; return from interupt.
add(inf,12) ; select new system table
; inf := inf + 12.
add(q,inf,2) ; q := inf+2, calculate register dump
; address in new system table.
ri1: cjmp(re2901,ri1) clre01; wait for hc2901 is ready.
invs(hc2901,q) ; move addrs of system table regdump
; addrs to hc2901
mover(wrk2,addrs) ; save old address in wrk2.
mover(wrk1,ic) ; save old address in wrk1.
ri2: cjmp(re2901,ri2) clre01 invs(wrk0,hc2901); wait for hc2901 is ready,
; get regdump addrs to wrk0.
jsb(redyen) clwr01 ; call subroutine for reestablishing
; the dynamic registers from hc2901,
; clear write hc2901.
add(wrk0,wrk2) ; reg dump addr := reg dump addr
; + old addrs
; ( reg dump addr is now addr of static
; registers, old addrs is the
; effective address of ri intruction).
invs(hc2901,wrk0) ; send address of dynamic register dump to
; to hc2901.
ri12: cjmp(re2901,ri12) clre01 invs(cpa,hc2901); wait for hc2901 ready,
; reestablish spa register.
cont clwr01 ; clock hc2901 ready to accept next
; data word.
ri14: cjmp(re2901,ri14) clre01 invs(base,hc2901); wait for hc2901 ready,
; reestablish base register.
cont clwr01 ; clock hc2901 ready to accept next
; data word.
ri15: cjmp(re2901,ri15) clre01 invs(lowlim,hc2901); wait for hc2901 ready,
; reestablish lower limit register.
cont clwr01 ; clock hc2901 ready to accept next data
; word.
ri16: cjmp(re2901,ri16) clre01 invs(uplim,hc2901); wait for hc2901 ready,
; reestablish upper limit register.
; set dump error count to 0.
and(status,'disbit) noload; if disable bit not set then
cjmp(zero,nopfic) ; fetch next instr wih no prefetch.
invr(hc2901,'e01sdl) ; else clock entry set disable level.
ri17: cjmp(re2901,ri17) clre01; wait for hc2901 ready.
jmp(nopfic) ; go to fetch next 8000 instr: with
; prefecth.
; monitor control
; ---------------
; HC8000 instr: general register, put: 'gp', numeric code 47.
; ---------------------------------------------------------
; escape pattern 2.1000001
gp/'47: mover(status,status) ; if not in monitor mode
cjmp(notneg,prgexp) moves(q,wreg); then goto program exeption,
; q := wreg(index).
sub(addrs,26) noload ; if address = 26 then
cjmp(equal,gp26) inctwo(ic) ; then goto generel put 26, ic := ic+2.
sub(addrs,64) noload ; if addrs = 64 then
cjmp(equal,gp64) ; goto generel put 64.
; else if no legal address then
jmp(pficin) ; goto get next prefetched instruction.
*skip: gp
mover(wrk1,addrs) rgtaoa; wrk1 := addrs shift (-1) .
cjmp(neg,pfneic) ; if shifted value is nagative
; goto interupt 0.
add(q,wrk1,'gp1) ; q:= wrk1 + address of gp1.
ldctre(q) ; counter in secvens controller := q.
moves(q,wreg) ; q := w_reg(index).
sub(wrk1,15) noload ; if wrk1 > 15 then
cjmrd(great,gp2) ; goto gp2 else to contents of eckens counter.
gp1: jmp(pfneic) moves(w0,q); w0 := q, goto pfneic.
jmp(pfneic) moves(w1,q); w1 := q, goto pfneic.
jmp(pfneic) moves(w2,q); w2 := q, goto pfneic.
jmp(pfneic) moves(w3,q); w3 := q, goto pfneic.
jmp(pfneic) moves(ic,q); ic := wreg(index), goto pfneic.
jmp(pfneic) moves(addrs,q); addrs := q. goto pfneic.
jmp(pfneic) moves(r6,q); r6 := q, goto pfneic.
jmp(pfneic) moves(r7,q); r7 := q, goto pfneic.
jmp(pfneic) moves(r8,q); r8 := q, goto pfneic.
jmp(pfneic) moves(r9,q); r9 := q, goto pfneic.
jmp(pfneic) moves(r10,q); r10 := q, goto pfneic.
jmp(pfneic) moves(r11,q); r11 := q, goto pfneic.
jmp(pfneic) moves(r12,q); r12 := q, goto pfneic.
jmp(pfneic) moves(r13,q); r13 := q, goto pfneic.
jmp(pfneic) moves(r14,q); r14 := q, goto pfneic.
jmp(pfneic) moves(r15,q); r15 := q, goto pfneic.
gp2: mover(addrs,addrs) slft; addrs := addrs*2.
add(q,addrs,e01p01) ; q := addrs + entry get reg 0 in hc2901.
invs(hc2901,q) ; hc2901 := clock and set etry to q.
*until: gp
gp64: invr(hc2901,'e01wtr) ; clock hc2901 in write test
; register.
gp3: cjmp(re2901,gp3) clre01; loop while hc2901 is not ready
invs(hc2901,q) ; hc2901 := q and clock
gp4: cjmp(re2901,gp4) clre01; loop until hc2901 is ready.
jmp(pficin) ; goto pfneic.
gp26: jmp(pficin) moves(inf,q) ; information register := q (
; selected working register), goto
; get next prefetched instrcution.
; HC8000 instr: general register, get: 'gg', numeric code 28.
; -----------------------------------------------------
; escape pattern: 2.000001
gg/'28: moves(q,wreg) ; save wreg(index).
sub(addrs,94) noload ; if address = 94 then
cjmp(equal,gg94) ; then goto generel get 94 else
sub(addrs,26) noload ; if addrs = 26 then
cjmp(equal,pfneic) mover(wreg,inf); wreg(index) := infromation
; register, goto pfneic.
; else
sub(addrs,100) noload ; if address = 100 then
cjmp(equal,gg100) ; then goto generel get 100 else
sub(addrs,200) noload ; if address > 200 then
cjmp(greq,ggm200) ; then goto generel get more than 200
; else
sub(addrs,64) noload ; if addres = 64 then
cjmp(equal,gg64) ; then goto generel get 64 else
sub(addrs,66) noload ; if addrs = 66 then
cjmp(equal,gg66) ; then goto generel get 66
; else
ggnle: jmp(pfneic) mover(wreg,q); if not legal then reestablish
; w reg(index) and goto pfneic
gg100: invr(hc2901,'e01rtc) ; send addrs of real time clock to
; hc2901.
jmp(gg4) ; goto gg4.
gg64: invr(hc2901,'e01rtr) ; send0address of read test register
; with no wait to hc2901.
jmp(gg4) ; goto gg4.
gg66: invr(hc2901,'e01rtw) ; clock hc2901 in read test register
; with wait.
jmp(gg4) ; goto wait word from hc2901.
gg94: ; generel get chrakter interupt level from
; amd9511 interupt controler.
mover(status,status) ; if not in monitor mode then
cjmp(notneg,ggnle) ; goto generel get no legal entry.
invr(hc2901,'e01cil) ; else clock hc2901 in entry
; get charakter interupt level.
gg4: cjmp(re2901,gg4) clre01; loop while hc2901 is not redy
jmp(pfneic) invs(wreg,hc2901); w_reg(index) := hc2901, gpfneic.
ggm200: ; entry for generel get with addres greather and equal 200.
sub(addrs,200) noload ; if address > 200 then
cjmp(great,ggm202) ; then goto generel get more 202
; else
; generel get 200.
; reverse bit in word.
moves(wrk0,q) dshinz ; wrk0 := q( selected working register),
; set shift condition in amd2904 to
; double shift with zero input.
lcpu(23) ; load counter with length or word.
; for 0 to 23 do
; begin
mover(wrk0,wrk0) rgtaql ; q.msb := wrk0.lsb, shift wrk0 rigth.
rep mover(wrk1,wrk1) lftaql ; wrk1.lsb := q.msb ; shift wrk1 left.
mover(wreg,wrk1) shinz; wreg(index) := wrk1 ( reversed word),
; set shift condition to singleshift
; and zero input.
jmp(pficin) inctwo(ic) ; goto get next prefetched
; instrcution.
; HC8000 instr: data out: 'do', numeric code 1.
; -------------------------------------------
do/'1: mover(wrk0,'e01dob) ; wrk0 := address of data out base block
; in hc2901.
jmp(dioent) ; goto common data in data out entry.
; HC8000 instr: data in: 'di', numeric code 0.
; --------------------------------------------
di/'29: mover(wrk0,'e01dib) ; wrk0 := entry in hc2901 for address
; block for data in.
dioent: ; common entry for data in and data out.
andinv(ex,7) ; ex(21,23) := 0, clear bit 21 to
; 23 in ex register (i.e. status
; register.)
cjmp(notneg,prgexp) mover(wrk1,addrs) slft; if status
; (same as ex) is not
; negative ( not monitor mode)
; then goto program exeption,
; wrk1 := addrs * 2 ( delete possible
; sign bit).
cjmp(notneg,dimemo) mover(wrk1,wrk1) srgt; if addrs is not negative
; then goto dimemo ( memory word fetch),
and(q,addrs,7) ; q := last 3 bits of
; effective address.
add1(wrk0,q,wrk0) ; wrk0 := wrk0 + address of first
; data in function, in hc2901 + 1,
; ( add 1 because the first entry in
; hc2901 is used to direct memory
; access).
andinv(wrk1,7) ; clear last 3 bits of device number.
; data in jump table.
dimemo: invs(hc2901,wrk0) ; clock hc2901 in address e01gmw.
diw1: cjmp(re2901,diw1) clre01; wait for ready.
invs(hc2901,wrk1) ; hc2901 := divice number.
moves(q,wreg) ; q := wreg(index).
diw2: cjmp(re2901,diw2) clre01; wait for hc2901 ready.
invs(hc2901,q) ; send contents of w reg to hc2901.
diw3: cjmp(re2901,diw3) invs(wreg,hc2901); wait for hc2901,
; wreg(index) := hc2901.
cont clwr01 ; clear write ready from hc2901.
diw4: cjmp(re2901,diw4) invs(wrk1,hc2901); wait for hc2901, wrk1 := hc2901.
and(wrk1,7) ; wrk1 := wrk1(21.23).
jmp(pfneic) or(ex,wrk1); ex := wrk1.
; goto pfneic.
; jumptable to not finished 8000 instr:
; schould not be prommed.
wd/'24: jmp(dowd) ; word divide.
cf/'53: jmp(docf) ; convert floating to integer.
ci/'32: jmp(doci) ; convert integer to floating.
fa/'48: jmp(dofa) ; floating point add.
fd/'52: jmp(dofd) ; floating point divide.
fm/'50: jmp(dofm) ; floating point multiply.
fs/'49: jmp(dofs) ; floating point subtract.
ggm202: ; entry next generel get instruction
; .
dowd:
docf:
doci:
dofa:
dofd:
dofm:
dofs:
jmp(prgexp) ; goto program exeption.
*notin: rhtest
; division removed in rhtest
; HC8000 instr: integer word, divide: 'wd', numeric code 24.
; --------------------------------------------------------
;.wd/'24: . entry notused.
andinv(ex,wrk2) ; ex(carry) := ex(owerflow) := 0.
jsb(getop) moves(q,wpre); wrk0 := getop(addrs),
; q := wreg(index-1), ( most
; significant word of dividend).
cjmp(zero,wd1) moves(wrk2,q); if wrk0 = 0 then goto wd1,
; wrk2 := q (most significant word
; of dividend).
mover(wrk1,wrk0) ; wrk1 := wrk0 ( divisor).
sgnmgn(wrk2) ; wrk2 := sign magnitude(wrk2).
cjmp(over,wd2) sgnmgn(wrk1); wrk1 := sign magnitude(wrk1)
; if overflow then goto wd2.
cjmp(over,wd3) mover(wrk1,wrk1) slft; if overflow then goto wd3,
; wrk1 := wrk1 shift 1.
mover(wrk2,wrk2) slft ; wrk2 := wrk2 shift 1.
sub(wrk1,wrk2) dshln ; wrk1 := wrk1 - wrk2.
; set shift double with link logic
wd3: cjmp(carry,wd4) moves(wrk2,q); if carry then goto wd4,
; wrk2 := q ( most significant
; word of dividend.)
moves(q,wreg) ; q := wreg(index).
lcpu(22) div1st(wrk2,wrk0); push micro program counter to stack
; load micro sekvens counter with 23,
;
rep div2c(wrk2,wrk0) ;
div2cr(wrk2,wrk0) shin1; set shift single with one input
mover(wpre,wrk2) ; wreg(index -1) := wrk2,
; wreg(index-1) := remainder.
moves(wreg,q) ; wreg(index) := q,
; wreg(index) := quotient.
jmp(pficin) inctwo(ic); goto prefetch next instr,
; ic := ic + 2.
wd1: or(ex,2) ; ex(overflow) := 1.
and(status,16) noload ; if status(integer overflow) = 1
cjmp(zero,pfneic) ; goto pfneic
jmp(intexp) ; goto integer exeption.
wd2: mover(wrk1,wrk1) srgt ; not finishd entry for scaling
wd4: cont
jmp(pfneic) ; dummy end.
*until: rhtest
; end of micro program
*end:
▶EOF◀