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Names: »kkmonret4«
└─⟦621cfb9a2⟧ Bits:30002817 RC8000 Dump tape fra HCØ. Detaljer om "HC8000" projekt.
└─⟦0364f57e3⟧
└─⟦this⟧ »kkmonret4«
(
message monchange release 7.0 to 7.14
clear temp mondef moncentral monprocs,
montabinit monprocfnc1 monprocfnc2 monmaster ,
mdef mcentral mprocs,
mtabinit mprocfnc1 mprocfnc2 mmaster
contract entry.kkmon4filer mondef moncentral monprocs,
montabinit monprocfnc1 monprocfnc2 monmaster
skip 36.1
c=copy mess.no 1
mdef=assign mondef
skip 36.1
c=copy mess.no 1
mcentral=set 1 disc3
mcentral=edit moncentral
skip 36.1
c=copy mess.no 1
mprocs=set 1 disc3
mprocs=edit monprocs
skip 36.1
c=copy mess.no 1
mtabinit=set 1 disc3
mtabinit=edit montabinit
skip 36.1
c=copy mess.no 1
mprocfnc1=set 1 disc3
mprocfnc1=edit monprocfnc1
skip 36.1
c=copy mess.no 1
mprocfnc2=set 1 disc3
mprocfnc2=edit monprocfnc2
skip 36.1
c=copy mess.no 1
mmaster=set 1 disc3
mmaster=edit monmaster
head cpu
end)
$def
;********************
f
$central
;********************
l./c6:/,l-4,d./ria179/,d./e./,i/
b. w.
c6: al w3 1
jl -1 ; hard stop
;
; power up
;
c25:
c. a430
jl. w3 d37. ; init cpu1
z.
al w3 b49 ; power up element
gp w3 b91 ;
ri a179; goto start proc
e.
;
/,
l./d7:ggw2b94/,d-1,i/
b. i15 w.
i14: 1<23+4<3+2.100 ; timer 2 most significant
i15: 1<23+5<3+2.100 ; timer 2 least significant
i13: 0
d7: di. w0 (i14.) ; read most significant
ls w0 8 ;
di. w2 (i15.) ; read least significant
wa w2 0 ; w2:=most<8+least
ws. w2 i9. ; -cw:= - 1<16 + most<8 +least
ac w2 x2 ;
/,
l./d35:/,g 2/.(2)/ x3/,f
$procs
;********************
l./e50 /,r/e50/c99/,
l./e58:/,l1,i/
c.-1
/,l./i55:/,l./e./,l1,i/
z.
/,l./c21:/,l./b8/,i/
ws w2 b0 ; w2:=interrupt level
rl w3 x2+1164
al w3 x3+1
rs w3 x2+1164
am x2-16 ; else save interrupt level
rs w2 x1+a302+2 ; in save area.proc
/,l./end of service for cpu(i)/,
l./segment3/,l./b127/,l1,i/
g2=g3
/,l./e3:/,l./g2;8:/,r/g2/h8/,
l./h72;72:/,i/
c.-1
/,l./h3=g6/,i/
z.
g2 ; 72:
g2 ; 74:
g2 ; 76:
g2 ; 78:
g2 ; 80:
g2 ; 82:
g2 ; 84:
g2 ; 86:
g2 ; 88:
g2 ; 90:
h8 ; 92: acia line
/,l./r3;8:/r,/r3 /i29/,r/8:/8: terminal or console/,
l./i9:/,i/
i29 ; 92: acia line
/,l./78clockdriver/,l./remoterprocess/,i/
h8: ; driver
; w0 : undef
; w1 = sender
; w2 = buf
; w3 = proc
p.<:ttydriv:>
c.-1
/,f
$tabinit
;*****************
i/
z.
/,l./f0:/,l./h22/,i/
c.-1
/,l./h24/,i/
z.
/,
l./b54/,r/b54/8;***microprogram error/,
l./b.i10/,d./j6:/,i/
b. i0 w.
h1: 0,r.a180>1 ; reg dump
h0:
c. -1
rl. w1 i0. ;
al w1 x1+1 ;
rs. w1 i0. ;
gp w1 64 ; write test register
i0:0
z.
jl. 0 ; dummy loop
/,
l./b54/,r/b54/8;***microprogram error should be 7/,
l./dummyexternal/,i/
c.-1
/,l./h23:/,l2,i/
z.
/,l./segment5:/,l./;get n/,d./gpw1/,i/
al w1 1024;
ls w1 6 ; core size is initiality set to 32 K words
/,l./b67/,l1,d4,
l./,b89/,r/b89/ 0/,l./a66/,r/a66/ 0/,l./b86/,r/b86/ 0/,f
$procfnc1
;********************
l./b60:/,l./d8:/,l-1,i/
w.
c.-1
/,l./d12:/,l-2,i/
z.
/,l./;pro/,i/
c. -1
/,l./e15:/,l./;pr/,i/
z.
/,l./e24:/,l./g3:/,l./e.;/,l1,i/
c.-1
/,l./g4:/,l./;the/,i/
z.
/,l./h1:/,l2,i/
c.-1
/,l./e42:/,l./h0:/,l2,i/
z.
/,l./e44:/,l./e.;/,l1,i/
c.-1
/,l./e48:/,l./h0:/,i/
z.
b. g20,h10 w.
/,l./g20:/,l./e.;/,l1,i/
c.-1
/,l./e51:/,l./jlx2/,l1,i/
z.
/,l./n50:/,l./j0:/,l./e1./,i/
c. -1
/,l./e7./,l1,i/
z.
/,f
$procfnc2
;****************
l./;btj1977/,i/
w.
c.-1
/,l./m6:/,l2,i/
z.
/,l./jl.n0./,l1,i/
c.-1
/,l./m11:/,l./;testname/,i/
z.
/,l./e24=k-2/,l1,i/
c. -1
/,l./;testnew/,i/
z.
/,l./e45./,i/
c. -1
/,l./b45/,l1,i/
z.
/,l./g8:/,l1,i/
c. -1
/,l./n2./,i/
z.
/,l./;test/,i/
c. -1
/,l./;subp/,i/
z.
/,l./e48./,i/
c. -1
/,l./n6./,l1,i/
z.
/,l./d17:/,l./e./,l1,i/
c.-1
/,l./d16:/,i/
z.
/,l./d15:/,l1,i/
c.-1
/,l./m32:/,l./g8:/,l./;if not bs-dev/,i/
z.
/,l./n5=/,l1,i/
c.-1
/,l./d21:/,i/
z.
d20: d2
/,l./d34:/,l1,i/
c.-1
/,l./m64:/,l./;set/,i/
z.
/,l./;doc/,i/
c.-1
/,l./m100:/,l./jl.e24./,l1,i/
z.
m101:
jl. e24.
m40:,m43:,m66:,m70:,m125:
c.-1
/,l./m128/,l./;test/,i/
z.
/,l./m155:/,l./e25./,l-1,i/
c. -1
/,l3,i/
z.
/,l./g7./,i/
c. -1
/,l2,i/
z.
/,l./e25./,l-1,i/
c. -1
/,l3,i/
z.
g15:
/,l./sz w2 2.01/,i/
c. -1
/,l3,i/
z.
/,l./a46/,i/
c. -1
/,l./g9./,i/
z.
/,l./g7:/,l-1,i/
c.-1
/,l./i3:<:host:/,l2,i/
z.
/,l./m00=m00/,i/
c.-1
/,l./m155=m155/,i/
z.
m8=m8-n50,m13=m13-n50,m15=m15-n50,m16=m16-n50,m17=m17-n50
m34=m34-n50,m40=m40-n50,m43=m43-n50,m65=m65-n50
m66=m66-n50,m70=m70-n50,m101=m101-n50,m125=m125-n50,m149=m149-n50
m150=m150-n50,m151=m151-n50,m152=m152-n50,m153=m153-n50,m154=m154-n50
/,l./m260=/,i/
c.-1
/,l./j0=/,i/
z.
/,l./r7:/,l1,i/
h.
c.-1
/,l./p46:/,l./;create per/,i/
z.
/,l./p35:/,l./;set/,i/
c.-1
/,l./p39:/,l./m32;/,l1,i/
z.
/,l./p42:/,l./;pr/,i/
c.-1
/,l./p44:/,l./n49:/,l./w./,i/
z.
n49:
h.
r7. ,r7. ,r7. ,r7. ,r7. ,r7. ,r7. ,p27.,p28.,p29.
p30.,p31.,p32.,r7. ,p34.,p35.,r7. ,r7. ,r7. ,r7.
p40.,r7. ,r7. ,r7. ,r7. ,r7. ,r7. ,r7. ,r7. ,r7.
r7. ,r7. ,r7. ,r7. ,r7. ,r7. ,r7. ,r7. ,r7. ,r7.
r7. ,r7.
/,l./j5=/,l./;recordcatb/,i/
c. -1
/,l./interruptadd/,i/
z.
/,l./e28:/,l-1,i/
c.-1
/,l./g11:/,l./;def/,i/
z.
/,f
$master
;********************
l./i10:/,l1,i/
/,l./<:ver:>/,l./a24,1<7/,r/1/0/,l./<:er:>/,l./a24,1<7/,r/1/0/,
l./a24,1<7/,r/1/0/,
l./; segment 10/,l./i10,j10/,l./i3:/,l-1,i/
;; init of timer
;;++++++++++++++++++++++++++++++++++++
;; entry i0.
;; return address in w2.
;; destroyed w1.
b. c40 w. ;
; constants for timer initialisation.
; cr = control reg. in timer (1 ,2 ,3 )
; interupt disabled from timer by 0<6
c10: 1<7+1<6+000<3+0<2+0<1+0; cr 1 operate all timers
c11: 1<7+0<6<000<3+0<2+0<1+1; cr 1 preset all timers.
c20: 1<7+0<6+000<3+0<2+0<1+0; cr 2 select cr 3.
c21: 1<7+0<6+000<3+0<2+0<1+1; cr 2 select cr 1.
c30: 1<7+0<6+000<3+0<2+1<1+0; cr 3 no prescale.
c31: 1<7+0<6+000<3+0<2+1<1+1; cr 3 prescale.
; device addrs for clock.
c0: 1<23+0<3+2.100 ;addrs for write cr 1 or 3.
; read nothing.
c1: 1<23+1<3+2.100 ; addrs write cr 2.
; addrs read status reg..
c2: 1<23+2<3+2.100 ; addrs write most sgnf. byte
; buffer reg..
; addrs read timer no 1 counter.
c3: 1<23+3<3+2.100 ; addrs write timer no 1 latches.
; addrs read least sgnf. bytes
; buffer reg..
c4: 1<23+4<3+2.100 ; addrs write most sgnf. byte buffer
;reg..
;
; addrs read timer no 2 counter.
c5: 1<23+5<3+2.100 ; addrs write timer 2 latches.
; read least sgnf. byte buffer reg..
c6: 1<23+6<3+2.100 ; addrs write most sgnf. byte buffer
;reg..
; addrs read timer 3 counter.
c7: 1<23+7<3+2.100 ; addrs write write timer no 3 latches.
; addrs read least sgnf. byte buffer
;reg..
c12: 0 ; most sgnf. byte to rtimer 0.
c14:255 ; leats sgnf. byte to timer 1.
c22: 255 ; most sgnf. byte to timewr 2.
c24: 255 ; least sgnf. byte to timer 2.
c32: 0 ; most sgnf. byte to timer 3.
c34: 49 ; least sgnf. byte to timer 3.
i9: ; init of timer.
rs. w2 c29. ; save return address.
rl. w1 c21. ; select control reg 1 as addrs 0.
do. w1 (c1.) ; write dev no 1.
rl. w1 c11. ; preset all timers.
do. w1 (c0.) ; write char dev. 0.
rl. w1 c20. ; select cr 3 ass addrs 0.
do. w1 (c1.) ; write char dev. 1.
rl. w1 c30. ; set cr 3 no prescale.
do. w1 (c0.) ; swrite char dev. 0.
rl. w1 c21. ; select cr as1 as addrs 0.
do. w1 (c1.) ; write char dev. 1.
rl. w1 c32. ; load most sgnf. counter
; value to timer bufffer.
do. w1 (c6.) ; write char dev. no 6.
rl. w1 c34. ; load least signif. byte to counter 3.
do. w1 (c7.) ; write char dev. no. 7.
rl. w1 c22. ; load most sgnf. byte to counter 2.
do. w1 (c4.) ; write char dev. 4.
rl. w1 c24. ; load least sgnf. byte to counter 3.
do. w1 (c5.) ; write char dev. no. 5.
rl. w1 c12. ; load most sgnf. byte to counter 1.
do. w1 (c2.) ; write char dev. no. 2.
rl. w1 c14. ; load least sgnf. byte to counter 1.
do. w1 (c3.) ; write char dev. no. 3.
rl. w1 c10. ; send cr 1 operate all timers
do. w1 (c0.) ; write char dev. no. 0.
di. w1 (c1.) ; data in char dev. 1.
jl. (c29.) ; return from subroutine.
c29: 0 ; return address.
e. ; end block init of timer.
n13: 2.10000000 ;C mask for disanble transmit enable receive.
n15: 2.00000011 ;C acia master reset command.
;; global entry inititlize acia controller.
o1: ;; schould be global entry address.
b. m10 w. ; begin
rs. w3 m1. ; save return address.
rl w3 x1+a50 ; load acia control address.
rl. w0 n15. ; load acia reset command.
do w0 x3 ; write acia reset command to acia controller.
rl w0 x1+a78+24 ; load acia transmission mode.
do w0 x3 ; write acia transmission mode to acia controller
; using acia control address.
di w0 x3+8 ; read acia data using acia data address.
di w0 x3 ; read acia status usin acia control address.
rl w0 x1+a78+24 ; load acia transmission mode command.
lo. w0 n13. ; mask receive enable transmit disable into
; transmision mode mask
do w0 x3 ; write receive enable/transmit disable to
; acia control register.
jl. ( m1. ; return from acia init.
m1: 0 ; return address of init acia.
e. ;; end init of acia drivers.
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;; init of hc8000 interupt controler.
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;; init of amd9519 interupt controler.
;; writen by: carsten gyrn, sept. 1982.
;; entry address: g18.
;; call:
;; w0 = not used.
;; w1 = address of value of level 0 in interupt
;; controler.
;; (evry level is initialized to
;; C(x1 + 2*level no)).
;; w2 = device address of control port of
;; interupt controler.
;; w3 = return address.
;; destroyed = w0 w1 w2 w3.
;; the amd9519 interupt controler is initialised
;; to auto clear for all interupt and to
;; fixed priority.
;; see: advancded micro devices 9519 universal
;; interupt controler documentation for
;; detailed and complete description,
;; and for other possibilities.
;;
;;
;; note: acknovlege of interupt is made by
;; the privilegd instruction: gg wX 94.
;;
;; for all amd9519 interupt controler:
;; device address = data address
;; device address + 1 = control address.
;;
;; function: initialize the interupt amd9519 interupt controler
;; no masked interupt, autoclear for all,
;; fixed priority ( = lower interupt before higher)
;; no polling.
;; and arm ( enable ) interupt controler.
g18:b.c8, b0 w.
ls w2 3 ; shift data address 3 left.
lo. w2 c1. ; mask device base into data address.
g19: ;; entry when device data address already is complete.
rs. w3 c0. ; save return address.
al w3 x2+8 ; calculate device control address.
ds. w3 c3. ; save device control and data address.
al w0 0 ; set master reset control byte.
do w0 x3 ; send master reset to device.
al w3 0 ; level counter := 0;
rl. w2 c4. ; load control byte preselecting response
; memory for writing.
b0: al w0 x2 ; get preselect mask
do. w0 ( c3. ; send preselect response memory for writing,
; to interupt controler.
rl w0 x1 ; get logical interupt level.
do. w0 ( c2. ; send logical level to interupt controler.
al w1 x1+2 ; next logical interupt level.
al w2 x2+1 ; next physical interupt level in this
; interupt controler, (last 3 bit of control
; byte for preselecting response memory for
; writing).
al w3 x3+1 ; next level counter.
se w3 8 ; if not last level then
jl. b0. ; goto repeat.
rl. w0 c5. ; get control byte for preselect
; autoclear mask register in interupt controler
; for writing.
do. w0 ( c3. ; send control byte to interupt controler
rl. w0 c6. ; get auto clear mask, ( clear all interupts).
do. w0 ( c2. ; send auto clear mask to interupt controler.
rl. w0 c7. ; get clear interupt and request bit mask.
do. w0 ( c3. ; send clear interupt and request bit mask to
; interupt controler.
rl. w0 c8. ; get mask for arm interupt controler and
; preselect interupt request register for reading.
do. w0 ( c3. ; send arm comand and preselect for reading
; to interupt controler.
jl. ( c0. ; return.
c0: 0 ; saved return address.
c1: 1<23+0<3+2.100 ; charakter device no.: 0
; (base for all charakter devices).
c2: 0 ; device address for data to intrupt controler.
c3: 0 ; device address for control of interupt
; controler.
c4: 2.11100000 ; control byte for preselect response
; memory for writing.
c5: 2.11000000 ; control byte for preselect auto clear
; register for writing.
c6: 2.11111111 ; data byte to auto clear register,
; 255 = auto clear on all interupts.
c7: 2.00010000 ; control byte for clear interupt mask
; ( all interupt active)
c8: 2.10101001 ; control byte for preselecting interupt
; request register for reading and arm
; ( arm = special word for enable) interupt
; controler.
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
e. ;; end of code to standard initialiation of interupt controler.
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;; read interupt controler status.
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;; entry address: g16
;; call: w0 = not used.
;; w1 = not used.
;; w2 = device address.
;; w3 = return address.
;; return: w0 = complete status word.
;; w1 = not used.
;; w2 = complete device address.
;; w3 = return address.
;;
;; function: reads the status word from the amd9519
;; interupt controler.
;;
;; not: the status words contents is the following:
;; bit 0 1 2 = binary vector indicating the number of
;; highest priority unmasked bit set in the
;; interupt request register. valid only
;; when bit 7 in the status register = 0.
;; bit 3 = set interupt controler armed.
;; not set interupt controler disarmed.
;; bit 4 = set interupt mode is polled.
;; not interupt mode is interupt.
;; bit 5 = set priority mode is rotating.
;; not set priority mode is fixed.
;; bit 6 = set input enabled.
;; not set input disabled.
;; bit 7 = set not unmasked interupt in irr
;; not set at least one interupt in irr.
;;
g16: ;; entry
b. f0 w.
ls w2 3 ; shift device control address 3 left
; so it fits into charakter device base word.
lo. w2 f0. ; mask device base word into device control address.
g17: ;; entry if device control address already is complete.
di w0 x2+8 ; read status register from interupt controler.
jl x3 ; return from subroutine.
f0: 1<23+0<3+2.100 ; charakter device base.
e. ;; end of read interupt controler status.
;; ++++++++++++++++++++++++++++++++++++++
/,l./i3:/,l2,i/
jl. w2 i9. ; goto init time
/,f
▶EOF◀