|
DataMuseum.dkPresents historical artifacts from the history of: RC4000/8000/9000 |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about RC4000/8000/9000 Excavated with: AutoArchaeologist - Free & Open Source Software. |
top - metrics - download
Length: 172032 (0x2a000)
Types: TextFile
Names: »listhc03«
└─⟦667bb35d6⟧ Bits:30007480 RC8000 Dump tape fra HCØ.
└─⟦4334b4c0b⟧
└─⟦this⟧ »listhc03«
\f
Micro asm.: micasm03 version date.810603.1340
Source file: tjoorder030 version date.820426.1533
Object file: hcorder03 version date.0820426.1539
;*page: XXXX micasm03
*load: m2903
; ----------------------------
; skipped is code 'finalx'
; skipped is code 'rhtest'
; 810810/1710:
; auto load interupt removed.
; skipped by code 'autoin'
; 810810/1700:
; fetch 8000 instr: from register repaired.
; 810810/1730:
; clearing of last bit in ic removed from jl
; instrcution and inserted in noprefetch module
; now ic can never be negative.
; also corrected in rh2901.
; 810817/2000:
; gg 94 introduced, get interupt level
; from amd9511 interupt controler.
; 810817/2000:
; gg with address >= 200 defined as
; user programmed instructions. (i.e
; instrcution which can be used from a
; user program and gives a result which
; is defines by a user.
; 810817/2000:
; gg 200 = reverse bits in register selected.
; 810818/0900:
; gg 201 = count register 1 and skip if zero.
; gg 202 = count register 2 and skip if zero.
; the skip is performed when the selected register
; reach or pass zero.
; the count can be both positive
; and negative depending on the sign of the
; contents of the selected working register.
; 810819/1100:
; fetch changed so address after jump vector
; is contained in wrk1, and wrk1 is subtracted
; the address register at external interupt.
; 810825/2000:
; all instruction code mnemonics changed
; so when in doubt they are prefixed with a
; letter r or a letter s signifing from which
; mux the operand is entering the alu.
;NEXT.
; ------------------------------------------------------------
; WHAT SCHOULD BE DONE:
; 001: if you define that yuo never double store
; overlabing registers and memory(8)
; or double load some check could be removed.
; 002: if you define that registers that contain
; HC8000 instr:s, never continue in memory(8)
; some check in module regins can be removed.
; 003: if you define that the word which is stored
; by a store 8000 instr: never is used by
; as the absolute next 8000 instr:, then
; some check can be removed in the store module.
; 004: the increment of the instruction counter could be
; much earlyer in most instrcution. fx. in the
; same moment you call get op, if you insure that
; the increment is removed from exeption.
; NEXT WHAT.
; --------------------------------------------------------------
; -------------------------------------------------------------
; micro 8000 instr: description.
;
; only one format.
; mir(0) is msb.
; mir(47) is lsb.
;
; mir(0) = -, cc ccenable.
; mir(1:4) = amd2910 micro program sequencer 8000 instr:.
; mir(5) = -,( ce my)
; mir(6) = -,( ce M)
; mir(7:10) = amd2904 condition select.
; mir(11:20) = amd2903 bitslice 8000 instr:.
; mir(14) is intruction bit 5 for msh.
; mir(15) is 8000 instr: bit 5 for lsh.
; mir(21:22) = amd2904 carry control.
; mir(23) = -,(amd2904 enable)
; mir(24) = -,(ea)
; mir(25) = hc8000 working register select.
; mir(26) = -,(Oeb)
; mir(27) = -,(write hc2901)
; mir(28:31) = source register address ( a address to amd2903).
; mir(32:35) = disitnation register address.
; mir(26:27) = jump address, imidiate operand.
*test:biton
*const: e01inp,23 ; entry get intr. with no prefetc
*const: e01ip,24 ; entry in hc2901 instr. with prefetch.
; - -- - -
*const: e01gmw,25 ; entry in hc2901 get memory word.
*const: e01pmw,26 ; entry in hc2901 put memory word.
*const: e01gdw,27 ; entry in hc2901 get double memory word.
*const: e01pdw,28 ; entry in hc2901 put double memory word.
*const: e01rtc,29 ; gg(100) , generel get real time clock.
*const: e01rtr,30 ; generel get test register ( 64)
*const: e01wtr,31 ; generel put testregister ( 64)
*const: e01rtw,32 ; generel get test register with wait
; (66).
*const: e01dom,13 ; data out memory word.
*const: e01dob,5 ; data out function jump table.
*const: e01dim,22 ; data in memory word.
*const: e01dib,14 ; data in function jumb table.
*const: e01drd,33 ; dynamic registers dump
*const: e01drr,36 ; dynamic registers restore.
*const: e01rin,37 ; return from interupt.
*const: e01aci,38 ; get and clear interupt or exeption.
*const: e01ini,0 ; initialize.
*const: e01sdl,35 ; set interupt disable level.
*const: e01sel,34 ; set interupt enable level.
*const: e01is1,39 ; interupt service entry 1.
*const: e01skn,40 ; entry skip next instr and fetch.
*const: e01cil,41 ; gg (94) get interupt level from
; amd9511 charakter interupt level
; controler.
*const: montop,256 ; the higest monitor operation is set to
*const: autoin,6 ; cause no of auto load. (interupt 3
*const: disbit,8 ; position of diable bit in
; the status register bit(20).
; system table error).
; a fixed valus of 512.
*origo: 0
0000 jmp(init) ; goto init.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; entries for mapping proms.
; --------------------------
0001 jmp(ielax3) ;indirect relative and x3
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0002 jmp(ielax2) ; -do.- and x2.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0003 jmp(ielax1) ; - do. - and x1.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0004 jmp(ielati) ; - do. - no index reg.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0005 jmp(relax3) ; relative and index reg 3.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0006 jmp(relax2) ; - do. - 2
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0007 jmp(relax1) ; - do. - 1
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0010 jmp(relati) ; - do. - no index register.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0011 jmp(inlyx3) ; indirect and index reg 3.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0012 jmp(inlyx2) ; - do. - 2.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0013 jmp(inlyx1) ; - do. - 1.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0014 jmp(iomodi) ; - do. - no index reg.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0015 jmp(onlyx3) ; direct addressing and index reg 3.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0016 jmp(onlyx2) ; - do. - 2.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0017 jmp(onlyx1) ; - do. - 1.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0020 jmp(nomodi) ;
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0021 jmp(prgexp) ; HC8000 instr: 63. xx unass.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0022 jmp(prgexp) ; HC8000 instr: 62. unassigned.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0023 jmp(prgexp) ; HC8000 instr: 61. unassigned..
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0024 jmp(prgexp) ; HC8000 instr: 60. unassigned.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0025 jmp(prgexp) ; HC8000 instr: 59. unassigned
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0026 jmp(prgexp) ; HC8000 instr: 58. unassigned.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0027 jmp(ss) ; HC8000 instr: 57.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0030 jmp(aa) ; HC8000 instr: 56.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0031 jmp(ds) ; HC8000 instr: 55.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0032 jmp(dl) ; HC8000 instr: 54.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0033 jmp(prgexp) ; HC8000 instr: 53. cf.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0034 jmp(prgexp) ; HC8000 instr: 52. fd.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0035 jmp(prgexp) ; HC8000 instr: 51. unas.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0036 jmp(prgexp) ; HC8000 instr: 50. fm.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0037 jmp(prgexp) ; HC8000 instr: 49. prgexp.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0040 jmp(prgexp) ; HC8000 instr: 48. fa.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0041 jmp(gp) ; HC8000 instr: 47. unas.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0042 jmp(sx) ; HC8000 instr: 46.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0043 jmp(sz) ; HC8000 instr: 45.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0044 jmp(so) ; HC8000 instr: 44.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0045 jmp(sn) ; HC8000 instr: 43.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0046 jmp(se) ; HC8000 instr: 42.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0047 jmp(sl) ; HC8000 instr: 41.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0050 jmp(sh) ; HC8000 instr: 40.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0051 jmp(ld) ; HC8000 instr: 39.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0052 jmp(ls) ; HC8000 instr: 38.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0053 jmp(ad) ; HC8000 instr: 37.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0054 jmp(as) ; HC8000 instr: 36.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0055 jmp(nd) ; HC8000 instr: 35.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0056 jmp(ns) ; HC8000 instr: 34.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0057 jmp(ac) ; HC8000 instr: 33.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0060 jmp(prgexp) ; HC8000 instr: 32. ci.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0061 jmp(prgexp) ; HC8000 instr: 31. unas.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0062 jmp(prgexp) ; HC8000 instr: 30. unas.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0063 jmp(di) ; HC8000 instr: 29.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0064 jmp(gg) ; HC8000 instr: 28.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0065 jmp(xs) ; HC8000 instr: 27.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0066 jmp(hs) ; HC8000 instr: 26.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0067 jmp(rx) ; HC8000 instr: 25.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0070 jmp(wd) ; HC8000 instr: 24.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0071 jmp(rs) ; HC8000 instr: 23.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0072 jmp(re) ; HC8000 instr: 22.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0073 jmp(sp) ; HC8000 instr: 21.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0074 jmp(rl) ; HC8000 instr: 20.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0075 jmp(bz) ; HC8000 instr: 19. zl.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0076 jmp(ba) ; HC8000 instr: 18. ea.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0077 jmp(bs) ; HC8000 instr: 17. ea.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0100 jmp(xl) ; HC8000 instr: 16.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0101 jmp(je) ; HC8000 instr: 15.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0102 jmp(jd) ; HC8000 instr: 14.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0103 jmp(jl) ; HC8000 instr: 13.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0104 jmp(ri) ; HC8000 instr: 12.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0105 jmp(al) ; HC8000 instr: 11.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0106 jmp(wm) ; HC8000 instr: 10.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0107 jmp(am) ; HC8000 instr: 9.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0110 jmp(ws) ; HC8000 instr: 8.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0111 jmp(wa) ; HC8000 instr: 7.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0112 jmp(lx) ; HC8000 instr: 6.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0113 jmp(lo) ; HC8000 instr: 5.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0114 jmp(la) ; HC8000 instr: 4.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0115 jmp(hl) ; HC8000 instr: 3.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0116 jmp(bl) ; HC8000 instr: 2. el.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0117 jmp(do) ; HC8000 instr: 1.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0120 jmp(prgexp) ; HC8000 instr: 00. unas.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; entry from vector prom with external interupt.
0121 jmp(extint) ; goto external interupt.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; address calculations.
; =====================
0122 nomodi/"0:jmap ; no modifiers
. ..1. . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0123 relati/"8:jmap add(addrs,ic) ; relative
. ..1. . 1 .... .1... ..11. .. 1.... .1.1 .111 .... .1 11 ....
0124 relax1/"9:jmp(relati) add(addrs,x1) ; reletive and x1
1 ..11 . 1 .... .1... ..11. .. 1.... ..1. .111 .... .1 11 ....
0125 relax2/"10:jmp(relati) add(addrs,x2) ; relative and x2
1 ..11 . 1 .... .1... ..11. .. 1.... ...1 .111 .... .1 11 ....
0126 relax3/"11:jmp(relati) add(addrs,x3) ; relative and x3
1 ..11 . 1 .... .1... ..11. .. 1.... .... .111 .... .1 11 ....
0127 onlyx1/"1:jmap add(addrs,x1) ; only x1
. ..1. . 1 .... .1... ..11. .. 1.... ..1. .111 .... .1 11 ....
0130 onlyx2/"2:jmap add(addrs,x2) ; only x2
. ..1. . 1 .... .1... ..11. .. 1.... ...1 .111 .... .1 11 ....
0131 onlyx3/"3:jmap add(addrs,x3) ; only x3
. ..1. . 1 .... .1... ..11. .. 1.... .... .111 .... .1 11 ....
0132 iomodi/"4:jsb(getop) ; only indirect
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0133 jmap mover(addrs,wrk0) ;
. ..1. . 1 .... .1... .11.. .. 1.... 1111 .111 .... .1 11 ....
0134 inlyx1/"5:jsb(getop) add(addrs,x1) ; indirect and x1.
1 ...1 . 1 .... .1... ..11. .. 1.... ..1. .111 .... .1 11 ....
0135 jmap mover(addrs,wrk0) ;
. ..1. . 1 .... .1... .11.. .. 1.... 1111 .111 .... .1 11 ....
0136 inlyx2/"6:jsb(getop) add(addrs,x2) ; indirect and x2.
1 ...1 . 1 .... .1... ..11. .. 1.... ...1 .111 .... .1 11 ....
0137 jmap mover(addrs,wrk0) ;
. ..1. . 1 .... .1... .11.. .. 1.... 1111 .111 .... .1 11 ....
0140 inlyx3/"7:jsb(getop) add(addrs,x3) ; indirect and x3.
1 ...1 . 1 .... .1... ..11. .. 1.... .... .111 .... .1 11 ....
0141 jmap mover(addrs,wrk0) ;
. ..1. . 1 .... .1... .11.. .. 1.... 1111 .111 .... .1 11 ....
0142 ielati/"12:jsb(getop) add(addrs,ic) ; indirect and relative
1 ...1 . 1 .... .1... ..11. .. 1.... .1.1 .111 .... .1 11 ....
0143 jmap mover(addrs,wrk0) ;
. ..1. . 1 .... .1... .11.. .. 1.... 1111 .111 .... .1 11 ....
0144 ielax1/"13:jmp(ielati) add(addrs,x1) ; indirect and relative and x1
1 ..11 . 1 .... .1... ..11. .. 1.... ..1. .111 .... .1 11 ....
0145 ielax2/"14:jmp(ielati) add(addrs,x2) ; indirect and relative and x2
1 ..11 . 1 .... .1... ..11. .. 1.... ...1 .111 .... .1 11 ....
0146 ielax3/"15:jmp(ielati) add(addrs,x3) ; indirect and relative and x3
1 ..11 . 1 .... .1... ..11. .. 1.... .... .111 .... .1 11 ....
▶01◀
; new initialize.
; ---------------
0147 init: mzero(base) nothm csmy shinz ; base := 0, reset half word
. 111. . 1 .... .1... 1.... .. ..... .... 1..1 .... .1 11 ....
; move logic, set normal condition
; select logic, set shift in
; zero.
0150 invr(cpa,base) srgt ; cpa := max integer.
. 111. . 1 .... ...11 .111. .. 1.... 1..1 1... .... .1 11 ....
0151 invr(status,cpa) ; status(1:23) := 0,
. 111. . 1 .... .1... .111. .. 1.... 1... .1.. .... .1 11 ....
; status(0) := 1 ( monitor mode).
0152 mover(uplim,cpa) ; uppper limit := max integer
. 111. . 1 .... .1... .11.. .. 1.... 1... 11.1 .... .1 11 ....
; schould be memory sixe.
0153 mover(lowlim,8) ; lower limit := 8.
. 111. . 1 .... .1... .11.. .. 11... .... 111. .... .. .. 1...
0154 cjvec(neg) ; if lowerlimit is negative then
. .11. . 1 1111 11... ....1 .. 1.... .... .... .... .1 11 ....
; jump vector prom, (this is not
; the case because 8 is put into
; lower limit, so next micro
; HC8000 instr: is allways performed
; next but it cause the interupt
; bit to be cleared).
0155 invr(hc2901,'e01ini) ; clock hc2901 in no address.
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
0156 init1: cjmp(re2901,init1) invs(ic,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... .1.1 .... .1 11 ....
; ic := hc2901.
0157 jmp(nopfic) ; goto nopfic ( fetch instr with
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; no prefetch.
; entry get 8000 instr: with no prefetch
; ---------------------------------------
0160 nopfne: inctwo(ic) ; ic:=ic+2.
. 111. . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
0161 nopfic: andinv(ic,1) ; clear possible last bit
. 111. . 1 .... .1... 1..1. .. 11... .... .1.1 .... .. .. ...1
; in 8000 instr: pointer.
0162 sub(ic,8) noload ; if ic < 8 then
. 111. . 1 .... 11... ...1. .1 11... .... .1.1 .... .. .. 1...
0163 cjmp(less,regins) mzero(addrs) ; goto regins, addrs := 0.
. ..11 . 1 ..11 .1... 1.... .. 1.... .... .111 .... .1 11 ....
0164 npref2: invr(hc2901,'e01inp) ;
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
0165 jsb(chlicp) mover(wrk0,ic) ; wrk0 := ic, call subroutine
1 ...1 . 1 .... .1... .11.. .. 1.... .1.1 1111 .... .1 11 ....
; check limit and cpa.
0166 fetch1: cjmp(re2901,fetch1) clre01 ; wait until hc2901 is ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0167 jmp(fetch2) invs(hc2901,wrk0) ; send address of next instr to
1 ..11 . 1 .... 11... .1.1. .. 1...1 .... 1111 .... .1 11 ....
; the hc2901, goto fetch2.
; entry skip next 8000 instr: and fetch.
; --------------------------------------
0170 sknini: inctwo(ic) ; ic := ic + 2.
. 111. . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
0171 sknins: sub(ic,10) noload ; if ic < 10 then
. 111. . 1 .... 11... ...1. .1 11... .... .1.1 .... .. .. 1.1.
0172 cjmp(less,regins) mzero(addrs) ; goto regins, addrs := 0.
. ..11 . 1 ..11 .1... 1.... .. 1.... .... .111 .... .1 11 ....
0173 invr(hc2901,'e01skn) ; clock hc2901 in skip next.
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
0174 jmp(fetch2) ; continue in wait instrcution.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; entry fetch 8000 instr: with prefetch
; --------------------------------------
0175 pfneic: inctwo(ic) ; ic := ic + 2.
. 111. . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
0176 pficin: sub(ic,10) noload ; if ic < 10 then
. 111. . 1 .... 11... ...1. .1 11... .... .1.1 .... .. .. 1.1.
0177 cjmp(less,regins) mzero(addrs) ; goto regins, addrs := 0.
. ..11 . 1 ..11 .1... 1.... .. 1.... .... .111 .... .1 11 ....
; if the previous 8000 instr: was
; taken from w3, then the prefetch
; function wil not work, so the next
; is taken without prefetch,
; this check is ofcource not performed
; in the getting of w3 because
; the 8000 instr: in w3 could be a
; jump to an 8000 instr: in w0.
; hold condition from previous
; HC8000 instr: to next.
0200 ftcam: invr(hc2901,'e01ip) ; clock hc2901 in entry get
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; instrcution with no prefetch.
; also entry from 'am' anstruction.
0201 fetch2: mover(wrk2,3) ; init wrk2 with 3.
. 111. . 1 .... .1... .11.. .. 11... .... 1.11 .... .. .. ..11
0202 fetch3: cjmp(re2901,fetch3) invs(wrk1,hc2901) signex ;
. ..11 . 1 1111 111.1 .1.1. .. 1..1. .... 1.1. .... .1 11 ....
; wait for hc2901 to send instrcution
; move instrcution with sign extension
; to wrk1 so wrk1 now contain
; the instrcutions displacement field.
0203 mover(q,wrk1) clre01 ; extra clock of read so their is time
. 111. . 1 .... .11.. .11.1 .. 1..1. 1.1. .... .... .1 11 ....
; to clock the vector and the mapping
; prom with the instrcution field
; and the address mofifier field,
; move the diaplacement field to
; the q register with a move out
; of the amd2903 r bus, so the
; it is certain that the birectional
; bus db is notclocked
; from any output the amd2903.
0204 jvec add(addrs,addrs,q)▶16◀▶16◀▶16◀▶16◀ clre01 nothm shinz csmy;
1 .11. . 1 .... .1... ..111 .. ...1. .111 .111 .... .1 11 ....
; addrs := addrs + displacement field,
; clock the hc2901
; read bit,
; get instr from register.
; if previous 8000 instr: was taken from w3,
; then will the prefetch not work so
; the next is taken witout prefetch,
; this check is of course not performed in
; the getting of w3 bacause the 8000 instr: in w3 could be
; a jump to 8000 instr: in w0 ( e.x dummy lowrk0 the monitor).
; registers is numbered:
; w0 = 0
; w1 = 2
; w2 = 4
; w3 = 6
; negative value = program exeption.
; 8 = get next from memory with no prefetch.
0205 regins: sub(ic,4) noload ; if ic < 4 then
. 111. . 1 .... 11... ...1. .1 11... .... .1.1 .... .. .. .1..
0206 cjmp(less,insw01) holdmy ; goto get w0 or w1 or negative
. ..11 1 1 ..11 11... ....1 .. 1.... .... .... .... .1 11 ....
; address, hold condition.
0207 cjmp(equal,regin1) mover(wrk0,w2); if ic =4 then wrk0:=w2,
. ..11 . 1 .1.1 .1... .11.. .. 1.... ...1 1111 .... .1 11 ....
; goto regin1.
0210 sub(ic,6) noload ; if ic = 8 then
. 111. . 1 .... 11... ...1. .1 11... .... .1.1 .... .. .. .11.
0211 cjmp(equal,regin1) mover(wrk0,w3); wrk0 := w3, goto regin1.
. ..11 . 1 .1.1 .1... .11.. .. 1.... .... 1111 .... .1 11 ....
; else
0212 jmp(npref2) ; goto noprefetch (location 8).
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0213 insw01: sub(ic,0) noload ; if ic > 0 then
. 111. . 1 .... 11... ...1. .1 11... .... .1.1 .... .. .. ....
0214 cjmp(great,regin1) mover(wrk0,w1) holdmy;wrk0 := w1 ,
. ..11 1 1 .... .1... .11.. .. 1.... ..1. 1111 .... .1 11 ....
; hold condition , goto regins.
0215 insw0m: cjmp(notneg,regin1) mover(wrk0,w0); else wrk0 := w0, goto regin1.
. ..11 . 1 111. .1... .11.. .. 1.... ..11 1111 .... .1 11 ....
0216 jmp(prgex0) mzero(cause) ; else goto program exeption, causec:=.0.
1 ..11 . 1 .... .1... 1.... .. 1.... .... .11. .... .1 11 ....
0217 regin1: mover(wrk1,wrk0) signex ; wrk1 := signextend ( 8000 instr:)
. 111. . 1 .... 111.1 .11.. .. 1.... 1111 1.1. .... .1 11 ....
; ( address field of 8000 instr:).
0220 add(addrs,wrk1) ; addrs := addrs + wrk1.
. 111. . 1 .... .1... ..11. .. 1.... 1.1. .111 .... .1 11 ....
0221 mover(wrk2,3) ; init wrk2 to constant 3,
. 111. . 1 .... .1... .11.. .. 11... .... 1.11 .... .. .. ..11
; used in aritmetric instructions to
; speed up calculations).
0222 invs(q,wrk0) ; send 8000 instr: through amd2903's
. 111. . 1 .... .11.. .1.11 .. 1.... 1111 .... .... .1 11 ....
; r bus, and there by out on the the
; bidirectional db-bus, this will send
; the 8000 instr: out to address the
; vector 8000 instr: prom and the
; map address modifier prom.
0223 jvec invs(q,wrk0) ; jump vector, repeat addressing
1 .11. . 1 .... .11.. .1.11 .. 1.... 1111 .... .... .1 11 ....
; of vector prom and map prom.
; interupt, exeption and escape control section.
; ----------------------------------------------
; subroutine perform limit check with wrk0 register
; -------------------------------------------------
; and return wrk0 register with added base if limit
; is not violated else if wrk0 < cpa then just wrk0,
; last instr subtract 8 from wrk0 with noload.
; ----------------------------------------------
0224 chlicp: add(wrk0,base) ; wrk0 := wrk0 + base,
. 111. . 1 .... .1... ..11. .. 1.... 1..1 1111 .... .1 11 ....
; ( wrk0 contains address to be
; be investigated)
0225 chlic1: sub(wrk0,uplim) noload ; if wrk0 >= upper limit then
. 111. . 1 .... 11... ...1. .1 1.... 11.1 1111 .... .1 11 ....
0226 cjmp(greq,prgex2) sub(wrk0,lowlim) noload; goto program exeption, with 2
. ..11 . 1 ..1. 11... ...1. .1 1.... 111. 1111 .... .1 11 ....
; wait for hc2901.
0227 crtn(greq) ; if q >= lower limit then return
. 1.1. . 1 ..1. 11... ....1 .. 1.... .... .... .... .1 11 ....
; where wrk0 = wrk0+base.
0230 sub(addrs,cpa) noload ; if addrs < cpa then
. 111. . 1 .... 11... ...1. .1 1.... 1... .111 .... .1 11 ....
0231 crtn(less) mover(wrk0,addrs)▶16◀▶16◀ ; return and wrk0 := addrs with no
. 1.1. . 1 ..11 .1... .11.. .. 1.... .111 1111 .... .1 11 ....
; base.
0232 jmp(prgex2) ; else goto program exeption, with 2
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; wait for hc2901.
; subroutine dump dynamic registers.
; ----------------------------------
dudyre:
0233 invr(hc2901,'e01drd) ; call function dynamic register dump in
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; hc2901.
0234 dudyr1: cjmp(re2901,dudyr1) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0235 invs(hc2901,wrk1) ; sen regdump addrs to hc2901.
. 111. . 1 .... 11... .1.1. .. 1...1 .... 1.1. .... .1 11 ....
0236 dudyr2: cjmp(re2901,dudyr2) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0237 dudyen: invs(hc2901,w0) ; send w0 to reg dump.
. 111. . 1 .... 11... .1.1. .. 1...1 .... ..11 .... .1 11 ....
0240 dudyr3: cjmp(re2901,dudyr3) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0241 invs(hc2901,w1) ; send w1 to reg dump.
. 111. . 1 .... 11... .1.1. .. 1...1 .... ..1. .... .1 11 ....
0242 dudyr4: cjmp(re2901,dudyr4) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0243 invs(hc2901,w2) ; send w2 to reg dump.
. 111. . 1 .... 11... .1.1. .. 1...1 .... ...1 .... .1 11 ....
0244 dudyr5: cjmp(re2901,dudyr5) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0245 invs(hc2901,w3) ; send w3 to reg dump.
. 111. . 1 .... 11... .1.1. .. 1...1 .... .... .... .1 11 ....
0246 dudyr6: cjmp(re2901,dudyr6) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0247 invs(hc2901,status) ; send status to reg dum.
. 111. . 1 .... 11... .1.1. .. 1...1 .... .1.. .... .1 11 ....
0250 dudyr7: cjmp(re2901,dudyr7) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0251 invs(hc2901,ic) ; sen ic to reg dump.
. 111. . 1 .... 11... .1.1. .. 1...1 .... .1.1 .... .1 11 ....
0252 dudyr8: cjmp(re2901,dudyr8) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0253 invs(hc2901,cause) ; send cause to reg dump.
. 111. . 1 .... 11... .1.1. .. 1...1 .... .11. .... .1 11 ....
0254 dudyr9: cjmp(re2901,dudyr9) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0255 invs(hc2901,addrs) ; send addrs to reg dump.
. 111. . 1 .... 11... .1.1. .. 1...1 .... .111 .... .1 11 ....
0256 dudy10: cjmp(re2901,dudy10) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0257 rtn add(wrk1,16) ; return from subroutine,
1 1.1. . 1 .... .1... ..11. .. 11... .... 1.1. .... .. .1 ....
; wrk1 := wrk1 + 16,
; ( wrk1 = reg. dump address).
; subroutine reestablish dynamic registers.
; -----------------------------------------
redyre:
0260 invr(hc2901,'e01drr) ; call function dunamic register reestablish
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; in hc2901.
0261 redyaw: cjmp(re2901,redyaw) clre01 ; wait for hc2901 ready to accept address
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
; of dump block.
0262 invs(hc2901,wrk0) ; send reg dump addrs to hc2901.
. 111. . 1 .... 11... .1.1. .. 1...1 .... 1111 .... .1 11 ....
redyen: ; entry dum dynamic registers.
0263 redyr1: cjmp(re2901,redyr1) clre01 invs(w0,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... ..11 .... .1 11 ....
; reestablish w0.
0264 cont clwr01 ; clock ready to hc2901.
. 111. . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
0265 redyr2: cjmp(re2901,redyr2) clre01 invs(w1,hc2901); wait for hc2901,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... ..1. .... .1 11 ....
; reestablish w1.
0266 cont clwr01 ; cont clock write ready to hc2901.
. 111. . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
0267 redyr3: cjmp(re2901,redyr3) clre01 invs(w2,hc2901); wair for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... ...1 .... .1 11 ....
; reestablish w2.
0270 cont clwr01 ; cont clock write ready to hc2901.
. 111. . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
0271 redyr4: cjmp(re2901,redyr4) clre01 invs(w3,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... .... .... .1 11 ....
; reestablish w3.
0272 cont clwr01 ; cont clock write ready to hc2901.
. 111. . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
0273 redyr5: cjmp(re2901,redyr5) clre01 invs(status,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... .1.. .... .1 11 ....
; reestablish status.
0274 cont clwr01 ; cont clock write ready to hc2901.
. 111. . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
0275 redyr6: cjmp(re2901,redyr6) clre01 invs(ic,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... .1.1 .... .1 11 ....
; reestablish ic.
0276 cont clwr01 ; cont clock write ready to hc2901.
. 111. . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
0277 redyr7: cjmp(re2901,redyr7) clre01 invs(cause,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... .11. .... .1 11 ....
; reestablish cause.
0300 cont clwr01 ; cont clock write ready to hc2901.
. 111. . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
0301 redyr8: cjmp(re2901,redyr8) clre01 invs(addrs,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... .111 .... .1 11 ....
; reestablish hc2901.
0302 rtn ; return from subroutine
1 1.1. . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
;
; exeption
; ---------
; program exeption.
; -----------------
; ( se also entry prgex1 prgex2 prgex3).
0303 prgexp/:jmp(expt) mzero(cause) ; goto exeption service, cause := 0.
1 ..11 . 1 .... .1... 1.... .. 1.... .... .11. .... .1 11 ....
; integer exeption.
; -----------------
0304 intexp/:mover(cause,2) ; cause := 2.
. 111. . 1 .... .1... .11.. .. 11... .... .11. .... .. .. ..1.
0305 jmp(expt) ; goto exeption service.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; floating point exeption.
; ------------------------
0306 flpexp/:mover(cause,4) ; cause := 4.
. 111. . 1 .... .1... .11.. .. 11... .... .11. .... .. .. .1..
0307 jmp(expt) ; goto exeption service.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; program exeption whwn double load is clocked.
0310 prgex3: cjmp(re2901,prgex2) clre01 ; wait for hc2901 is ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0311 cont clwr01 invr(hc2901,8) ; clear write ready to hc2901.
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. 1...
; entry for program exeption
; when read memory word is clocked.
0312 prgex2: cjmp(re2901,prgex2) clre01 ; wait for hc2901 is ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0313 cont clwr01 invr(hc2901,8) ; clear write ready to hc2901.
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. 1...
0314 prgex1: cjmp(re2901,prgex1) mzero(cause) clre01; wait for hc201 is ready.
. ..11 . 1 1111 .1... 1.... .. 1..1. .... .11. .... .1 11 ....
; exeption.
; ---------
prgex0: ; entry when cause is zero.
0315 expt/: invr(hc2901,'e01gmw) ; call get word from memory with
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; no limit check in hc2901.
0316 inctwo(ic) ; ic := ic + 2.
. 111. . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
0317 add(inf,4) ; inf := inf + 4.
. 111. . 1 .... .1... ..11. .. 11... .... 11.. .... .. .. .1..
0320 expt1: cjmp(re2901,expt1) clre01 ; wait for hc2901 is ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0321 invs(hc2901,inf) ; send address of reg. dump to hc2901.
. 111. . 1 .... 11... .1.1. .. 1...1 .... 11.. .... .1 11 ....
0322 sub(inf,4) ; inf := inf - 4.
. 111. . 1 .... .1... ...1. .1 11... .... 11.. .... .. .. .1..
0323 expt2: cjmp(re2901,expt2) clre01 invs(wrk1,hc2901); get reg dump addrs to wrk1.
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... 1.1. .... .1 11 ....
; wrk1 := register dum address.
0324 cjmp(zero,intser) ; if regdump address = 0 then goto
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
; interupt service.
; entry for dump registers from escape routine
; after control of register dump address <> 0.
; wrk1 = register dump address <> 0.
extp3:
dmpreg:
0325 add(wrk1,base) ; reg dump addrs := reg dump addrs + base.
. 111. . 1 .... .1... ..11. .. 1.... 1..1 1.1. .... .1 11 ....
0326 sub(wrk1,lowlim) noload ; if reg dump addrs + base <
. 111. . 1 .... 11... ...1. .1 1.... 111. 1.1. .... .1 11 ....
; lower limit then
0327 cjmp(less,stbe1) ; then goto syetm table error.
. ..11 . 1 ..11 11... ....1 .. 1.... .... .... .... .1 11 ....
0330 add(wrk1,14) ; reg dump addrs := reg dump addrs + 14.
. 111. . 1 .... .1... ..11. .. 11... .... 1.1. .... .. .. 111.
0331 sub(wrk1,uplim) noload ; if reg dump addrs >= upper limit then
. 111. . 1 .... 11... ...1. .1 1.... 11.1 1.1. .... .1 11 ....
0332 cjmp(greq,stbe1) ; goto system table error.
. ..11 . 1 ..1. 11... ....1 .. 1.... .... .... .... .1 11 ....
0333 sub(wrk1,14) ; reg dump addrs := reg dump addrs - 14.
. 111. . 1 .... .1... ...1. .1 11... .... 1.1. .... .. .. 111.
0334 jsb(dudyre) ; call sub routine to dump dynamic registers.
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0335 mover(w0,ic) ; w0 := old ic.
. 111. . 1 .... .1... .11.. .. 1.... .1.1 ..11 .... .1 11 ....
; w1 is not initialized acording to
; the the rc8000 family refference
; manual.
0336 mover(w2,addrs) ; w2 := addrs.
. 111. . 1 .... .1... .11.. .. 1.... .111 ...1 .... .1 11 ....
0337 and(cause,63) ; cause := cause(18..23).
. 111. . 1 .... .1... 11... .. 11... .... .11. .... .. 11 1111
0340 mover(ic,wrk1) ; new ic := reg dump addrs + 16,
. 111. . 1 .... .1... .11.. .. 1.... 1.1. .1.1 .... .1 11 ....
; ( reg. dump. address is increased
; with 16 in subroutine dump dynamic
; registers).
0341 jmp(nopfic) mover(w3,cause) ; w3 := cause, goto next 8000 instr:
1 ..11 . 1 .... .1... .11.. .. 1.... .11. .... .... .1 11 ....
; with no prefetch.
stbe1: ; system table error from exeption.
0342 mover(cause,6) ; cause := 6.
. 111. . 1 .... .1... .11.. .. 11... .... .11. .... .. .. .11.
0343 sub(wrk1,base) ; reg dump addr := reg dump addr - base.
. 111. . 1 .... .1... ...1. .1 1.... 1..1 1.1. .... .1 11 ....
0344 jmp(intser) mover(addrs,wrk1) ; addrs := reg dump addrs ,
1 ..11 . 1 .... .1... .11.. .. 1.... 1.1. .111 .... .1 11 ....
; goto interupt service.
; external interupt.
; ------------------
; this address is reached after an 'jvec' micro 8000 instr:
; in the fetch next 8000 instr: section and the interupt is
; set from the hc2901.
0345 extint/:invr(hc2901,'e01aci) ; clock hc2901 in address answer
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; and clear interupt.
; the answer is given as an exact interupt
; interupt no.
0346 mzero(base) ; base := 0.
. 111. . 1 .... .1... 1.... .. 1.... .... 1..1 .... .1 11 ....
0347 sub(addrs,wrk1) ; reestablish addrs register as before
. 111. . 1 .... .1... ...1. .1 1.... 1.1. .111 .... .1 11 ....
; fetch instrcution. (i.e. if after am
; then address register is unchanged).
0350 extin1: cjmp(re2901,extin1) clre01 invs(cause,hc2901); wait for hc2901 to be
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... .11. .... .1 11 ....
; to be ready , cause := interupt no * 2.
0351 jmp(intse3) mover(cause,cause) slft; cause := cause * 2, continue
1 ..11 . 1 .... 1..11 .11.. .. 1.... .11. .11. .... .1 11 ....
; interupt service entry 3.
intser/: ; common interupt service routine.
; --------------------------------
0352 invr(hc2901,'e01is1) ; call function in hc2901 for starting
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; interupt service 1.
0353 intse1: mzero(base) ; base := 0, (disabling memory
. 111. . 1 .... .1... 1.... .. 1.... .... 1..1 .... .1 11 ....
; relocation).
0354 intse2: cjmp(re2901,intse2) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0355 intse3: invs(hc2901,inf) ; send information register to hc2901.
. 111. . 1 .... 11... .1.1. .. 1...1 .... 11.. .... .1 11 ....
0356 mover(lowlim,8) ; lower limit := 8.
. 111. . 1 .... .1... .11.. .. 11... .... 111. .... .. .. 1...
0357 invr(uplim,base) srgt ; lower limit := max integer ( schould be
. 111. . 1 .... ...11 .111. .. 1.... 1..1 11.1 .... .1 11 ....
; size of memory).
; this diables the limit check.
0360 intse4: cjmp(re2901,intse4) clre01 invs(wrk2,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... 1.11 .... .1 11 ....
; get system table status and interupt
; initialization.
0361 mover(lowlim,8) clwr01 ; lower limit := const(8).
. 111. . 1 .... .1... .11.. .. 11..1 .... 111. .... .. .. 1...
; clear write ready to hc2901.
0362 intse6: cjmp(re2901,intse6) clre01 invs(wrk1,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... 1.1. .... .1 11 ....
; get system table reg dump addrs.
0363 jsb(dudyen) ; call subroutine dump dynamic
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; registers, in entry 1 with
; no init clock of hc2901.
0364 mover(w1,wrk1) clwr01 ; sync of hc2901 with a clear of the
. 111. . 1 .... .1... .11.. .. 1...1 1.1. ..1. .... .1 11 ....
; sync bit to hc2901,
; w1 := reg dump address + 16,
; ( reg. dump address is increassed
; by 16 in subroutine dump dynamic
; registers).
0365 ints19: cjmp(re2901,ints19) clre01 invs(ic,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... .1.1 .... .1 11 ....
; get new ic address from system table.
0366 mover(status,wrk2) ; status := system table status initialistion
. 111. . 1 .... .1... .11.. .. 1.... 1.11 .1.. .... .1 11 ....
0367 andinv(status,4095) ; status := system table status and
. 111. . 1 .... .1... 1..1. .. 11... .... .1.. 1111 11 11 1111
; intlim initialiation (0..11).
0370 sub(inf,12) ; inf := inf - 12.
. 111. . 1 .... .1... ...1. .1 11... .... 11.. .... .. .. 11..
0371 or(inf,1) ; inf(23) := 1.
. 111. . 1 .... .1... 1111. .. 11... .... 11.. .... .. .. ...1
0372 jmp(nopfic) mover(w2,cause) ; w2 := cause, goto fetch next
1 ..11 . 1 .... .1... .11.. .. 1.... .11. ...1 .... .1 11 ....
; HC8000 instr: with no prefetch.
; carry and owerflow control section.
; -----------------------------------
0373 ccowc: cjmp(over,ccowc1) holdmy ; if overflow then goto ccowc1,
. ..11 1 1 .111 11... ....1 .. 1.... .... .... .... .1 11 ....
; hold control.
0374 cjmp(ncarry,pfneic) ; if not carry then goto nexin.
. ..11 . 1 1.1. 11... ....1 .. 1.... .... .... .... .1 11 ....
0375 or(ex,1) ; ex(carry) := 1.
. 111. . 1 .... .1... 1111. .. 11... .... .1.. .... .. .. ...1
0376 jmp(pfneic) ; ex(carry) := 1, goto pfneic.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0377 ccowc1: or(ex,2) holdmy ; ex(overflow) := 1, hold condition
. 111. 1 1 .... .1... 1111. .. 11... .... .1.. .... .. .. ..1.
; control.
0400 cjmp(ncarry,ccowc2) ; ex(overflow) := 1, if not carry
. ..11 . 1 1.1. 11... ....1 .. 1.... .... .... .... .1 11 ....
; then goto ccowc2.
0401 or(ex,1) ; ex(carry) := 1.
. 111. . 1 .... .1... 1111. .. 11... .... .1.. .... .. .. ...1
0402 ccowc2: and(status,16) noload ; if status(integer mask) = 0 then
. 111. . 1 .... 11... 11... .. 11... .... .1.. .... .. .1 ....
0403 cjmp(zero,pfneic) ; goto pfneic.
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
0404 jmp(intexp) ; goto integer exeption.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; subroutine get operand
; -----------------------
; call: address of operand in reg. 'addrs'.
; return: operand in reg. 'wrk0'.
; destroyed: none.
; condition select is expected to b 'csmy'
0405 getop: sub(addrs,8) noload ;
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .. 1...
0406 cjmp(less,regget) mover(wrk0,addrs); wrk0 := addrs.
. ..11 . 1 ..11 .1... .11.. .. 1.... .111 1111 .... .1 11 ....
0407 getop1: invr(hc2901,'e01gmw) ; call function in hc2901 get operand
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; get opreand without limit control.
0410 jsb(chlic1) add(wrk0,base) ; wrk0:= wrk0 + base , call subroutine
1 ...1 . 1 .... .1... ..11. .. 1.... 1..1 1111 .... .1 11 ....
; to perform limit check and cpa
; limit check.
0411 getop2: andinv(wrk0,1) ; remove possible last bit in address.
. 111. . 1 .... .1... 1..1. .. 11... .... 1111 .... .. .. ...1
0412 getop4: cjmp(re2901,getop4) clre01 ; wait for hc2901 to accept address.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0413 invs(hc2901,wrk0) ;send daddress to hc2901, and clock
. 111. . 1 .... 11... .1.1. .. 1...1 .... 1111 .... .1 11 ....
; write bit.
0414 getop3: cjmp(re2901,getop3) invs(wrk0,hc2901); wait for hc2901 to sned data,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... 1111 .... .1 11 ....
; inver data into wrk0 from hc2901
; buffer register.
0415 rtn mover(wrk0,wrk0) shinz nothm csmy; return from subroutine,
1 1.1. . 1 .... .1... .11.. .. ..... 1111 1111 .... .1 11 ....
; prepere for negative or zero test
; data.
; subroutine load from internal reg.
; ----------------------------------
0416 regget: cjmp(neg,prgexp) mover(wrk0,wrk0) srgt; if addres if negative then goto
. ..11 . 1 1111 ...11 .11.. .. 1.... 1111 1111 .... .1 11 ....
; program exeption, shift wrk0 rigth 1,
; so wrk0 points to exact register no.
0417 regge1: add(wrk0,'regge2) ; microsekvens counter := address
. 111. . 1 .... .1... ..11. .. 11... .... 1111 .... .. .. ....
0420 ldctre(wrk0) ; shift -1 + mic. instr addres
. 11.. . 1 .... 11... .11.1 .. 1.1.. 1111 ..1. .... .1 11 ....
; regge1.
0421 cjmrd(neg,prgexp) ; jump in micro. program to
. .111 . 1 1111 11... ....1 .. 1.... .... .... .... .1 11 ....
; to address indexd by regge1 +
; addrs // 2.
0422 regge2: rtn mover(wrk0,w0) ; wrk0 := w0.
1 1.1. . 1 .... .1... .11.. .. 1.... ..11 1111 .... .1 11 ....
0423 rtn mover(wrk0,w1) ; wrk0 := w1.
1 1.1. . 1 .... .1... .11.. .. 1.... ..1. 1111 .... .1 11 ....
0424 rtn mover(wrk0,w2) ; wrk0 := w2.
1 1.1. . 1 .... .1... .11.. .. 1.... ...1 1111 .... .1 11 ....
0425 rtn mover(wrk0,w3) ; wrk0 := w3.
1 1.1. . 1 .... .1... .11.. .. 1.... .... 1111 .... .1 11 ....
; subroutine get double word from memory with
; write protection check.
; -------------------------------------------
0426 getdo1: sub(addrs,8) noload ; if addrs < 8 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .. 1...
0427 cjmp(less,regget) mover(wrk0,addrs); wrk0 := address, goto regget.
. ..11 . 1 ..11 .1... .11.. .. 1.... .111 1111 .... .1 11 ....
0430 getdo3: invr(hc2901,'e01gdw) ; send entry to hc2901.
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
0431 add(wrk0,base) ; wrk0 := addrs + base.
. 111. . 1 .... .1... ..11. .. 1.... 1..1 1111 .... .1 11 ....
0432 sub(wrk0,uplim) noload ; if wrk0 >= upper limit then
. 111. . 1 .... 11... ...1. .1 1.... 11.1 1111 .... .1 11 ....
0433 cjmp(greq,prgex3) sub(wrk0,lowlim) noload; goto program exeption
. ..11 . 1 ..1. 11... ...1. .1 1.... 111. 1111 .... .1 11 ....
; with 3 wait for hc2901.
0434 cjmp(greq,getop2) sub(addrs,cpa) noload; if wrk0 >= lower limit
. ..11 . 1 ..1. 11... ...1. .1 1.... 1... .111 .... .1 11 ....
; then goto getop2.
0435 cjmp(less,getop2) mover(wrk0,addrs); if addrs < cpa then goto getop2.
. ..11 . 1 ..11 .1... .11.. .. 1.... .111 1111 .... .1 11 ....
0436 jmp(prgex3) ; else goto program exeption
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; with 3 wait for hc2901.
; second entry in get double word from memory
; with protection check.
; -------------------------------------------
0437 getdo2: mover(wrk1,addrs) ; wrk1 := addrs.
. 111. . 1 .... .1... .11.. .. 1.... .111 1.1. .... .1 11 ....
0440 andinv(wrk1,1) ; wrk1.lsb := 0.
. 111. . 1 .... .1... 1..1. .. 11... .... 1.1. .... .. .. ...1
; (remove possible uneven address.)
0441 sub(wrk1,2) ; wrk1 := wrk1 - 2.
. 111. . 1 .... .1... ...1. .1 11... .... 1.1. .... .. .. ..1.
0442 cjmp(neg,getdo4) mover(wrk0,w3) ; if new address < 0 then
. ..11 . 1 1111 .1... .11.. .. 1.... .... 1111 .... .1 11 ....
; data word in register w3)
; goto getdo4,
0443 sub(wrk1,6) noload ; if address < 6 then
. 111. . 1 .... 11... ...1. .1 11... .... 1.1. .... .. .. .11.
0444 cjmp(less,regge1) mover(wrk0,wrk1) srgt holdmy; wrk0 := address shift -1,
. ..11 1 1 ..11 ...11 .11.. .. 1.... 1.1. 1111 .... .1 11 ....
; hold condition, goto regge1.
0445 cjmp(great,getop3) clwr01 ; if address > 6 then
. ..11 . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
; clock write hc2901 and goto
; wait for last operand in
; getop3.
; else
0446 jmp(regge1) ; if address = 6 then
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; (previus was memory(8))
; goto regget ( clock of
; write ready was done in
; just previus micro insteuction.
0447 getdo4: rtn mover(addrs,6) ; addrs := 6 , and return from
1 1.1. . 1 .... .1... .11.. .. 11... .... .111 .... .. .. .11.
; subroutine.
; subroutine putoperand.
; ----------------------
; call: address in reg. 'addrs'
; operand in reg. 'q'.
; destroyed: wrk0.
0450 putop: sub(addrs,8) noload ; if addrs < 8 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .. 1...
0451 cjmp(less,regput) mover(wrk0,addrs); then goto put register.
. ..11 . 1 ..11 .1... .11.. .. 1.... .111 1111 .... .1 11 ....
0452 add(wrk0,base) ; wrk0 := addr+ base.
. 111. . 1 .... .1... ..11. .. 1.... 1..1 1111 .... .1 11 ....
0453 sub(wrk0,uplim) noload ; if wrk0 >= uppper limit then
. 111. . 1 .... 11... ...1. .1 1.... 11.1 1111 .... .1 11 ....
0454 cjmp(greq,prgexp) sub(wrk0,lowlim) noload; goto program exeption
. ..11 . 1 ..1. 11... ...1. .1 1.... 111. 1111 .... .1 11 ....
; else if wrk0 < lower limit then
0455 cjmp(less,prgexp) ; then goto program exeption.
. ..11 . 1 ..11 11... ....1 .. 1.... .... .... .... .1 11 ....
0456 invr(hc2901,'e01pmw) ; call function put operand
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; protected.
0457 andinv(wrk0,1) ; remove possible uneven address
. 111. . 1 .... .1... 1..1. .. 11... .... 1111 .... .. .. ...1
; bit in address.
0460 putop1: cjmp(re2901,putop1) clre01 ;
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0461 invs(hc2901,wrk0) ; send fysical address to hc2901.
. 111. . 1 .... 11... .1.1. .. 1...1 .... 1111 .... .1 11 ....
0462 putop2: cjmp(re2901,putop2) clre01 ;
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0463 invs(hc2901,q) ; send data word to hc2901.
. 111. . 1 .... 11... .1.11 .. 1...1 .... .... .... .1 11 ....
0464 putop3: cjmp(re2901,putop3) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0465 inctwo(ic) ; ic := ic + 2 ( next 8000 instr:).
. 111. . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
0466 sub(ic,wrk0) noload ; if next ic <> from just used physical
. 111. . 1 .... 11... ...1. .1 1.... 1111 .1.1 .... .1 11 ....
0467 cjmp(nzero,pficin) ; then goto prefetch next instr else
. ..11 . 1 .1.. 11... ....1 .. 1.... .... .... .... .1 11 ....
0470 jmp(nopfic) ; goto get 8000 instr: with no prefetch.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0471 regput: cjmp(neg,intexp) mover(wrk0,wrk0) srgt; if the effective address is
. ..11 . 1 1111 ...11 .11.. .. 1.... 1111 1111 .... .1 11 ....
; negative then goto intexp,
; shift wrk1 1 rigth so wrk1
; contains absolute register no.
0472 add(wrk0,'regpu0) ;
. 111. . 1 .... .1... ..11. .. 11... .... 1111 .... .. .. ....
0473 ldctre(wrk0)
. 11.. . 1 .... 11... .11.1 .. 1.1.. 1111 ..1. .... .1 11 ....
0474 cjmrd(neg,intexp) ;
. .111 . 1 1111 11... ....1 .. 1.... .... .... .... .1 11 ....
0475 regpu0: jmp(pfneic) moves(w0, q)
1 ..11 . 1 .... .1... .1..1 .. 1.... .... ..11 .... .1 11 ....
0476 regpu1: jmp(pfneic) moves(w1,q)
1 ..11 . 1 .... .1... .1..1 .. 1.... .... ..1. .... .1 11 ....
0477 regpu2: jmp(pfneic) moves(w2,q)
1 ..11 . 1 .... .1... .1..1 .. 1.... .... ...1 .... .1 11 ....
0500 regpu3: jmp(pfneic) moves(w3,q)
1 ..11 . 1 .... .1... .1..1 .. 1.... .... .... .... .1 11 ....
;*page: XXX
; address handling
; ----------------
; HC8000 instr: next address, modify: 'am', numeric code 9.
; ------------------------------------------------------
0501 am/'9: sub(ic,8) noload ; if ic >= 10 (i.e ic + 2) then
. 111. . 1 .... 11... ...1. .1 11... .... .1.1 .... .. .. 1...
0502 cjmp(greq,ftcam) inctwo(ic) ; goto fetch 8000 instr: after
. ..11 . 1 ..1. .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; address modify (entry in
; prefetch 8000 instr:),
; ic := ic + 2.
0503 jmp(regins) ; else goto regins ( 8000 instr: in
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; register or location 8).
; HC8000 instr: address, load: 'al', numeric code 11.
; --------------------------------------------------
0504 al/'11: jmp(pfneic) mover(wreg,addrs) ; w_reg(index) := addrs,
1 ..11 . 1 .... .1... .11.. .. 1.1.. .111 .... .... .1 11 ....
; goto pfneic
; HC8000 instr: address complemented, load: 'ac', numeric code 33.
; --------------------------------------------------------------
0505 ac/'33: andinv(ex,3) ; ex(carry) := ex(overflow) := 0.
. 111. . 1 .... .1... 1..1. .. 11... .... .1.. .... .. .. ..11
0506 jmp(ccowc) invr1(wreg,addrs) ; w_reg(index) := not(addrs)+1,
1 ..11 . 1 .... .1... .111. .1 1.1.. .111 .... .... .1 11 ....
; goto ccowc.
;*page: XXX
; register transfer.
; ------------------
; HC8000 instr: half register, load: 'hl', numreic code 3.
; -------------------------------------------------------
0507 hl/'3: jsb(getop) ; wrk0 := core(addrs),
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0510 and(addrs,1) noload ; if addrs(23) = 0 ( addrs even) then
. 111. . 1 .... 11... 11... .. 11... .... .111 .... .. .. ...1
0511 cjmp(zero,hl1) ; goto hl1,
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
0512 mover(wrk0,wrk0) hmrl ; wrk0(0:11) := wrk0(12:23)
. 111. . 1 .... .1... .11.. .. ..... 1111 1111 .... .1 .. ....
0513 hl1: mover(wreg,wrk0) hmlr ; w_reg(index,12:23) := wrk0(0:11),
. 111. . 1 .... .1... .11.. .. ..1.. 1111 .... .... .1 .1 ....
0514 cont nothm csmy ; reset half word move logic
. 111. . 1 .... 11... ....1 .. ..... .... .... .... .1 11 ....
0515 jmp(pficin) inctwo(ic) ; goto pfneic, ic := ic +2.
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; HC8000 instr: half register, store: 'hs', numeric code 26.
; --------------------------------------------------------
0516 hs/'26: jsb(getop) moves(q,wreg) ; wrk0( := core(addrs), q := w_reg(index)
1 ...1 . 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
0517 hsnoen: and(addrs,1) noload ; normalisze single and double entry:
. 111. . 1 .... 11... 11... .. 11... .... .111 .... .. .. ...1
; if addrs(23) = 0 ( addrs even) then
0520 cjmp(zero,hs1) moves(wrk1,q) ; goto hs1, wrk1 := q,
. ..11 . 1 .1.1 .1... .1..1 .. 1.... .... 1.1. .... .1 11 ....
0521 mover(wrk1,wrk1) hmrl ; wrk1(12:23) := wrk1(0:11),
. 111. . 1 .... .1... .11.. .. ..... 1.1. 1.1. .... .1 .. ....
0522 mover(wrk0,wrk1) hmlr ; wrk0(12:23) := wrk1(0:11).
. 111. . 1 .... .1... .11.. .. ..... 1.1. 1111 .... .1 .1 ....
0523 mover(q,wrk0) nothm csmy shinz ; q:=wrk0, reset half word move
. 111. . 1 .... .11.. .11.1 .. ..... 1111 .... .... .1 11 ....
; logic.
0524 jmp(putop) ; goto putop.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0525 hs1: mover(wrk0,wrk1) hmrl ; wrk0(0:11):= wrk1(12:23)
. 111. . 1 .... .1... .11.. .. ..... 1.1. 1111 .... .1 .. ....
0526 mover(q,wrk0) nothm csmy shinz ; q:=wrk0, reset half word
. 111. . 1 .... .11.. .11.1 .. ..... 1111 .... .... .1 11 ....
; move logic.
0527 jmp(putop) ; goto putop.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; HC8000 instr: register, load: 'rl', numeric code 20.
; ---------------------------------------------------
0530 rl/'20: jsb(getop) ; wrk0 := core(addrs)
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0531 jmp(pfneic) mover(wreg,wrk0) ; w_reg(index) := wrk0, goto pfneic
1 ..11 . 1 .... .1... .11.. .. 1.1.. 1111 .... .... .1 11 ....
; HC8000 instr: register, store: 'rs', numeric code 23.
; ---------------------------------------------------
0532 rs/'23: jmp(putop) moves(q,wreg) ;q := w_reg(index), goto putop.
1 ..11 . 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
; HC8000 instr: register and memory word, exchange: 'rx', numeric code 25.
; ----------------------------------------------------------------------
0533 rx/'25: jsb(getop) moves(q,wreg) ; q := w_reg(index) call subroutine get operand from memory
1 ...1 . 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
0534 jmp(putop) mover(wreg,wrk0) ; w_reg(index) := wrk0,
1 ..11 . 1 .... .1... .11.. .. 1.1.. 1111 .... .... .1 11 ....
; goto putop, (addrs(core) := q)
; HC8000 instr: double register, load: 'dl', numeric code 54.
; ---------------------------------------------------------
0535 dl/'54: jsb(getdo1) ;
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0536 jsb(getdo2) mover(wreg,wrk0) ;
1 ...1 . 1 .... .1... .11.. .. 1.1.. 1111 .... .... .1 11 ....
0537 jmp(pfneic) mover(wpre,wrk0) ;move word previus to address
1 ..11 . 1 .... .1... .11.. .. 1.1.. 1111 ...1 .... .1 11 ....
; to register previus to selected
; register, goto get nest prefetched
; instruction.
; HC8000 instr: double register, store: 'ds', numeric code 55.
; -----------------------------------------------------------
0540 ds/'55: sub(addrs,8) noload ; if addrs >= 8 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .. 1...
0541 cjmp(greq,ds4) mover(wrk1,addrs); goto ds4, wrk1 := addrs.
. ..11 . 1 ..1. .1... .11.. .. 1.... .111 1.1. .... .1 11 ....
0542 cjmp(neg,prgexp) ; if addrs is negative then goto
. ..11 . 1 1111 11... ....1 .. 1.... .... .... .... .1 11 ....
; program exeption.
0543 andinv(wrk1,1) ; remove possible last bit in address.
. 111. . 1 .... .1... 1..1. .. 11... .... 1.1. .... .. .. ...1
0544 add(wrk1,'ds7) ; add mic. address
. 111. . 1 .... .1... ..11. .. 11... .... 1.1. .... .. .. ....
; of first load sentence to no of reg.
0545 ldctre(wrk1) ; load mic sekvens counter with
. 11.. . 1 .... 11... .11.1 .. 1.1.. 1.1. ..1. .... .1 11 ....
; counter with addrs + addres of
; first instr. of load reg.
; instr.
0546 cjmrd(neg,intexp) moves(q,wreg) ; jump indexed by counter to
. .111 . 1 1111 .11.. .1... .. 1.1.. .... .... .... .1 11 ....
; to micro. instr based by ds7,
; q := wreg(index).
0547 ds7: moves(w0,q) ; w0 := q.
. 111. . 1 .... .1... .1..1 .. 1.... .... ..11 .... .1 11 ....
0550 jmp(regpu3) moves(q,wpre) ; q := wreg(index-1) , goto reg put 3.
1 ..11 . 1 .... .11.. .1... .. 1.1.. .... ...1 .... .1 11 ....
0551 moves(w1,q) ; w1 := q.
. 111. . 1 .... .1... .1..1 .. 1.... .... ..1. .... .1 11 ....
0552 jmp(regpu0) moves(q,wpre) ; q := wreg(index-1) , goto reg put w0.
1 ..11 . 1 .... .11.. .1... .. 1.1.. .... ...1 .... .1 11 ....
0553 moves(w2,q) ; w2 := q.
. 111. . 1 .... .1... .1..1 .. 1.... .... ...1 .... .1 11 ....
0554 jmp(regpu1) moves(q,wpre) ; q := wreg(index-1) , goto reg put w1.
1 ..11 . 1 .... .11.. .1... .. 1.1.. .... ...1 .... .1 11 ....
0555 moves(w3,q) ; w3 := q.
. 111. . 1 .... .1... .1..1 .. 1.... .... .... .... .1 11 ....
0556 jmp(regpu2) moves(q,wpre) ; q := wreg(index-1) , goto reg put w2.
1 ..11 . 1 .... .11.. .1... .. 1.1.. .... ...1 .... .1 11 ....
0557 ds4: andinv(wrk1,1) ; remove possible last bit in address.
. 111. . 1 .... .1... 1..1. .. 11... .... 1.1. .... .. .. ...1
0560 add(wrk1,base) ; wrk1 := wrk1 ( addrs) + base.
. 111. . 1 .... .1... ..11. .. 1.... 1..1 1.1. .... .1 11 ....
0561 sub(wrk1,uplim) noload ; if wrk1 => uplim then
. 111. . 1 .... 11... ...1. .1 1.... 11.1 1.1. .... .1 11 ....
0562 cjmp(greq,prgexp) mover(wrk2,wrk1); goto program exeption.
. ..11 . 1 ..1. .1... .11.. .. 1.... 1.1. 1.11 .... .1 11 ....
0563 sub(wrk2,2) ; wrk2 := wrk2 - 2.
. 111. . 1 .... .1... ...1. .1 11... .... 1.11 .... .. .. ..1.
0564 sub(wrk2,lowlim) noload ; if wrk2 < lowlimt then
. 111. . 1 .... 11... ...1. .1 1.... 111. 1.11 .... .1 11 ....
0565 cjmp(less,prgexp) ; goto program exeption.
. ..11 . 1 ..11 11... ....1 .. 1.... .... .... .... .1 11 ....
0566 invr(hc2901,'e01pdw) ; clock the hc2901 with the
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; entry address put double word
; unprotected.
0567 ds1: cjmp(re2901,ds1) clre01 ; wait for the hc2901 to be ready
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
; to recieve first storage address.
0570 invs(hc2901,wrk1) ; hc2901 := wrk1.
. 111. . 1 .... 11... .1.1. .. 1...1 .... 1.1. .... .1 11 ....
0571 moves(q,wreg) ; move wreg(index) to q register.
. 111. . 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
0572 ds2: cjmp(re2901,ds2) clre01 ; wait for the hc2901 to be ready
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
; to recieve first data word.
0573 invs(hc2901,q) ; hc2901 := q.
. 111. . 1 .... 11... .1.11 .. 1...1 .... .... .... .1 11 ....
0574 moves(q,wpre) ; move wreg(index-1) to q register.
. 111. . 1 .... .11.. .1... .. 1.1.. .... ...1 .... .1 11 ....
0575 ds3: cjmp(re2901,ds3) clre01 ; wait for the hc2901 to be
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
; ready for recieving the next
; data word.
0576 invs(hc2901,q) ; hc2901 := q.
. 111. . 1 .... 11... .1.11 .. 1...1 .... .... .... .1 11 ....
0577 inctwo(ic) ; ic := ic + 2.
. 111. . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
0600 ds6: cjmp(re2901,ds6) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
0601 sub(wrk1,ic) noload ; if wrk1 = next ic then goto
. 111. . 1 .... 11... ...1. .1 1.... .1.1 1.1. .... .1 11 ....
0602 cjmp(equal,nopfic) sub(wrk2,ic) noload; goto nopfic
. ..11 . 1 .1.1 11... ...1. .1 1.... .1.1 1.11 .... .1 11 ....
; if addrs = next ic then
0603 cjmp(equal,nopfic) ; goto nopfic.
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
0604 jmp(pficin) ; else goto nexti2.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; HC8000 instr: exeption register, load: 'xl', numeric code 16.
; -----------------------------------------------------------
0605 xl/'16: jsb(getop) ; call getop,
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0606 and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) then
. 111. . 1 .... 11... 11... .. 11... .... .111 .... .. .. ...1
0607 cjmp(nzero,xl1) ; goto xl1.
. ..11 . 1 .1.. 11... ....1 .. 1.... .... .... .... .1 11 ....
0610 mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
. 111. . 1 .... .1... .11.. .. ..... 1111 1111 .... .1 .1 ....
0611 xl1: and(wrk0,7) csmy nothm csmy shinz; wrk0:= wrk0(21:23) reset move
. 111. . 1 .... .1... 11... .. .1... .... 1111 .... .1 11 ....
; half word logic.
0612 jmp(pfneic) or(ex,wrk0) ; ex := ex or wrk0,
1 ..11 . 1 .... .1... 1111. .. 1.... 1111 .1.. .... .1 11 ....
; goto pfneic.
; HC8000 instr: exeption register, store: 'xs', numeric code 27.
; ------------------------------------------------------------
0613 xs/'27: and(q,ex,7) ; q:= ex, (i.e. status(21:23)).
. 111. . 1 .... .11.. 11... .. 11... .... .1.. .... .. .. .111
0614 jsb(getop) ; call getop.
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0615 and(addrs,1) noload ; if addrs(23) = 1 ( addrs odd ) then
. 111. . 1 .... 11... 11... .. 11... .... .111 .... .. .. ...1
0616 cjmp(zero,xs1) moves(wrk1,q) ; goto xs1, wrk1 := q.
. ..11 . 1 .1.1 .1... .1..1 .. 1.... .... 1.1. .... .1 11 ....
0617 mover(wrk1,wrk1) hmrl ; wrk1(0:11) := wrk1(12:23).
. 111. . 1 .... .1... .11.. .. ..... 1.1. 1.1. .... .1 .. ....
0620 mover(wrk0,wrk1) hmlr ; wrk0(12:23) := wrk(0:11).
. 111. . 1 .... .1... .11.. .. ..... 1.1. 1111 .... .1 .1 ....
0621 jmp(putop) mover(q,wrk0) ; q:=wrk0, goto putop.
1 ..11 . 1 .... .11.. .11.1 .. 1.... 1111 .... .... .1 11 ....
0622 xs1: mover(wrk0,wrk1) hmrl ; wrk0(0:11) := wrk1(wrk1(12:23)
. 111. . 1 .... .1... .11.. .. ..... 1.1. 1111 .... .1 .. ....
0623 cont csmy nothm shinz ; clear half word move logic.
. 111. . 1 .... 11... ....1 .. ..... .... .... .... .1 11 ....
0624 jmp(putop) mover(q,wrk0) ; q:=wrk0, reset half word move
1 ..11 . 1 .... .11.. .11.1 .. 1.... 1111 .... .... .1 11 ....
; logic, goto putop.
; integer halfword arithmetic
; ---------------------------
; HC8000 instr: integer byte, load (zero extension): 'bz', numeric code 19.
; ------------------------------------------------------------------------
0625 bz/'19: jsb(getop) ; call getop.
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0626 and(addrs,1) noload ; if addrs(23) = 0 (addrs even) then
. 111. . 1 .... 11... 11... .. 11... .... .111 .... .. .. ...1
0627 cjmp(zero,bz1)mzero(wreg) ; goto bz1, reset selected working
. ..11 . 1 .1.1 .1... 1.... .. 1.1.. .... .... .... .1 11 ....
; register.
0630 mover(wrk0,wrk0) hmrl ; wrk0(0:11) := wrk0(12:23).
. 111. . 1 .... .1... .11.. .. ..... 1111 1111 .... .1 .. ....
0631 bz1: mover(wreg,wrk0) hmlr ; w_regg(index,12:23):=wrk0(0:11).
. 111. . 1 .... .1... .11.. .. ..1.. 1111 .... .... .1 .1 ....
0632 cont csmy nothm csmy shinz ; reset half word move control
. 111. . 1 .... 11... ....1 .. ..... .... .... .... .1 11 ....
0633 jmp(pficin) inctwo(ic) ; goto pfneic, ic := ic + 2.
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; HC8000 instr: integer byte, load (sign extension): 'bl', numeric code 2.
; ----------------------------------------------------------------------
0634 bl/'2: jsb(getop) ; call getop.
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0635 and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) then
. 111. . 1 .... 11... 11... .. 11... .... .111 .... .. .. ...1
0636 cjmp(nzero,bl1) inctwo(ic) ; goto bl1, ic := ic + 2.
. ..11 . 1 .1.. .1... ..... .1 1.... .... .1.1 .... .1 11 ....
0637 mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
. 111. . 1 .... .1... .11.. .. ..... 1111 1111 .... .1 .1 ....
0640 cont csmy nothm csmy shinz ; reset half word move control
. 111. . 1 .... 11... ....1 .. ..... .... .... .... .1 11 ....
0641 bl1: jmp(pficin) mover(wreg,wrk0) signex; w_reg(index)
1 ..11 . 1 .... 111.1 .11.. .. 1.1.. 1111 .... .... .1 11 ....
; := signextend(wrk0(12:23)),
; goto pfneic.
; HC8000 instr: integer byte, add: 'ba', numeric code 18.
; -----------------------------------------------------
ba/'18: ; ex(carry):=ex(overflow):=0.
0642 jsb(getop) andinv(ex,wrk2) ; call getop
1 ...1 . 1 .... .1... 1..1. .. 1.... 1.11 .1.. .... .1 11 ....
0643 and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) the
. 111. . 1 .... 11... 11... .. 11... .... .111 .... .. .. ...1
0644 cjmp(nzero,ba1) ; goto ba1.
. ..11 . 1 .1.. 11... ....1 .. 1.... .... .... .... .1 11 ....
0645 mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
. 111. . 1 .... .1... .11.. .. ..... 1111 1111 .... .1 .1 ....
0646 cont csmy nothm csmy shinz ; reset half word move control
. 111. . 1 .... 11... ....1 .. ..... .... .... .... .1 11 ....
0647 ba1: mover(wrk0,wrk0) signex ; signextend(wrk0(12:23)).
. 111. . 1 .... 111.1 .11.. .. 1.... 1111 1111 .... .1 11 ....
0650 jmp(ccowc) add(wreg,wrk0) ; w_reg(index) := w_reg(index)
1 ..11 . 1 .... .1... ..11. .. 1.1.. 1111 .... .... .1 11 ....
; + wrk0, goto ccowc.
; HC8000 instr: integer byte subtract: 'bs', numeric code 17.
; ---------------------------------------------------------
bs/'17: ; ex(carry):=ex(overflow):=0.
0651 jsb(getop) andinv(ex,wrk2) ; call getop.
1 ...1 . 1 .... .1... 1..1. .. 1.... 1.11 .1.. .... .1 11 ....
0652 and(addrs,1) noload ; if addrs(23) = 1 (addrs odd) then
. 111. . 1 .... 11... 11... .. 11... .... .111 .... .. .. ...1
0653 cjmp(nzero,bs1) ; goto bs1.
. ..11 . 1 .1.. 11... ....1 .. 1.... .... .... .... .1 11 ....
0654 mover(wrk0,wrk0) hmlr ; wrk0(12:23) := wrk0(0:11).
. 111. . 1 .... .1... .11.. .. ..... 1111 1111 .... .1 .1 ....
0655 cont csmy nothm csmy shinz ; reset half word mov control
. 111. . 1 .... 11... ....1 .. ..... .... .... .... .1 11 ....
0656 bs1: mover(wrk0,wrk0) signex ; signextend(wrk0(12:23)).
. 111. . 1 .... 111.1 .11.. .. 1.... 1111 1111 .... .1 11 ....
0657 jmp(ccowc) sub(wreg,wrk0) ; w_reg(index):=w_reg(index)
1 ..11 . 1 .... .1... ...1. .1 1.1.. 1111 .... .... .1 11 ....
; - wrk0, goto ccowc.
; integer word arithmetic
; ------------------------
; HC8000 instr: integer word, add: 'wa', numeric code 7.
; ----------------------------------------------------
wa/'7: ; ex(carry):=ex(overflow):=0.
0660 jsb(getop) andinv(ex,wrk2) ; call subroutine get operand from memory.
1 ...1 . 1 .... .1... 1..1. .. 1.... 1.11 .1.. .... .1 11 ....
0661 jmp(ccowc) add(wreg,wrk0) ; w_reg(index) := w_reg(index) +
1 ..11 . 1 .... .1... ..11. .. 1.1.. 1111 .... .... .1 11 ....
; wrk0, goto ccowc.
; HC8000 instr: integer word, subtract: 'ws', numeric code 8.
; ---------------------------------------------------------
ws/'8: ; ex(carry):=ex(overflow):=0.
0662 jsb(getop) andinv(ex,wrk2) ; call subroutine get operand from memory.
1 ...1 . 1 .... .1... 1..1. .. 1.... 1.11 .1.. .... .1 11 ....
0663 jmp(ccowc) sub(wreg,wrk0) ; w_reg(index) := w_reg(index) -
1 ..11 . 1 .... .1... ...1. .1 1.1.. 1111 .... .... .1 11 ....
; wrk0, goto ccowc.
; HC8000 instr: integer word, multiply: 'wm', numeric code 10.
; ----------------------------------------------------------
0664 wm/'10: jsb(getop) moves(q,wreg) ; call getop, q := wreg(index).
1 ...1 . 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
0665 lcpu(22) mzero(wrk2) ; push next micro instr to stack
1 .1.. . 1 .... .1... 1.... .. 1.... .... 1.11 .... .. .1 .11.
; mic. sekv. counter := 23,
; wrk2 := 0.
0666 rep mult2c(wrk2,wrk0) dshinz ;
. 1... . 1 .... ..1.. ..... .. ..... 1111 1.11 .... .1 11 .11.
0667 mult2l(wrk2,wrk0) ;
. 111. . 1 .... .11.. ..... 1. 1.... 1111 1.11 .... .1 11 ....
0670 mover(wpre,wrk2) nothm csmy shinz; wreg(index) := wrk2.
. 111. . 1 .... .1... .11.. .. ..1.. 1.11 ...1 .... .1 11 ....
0671 jmp(pfneic) moves(wreg,q) ; goto pfneic, wreg(index-1) := q.
1 ..11 . 1 .... .1... .1..1 .. 1.1.. .... .... .... .1 11 ....
; ========
; division
; ========
; division moved to en program until final version.
; integer double word arithmetic.
; -------------------------------
; removed until final
;*onlyin: final
; HC8000 instr: integer double word, add: 'aa', numeric code 56.
; ------------------------------------------------------------
aa/'56: ; ex(carry):=ex(overflow):=0.
0672 jsb(getdo1) andinv(ex,wrk2) ; call subroutine get operand from memory.
1 ...1 . 1 .... .1... 1..1. .. 1.... 1.11 .1.. .... .1 11 ....
0673 add(wreg,wrk0) ; w_reg(index) := w_reg(index) +
. 111. . 1 .... .1... ..11. .. 1.1.. 1111 .... .... .1 11 ....
; wrk0.
0674 cjmp(carry,aa1) ; if carry then goto aa1.
. ..11 . 1 1.11 11... ....1 .. 1.... .... .... .... .1 11 ....
0675 jsb(getdo2) ; call(getd2o).
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0676 jmp(ccowc) add(wpre,wrk0) ; w_reg(index-1):=w_reg(index-1)
1 ..11 . 1 .... .1... ..11. .. 1.1.. 1111 ...1 .... .1 11 ....
; + wrk0, goto ccowc.
0677 aa1: jsb(getdo2) ; call(getdo2).
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0700 jmp(ccowc) add1(wpre,wrk0) ; w_reg(index-1):=w_reg(index-1)
1 ..11 . 1 .... .1... ..11. .1 1.1.. 1111 ...1 .... .1 11 ....
; + wrk0 + 1, goto ccowc.
; HC8000 instr: integer double word, subtract: 'ss', numeric code 57.
; -----------------------------------------------------------------
ss/'57: ; ex(carry):=ex(overflow):=.
0701 jsb(getdo1) andinv(ex,wrk2) ; call(getdo1).
1 ...1 . 1 .... .1... 1..1. .. 1.... 1.11 .1.. .... .1 11 ....
0702 sub(wreg,wrk0) ; w_reg(index) := w_reg(index) -
. 111. . 1 .... .1... ...1. .1 1.1.. 1111 .... .... .1 11 ....
; wrk0.
0703 cjmp(carry,ss1) ; if carry then goto ss1.
. ..11 . 1 1.11 11... ....1 .. 1.... .... .... .... .1 11 ....
0704 jsb(getdo2) ; call(getdo2).
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0705 jmp(ccowc) sub(wpre,wrk0) ; w_reg(index-1):=w_reg(index-1)
1 ..11 . 1 .... .1... ...1. .1 1.1.. 1111 ...1 .... .1 11 ....
; - wrk0, goto ccowc.
0706 ss1: jsb(getdo2) ; call(getdo2).
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0707 jmp(ccowc) sub1(wpre,wrk0) ; w_reg(index-1):=w_reg(index-1)
1 ..11 . 1 .... .1... ...1. .. 1.1.. 1111 ...1 .... .1 11 ....
; - wrk0 + 1, goto ccowc.
;*until: final
; logical operation.
; ------------------
; HC8000 instr: logical and: 'la', numeric code 4.
; ----------------------------------------------
0710 la/'4: jsb(getop) ; call subroutine get operand from memory.
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0711 jmp(pfneic) and(wreg,wrk0) ; w_reg(index):=w_reg(index)
1 ..11 . 1 .... .1... 11... .. 1.1.. 1111 .... .... .1 11 ....
; and wrk0, goto pfneic.
; HC8000 instr: logical or: 'lo', numeric code 5.
; ---------------------------------------------
0712 lo/'5: jsb(getop) ; call subroutine get operand from memory.
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0713 jmp(pfneic) or(wreg,wrk0) ; w_reg(index) := w_reg(index) or
1 ..11 . 1 .... .1... 1111. .. 1.1.. 1111 .... .... .1 11 ....
; wrk0, goto pfneic.
; HC8000 instr: logical exclusive or: 'lx', numeric code 6.
; -------------------------------------------------------
0714 lx/'6: jsb(getop) ; call subroutine get operand from memory.
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0715 jmp(pfneic) exor(wreg,wrk0) ; w_reg(index) := w_reg(index) exor
1 ..11 . 1 .... .1... 1.11. .. 1.1.. 1111 .... .... .1 11 ....
; wrk0, goto pfneic.
;*page: XXX
; shift operations.
; -----------------
;
;*skip: ashift .
; HC8000 instr: aritmetically shift single: 'as', numeric code 36.
; --------------------------------------------------------------
0716 as/'36: andinv(ex,3) ; ex(carry):=ex(overflow):=0.
. 111. . 1 .... .1... 1..1. .. 11... .... .1.. .... .. .. ..11
0717 sub(addrs,0) noload ; if addrs > 0 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .. ....
0720 cjmp(great,as1) moves(q,wreg) holdmy; goto as2, q:=w_reg(index), hold condition.
. ..11 1 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
0721 cjmp(less,as2) moves(wrk1,q) ; if addrs < 0 then goto as2, wrk1:=q.
. ..11 . 1 ..11 .1... .1..1 .. 1.... .... 1.1. .... .1 11 ....
0722 jmp(pfneic) ; if addrs = 0 then goto pfneic..
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0723 as1: sub(addrs,24) noload ; if addrs < 24 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .1 1...
0724 cjmp(less,as4) moves(wrk1,q) ; goto as4, wrk1:=q.
. ..11 . 1 ..11 .1... .1..1 .. 1.... .... 1.1. .... .1 11 ....
0725 mover(addrs,24) ; addrs := 24.
. 111. . 1 .... .1... .11.. .. 11... .... .111 .... .. .1 1...
0726 as4: sub(addrs,1) ; addrs := addrs - 1.
. 111. . 1 .... .1... ...1. .1 11... .... .111 .... .. .. ...1
0727 pushre(addrs) ; counter := addrs,
1 .1.. . 1 .... 11... .11.1 .. 1.1.. .111 ..1. .... .1 11 ....
0730 twb(over,as5) mover(wrk1,wrk1) slft; wrk1:= leftshift_1(wrk1),wrk1(0):=0.
. 1111 . 1 .111 1..11 .11.. .. 1.... 1.1. 1.1. .... .1 11 ....
0731 as6: rpct(as6) mover(wrk1,wrk1) slft ; repeat this while counter <> 0
. 1..1 . 1 .... 1..11 .11.. .. 1.... 1.1. 1.1. .... .1 11 ....
; (wrk := left_shift_1(wrk1) ,wrk(0):=0,
; decrease (counter) ).
0732 mover(wreg,wrk1) ; w_reg(index):=wrk1.
. 111. . 1 .... .1... .11.. .. 1.1.. 1.1. .... .... .1 11 ....
0733 or(ex,2) ; ex(overflow) := 1.
. 111. . 1 .... .1... 1111. .. 11... .... .1.. .... .. .. ..1.
0734 and(status,16) noload ; if integer mask = 1 then
. 111. . 1 .... 11... 11... .. 11... .... .1.. .... .. .1 ....
0735 cjmp(zero,pfneic) ; goto pfneic.
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
0736 jmp(intexp) ; goto integer exeption.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0737 as2: cjmp(neg,as3) invr(wrk2,addrs) ; if q (i.e wreg) < 0 then
. ..11 . 1 1111 .1... .111. .. 1.... .111 1.11 .... .1 11 ....
; goto as3, wrk2 := abs(addrs).
0740 sub(wrk2,23) noload ; if wrk2 > 23 then
. 111. . 1 .... 11... ...1. .1 11... .... 1.11 .... .. .1 .111
0741 cjmp(great,pfneic) mzero(wreg) ; goto pfneic, w_reg(index) :=0.
. ..11 . 1 .... .1... 1.... .. 1.1.. .... .... .... .1 11 ....
0742 sub(wrk1,1) ; wrk2 := wrk2 - 1.
. 111. . 1 .... .1... ...1. .1 11... .... 1.1. .... .. .. ...1
0743 pushre(wrk2) ; counter := wrk2.
1 .1.. . 1 .... 11... .11.1 .. 1.1.. 1.11 ..1. .... .1 11 ....
; push next mic.instr addres.
0744 rep mover(wrk1,wrk1) slft shinz ;
. 1... . 1 .... 1..11 .11.. .. ..... 1.1. 1.1. .... .1 11 ....
0745 jmp(pfneic) mover(wreg,wrk1) ; w_reg(index) := wrk1, goto nein
1 ..11 . 1 .... .1... .11.. .. 1.1.. 1.1. .... .... .1 11 ....
0746 as3: sub(addrs,23) noload ; if addrs > 23 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .1 .111
0747 cjmp(great,pfneic) ;
. ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0750 sub(addrs,1) ; addrs := addrs - 1.
. 111. . 1 .... .1... ...1. .1 11... .... .111 .... .. .. ...1
0751 pushre(addrs) ; counter := addrs.
1 .1.. . 1 .... 11... .11.1 .. 1.1.. .111 ..1. .... .1 11 ....
; push next mic. instr. address.
0752 rep mover(wrk1,wrk1) shin1 srgt ;
. 1... . 1 .... ...11 .11.. .. ..... 1.1. 1.1. .... .1 11 ...1
0753 as5: jmp(pfneic) mover(wreg,wrk1) ;
1 ..11 . 1 .... .1... .11.. .. 1.1.. 1.1. .... .... .1 11 ....
; HC8000 instr: arithmetically shift double: 'ad', numeric code 37.
; ---------------------------------------------------------------
0754 ad/'37: andinv(ex,3) ; ex(carry) := ex(overflow):=0.
. 111. . 1 .... .1... 1..1. .. 11... .... .1.. .... .. .. ..11
0755 sub(addrs,0) noload ; if addrs > 0 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .. ....
0756 cjmp(great,ad1) holdmy moves(q,wpre); goto ad2, q:= wreg(index-1).
. ..11 1 1 .... .11.. .1... .. 1.1.. .... ...1 .... .1 11 ....
0757 cjmp(less,ad2) moves(wrk1,q) ; else if addrs < 0 then goto ad2,
. ..11 . 1 ..11 .1... .1..1 .. 1.... .... 1.1. .... .1 11 ....
; wrk1 := q.
0760 jmp(pficin) inctwo(ic) ; goto pficin, ic := ic + 2.
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
0761 ad1: sub(addrs,48) noload
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. 11 ....
0762 cjmp(less,ad4) moves(wrk1,q) ; goto ad4, wrk1 := q.
. ..11 . 1 ..11 .1... .1..1 .. 1.... .... 1.1. .... .1 11 ....
0763 mover(addrs,48) ; addrs := 48.
. 111. . 1 .... .1... .11.. .. 11... .... .111 .... .. 11 ....
0764 ad4: moves(q,wreg) dshinz ; q := wreg(index).
. 111. . 1 .... .11.. .1... .. ..1.. .... .... .... .1 11 .11.
0765 sub(addrs,1) ; addrs := addrs - 1.
. 111. . 1 .... .1... ...1. .1 11... .... .111 .... .. .. ...1
0766 pushre(addrs) ; micro sekvens counter := addrs.
1 .1.. . 1 .... 11... .11.1 .. 1.1.. .111 ..1. .... .1 11 ....
; push next micro instr. addrs.
; to micro sekvenser stack.
0767 twb(over,ad3) mover(wrk1,wrk1) lftaql; repeat
. 1111 . 1 .111 1.111 .11.. .. 1.... 1.1. 1.1. .... .1 11 ....
; double shift wrk1 and q
; with zero input,
; mic. sekvens counter :=
; mic. sekvens counter -1.
; if mi. sekvens counter = 0 then
; goto ad5.
; until overflow.
0770 push ; if owerflow then
1 .1.. . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
0771 rep mover(wrk1,wrk1) lftaql ; repeat double shift wrk1 and q
. 1... . 1 .... 1.111 .11.. .. 1.... 1.1. 1.1. .... .1 11 ....
; with zero input,
; mic. secvens counter:=
; mic. sekvens counter - 1.
; until mic. sekvens counter = 0.
0772 mover(wreg,wrk1) ; wreg(index)
. 111. . 1 .... .1... .11.. .. 1.1.. 1.1. .... .... .1 11 ....
0773 mover(wpre,wrk1) ; wreg(index -1) := wrk1.
. 111. . 1 .... .1... .11.. .. 1.1.. 1.1. ...1 .... .1 11 ....
0774 moves(wreg,q) ; wreg(index) := q.
. 111. . 1 .... .1... .1..1 .. 1.1.. .... .... .... .1 11 ....
0775 or(ex,2) ; exeption(owerflow) := 1.
. 111. . 1 .... .1... 1111. .. 11... .... .1.. .... .. .. ..1.
0776 and(status,16) noload ; if integer mask = 1 then
. 111. . 1 .... 11... 11... .. 11... .... .1.. .... .. .1 ....
0777 cjmp(zero,pfneic) ; goto pfneic.
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
1000 jmp(intexp) ; goto intger exeption.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1001 ad3: moves(wreg,q) ; wreg(index) :=q.
. 111. . 1 .... .1... .1..1 .. 1.1.. .... .... .... .1 11 ....
1002 mover(wpre,wrk1) ; wreg(index-1) := wrk1.
. 111. . 1 .... .1... .11.. .. 1.1.. 1.1. ...1 .... .1 11 ....
1003 jmp(pfneic) ; goto pfneic.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1004 ad2: cjmp(neg,ad5) invr(wrk2,addrs) ; if q < 0 (i.e. wreg(index-1)) then
. ..11 . 1 1111 .1... .111. .. 1.... .111 1.11 .... .1 11 ....
; goto ad5, wrk2 := abs(addrs).
1005 sub(wrk2,47) noload ; if wrk2 (i.e. abs(addrs)) > 47 then
. 111. . 1 .... 11... ...1. .1 11... .... 1.11 .... .. 1. 1111
1006 cjmp(great,ad6) mzero(wpre) ; goto ad6, wreg(index-1) := 0.
. ..11 . 1 .... .1... 1.... .. 1.1.. .... ...1 .... .1 11 ....
1007 moves(q,wreg) dshinz ; q := wreg(index)
. 111. . 1 .... .11.. .1... .. ..1.. .... .... .... .1 11 .11.
1010 ad7: sub(wrk2,1) ; wrk2 := wrk2 - 1.
. 111. . 1 .... .1... ...1. .1 11... .... 1.11 .... .. .. ...1
1011 pushre(wrk2) ; mic. sekvens counter := wrk2.
1 .1.. . 1 .... 11... .11.1 .. 1.1.. 1.11 ..1. .... .1 11 ....
; push next mic. instr. address to
; to sekvens stack, set shift
; shift to double shift in zero.
1012 rep mover(wrk1,wrk1) rgtaql; repeat
. 1... . 1 .... ..111 .11.. .. 1.... 1.1. 1.1. .... .1 11 ....
; shift wrk1 and q rigth double
; with zero input from rigth.
; counter := counter - 1.
; until counter = 0.
1013 mover(wpre,wrk1) nothm csmy; wreg(index - 1) := wrk1,
. 111. . 1 .... .1... .11.. .. ..1.. 1.1. ...1 .... .1 11 ....
;
1014 jmp(pfneic) moves(wreg,q) ; wreg(index) := q, goto pfneic.
1 ..11 . 1 .... .1... .1..1 .. 1.1.. .... .... .... .1 11 ....
1015 ad5: sub(wrk2,47) noload ; if q < 47 then
. 111. . 1 .... 11... ...1. .1 11... .... 1.11 .... .. 1. 1111
1016 cjmp(great,ad8) ; goto ad8.
. ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1017 moves(q,wreg) dshin1 ; q := wreg, set shift logic
. 111. . 1 .... .11.. .1... .. ..1.. .... .... .... .1 11 ..11
; to doubble shift with 1 input.
1020 jmp(ad7)
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1021 ad6: jmp(pfneic) mzero(wreg) ; goto pfneic, wreg(index) := 0.
1 ..11 . 1 .... .1... 1.... .. 1.1.. .... .... .... .1 11 ....
1022 ad8: invr(wpre,0) ;
. 111. . 1 .... .1... .111. .. 111.. .... ...1 .... .. .. ....
1023 invr(wreg,0) ;
. 111. . 1 .... .1... .111. .. 111.. .... .... .... .. .. ....
1024 jmp(pfneic)
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
;*until: ashift .
; HC8000 instr: logically shift single: 'ls', numeric code 38.
; ----------------------------------------------------------
1025 ls/'38: sub(addrs,0) noload ; if addrs > 0 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .. ....
1026 cjmp(great,ls1) moves(q,wreg) holdmy; goto ls1, q:=w_reg(index), hold
. ..11 1 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
; condition bits.
1027 cjmp(less,ls2) moves(wrk1,q) ; if addrs < 0 then goto ls2, wrk1:=q.
. ..11 . 1 ..11 .1... .1..1 .. 1.... .... 1.1. .... .1 11 ....
1030 jmp(pficin) inctwo(ic) ; <* if addrs = 0 *> then goto
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; goto pficin, ic := ic + 2.
1031 ls1: sub(addrs,23) noload ; if addrs > 23 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .1 .111
1032 cjmp(great,pfneic) mzero(wreg) ; goto pfneic, w_reg(index):=0.
. ..11 . 1 .... .1... 1.... .. 1.1.. .... .... .... .1 11 ....
1033 sub(addrs,1) ; addrs := addrs - 1.
. 111. . 1 .... .1... ...1. .1 11... .... .111 .... .. .. ...1
1034 pushre(addrs) ; counter := 0.
1 .1.. . 1 .... 11... .11.1 .. 1.1.. .111 ..1. .... .1 11 ....
; push next mic. instr.
1035 rep mover(wrk1,wrk1) lftqil ; q_reg := q_reg shift left 1
. 1... . 1 .... 11.11 .11.. .. 1.... 1.1. 1.1. .... .1 11 ....
; the opration with the
; wrk1 reg is dummy.
1036 jmp(pfneic) moves(wreg,q) ; w_reg(index):=q, goto pfneic.
1 ..11 . 1 .... .1... .1..1 .. 1.1.. .... .... .... .1 11 ....
1037 ls2: invr1(wrk2,addrs) ; wrk2:=abs(addrs)
. 111. . 1 .... .1... .111. .1 1.... .111 1.11 .... .1 11 ....
1040 sub(wrk2,23) noload ; if addrs > 23 then
. 111. . 1 .... 11... ...1. .1 11... .... 1.11 .... .. .1 .111
1041 cjmp(great,pfneic) mzero(wreg) ; goto pfneic, w_reg(index):=0.
. ..11 . 1 .... .1... 1.... .. 1.1.. .... .... .... .1 11 ....
1042 sub(wrk2,1) ; wrk2 := wrk2 - 1.
. 111. . 1 .... .1... ...1. .1 11... .... 1.11 .... .. .. ...1
1043 pushre(wrk2) ; counter := wrk2.
1 .1.. . 1 .... 11... .11.1 .. 1.1.. 1.11 ..1. .... .1 11 ....
; push next mic. instr. address.
1044 rep mover(wrk1,wrk1) srgt shinz ; shift rigth zero input
. 1... . 1 .... ...11 .11.. .. ..... 1.1. 1.1. .... .1 11 ....
1045 jmp(pfneic) mover(wreg,wrk1) ; w_reg(index):= wrk1, goto prefn.
1 ..11 . 1 .... .1... .11.. .. 1.1.. 1.1. .... .... .1 11 ....
; HC8000 instr: logically shift double: 'ld', numeric code 39.
; ----------------------------------------------------------
;*onlyin: final
1046 ld/'39: sub(addrs,0) noload ; if addrs > 0 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .. ....
1047 cjmp(great,ld1) holdmy moves(q,wpre); goto ls1, hold condition bits,
. ..11 1 1 .... .11.. .1... .. 1.1.. .... ...1 .... .1 11 ....
; q := wreg(index - 1).
1050 cjmp(less,ld2) moves(wrk1,q) ; if addrs < 0 then goto ld2,
. ..11 . 1 ..11 .1... .1..1 .. 1.... .... 1.1. .... .1 11 ....
; wrk1 := q.
1051 jmp(pficin) inctwo(ic) ; ic := ic + 2, goto pficin.
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
1052 ld1: sub(addrs,47) noload ; if addrs > 47 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. 1. 1111
1053 cjmp(great,ld3) mzero(wpre) ; goto ld3, wreg(index-1) := 0.
. ..11 . 1 .... .1... 1.... .. 1.1.. .... ...1 .... .1 11 ....
1054 moves(wrk1,q) ; wrk1 := q.
. 111. . 1 .... .1... .1..1 .. 1.... .... 1.1. .... .1 11 ....
1055 moves(q,wreg) ; q := wreg(index).
. 111. . 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
1056 sub(addrs,1) ; addrs := addrs - 1.
. 111. . 1 .... .1... ...1. .1 11... .... .111 .... .. .. ...1
1057 pushre(addrs) ; micro sekvenser counter := addrs.
1 .1.. . 1 .... 11... .11.1 .. 1.1.. .111 ..1. .... .1 11 ....
; pusch next micro. instr addrs.
; to stack,
1060 rep mover(wrk1,wrk1) lftaql dshinz; shift wrk1 and q left with conection
. 1... . 1 .... 1.111 .11.. .. ..... 1.1. 1.1. .... .1 11 .11.
; until counter = 0.
1061 mover(wpre,wrk1) nothm csmy shinz; wreg(index-1) := wrk1.
. 111. . 1 .... .1... .11.. .. ..1.. 1.1. ...1 .... .1 11 ....
1062 jmp(pfneic) moves(wreg,q) ; w(index) := q, goto pficin.
1 ..11 . 1 .... .1... .1..1 .. 1.1.. .... .... .... .1 11 ....
1063 ld2: invr1(addrs,addrs) ; addrs := - addrs.
. 111. . 1 .... .1... .111. .1 1.... .111 .111 .... .1 11 ....
1064 sub(addrs,47) noload ; if addrs > 47 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. 1. 1111
1065 cjmp(great,ld3) mzero(wpre) ; goto ld3, wreg(index-1) :=0.
. ..11 . 1 .... .1... 1.... .. 1.1.. .... ...1 .... .1 11 ....
1066 moves(q,wreg)
. 111. . 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
1067 sub(addrs,1) ; addrs := addrs -1 .
. 111. . 1 .... .1... ...1. .1 11... .... .111 .... .. .. ...1
1070 pushre(addrs) ; micro sekvenser counter := 0.
1 .1.. . 1 .... 11... .11.1 .. 1.1.. .111 ..1. .... .1 11 ....
; push address of the next
; micro instr into the stack,
1071 rep mover(wrk1,wrk1) rgtaql dshinz; repeat
. 1... . 1 .... ..111 .11.. .. ..... 1.1. 1.1. .... .1 11 .11.
; counter := counter -1,
; double shift wrk1 and q
; rigth with zero input,
; until counter = 0.
1072 mover(wpre,wrk1) nothm csmy shinz; wreg(index - 1) := wrk1.
. 111. . 1 .... .1... .11.. .. ..1.. 1.1. ...1 .... .1 11 ....
1073 jmp(pfneic) moves(wreg,q) ; wreg(index) := q, goto pficin.
1 ..11 . 1 .... .1... .1..1 .. 1.1.. .... .... .... .1 11 ....
1074 ld3: jmp(pfneic) mzero(wreg) ; wreg(index) := 0, goto pfneic.
1 ..11 . 1 .... .1... 1.... .. 1.1.. .... .... .... .1 11 ....
;*until: final
;*skip: norm
; HC8000 instr: normalize single: 'ns', numeric code 34.
; ----------------------------------------------------
1075 ns/'34: moves(q,wreg) ; q := wreg(index).
. 111. . 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
1076 cjmp(zero,ns2) mzero(wrk1) ; if wreg(index) = 0 then
. ..11 . 1 .1.1 .1... 1.... .. 1.... .... 1.1. .... .1 11 ....
; goto ns2, wrk1 := 0.
1077 ns1: cjmp(nover,ns1) slnorm(wrk1) ;
. ..11 . 1 .11. 1.... ..... .1 1.... .... 1.1. .... .1 11 ....
1100 moves(wreg,q) ; wreg(index) := q.
. 111. . 1 .... .1... .1..1 .. 1.1.. .... .... .... .1 11 ....
1101 jsb(getop) mover(q,wrk1) ; q := wrk1, call getop.
1 ...1 . 1 .... .11.. .11.1 .. 1.... 1.1. .... .... .1 11 ....
1102 jmp(hsnoen) ; goto hsnoen. (i.e. normalize
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; entry in instr. half word
; store ).
1103 ns2: mover(q,-2048) ; q := -2048
. 111. . 1 .... .11.. .11.1 .. 11... .... .... 1... .. .. ....
1104 jsb(getop) ;
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1105 jmp(hsnoen) ;
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; HC8000 instr: normalize double: 'nd', numeric code 35.
; ------------------------------------------------------
1106 nd/'35: moves(q,wpre) dshinz ; q := wreg(index-1), set shift control
. 111. . 1 .... .11.. .1... .. ..1.. .... ...1 .... .1 11 .11.
; to shift double with zero input.
1107 moves(wrk1,q) ; wrk1 := q.
. 111. . 1 .... .1... .1..1 .. 1.... .... 1.1. .... .1 11 ....
1110 cjmp(zero,nd2) moves(q,wreg) ; if wrk1 (i.e. wreg(index-1)) = 0 then
. ..11 . 1 .1.1 .11.. .1... .. 1.1.. .... .... .... .1 11 ....
; goto nd2, q := wreg(index).
1111 mzero(wrk2) ; wrk2 := 0.
. 111. . 1 .... .1... 1.... .. 1.... .... 1.11 .... .1 11 ....
1112 nd1: dlnorm(wrk1) ; double normalize wrk1 and q.
. 111. . 1 .... 1.1.. ..... .. 1.... .... 1.1. .... .1 11 ....
1113 cjmp(ncarry,nd1) incone(wrk2) ; if not carry then goto nd1,
. ..11 . 1 1.1. .1... ..... .. 1.... .... 1.11 .... .1 11 ....
; wrk2 := wrk2 + 1.
1114 moves(wpre,wrk1) ; wreg(index-1) := wrk1.
. 111. . 1 .... .1... .1... .. 1.1.. 1.1. ...1 .... .1 11 ....
1115 jsb(getop) moves(wreg,q) ; wreg(index) := q, call getop.
1 ...1 . 1 .... .1... .1..1 .. 1.1.. .... .... .... .1 11 ....
1116 jmp(hsnoen) mover(q,wrk2) ; goto hsnoen ( i.e. entry inhalf
1 ..11 . 1 .... .11.. .11.1 .. 1.... 1.11 .... .... .1 11 ....
; word store) , q := wrk2.
1117 nd2: cjmp(nzero,nd1) mzero(wrk2) ; if q <(i.e. wreg(index)) <> 0 then
. ..11 . 1 .1.. .1... 1.... .. 1.... .... 1.11 .... .1 11 ....
; goto nd1, wrk2 := 0.
1120 jsb(getop) ; call getop.
1 ...1 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1121 mover(q,8.4000) ; q := -2048.
. 111. . 1 .... .11.. .11.1 .. 11... .... .... 1... .. .. ....
1122 jmp(hsnoen) ; goto hsnoen.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
;*until: norm
;*page: XXX
; sequencing .
; -----------
; HC8000 instr: jump and select enable level: 'je', numeric code 15.
;-----------------------------------------------------------------
je/'15:
1123 invr(hc2901,'e01sel) ; closk hc2901 in function set enable level.
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
1124 andinv(status,'disbit) ; clear disable bit in status register.
. 111. . 1 .... .1... 1..1. .. 11... .... .1.. .... .. .. ....
1125 jmp(jd2) ; continue in jump disable 2.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; HC8000 instr: jump and select diable level: 'jd', numeric code 14.
;------------------------------------------------------------------
1126 jd/'14: add(addrs,'montop) noload ; if addrs >= -montop then
. 111. . 1 .... 11... ..11. .. 11... .... .111 .... .. .. ....
1127 cjmp(notneg,jd1) ; then goto jd1.
. ..11 . 1 111. 11... ....1 .. 1.... .... .... .... .1 11 ....
1130 mover(wrk0,-2048) signex ; wrk0 := -2048.
. 111. . 1 .... 111.1 .11.. .. 11... .... 1111 1... .. .. ....
1131 sub(addrs,wrk0) noload ; if addrs < -2048 then
. 111. . 1 .... 11... ...1. .1 1.... 1111 .111 .... .1 11 ....
1132 cjmp(less,jd1) ; then goto jd1.
. ..11 . 1 ..11 11... ....1 .. 1.... .... .... .... .1 11 ....
1133 mover(cause,addrs) ; cause := addrs.
. 111. . 1 .... .1... .11.. .. 1.... .111 .11. .... .1 11 ....
1134 add(cause,2048) ; cause := cause + 2048.
. 111. . 1 .... .1... ..11. .. 11... .... .11. 1... .. .. ....
1135 sub(inf,1) ; inf := inf -1.
. 111. . 1 .... .1... ...1. .1 11... .... 11.. .... .. .. ...1
1136 jmp(intser) inctwo(ic) ; ic := ic + 2, goto service interupt.
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
1137 jd1: invr(hc2901,'e01sdl) ; closk hc2901 in set diable level.
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
1140 or(status,'disbit) ; set disable bit in status register.
. 111. . 1 .... .1... 1111. .. 11... .... .1.. .... .. .. ....
1141 jd2: cjmp(re2901,jd2) clre01 ; wait until hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
; HC8000 instr: jump with register link: 'jl', numeric code 13.
; -----------------------------------------------------------
1142 jl/'13: mover(wrk1,w0) ; save w_reg(0) in wrk1.
. 111. . 1 .... .1... .11.. .. 1.... ..11 1.1. .... .1 11 ....
1143 mover(wreg,ic) ; move old ic to wreg(index).
. 111. . 1 .... .1... .11.. .. 1.1.. .1.1 .... .... .1 11 ....
1144 inctwo(wreg) ; w_reg(index) := wreg(index) + 2.
. 111. . 1 .... .1... ..... .1 1.1.. .... .... .... .1 11 ....
1145 mover(ic,addrs) ; get new ic form address.
. 111. . 1 .... .1... .11.. .. 1.... .111 .1.1 .... .1 11 ....
1146 jmp(nopfic) mover(w0,wrk1) ; goto nopfne, w0 := originaaly w0.
1 ..11 . 1 .... .1... .11.. .. 1.... 1.1. ..11 .... .1 11 ....
; HC8000 instr: skip if register high: 'sh', numeric code 40.
;---------------------------------------------------------
1147 sh/'40: sub(wreg,addrs) noload ; if w_reg(index) <= addrs then
. 111. . 1 .... 11... ...1. .1 1.1.. .111 .... .... .1 11 ....
1150 cjmp(lseq,pficin) inctwo(ic) ; ic := ic + 2,goto pfnicin
. ..11 . 1 ...1 .1... ..... .1 1.... .... .1.1 .... .1 11 ....
1151 jmp(sknins) inctwo(ic) ; ic := ic + 2, goto sknins.
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; HC8000 instr: skip if register low: 'sl', numeric code 41.
;----------------------------------------------------------
1152 sl/'41: sub(wreg,addrs) noload ; if w_reg(index) >= addrs then
. 111. . 1 .... 11... ...1. .1 1.1.. .111 .... .... .1 11 ....
1153 sl1: cjmp(greq,pficin) inctwo(ic) ; entry skip limit violation,
. ..11 . 1 ..1. .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; ic := ic + 2, goto pficin.
1154 jmp(sknins) inctwo(ic) ; ic := ic + 2, goto sknins.
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; HC8000 instr: skip if register equal: 'se', numeric code 42.
;----------------------------------------------------------
1155 se/'42: sub(wreg,addrs) noload ; if w_reg(index) <> addrs then
. 111. . 1 .... 11... ...1. .1 1.1.. .111 .... .... .1 11 ....
1156 se1: cjmp(nequal,pficin) inctwo(ic) ; ( entry from skip one),
. ..11 . 1 .1.. .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; ic := ic + 2, goto pficin.
1157 jmp(sknins) inctwo(ic) ; ic := ic + 2, goto sknins.
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; HC8000 instr: skip if register not equal: 'sn', numeric code 43.
;----------------------------------------------------------------
1160 sn/'43: sub(wreg,addrs) noload ; if w_reg(index) = addrs then
. 111. . 1 .... 11... ...1. .1 1.1.. .111 .... .... .1 11 ....
1161 cjmp(equal,pficin) inctwo(ic) ; ic := ic+2, goto pficin.
. ..11 . 1 .1.1 .1... ..... .1 1.... .... .1.1 .... .1 11 ....
1162 jmp(sknins) inctwo(ic) ; ic := ic + 2, goto sknins,
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; HC8000 instr: skip if register bits one: 'so', numeric code 44.
; -------------------------------------------------------------
1163 so/'44: and(q,wreg,addrs) ; q := w_reg(index) and addrs.
. 111. . 1 .... .11.. 11... .. 1.1.. .111 .... .... .1 11 ....
1164 jmp(se1) sub(q,addrs) noload ; if addrs <> q then
1 ..11 . 1 .... 11... ...11 .1 1.... .111 .... .... .1 11 ....
; condition test performed in skip equal.
; HC8000 instr: skip if register bits zero: 'sz', numeric code 45.
;----------------------------------------------------------------
1165 sz/'45: and(wreg,addrs) noload ; if w_reg(index) and addrs <> 0 then
. 111. . 1 .... 11... 11... .. 1.1.. .111 .... .... .1 11 ....
1166 sz1: cjmp(nzero,pficin) inctwo(ic) ; ( entry from skip exeption)
. ..11 . 1 .1.. .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; ic := ic + 2, goto pficin.
1167 jmp(sknins) inctwo(ic) ; ic := ic + 2, goto sknins.
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; HC8000 instr: skip if no exeption: 'sx', numeric code 46.
; -------------------------------------------------------
1170 sx/'46: and(addrs,7) ; addrs := addrs and 7.
. 111. . 1 .... .1... 11... .. 11... .... .111 .... .. .. .111
1171 jmp(sz1) and(addrs,ex) noload ; if (ex and addrs) <> 0 then
1 ..11 . 1 .... 11... 11... .. 1.... .1.. .111 .... .1 11 ....
; skip test performed in skip zero.
; HC8000 instr: skip if no write protection: 'sp', numeric code 21.
; ---------------------------------------------------------
1172 sp/'21: sub(addrs,8) noload ; if sp < 8 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .. 1...
1173 cjmp(less,sp1) add(q,addrs,base); goto sp1, q := addrs + base.
. ..11 . 1 ..11 .11.. ..11. .. 1.... 1..1 .111 .... .1 11 ....
1174 sub(q,lowlim) noload ; if addrs + base < lower_limit then
. 111. . 1 .... 11... ...11 .1 1.... 111. .... .... .1 11 ....
1175 cjmp(less,pfneic) ; goto pfneic.
. ..11 . 1 ..11 11... ....1 .. 1.... .... .... .... .1 11 ....
1176 jmp(sl1) sub(q,uplim) noload ; if addrs+base >=
1 ..11 . 1 .... 11... ...11 .1 1.... 11.1 .... .... .1 11 ....
; skip action performed in skil low.
1177 sp1: sub(addrs,0) noload ; if addrs < 0 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .. ....
1200 cjmp(less,pficin) inctwo(ic) ; ic := ic + 1, goto pficin.
. ..11 . 1 ..11 .1... ..... .1 1.... .... .1.1 .... .1 11 ....
1201 jmp(sknins) inctwo(ic) ; ic := ic + 2 , goto skins.
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; escape and interupt sequencing.
; -------------------------------
; HC8000 instr: return from excape: 're', numeric code 22.
; ------------------------------------------------------
; escape pattern /.11.1./
1202 re/'22: mover(wrk0,addrs) ; wrk0 ( reg dump addrs) := addrs.
. 111. . 1 .... .1... .11.. .. 1.... .111 1111 .... .1 11 ....
1203 add(wrk0,base) ; reg dump addrs := reg dump addrs + base.
. 111. . 1 .... .1... ..11. .. 1.... 1..1 1111 .... .1 11 ....
1204 add(q,wrk0,14) ; q := addrs of last reg to be
. 111. . 1 .... .11.. ..11. .. 11... .... 1111 .... .. .. 111.
; reestablished.
1205 sub(lowlim,wrk0) noload ; if lower limit > reg dump addrs then
. 111. . 1 .... 11... ...1. .1 1.... 1111 111. .... .1 11 ....
1206 cjmp(great,re5) sub(q,uplim) noload; goto re5, if reg dump addrs
. ..11 . 1 .... 11... ...11 .1 1.... 11.1 .... .... .1 11 ....
1207 cjmp(greq,re5) mover(wrk2,status); save monitor mode bit for
. ..11 . 1 ..1. .1... .11.. .. 1.... .1.. 1.11 .... .1 11 ....
; preventing illegal setting of
; monitor mode in werk2.
1210 re7: jsb(redyre) mover(wrk1,ic) ; call reestablish dynamic registers,
1 ...1 . 1 .... .1... .11.. .. 1.... .1.1 1.1. .... .1 11 ....
; save old ic.
1211 re3: mover(wrk2,wrk2) ; if process previus was in monitor
. 111. . 1 .... .1... .11.. .. 1.... 1.11 1.11 .... .1 11 ....
1212 cjmp(neg,re4) mover(wrk2,status) slft; then goto re4 , else
. ..11 . 1 1111 1..11 .11.. .. 1.... .1.. 1.11 .... .1 11 ....
1213 mover(status,wrk2) srgt ; clear monitor mode bit in status reg.
. 111. . 1 .... ...11 .11.. .. 1.... 1.11 .1.. .... .1 11 ....
re4:
1214 jmp(nopfic) ; goto get next 8000 instr:.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1215 re5: mover(wrk0,addrs) ; wrk0 := reg dump addrs.
. 111. . 1 .... .1... .11.. .. 1.... .111 1111 .... .1 11 ....
1216 sub(q,base) ; q := reg dump addrs + 14.
. 111. . 1 .... .11.. ...11 .1 1.... 1..1 .... .... .1 11 ....
1217 mover(wrk2,status) ; save monitor mode bit.
. 111. . 1 .... .1... .11.. .. 1.... .1.. 1.11 .... .1 11 ....
1220 sub(wrk0,8) noload ; if reg dump addrs < 8 then
. 111. . 1 .... 11... ...1. .1 11... .... 1111 .... .. .. 1...
1221 cjmp(less,expt) sub(q,cpa) noload; goto re6, else if reg dumpadd + 14
. ..11 . 1 ..11 11... ...11 .1 1.... 1... .... .... .1 11 ....
1222 cjmp(less,re7) ; < cpa then goto re7 ( reestablish
. ..11 . 1 ..11 11... ....1 .. 1.... .... .... .... .1 11 ....
; registers) else
1223 jmp(expt) ; goto exeption.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; HC8000 instr: return from interupt: 'ri', numeric code 12.
; --------------------------------------------------------
; escape pattern /111.1./
1224 ri/'12: mover(status,status) ; if not in monitor mode then
. 111. . 1 .... .1... .11.. .. 1.... .1.. .1.. .... .1 11 ....
1225 cjmp(notneg,prgexp) ; then goto program exeption.
. ..11 . 1 111. 11... ....1 .. 1.... .... .... .... .1 11 ....
1226 invr(hc2901,'e01rin) ; clok hc2901 in entry
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; return from interupt.
1227 add(inf,12) ; select new system table
. 111. . 1 .... .1... ..11. .. 11... .... 11.. .... .. .. 11..
; inf := inf + 12.
1230 add(q,inf,2) ; q := inf+2, calculate register dump
. 111. . 1 .... .11.. ..11. .. 11... .... 11.. .... .. .. ..1.
; address in new system table.
1231 ri1: cjmp(re2901,ri1) clre01 ; wait for hc2901 is ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
1232 invs(hc2901,q) ; move addrs of system table regdump
. 111. . 1 .... 11... .1.11 .. 1...1 .... .... .... .1 11 ....
; addrs to hc2901
1233 mover(wrk2,addrs) ; save old address in wrk2.
. 111. . 1 .... .1... .11.. .. 1.... .111 1.11 .... .1 11 ....
1234 mover(wrk1,ic) ; save old address in wrk1.
. 111. . 1 .... .1... .11.. .. 1.... .1.1 1.1. .... .1 11 ....
1235 ri2: cjmp(re2901,ri2) clre01 invs(wrk0,hc2901); wait for hc2901 is ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... 1111 .... .1 11 ....
; get regdump addrs to wrk0.
1236 jsb(redyen) clwr01 ; call subroutine for reestablishing
1 ...1 . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
; the dynamic registers from hc2901,
; clear write hc2901.
1237 add(wrk0,wrk2) ; reg dump addr := reg dump addr
. 111. . 1 .... .1... ..11. .. 1.... 1.11 1111 .... .1 11 ....
; + old addrs
; ( reg dump addr is now addr of static
; registers, old addrs is the
; effective address of ri intruction).
1240 invs(hc2901,wrk0) ; send address of dynamic register dump to
. 111. . 1 .... 11... .1.1. .. 1...1 .... 1111 .... .1 11 ....
; to hc2901.
1241 ri12: cjmp(re2901,ri12) clre01 invs(cpa,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... 1... .... .1 11 ....
; reestablish spa register.
1242 cont clwr01 ; clock hc2901 ready to accept next
. 111. . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
; data word.
1243 ri14: cjmp(re2901,ri14) clre01 invs(base,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... 1..1 .... .1 11 ....
; reestablish base register.
1244 cont clwr01 ; clock hc2901 ready to accept next
. 111. . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
; data word.
1245 ri15: cjmp(re2901,ri15) clre01 invs(lowlim,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... 111. .... .1 11 ....
; reestablish lower limit register.
1246 cont clwr01 ; clock hc2901 ready to accept next data
. 111. . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
; word.
1247 ri16: cjmp(re2901,ri16) clre01 invs(uplim,hc2901); wait for hc2901 ready,
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... 11.1 .... .1 11 ....
; reestablish upper limit register.
; set dump error count to 0.
1250 and(status,'disbit) noload ; if disable bit not set then
. 111. . 1 .... 11... 11... .. 11... .... .1.. .... .. .. ....
1251 cjmp(zero,nopfic) ; fetch next instr wih no prefetch.
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
1252 invr(hc2901,'e01sdl) ; else clock entry set disable level.
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
1253 ri17: cjmp(re2901,ri17) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
1254 jmp(nopfic) ; go to fetch next 8000 instr: with
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; prefecth.
; monitor control
; ---------------
; HC8000 instr: general register, put: 'gp', numeric code 47.
; ---------------------------------------------------------
; escape pattern 2.1000001
1255 gp/'47: mover(status,status) ; if not in monitor mode
. 111. . 1 .... .1... .11.. .. 1.... .1.. .1.. .... .1 11 ....
1256 cjmp(notneg,prgexp) moves(q,wreg); then goto program exeption,
. ..11 . 1 111. .11.. .1... .. 1.1.. .... .... .... .1 11 ....
; q := wreg(index).
1257 sub(addrs,26) noload ; if address = 26 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .1 1.1.
1260 cjmp(equal,gp26) inctwo(ic) ; then goto generel put 26, ic := ic+2.
. ..11 . 1 .1.1 .1... ..... .1 1.... .... .1.1 .... .1 11 ....
1261 sub(addrs,64) noload ; if addrs = 64 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .1 .. ....
1262 cjmp(equal,gp64) ; goto generel put 64.
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
; else if no legal address then
1263 jmp(pficin) ; goto get next prefetched instruction.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1264 gp64: invr(hc2901,'e01wtr) ; clock hc2901 in write test
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; register.
1265 gp3: cjmp(re2901,gp3) clre01 ; loop while hc2901 is not ready
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
1266 invs(hc2901,q) ; hc2901 := q and clock
. 111. . 1 .... 11... .1.11 .. 1...1 .... .... .... .1 11 ....
1267 gp4: cjmp(re2901,gp4) clre01 ; loop until hc2901 is ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
1270 jmp(pficin) ; goto pfneic.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1271 gp26: jmp(pficin) moves(inf,q) ; information register := q (
1 ..11 . 1 .... .1... .1..1 .. 1.... .... 11.. .... .1 11 ....
; selected working register), goto
; get next prefetched instrcution.
; HC8000 instr: general register, get: 'gg', numeric code 28.
; -----------------------------------------------------
; escape pattern: 2.000001
1272 gg/'28: moves(q,wreg) ; save wreg(index).
. 111. . 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
1273 sub(addrs,94) noload ; if address = 94 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .1 .1 111.
1274 cjmp(equal,gg94) ; then goto generel get 94 else
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
1275 sub(addrs,26) noload ; if addrs = 26 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .. .1 1.1.
1276 cjmp(equal,pfneic) mover(wreg,inf); wreg(index) := infromation
. ..11 . 1 .1.1 .1... .11.. .. 1.1.. 11.. .... .... .1 11 ....
; register, goto pfneic.
; else
1277 sub(addrs,100) noload ; if address = 100 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .1 1. .1..
1300 cjmp(equal,gg100) ; then goto generel get 100 else
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
1301 sub(addrs,200) noload ; if address > 200 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... 11 .. 1...
1302 cjmp(greq,ggm200) ; then goto generel get more than 200
. ..11 . 1 ..1. 11... ....1 .. 1.... .... .... .... .1 11 ....
; else
1303 sub(addrs,64) noload ; if addres = 64 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .1 .. ....
1304 cjmp(equal,gg64) ; then goto generel get 64 else
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
1305 sub(addrs,66) noload ; if addrs = 66 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... .1 .. ..1.
1306 cjmp(equal,gg66) ; then goto generel get 66
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
; else
1307 ggnle: jmp(pfneic) moves(wreg,q) ; if not legal then reestablish
1 ..11 . 1 .... .1... .1..1 .. 1.1.. .... .... .... .1 11 ....
; w reg(index) and goto pfneic
1310 gg100: invr(hc2901,'e01rtc) ; send addrs of real time clock to
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; hc2901.
1311 jmp(gg4) ; goto gg4.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1312 gg64: invr(hc2901,'e01rtr) ; send0address of read test register
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; with no wait to hc2901.
1313 jmp(gg4) ; goto gg4.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1314 gg66: invr(hc2901,'e01rtw) ; clock hc2901 in read test register
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; with wait.
1315 jmp(gg4) ; goto wait word from hc2901.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
gg94: ; generel get chrakter interupt level from
; amd9511 interupt controler.
1316 mover(status,status) ; if not in monitor mode then
. 111. . 1 .... .1... .11.. .. 1.... .1.. .1.. .... .1 11 ....
1317 cjmp(notneg,ggnle) ; goto generel get no legal entry.
. ..11 . 1 111. 11... ....1 .. 1.... .... .... .... .1 11 ....
1320 invr(hc2901,'e01cil) ; else clock hc2901 in entry
. 111. . 1 .... 11... .111. .. 11..1 .... .... .... .. .. ....
; get charakter interupt level.
1321 gg4: cjmp(re2901,gg4) clre01 ; loop while hc2901 is not redy
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
1322 jmp(pfneic) invs(wreg,hc2901) ; w_reg(index) := hc2901, gpfneic.
1 ..11 . 1 .... .1... .1.1. .. 1.11. .... .... .... .1 11 ....
ggm200: ; entry for generel get with addres greather and equal 200.
1323 sub(addrs,200) noload ; if address > 200 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... 11 .. 1...
1324 cjmp(great,ggm202) ; then goto generel get more 202
. ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; else
; generel get 200.
; reverse bit in word.
1325 moves(wrk0,q) dshinz ; wrk0 := q( selected working register),
. 111. . 1 .... .1... .1..1 .. ..... .... 1111 .... .1 11 .11.
; set shift condition in amd2904 to
; double shift with zero input.
1326 lcpu(23) ; load counter with length or word.
1 .1.. . 1 .... 11... ....1 .. 1.... .... .... .... .. .1 .111
; for 0 to 23 do
; begin
1327 mover(wrk0,wrk0) rgtaql ; q.msb := wrk0.lsb, shift wrk0 rigth.
. 111. . 1 .... ..111 .11.. .. 1.... 1111 1111 .... .1 11 ....
1330 rep mover(wrk1,wrk1) lftaql ; wrk1.lsb := q.msb . shift wrk1 left.
. 1... . 1 .... 1.111 .11.. .. 1.... 1.1. 1.1. .... .1 11 ....
1331 mover(wreg,wrk1) shinz ; wreg(index) := wrk1 ( reversed word),
. 111. . 1 .... .1... .11.. .. ..1.. 1.1. .... .... .1 11 ....
; set shift condition to singleshift
; and zero input.
1332 jmp(pficin) inctwo(ic) ; goto get next prefetched
1 ..11 . 1 .... .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; instrcution.
ggm202: ; entry for instruction greather than 200.
1333 sub(addrs,202) noload ; if address > 202 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... 11 .. 1.1.
1334 cjmp(great,ggm204) ; goto continue with generel get instructions
. ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; with address greather than 202.
; else gg 202 and 201.
1335 moves(wrk0,q) ; wrk0 := C(selected w register).
. 111. . 1 .... .1... .1..1 .. 1.... .... 1111 .... .1 11 ....
1336 cjmp(neg,gg2021) inctwo(ic) ; if c(wreg) negative then
. ..11 . 1 1111 .1... ..... .1 1.... .... .1.1 .... .1 11 ....
; goto gg201 else
1337 sub(addrs,201) noload ; if address = 201 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... 11 .. 1..1
1340 cjmp(equal,gg2024) ; goto one decrement of wrk0.
. ..11 . 1 .1.1 11... ....1 .. 1.... .... .... .... .1 11 ....
1341 sub(wrk0,1) ; decrement wrk0 by 1.
. 111. . 1 .... .1... ...1. .1 11... .... 1111 .... .. .. ...1
1342 gg2024: sub(wrk0,1) ; decrement wrk0 by 1.
. 111. . 1 .... .1... ...1. .1 11... .... 1111 .... .. .. ...1
1343 cjmp(greq,pficin) moves(wreg,wrk0); if wrk0 >= 1 then goto
. ..11 . 1 ..1. .1... .1... .. 1.1.. 1111 .... .... .1 11 ....
; get next instruction prefetched
; selected working register := wrk0.
1344 jmp(sknini) mzero(wreg) ; else goto get next instrcution
1 ..11 . 1 .... .1... 1.... .. 1.1.. .... .... .... .1 11 ....
; with skip, reset seleted working
; register.
1345 gg2021: sub(addrs,202) noload ; if address = 202 then
. 111. . 1 .... 11... ...1. .1 11... .... .111 .... 11 .. 1.1.
1346 cjmp(equal,gg2023) inctwo(wrk0) ; goto gg2023 wrk0 :=
. ..11 . 1 .1.1 .1... ..... .1 1.... .... 1111 .... .1 11 ....
; wrk0 + 2.
1347 sub(wrk0,1) ; else wrk0 := wrk0+1.
. 111. . 1 .... .1... ...1. .1 11... .... 1111 .... .. .. ...1
1350 gg2023: cjmp(neg,pficin) mover(wreg,wrk0); if wrk0 < 0 then goto
. ..11 . 1 1111 .1... .11.. .. 1.1.. 1111 .... .... .1 11 ....
; get next prefetched instruction
; selected working register := wrk0
1351 jmp(sknini) mzero(wreg) ; else goto get next skipped prefetched
1 ..11 . 1 .... .1... 1.... .. 1.1.. .... .... .... .1 11 ....
; instruction, reset selected
; working register.
; HC8000 instr: data out: 'do', numeric code 1.
; -------------------------------------------
1352 do/'1: mover(wrk0,'e01dob) ; wrk0 := address of data out base block
. 111. . 1 .... .1... .11.. .. 11... .... 1111 .... .. .. ....
; in hc2901.
1353 jmp(dioent) ; goto common data in data out entry.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; HC8000 instr: data in: 'di', numeric code 0.
; --------------------------------------------
1354 di/'29: mover(wrk0,'e01dib) ; wrk0 := entry in hc2901 for address
. 111. . 1 .... .1... .11.. .. 11... .... 1111 .... .. .. ....
; block for data in.
dioent: ; common entry for data in and data out.
1355 andinv(ex,7) ; ex(21,23) := 0, clear bit 21 to
. 111. . 1 .... .1... 1..1. .. 11... .... .1.. .... .. .. .111
; 23 in ex register (i.e. status
; register.)
1356 cjmp(notneg,prgexp) mover(wrk1,addrs) slft; if status
. ..11 . 1 111. 1..11 .11.. .. 1.... .111 1.1. .... .1 11 ....
; (same as ex) is not
; negative ( not monitor mode)
; then goto program exeption,
; wrk1 := addrs * 2 ( delete possible
; sign bit).
1357 cjmp(notneg,dimemo) mover(wrk1,wrk1) srgt; if addrs is not negative
. ..11 . 1 111. ...11 .11.. .. 1.... 1.1. 1.1. .... .1 11 ....
; then goto dimemo ( memory word fetch),
1360 and(q,addrs,7) ; q := last 3 bits of
. 111. . 1 .... .11.. 11... .. 11... .... .111 .... .. .. .111
; effective address.
1361 add1(wrk0,q,wrk0) ; wrk0 := wrk0 + address of first
. 111. . 1 .... .1... ..111 .1 1.... 1111 1111 .... .1 11 ....
; data in function, in hc2901 + 1,
; ( add 1 because the first entry in
; hc2901 is used to direct memory
; access).
1362 andinv(wrk1,7) ; clear last 3 bits of device number.
. 111. . 1 .... .1... 1..1. .. 11... .... 1.1. .... .. .. .111
; data in jump table.
1363 dimemo: invs(hc2901,wrk0) ; clock hc2901 in address e01gmw.
. 111. . 1 .... 11... .1.1. .. 1...1 .... 1111 .... .1 11 ....
1364 diw1: cjmp(re2901,diw1) clre01 ; wait for ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
1365 invs(hc2901,wrk1) ; hc2901 := divice number.
. 111. . 1 .... 11... .1.1. .. 1...1 .... 1.1. .... .1 11 ....
1366 moves(q,wreg) ; q := wreg(index).
. 111. . 1 .... .11.. .1... .. 1.1.. .... .... .... .1 11 ....
1367 diw2: cjmp(re2901,diw2) clre01 ; wait for hc2901 ready.
. ..11 . 1 1111 11... ....1 .. 1..1. .... .... .... .1 11 ....
1370 invs(hc2901,q) ; send contents of w reg to hc2901.
. 111. . 1 .... 11... .1.11 .. 1...1 .... .... .... .1 11 ....
1371 diw3: cjmp(re2901,diw3) invs(wreg,hc2901); wait for hc2901,
. ..11 . 1 1111 .1... .1.1. .. 1.11. .... .... .... .1 11 ....
; wreg(index) := hc2901.
1372 cont clwr01 ; clear write ready from hc2901.
. 111. . 1 .... 11... ....1 .. 1...1 .... .... .... .1 11 ....
1373 diw4: cjmp(re2901,diw4) invs(wrk1,hc2901); wait for hc2901, wrk1 := hc2901.
. ..11 . 1 1111 .1... .1.1. .. 1..1. .... 1.1. .... .1 11 ....
1374 and(wrk1,7) ; wrk1 := wrk1(21.23).
. 111. . 1 .... .1... 11... .. 11... .... 1.1. .... .. .. .111
1375 jmp(pfneic) or(ex,wrk1) ; ex := wrk1.
1 ..11 . 1 .... .1... 1111. .. 1.... 1.1. .1.. .... .1 11 ....
; goto pfneic.
; jumptable to not finished 8000 instr:
; schould not be prommed.
1376 wd/'24: jmp(dowd) ; word divide.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1377 cf/'53: jmp(docf) ; convert floating to integer.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1400 ci/'32: jmp(doci) ; convert integer to floating.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1401 fa/'48: jmp(dofa) ; floating point add.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1402 fd/'52: jmp(dofd) ; floating point divide.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1403 fm/'50: jmp(dofm) ; floating point multiply.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
1404 fs/'49: jmp(dofs) ; floating point subtract.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
ggm204: ; entry next generel get instruction
; .
;dowd:
docf:
doci:
dofa:
dofd:
dofm:
dofs:
1405 jmp(prgexp) ; goto program exeption.
1 ..11 . 1 .... 11... ....1 .. 1.... .... .... .... .1 11 ....
; division removed in rhtest
; HC8000 instr: integer word, divide: 'wd', numeric code 24.
; --------------------------------------------------------
;.wd/'24: . entry notused.
1406 dowd: andinv(ex,wrk2) ; ex(carry) := ex(owerflow) := 0.
. 111. . 1 .... .1... 1..1. .. 1.... 1.11 .1.. .... .1 11 ....
1407 jsb(getop) moves(q,wpre) ; wrk0 := getop(addrs),
1 ...1 . 1 .... .11.. .1... .. 1.1.. .... ...1 .... .1 11 ....
; q := wreg(index-1), ( most
; significant word of dividend).
1410 cjmp(zero,wd1) moves(wrk2,q) ; if wrk0 = 0 then goto wd1,
. ..11 . 1 .1.1 .1... .1..1 .. 1.... .... 1.11 .... .1 11 ....
; wrk2 := q (most significant word
; of dividend).
break 0 line 602-605
▶EOF◀