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Types: RcTekst
Names: »99109944.WP«
└─⟦670c8f5a6⟧ Bits:30005866/disk2.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99109944.WP«
╱04002d4e0c00060000000003014831600000000000000000000000000000000000000000000000002d37414b555f69737d8791ffffffffff04╱
↲
╞ __________________________↲
╞ Edition:╞ 1984.11.20↲
╞ Author: ╞ Peter Lundbo↲
╞ RCSL No.:╞ 99 - 1 - 09944↲
↲
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INTERNAL DOCUMENT↲
↲
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________________________________________________________________________↲
↲
Title:↲
↲
ETC 601 Hardware Selftest↲
User's Manual↲
Version 1.0↲
↲
↲
↲
________________________________________________________________________↲
════════════════════════════════════════════════════════════════════════
↓
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-----------------------------------------------------------------------↲
KEYWORDS :↲
↲
ETC 601, RC 3900, Intel, Multibus, Hardware Selftest.↲
↲
↲
↲
↲
↲
↲
----------------------------------------------------------------------↲
ABSTRACT :↲
↲
┆84┆This manual covers the ETC 601 (Ethernet Controller) Hardware ↓
┆19┆┆8a┆┄┄Selftest program installed in on-board PROM's together with ↓
┆19┆┆8a┆┄┄the bootloader.↲
↲
↲
↲
↲
↲
(56 printed pages)↲
════════════════════════════════════════════════════════════════════════
↓
┆06┆i↲
↲
┆b0┆┆a1┆TABLE OF CONTENTS┆05┆PAGE↲
↲
╱04002d4e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f17464b555f69737dffffffffff04╱
╱04002d4e0c00060000000003014831600000000000000000000000000000000000000000000000002d37414b555f69737d8791ffffffffff04╱
↓
↲
↲
1.╞ INTRODUCTION ................................................... 1↲
1.1 The Object of the Tests ................................... 2↲
1.2 Automatic Configuration ................................... 2↲
1.3 Selftest Equipment ........................................ 3↲
1.4 List of Included Tests .................................... 3↲
↲
2.╞ Testadministraor ............................................... 5↲
2.1 Operator Stimuli of the Selftest .......................... 5↲
2.2 Parameters ................................................ 9↲
2.3 Test Numbers .............................................. 11↲
2.4 Output from a Test ........................................ 12↲
2.5 Default Interrupt Handling ................................ 12↲
2.5.1 Instruction Exception .............................. 12↲
2.5.2 Illegal Interrupt .................................. 13↲
↲
3. I/O Procedure and Table Indexing ............................... 15↲
3.1 Input ..................................................... 15↲
3.2 Output .................................................... 15↲
3.3 Test Selection ............................................ 15↲
↲
4. Selftest Switch Settings ....................................... 17↲
↲
5. Initialization ................................................. 18↲
5.1 Wait States ............................................... 18↲
5.2 iAPX186 Interrupt Controller .............................. 18↲
5.3 Programmable Interrupt Controller 8259 .................... 19↲
5.4 iAPX186 Timer 1 ........................................... 19↲
5.5 MPSC 8274 Ch. B (Console Interface) ....................... 20↲
5.6 Bustest, Chip Select ...................................... 20↲
↲
6. Automatic Baud Rate Determination .............................. 22↲
↲
7.╞ The Selftest Snooper ...........................................╞ 23↲
7.1 Press <R> ................................................. 24↲
7.2 Press <S> ................................................. 24↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆06┆ ii↲
↲
┆a1┆┆b0┆TABLE OF CONTENTS PAGE╞ ↲
↲
7.3 Press <I> ................................................. 25↲
7.4 Press <O> ................................................. 25↲
↲
┆a1┆┆e1┆8┆e1┆. Test 0 = Memory Test ........................................... 27↲
8.1 PROM Checksum Test ........................................ 27↲
8.2 RAM Memory Test ........................................... 28↲
8.2.2 Memory Test Pattern ................................ 28↲
↲
9. Test 1 = RAM Refresh Test ...................................... 30↲
↲
10. Test 2 = iAPX186 DMA Test ...................................... 31↲
↲
11. Test 3 = PIC (8259) Interrupt Test ............................. 34↲
↲
12. Test 4 = iAPX186 Interrupt Test ................................ 35↲
↲
13. Test 5 = Ethernet Test 2 ....................................... 36↲
↲
14. Test 6 = 8274 ChA Test ......................................... 38↲
↲
15. Test 7 = Floppy Test ........................................... 42↲
╞ 15.1 Test Results .............................................. 42↲
15.2 The Test Disk ............................................. 44↲
↲
16. Multibus Configuration and Test Monitor ........................ 45↲
╞ 16.1 Automatic Configuration ................................... 45↲
16.2 "Test Slave" Management ................................... 46↲
16.3 Bootload .................................................. 47↲
↲
17. ETC601 as a "Test-Slave" ....................................... 48↲
↲
↲
┆b0┆┆a1┆APPENDIX↲
↲
A. LAYOUT OF THE MASTER TO SLAVE COMMUNICATION BUFFER ............ 49↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆┆06┆┆0b┆↲
┆b0┆┆a1┆1. Introduction.↲
↲
↲
RC3900 is a family based on the Intel Multibus card format. ↓
An actual configuration may consists of one or more CPU-boards, ↓
one or more communication controllers (COM601) and a number of ↓
other controllers. The ETC601 which is covered by this manual may ↓
in some system be the main CPU board, whereas in others it may be ↓
a communication controller only.↲
↲
These Single Board Computers (SBC) may each be considered as ↓
intelligent units. Some with the role as potentional Multibus ↓
masters (ETC601), and some as potentional slaves (COM601).↲
↲
Every RC-manufactured intelligent Multibus SBC will contain a ↓
built-in PROM-based selftest program which can be considered as ↓
an integrated part of the SBC bootload-facility. In other words ↓
the power up of a system could be devided into three phases. The ↓
first would be an initialization of the onboard controller chips. ↓
Second would be a selftest of each SBC, terminated by a ↓
centrallization of informations in one of the boards connected to ↓
the Multibus, namely the "test-master". The third phase is a ↓
common bootload of all boards connected to the Multibus.↲
↲
In the test-phase, an RC3900 system, must be considered as ↓
consisting of one and only one "test-master" card and a number of ↓
"test-slave" cards. After power on the "test-master" and "test-↓
slaves" execute their selftest programs concurrently. When the ↓
"test-master" has finished it's own selftest, it will be able to ↓
monitor messages from the "test-slaves", and to influence these ↓
to i.e. loop in a specific test several times. This means, that ↓
the "test-master" may act as an intelligent monitor for a ↓
debugging session on the "test-slaves".↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆81┆┆b0┆┆a1┆┆f0┆1.1 The Object of the Tests.↲
↲
↲
It is the intention of this system of SBC-selftests to cover ↓
three in the nature different needs.↲
↲
↲
a) ┆84┆The RC3900 is equipped with a power up selftest, consisting of ↓
┆19┆┆83┆┄┄a sequence of different test programs. These tests are ↓
┆19┆┆83┆┄┄organized with rising complexity, so that as far as possible ↓
┆19┆┆83┆┄┄no part of the hardware is used, before it is tested. It ↓
┆19┆┆83┆┄┄should establish a basic level of confidence to the hardware ↓
┆19┆┆83┆┄┄included in the RC3900 system. It requires no interaction from ↓
┆19┆┆83┆┄┄the operator.↲
↲
b) ┆84┆It gives the production department the possibility of using ↓
┆19┆┆83┆┄┄the same test programs as a burn-in facility. This is uptained ↓
┆19┆┆83┆┄┄by the fact that the test programs may be controlled from a ↓
┆19┆┆83┆┄┄connected console. The tests in the ETC601 may each either run ↓
┆19┆┆83┆┄┄in loop-mode, or in a big sequencial loop including all tests. ↓
┆19┆┆83┆┄┄Furthermore there is a possibility of having several SBC's ↓
┆19┆┆83┆┄┄running their tests in parallel, and make them repeat it in ↓
┆19┆┆83┆┄┄the infinite, under the controle of a "test-master".↲
↲
c) ┆84┆It supplies the Technical Service Department with a diagnostic ↓
┆19┆┆83┆┄┄tool, that will assist them during their debugging sessions.↲
↲
↲
┆b0┆┆a1┆┆f0┆1.2 Automatic Configuration.↲
↲
↲
The selftest of the ETC601 consists of a set of different ↓
testprograms which is run in sequence. When the selftest runs in ↓
the default mode with no operator interference, then the selftest ↓
terminates by performing a configuration of the Multibus address-↓
space. It will act as a "test-master" and collect test results ↓
from all connected RC-manufactured SBC's. If none of the ↓
connected SBC's has exhibited an error during the selftest, then ↓
the complete system will enter its bootload phase.↲
↲
┆8c┆┆83┆┆e0┆↓
It is possible by operator intervention to prevent the system ↓
from entering the bootload phase, and instead enter an ↓
interactive test mode. This gives the possibility of monitoring ↓
tests executed cuncurrently on several "test-slaves".↲
↲
↲
┆b0┆┆a1┆┆f0┆1.3 Selftest Equipment.↲
↲
↲
One of the extended tests, the 8274 ChA test (not run by default) ↓
requires a loopback cable either CBL 788 (rear cabinet) or CBL ↓
789 (card edge) to be installed.↲
↲
Another extended test the floppy test requires an iSBX board ↓
named FDC601 to be installed and connected to a 5 1/4" floppy ↓
disk drive.↲
↲
↲
┆b0┆┆a1┆┆f0┆1.4 List of Included Tests.↲
↲
↲
Besides the test programs, the RC3900, SBC Selftests includes a ↓
test administrator and a library of some simple input and output ↓
routines.↲
↲
The simple test administrator administers the mode in which a ↓
particular test is run. Different modes is determined by ↓
parameter settings. See chapter 2.↲
↲
The test programs are as follows:↲
↲
Simple Bustest - ┆84┆a part of the initialization. This test ↓
┆19┆┆9a┆┄┄may be selected by the 8255 switch PA3 ↓
┆19┆┆9a┆┄┄and is intended to be used for complex ↓
┆19┆┆9a┆┄┄fault finding of bus errors.↲
↲
PROM checksum test - ┆84┆a simple PROM checkseum is calculated. ↓
┆19┆┆9a┆┄┄It is only executed once after each ↓
┆19┆┆9a┆┄┄power up unitialization.↲
↲
┆8c┆┆83┆┆e0┆↓
RAM memory test - ┆84┆a modulus 3 pattern test of the board ↓
┆19┆┆9a┆┄┄resident RAM memory.↲
↲
RAM refresh test - ┆84┆a test of the automatic refreshing of ↓
┆19┆┆9a┆┄┄the RAM-memory.↲
↲
iAPX186 DMA test - ┆84┆a test of the iAPX186 on-chip DMA ↓
┆19┆┆9a┆┄┄controller.↲
↲
iAPX186 interrupt test - ┆84┆a test of the on-chip interrupt ↓
┆19┆┆9a┆┄┄controller and its ability to receive ↓
┆19┆┆9a┆┄┄interrupts from the on-chip timer.↲
↲
8259 interrupt test - ┆84┆a test of the 8259 interrupt controller ↓
┆19┆┆9a┆┄┄and its ability to receive a flagbyte ↓
┆19┆┆9a┆┄┄interrupt.↲
↲
Ethernet test 2╞ - ┆84┆a test that makes an external loop back ↓
┆19┆┆9a┆┄┄data transport with the Ethernet ↓
┆19┆┆9a┆┄┄Controller.↲
↲
8274 CHA test╞ ╞ - ┆84┆a test that makes an external loop back ↓
┆19┆┆9a┆┄┄data transport on the 8274 MPSC ↓
┆19┆┆9a┆┄┄controller channel A.↲
↲
Floppy test╞ ╞ - ┆84┆a test that verifies the iSBX interface ↓
┆19┆┆9a┆┄┄where a FDC601 Floppy Disc Controller ↓
┆19┆┆9a┆┄┄should be attached.↲
↲
Multibus Test Monitor - ┆84┆a Monitor that supplies the operator ↓
┆19┆┆9a┆┄┄with remote control the execution of ↓
┆19┆┆9a┆┄┄other SBC selftests.↲
↲
Messages from the test programs are explained along with the ↓
description of the individual test loops. The message "OK" is ↓
used by all test programs, and indicates that no error has been ↓
detected.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2. Testadministrator.↲
↲
↲
The ETC601 SBC Selftest is equipped with a simple test ↓
administrator, that administers the mode in which a particular ↓
test is executed.↲
↲
The selftest consists of a set of test programs and a Multibus ↓
configuration module. By default all the tests are run sequential ↓
and terminated by entering the bootloader. The main purpose of ↓
the testadministrator is to compute the address of the next test ↓
in sequence and to generate error messages to the console.↲
↲
The mode and sequence in which the tests are executed may be ↓
controlled from a connected console.↲
↲
Note that the ETC601 SBC Selftest is equipped with two versions ↓
of the testadministrator, one when configurated as a "test-↓
master" and another when configurated as a "test-slave". Which of ↓
the two that is active is determined by the 8255, PA2 strap ↓
(S23), see chapter 4.↲
↲
The description of the differences in the testadministrator, when ↓
in "test-slave" mode is in chapter 17.↲
↲
Fig. 1 gives a simple overview of the Selftest program flow.↲
↲
↲
┆b0┆┆a1┆┆f0┆2.1 Operator Stimuli of the Selftest.↲
↲
↲
The ETC601 SBC Selftest recognizes receive interrupts from the ↓
8274 USART and reads the corrosponding character, which enables ↓
operator manipulation of the Selftest flow. It is a fact, that ↓
the ETC601 SBC Selftest is designed to ensure "no stop" in the ↓
default power up bootload. Therefore be aware, that if any ↓
manipulation of the test flow is wanted, that be looping in the ↓
ETC601 Selftest or monitoring of "test-slaves", the decision must ↓
┆8c┆┆83┆┆c8┆↓
be taken before the bootloading is started, else the control is ↓
lost.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
The ETC601 SBC Selftest is sensitive to several kinds of inputs, ↓
which has different meanings:↲
↲
Press <esc> : ┆84┆enables interactive change of program flow ↓
┆19┆┆93┆┄┄parameters. See section 2.2.↲
↲
Press <cntrl><@> : ┆84┆starts the test snooper facility. See chapter ↓
┆19┆┆93┆┄┄7.↲
↲
Press <cntrl><Q> : ┆84┆quit present state. This could be an error-↓
┆19┆┆93┆┄┄halt condition or the Multibus test monitoring ↓
┆19┆┆93┆┄┄of "test-slaves".↲
↲
Press <cntrl><S> : ┆84┆request Multibus test monitoring of "test-↓
┆19┆┆93┆┄┄slaves" at the end of the ETC601 selftest.↲
↲
If any other character is typed the ETC601 SBC Selftest will ↓
respond with the following menu and wait for yet another ↓
character to continue.↲
↲
┆f0┆----MENU----↲
<esc> : change parameters↲
<cntrl><@> : enter snooper↲
<cntrl><Q> : quit present state↲
<cntrl><S> : request debug of test slaves↲
test no.:↲
00007: Floppy test↲
00006: 8274 CHA test↲
00005: Ethernet test 2↲
00004: iAPX186 slave interrupt test↲
00003: PIC test↲
00002: iAPX186 DMA test↲
00001: RAM refresh test↲
00000: memory test↲
----MENU----↲
↲
Figure 2: Selftest menu.↲
↲
┆8c┆┆83┆┆c8┆↓
┆a1┆2.2 Parameters.↲
↲
↲
The flow of the ETC601 SBC Selftest is based upon the fact that ↓
each test program receives a set of parameters as input and ↓
deliveres a buffer of error informations as output.↲
↲
The parameters are contained in a 16 bit word variable, a ↓
socalled switch variable, which survives the memory test in an ↓
internal iAPX186 CPU register. This variable contains the ↓
information necessary for the test administrator to manage the ↓
flow of the test program.↲
┆8c┆┆81┆┆90┆↓
┆0e┆↓
↲
┆a1┆name initial value ┆06┆comment┆05┆↲
halt bit 1 1: ┆84┆halts execution when an error is ↓
┆19┆┆a0┆┄┄discovered.↲
0: bypasses errors.↲
↲
loop bit 0 1: ┆84┆repeats the selection of the test ↓
┆19┆┆a0┆┄┄specified.↲
0: sequential flow.↲
↲
wait bit 0 1: ┆84┆used in the configuration phase ↓
┆19┆┆a0┆┄┄by the "test slaves".↲
0: ┆84┆release "test-slaves" (only ↓
┆19┆┆a0┆┄┄internal).↲
↲
boot bit 1 1: ┆84┆configurate and bootload after ↓
┆19┆┆a0┆┄┄end of selftest.↲
0: repeat own selftest.↲
↲
status bit 0 1: ┆84┆suppress status check.↲
0: perform status check.↲
↲
data bit 0 1: suppress data check.↲
0: perform data check.↲
↲
not used 0↲
↲
┆a1┆not used 0 ┆05┆↲
┆a1┆test.no. 00 identification of test program┆05┆↲
↲
Figure 3: Test parameter variable.↲
┆0f┆↓
↲
It is possible for the operator to manipulate these parameters by ↓
typing <esc>. this will cause the following questions, which must ↓
be answered one by one, to appear on the screen.↲
↲
============== Onboard memory size (k bytes): 00256↲
halt on error ? <Y/N>, Y/↲
┆8c┆┆83┆┆c8┆↓
loop ? <Y/N>, N/↲
boot after test ? <Y/N>, Y/↲
suppress status check ? <Y/N>, N/↲
suppress data check ? <Y/N>, N/↲
test no.: 00000/↲
↲
Figure 4: parameter setting.↲
↲
The answers to the "<Y/N>" questions are "Y", "N" or carriage ↓
return.↲
↲
The answer to the "test no.:" question is a legal test number ↓
and/or carriage return.↲
↲
↲
┆b0┆┆a1┆┆f0┆2.3 Test Numbers.↲
↲
↲
The relationship between test numbers and actual test programs ↓
are as follows:↲
┆0e┆↓
↲
┆a2┆┆e2┆┆a1┆Test No Test name ↲
0 memory test↲
1 RAM refresh test↲
2 iAPX186 DMA test power up↲
3 PIC test╞ ╞ tests↲
┆a1┆ 4 iAPX186 slave interrupt test↲
┆a1┆┆e1┆ 5 Ethernet test 2↲
6 8274 CHA test╞ ╞ extended↲
┆a1┆ 7╞ Floppy test┆e1┆╞ ╞ tests↲
┆0f┆↓
↲
The tests numbered 5-7 are not run in the default power up ↓
sequence. They are included as extended tests and must be ↓
requested explicit by operator intervention.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆f0┆2.4 Output From a Test.↲
↲
↲
At the end of every test program, the selftest will inform about ↓
its state, ok or error, to the operator via the connected ↓
console. The format will normally look as follows:↲
╱04002d4e0a0006000000000201413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f17464b555f69737dffffffffff04╱
↓
↲
<OK>↲
<test name:> , N↲
<error type> , <text><error data> ↲
0↲
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000201413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
↲
<error type> is a primary errortext informing about the specific ↓
error. <text> is of the kind "addr:", "exp:" and the like.↲
↲
↲
┆b0┆┆a1┆┆f0┆2.5 Default Interrupt Handling.↲
↲
↲
When the ETC601 SBC Selftest has finished the memory test, a set ↓
of default interrupt vectors are placed in the interrupt vector ↓
table. These vectors are primarily used to handle unexpected ↓
interrupts. There are two kinds of unexpected interrupts. The ↓
first is handled by the interrupt procedure for internal iAPX186 ↓
instruction interrupts and the second is handled by the interrupt ↓
procedure for illegal device interrupts.↲
↲
↲
┆b0┆┆a1┆┆f0┆2.5.1 Instruction Exception.↲
↲
↲
If an Instruction Exception interrupt occurs, it is likely to ↓
believe that this was caused by a malfunction of the iAPX186, ↓
because this interrupt is related to some CPU instructions.↲
↲
If this error should occur it will produce the following ↓
errortext:↲
↲
┆b0┆╞ ╞ ">> instruction exception"↲
↲
The corrosponding error number is 8.↲
↲
↲
┆8c┆┆83┆┆f0┆↓
┆b0┆┆a1┆┆f0┆2.5.2 Illegal Interrupt.↲
↲
↲
At the end of every test loop the reception of interrupts are ↓
enabled. Only two of the interrupt request lines will be used in ↓
the Selftest. This is the MPSC 8274 receive interrupt which is ↓
connected to the 80186 interrupt request INT1 and the parity ↓
interrupt which is connected to the 8259 interrupt request IR3.↲
↲
↲
All other interrupt requests will be decoded as illegal ↓
interrupts and will produce the following errortext:↲
↲
┆b0┆╞ ╞ "illegal interrupt"↲
↲
followed by the information about, which level was issuing the ↓
interrupt.↲
↲
The corresponding error number is 5.↲
↲
↲
In the PIC interrupt test and the Multibus interrupt test an ↓
"illegal interrupt" error is produced if it is impossible to ↓
clear the interrupt following the test. This may happen if a ↓
jumper in the interrupt strap area S6 is missing.↲
┆8c┆┆82┆┆ac┆↓
┆0e┆↓
↲
┆a1┆Interrupt name Vector type Related instructions┆05┆↲
Divide Error 0 DIV, IDIV↲
Single step 1 ALL↲
NMI 2 ALL↲
Breakpoint 3 INT↲
INT0 Detected 4 INT0↲
overflow↲
Array Bounds 5 BOUND↲
Unused Opcode 6 Undefined Opcodes↲
┆a1┆ESC Opcode 7 ESC Opcodes┆05┆↲
┆a1┆Interrupt name Vector type Related interrupt level┆05┆↲
Timer 0 Interrupt 8 8↲
Reserved 9 -↲
DMA 0 Interrupt 10 10↲
DMA 1 Interrupt 11 11↲
INT0 Interrupt 12* 12↲
INT1 Interrupt 13** 13↲
INT2 Interrupt 14* 14↲
INT3 Interrupt 15** 15↲
Timer 1 Interrupt 18 8↲
┆a1┆Timer 2 Interrupt 19 8┆05┆↲
8259 IR0 20 20↲
8259 IR1 21 21↲
8259 IR2 22 22↲
Par-int 23 23↲
8259 IR4 24 24↲
8259 IR5 25 25↲
8259 IR6 26 26↲
8259 IR7 27 27↲
↲
Figure 5: Interrupt Level Table.↲
↲
* INT0 and INT2 are used as INT0 and INTA0 for the 8259.↲
** INT1 and INT3 are used as INT1 and INTA2 for the 8274 MPSC.↲
┆0f┆↓
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆3. I/O Procedures and Table Indexing.↓
↲
↲
Included in the ETC601 SBC Selftest is a rather simple handling ↓
of console input and output. Furthermore it uses array tables to ↓
decide which test is to be started and which errortext is to be ↓
written.↲
↲
↲
┆b0┆┆a1┆┆f0┆3.1 Input.↲
↲
↲
Input is handled in the most simple way possible. It works ↓
operator interactive using the one character buffer in the USART ↓
itself.↲
↲
USART receive interrupts is only used to give different ↓
attentions to the selftest. These are <esc>, <cntrl><@>, ↓
<cntrl><Q>, and <cntrl><S>. See section 2.1.↲
↲
↲
┆b0┆┆a1┆┆f0┆3.2 Output.↲
↲
↲
The testoutput from the selftest is a character by character ↓
output without any interrupt generation. The condition for ↓
sending a character to the MPSC 8274 is the status, transmitter ↓
buffer empty.↲
↲
┆b0┆┆a1┆┆f0┆3.3 Test Selection.↲
↲
↲
The test number field of the test parameter switch (see fig. 3) ↓
is used to select the next test to be run. This number is an ↓
index in an array, which for every test contains the offset to ↓
the introduction text and the starting address.↲
↲
┆8c┆┆83┆┆bc┆↓
The ETC601 SBC Selftest will always write the test introduction ↓
text before the test is started.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4┆a1┆. Selftest Switch Settings.↲
↲
↲
The ETC601 is equipped with a Selftest configuration switch ↓
(S23), which is connected to the 8255, PA port.↲
↲
PA, bit 0-1 : ┆84┆These bits are used by the memory test to determine ↓
┆19┆┆8e┆┄┄the onboard memory size.↲
↲
PA, bit 2 : ┆84┆this bit is used to configurate the CPU as a "test-↓
┆19┆┆8e┆┄┄host" or "test-slave".↲
↲
PA, bit 3 : ┆84┆This bit, if "1", will cause the Selftest to ↓
┆19┆┆8e┆┄┄continously run in a loop that is testing the CPU ↓
┆19┆┆8e┆┄┄to memory bus and generate chip select on all ↓
┆19┆┆8e┆┄┄onboard controller chips. See chapter 7. This is ↓
┆19┆┆8e┆┄┄intended for complex fault finding.↲
↲
PA, bit 4 : ┆84┆this bit, if "1" makes the testprogram to assume an ↓
┆19┆┆8e┆┄┄8 MHz CPU installed. This information is used to ↓
┆19┆┆8e┆┄┄control the on-chip timer used as baudrate ↓
┆19┆┆8e┆┄┄generator.↲
↲
╞ ╞ ╞ ╞ ╞ 00 : 128 Kbytes RAM↲
. . . . .╞ ╞ ╞ ╞ 01 : 256 Kbytes RAM↲
1┆b0┆.┆f0┆ . . . .╞ ╞ ╞ ╞ 10 : 512 Kbytes RAM↲
! ! ! ┆a1┆! ! 11 : 1 Mbytes RAM ╞ ↲
! ! !↲
! ! !╞ ╞ ╞ ╞ 0 : Master ETC601↲
! ! !┆a2┆┆a1┆┆e2┆ ╞ ╞ ╞ ╞ 1 : Slave ETC601 ↲
! !↲
! !╞ ╞ ╞ ╞ 0 : Normal mode↲
! !┆a1┆╞ ╞ ╞ ╞ 1 : Chip select mode ↲
!↲
!╞ ╞ ╞ ╞ 0 : 6 MHz iAPX186 ↲
!┆a1┆ ╞ ╞ ╞ ╞ 1 : 8 MHz iAPX186 ↲
↲
┆a1┆┆e1┆┆e1┆┆e1┆↲
┆a1┆Figure 8 : The S23 jumper area.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5. Initialization.↲
↲
↲
After power up/reset the ETC601 SBC Selftest will perform some ↓
initializations of the onboard controllers.↲
↲
The initializations are common for the Selftest and the ↓
bootloader.↲
↲
↲
┆b0┆┆a1┆┆f0┆5.1 Wait States.↲
↲
↲
The PROM and RAM memory will have 0 wait states.↲
↲
Pheripherals on PCS 0-3 will have 1 wait state↲
Pheripherals on PCS 4-6 will have 2 wait states.↲
↲
↲
┆b0┆┆a1┆┆f0┆5.2 iAPX186 Interrupt Controller.↲
↲
↲
The interrupt vector for the iAPX186 controllers is tied to ↓
specific memory locations, equal to the location 20H for the ↓
first vector in the table. See section 2.5.↲
↲
╞ ┆1f┆┆a1┆INT0/INT2:↲
Port : FF38H↲
Value : 37H↲
↲
These two pins of the iAPX186 is used for cascading to the extern ↓
interrupt controller 8259.↲
↲
╞ ┆a1┆INT1/INT3:↲
Port : FF3AH↲
Value : 37H↲
↲
┆8c┆┆83┆┆bc┆↓
These two pins of the iAPX80186 is used for cascading to the MPSC ↓
8274.↲
↲
╞ ┆a1┆Mask Register:↲
Port : FF28H↲
Value : FDH↲
↲
Which will mask the following:↲
↲
╞ I3 : 1╞ ; INT3↲
╞ I2 : 1╞ ; INT2↲
╞ I1 : 1╞ ; INT1↲
╞ I0 : 0╞ ; INT0↲
╞ D1 : 1╞ ; DMA1↲
╞ D0 : 1╞ ; DMA0↲
╞ TRM : 1╞ ; Timers↲
↲
↲
┆b0┆┆a1┆┆f0┆5.3 Programable Interrupt Controller 8259.↲
↲
↲
The ETC601 SBC Selftest is configurated with USART parity ↓
interrupt connected to IR3.↲
↲
╞ ┆a1┆8259 setup:↲
ICW 1 : 1BH ; level triggered input, single mode↲
ICW 2 : 20H ; the interrupt vector table starts in 80H↲
ICW 4 : 1DH ┆84┆; non buffer mode, normal EOI and not fully ↓
┆19┆┆95┆┄┄; nested.↲
MASK : F7H ; enable parity interrupt on IR3.↲
↲
↲
┆b0┆┆a1┆┆f0┆5.4 iAPX186 Timer 1.↲
↲
↲
Timer 1 is initialized as a baudrate generator in alternating ↓
mode with even duty cycle. If no console is connected the ↓
baudrate is set to 9600 baud, otherwise the Baud Rate ↓
Determination procedure is entered see chapter 6.↲
↲
↲
┆8c┆┆83┆┆ec┆↓
┆b0┆┆a1┆┆f0┆5.5 MPSC 8274 Ch. B (Console Interface).↲
↲
↲
Baudrate factor : X16↲
Character length : 8 bits↲
Parity : none↲
Stop bits : 2↲
Mode : asynchronous.↲
↲
↲
┆b0┆┆a1┆┆f0┆5.6 Bustest, Chip Select.↲
↲
↲
To ease complex debugging, a CPU to memory bustest and a chip ↓
select loop are supplied as a function of the 8255 PA3 bit.↲
↲
If the 8255 PA3 bit is set to "1" both the bustest and the chip ↓
select loop are executed. First there will be performed input ↓
instructions on all relevant I/O-devices. These are:↲
↲
Port 0, 80H, 100H, 180H, 182H, 184H, 186H, 190H, 1C0H, 1C2H, ↓
200H, 280H and 300H.↲
↲
This might be used for measurements.↲
↲
Secondly a CPU to memory bustest is performed. This loop will use ↓
one word in the RAM-memory. This word is initialized with a zero, ↓
whereafter a one-bit is shifted from the LSB towards the MSB. For ↓
every shift, the pattern is read and checked. Should it occur, ↓
that the pattern was not written, the program will loop ↓
continously trying to read the correct pattern. This means, that ↓
if the bus signals are checked by an oscilloscope and the word ↓
read is found to have the bits 0 and 1 to the one level and the ↓
rest to the zero level, it must be bit 2, that contains the ↓
error.↲
↲
When the one-bit has been shifted through the entire word, this ↓
word is reinitialized to all ones and a zero-bit is shifted ↓
through it.↲
↲
┆8c┆┆83┆┆e0┆↓
If the 8255 PA3 bit is strapped to "0", these measurement loops ↓
are bypassed when powering up.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆6. Automatic Baud Rate Determination.↲
↲
↲
After power on or external reset the selftest determines whether ↓
a console is present or not by sampling the DSR signal.↲
↲
If a console is present then the selftest enters the Automatic ↓
Baud Rate determination phase, otherwise the baud rate is set to ↓
9600 Baud and the selftest proceeds.↲
↲
In the Automatic Baud Rate Determination phase the test program ↓
initializes the console to 9600 Baud, and starts to write * ↓
(stars) to the console. Note that the appearance on the operator ↓
console may not be stars, worst case nothing is seen at all. The ↓
selftest waits for the operator to type one or two upper case U, ↓
this will allow the selftest to determine the baud rate of the ↓
attached console. After the determination of the baud rate the ↓
test proceeds. Baud rate recognized are 300, 600, 1200, 2400, ↓
4800 and 9600 Baud.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆7. The Selftest Snooper.↲
↲
↲
The ETC601 SBC Selftest is equipped with a socalled Snooper ↓
facility, which enables the user to manipulate with RAM data and ↓
input, output ports. It is envoked by entering af <cntrl><@> on ↓
the connected console.↲
↲
The Snooper can be entered at the termination of any of the test ↓
programs.↲
↲
When the Snooper is entered, it will respond with the following ↓
menu:↲
↲
>> Snooper↲
↲
<R> : display memory↲
<S> : substitute word↲
<I> : input from port↲
<O> : output to port↲
<,> : continue selected↲
<X> : exit from snooper↲
↲
*** Note: ┆84┆that canging the content of RAM memory words or ↓
┆19┆┆8a┆┄┄performing output to devices may have som drastic ↓
┆19┆┆8a┆┄┄effect to the Selftest system.↲
↲
When entering the character "X" on the connected console, the ↓
Snooper will return control to the Selftest, which will proceed ↓
its operation.↲
↲
The Snooper works in an interrupt disabled mode.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆f0┆7.1 Press <R>.↲
↲
↲
When the character "R" has been selected, the following two ↓
questions concerning the address will be asked:↲
↲
Segm.: _ _ _ _ Addr.: _ _ _ _↲
↲
These questions must be answered with the address of the first ↓
memory word to be displayed.↲
↲
When the address has been selected, 100 - 16 bit words will be ↓
shown on the display of the connected console. The format of the ↓
output is 20 lines each with the content of 5 words. It is shown ↓
in hexadecimal and in ascii.↲
↲
The following 100 words will be displayed if a "," is entered.↲
↲
A new first address can be selected by reentering the character ↓
"R".↲
↲
↲
┆b0┆┆a1┆┆f0┆7.2 Press <S>.↲
↲
↲
When the character "S" has been selected, the following two ↓
questions concerning the address will be asked:↲
↲
Segm.: _ _ _ _ Addr.: _ _ _ _↲
↲
These questions must be answered with the address of the first ↓
word to be changed.↲
↲
When the address has been selected, the first word is displayed.↓
Now there are two possibilities, either to fill in a new value or↓
to press ",".↲
↲
A new value may consist of from one up to four digits. If less↓
than four digits is input, the number will be entered by pressing↓
"return".↲
↲
┆8c┆┆83┆┆ec┆↓
When a new value has been entered, the value of the next word is ↓
shown.↲
┆b0┆┆a1┆↲
If the character "," is entered, the memory word displayed is ↓
left unchanged, and the next word is displayed.↲
↲
The way to escape the substitute session, is to select a new ↓
function or to exit the snooper.↲
↲
It is possible to fill an amount of i.e. the DMA-transmit buffer ↓
with a certain data pattern by pressing repeat and the data (e.g. ↓
0-F). This is due to the fact that entering 4 digits, will ↓
automatically enter these data into the word and continue with ↓
the next word.↲
↲
↲
┆b0┆┆a1┆┆f0┆7.3 Press <I>.↲
↲
↲
When the character "I" has been selected the Snooper will respond ↓
with the question:↲
↲
port: _ _ _ _↲
↲
When a port number has been entered, the 16 bit word contained in ↓
this port is shown. If the port is an 8 bit type, it is the 8 ↓
LSB, that is significant.↲
↲
↲
┆b0┆┆a1┆┆b0┆┆f0┆7.4 Press <O>.↲
↲
↲
When the character "O" has been selected the Snooper will respond ↓
with the question:↲
↲
port: _ _ _ _↲
↲
════════════════════════════════════════════════════════════════════════
↓
When a port number has been entered, the 16 bit word to be send, ↓
must be entered. If the port is an 8 bit type, it is the 8 LSB, ↓
that is significant.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆8. Test 0 = Memory Test.↲
↲
↲
The memory test of the ETC601 SBC Selftest consists of two ↓
parts, a PROM checksum test and a RAM memory test. The PROM ↓
checksum test is only run once at power up, whereas the RAM ↓
memory test may be run several times, if requested by the ↓
operator.↲
↲
↲
┆b0┆┆a1┆┆f0┆8.1 PROM Checksum Test.↲
↲
↲
The content of the two PROM's, located in U34 and U35, are ↓
summarixed independently of each other. The summation for each ↓
PROM must result in a zero. For that reason each of the PROM's ↓
contains a compensation byte.↲
↲
U34 contains all the even bytes and U35 all the odd bytes.↲
↲
If the summation is different from zero the following error-↓
message will be output to the console:↲
↲
┆b0┆checksum: <00><EE> error↲
↲
where <00> is the 8 bit sum of U35, and <EE> is the 8 bit sum of ↓
U34.↲
↲
This error means that the content of the program PROM's has been ↓
damaged and that the PROM's must be changed.↲
↲
The corresponding error number is 1.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆f0┆8.2 RAM Memory Test.↲
↲
The RAM memory test of the ETC601 SBC Selftest verifies the ↓
onboard memory.↲
↲
The RAM memory test is able to test onboard memory of four ↓
different sizes. These are 128 k-, 256 k-, 512 k-bytes, or 1 ↓
Mbytes.↲
↲
The size of the memory is configurated in the S23 strap, PA bit 0 ↓
and 1, see chapter 4 fig. 8.↲
↲
The memory test is a register based test not using memory ↓
variables at all, neither for values nor stack. It is testing ↓
every single byte of the onboard memory.↲
↲
This fact leaves only two registers for variables that can ↓
survive the memory test, a pass-counter and the parameter word. ↓
It gives some of the explanation for the simple structure of the ↓
selftest testadministrator.↲
↲
↲
┆b0┆┆a1┆┆f0┆8.2.2 Memory Test Pattern.↲
↲
↲
The onboard Dual Port RAM memory consists of memory chips of 1 ↓
bit x 64 k. the memory test executes 4 passes through the entire ↓
memory, two times writing and two times reading.↲
↲
The test starts in the highest address, derived from the S23 ↓
strap, and inserts the pattern towards lower addresses.↲
↲
When all memory words have been written and tested, they are ↓
tested again with the inversed pattern, this means, all bits are ↓
tested for "zero" and "one" insertion.↲
↲
If an error occurs, a message will be written as follows:↲
↲
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆b0┆memory test: error, addr.: <ssss>:<aaaa>, exp.: <eeee>,rec.: <rrrr>↲
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
↲
┆8c┆┆83┆┆e0┆↓
Where ↲
╞ <ssss> is the segment address↲
╞ <aaaa> is the offset address↲
╞ <eeee> is the expected pattern↲
╞ <rrrr> is the received pattern.↲
↲
In case of an error the testadministrator pass-counter will be ↓
destroyed.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆9. Test 1 = RAM Refresh Test.↲
↲
↲
The RAM refresh test of the ETC601 SBC Selftest assist in the ↓
verification of the memory control logic functionality. The main ↓
purpose is to discover the decay of data caused by a malfunction ↓
of the RAM refresh circuitry.↲
↲
The test pattern written is a counting pattern and the size of ↓
the test buffer is 4 K, 16 bit words.↲
↲
When the pattern has been written the test program enters a ↓
waiting loop for approximate 5 sec., in which the CPU will not ↓
access the RAM memory. After the delay, the buffer will be ↓
checked to discover any decay.↲
↲
If decay is found, a message is written like this:↲
↲
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆b0┆RAM refresh test: error, addr.: <aaaa>, exp.: <eeee>, rec.: <rrrr>↲
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
↲
Where↲
╞ <aaaa> ┆84┆is the offset address relative to the start of the ↓
┆19┆┆8b┆┄┄test buffer.↲
<eeee> is the pattern written in this word.↲
╞ <rrrr> is the pattern read from this word.↲
↲
The corresponding error number is 9.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆10. Test 2 = iAPX186 DMA Test.↲
↲
↲
The iAPX186 DMA Test of ETC601 SBC Selftest applies to the ↓
verification of the functionality of the two on-chip iAPX186 DMA ↓
channels.↲
↲
Both DMA channels are initialized to memory to memory transports. ↓
Channel 0 will transfer to the lowest address of its receive ↓
buffer first, and channel 1 will transfer to the highest address ↓
of its receive buffer first.↲
↲
Both channels are started and will transfer bytes simultaneously. ↓
The procedure of the test is to check that the transfer count ↓
reaches zero before a programmed time-interval elapses. The ↓
timeout is approximate 200mS.↲
↲
If both channels have transferred the test buffer of 8 k bytes ↓
each without timeout, a datacheck of both receive buffers is ↓
performed. The data compare routine is based upon a string ↓
compare instruction. If a difference between the transmit and ↓
receive buffer is discovered, the 16 bit word in question is ↓
fetched from memory and shown as an errormessage. In other words, ↓
the errorneous word is fetches in both the string compare ↓
instruction and for the errormessage. This could mean, that if ↓
the discovered error was due to a sporadic memory error, the ↓
shown expected and received values could turn out to be equal.↲
↲
the control word of channel 0 is initialized to B606H and the ↓
control word of channel 1 is initialized to DA06H.↲
┆8c┆┆82┆┆e8┆↓
┆0e┆↓
↲
< ┆a1┆ Register Address ↲
┆a1┆ Register name Ch. 0 Ch.1 ↲
Control Word FFCAH FFDAH↲
Transfer Count FFC8H FFD8H↲
Destination Pointer FFC6H FFD6H↲
(upper 4 bits)↲
Destination Pointer FFC4H FFD4H↲
Source Pointer FFC2H FFD2H↲
(upper 4 bits)↲
┆a1┆ Source Pointer FFC0H FFC0H ↲
↲
Figure 13: DMA Control Block Format.↲
┆0f┆↓
↲
If the Transfer Count of one of the channels does not reach zero ↓
before timeout, a message as follows will be written:↲
↲
┆b0┆iAPX186 DMA test: transfer count error, reg.:<aaaa>, exp.:<eeee>↲
╞ ╞ ╞ ┆b0┆rec.:<rrrr>↲
↲
The corresponding error number is 4.↲
↲
where↲
╞ <aaaa> is the related Transfer Count Register.↲
╞ <eeee> is the expected value, always zero.↲
╞ <rrrr> is the content of the Transfer Count Register.↲
↲
If a data error is discovered, a message as follows will be ↓
written.↲
↲
┆b0┆iAPX186 DMA test: data error, addr.:<aaaa>, exp.:<eeee>,↲
┆b0┆ rec.: <rrrr>↲
↲
The corresponding error number is 3.↲
↲
where↲
╞ <aaaa> is the offset address in the receive buffer.↲
╞ <eeee> is the 16 bit word in the transmit buffer.↲
┆8c┆┆83┆┆c8┆↓
╞ <rrrr> is the 16 bit word in the received buffer.↲
↲
Both errors might be internal to the iAPX186 chip. ↓
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆11. Test 3 = PIC (8259) Interrupt Test.↲
↲
↲
The PIC (8259) Interrupt Test of the ETC601 SBC Selftest applies ↓
to the verification of the functionality of the 8259 interrupt ↓
controller.↲
↲
The procedure of the test is that the CPU writes the flagbyte. ↓
This will cause an interrupt request on the PIC level IR4. It is ↓
verified that the interrupt is generated within a programmed time ↓
interval, and that the interrupt arrived on the expected level. ↲
If no interrupt has arrived within the 4 mSec. a message is ↓
written like this:↲
↲
┆b0┆PIC test: interrupt timeout.↲
↲
The corresponding error number is 6.↲
If an interrupt has arrived, but on an unexpected level, a ↓
message is written like this:↲
↲
┆b0┆PIC test: illegal interrupt serviced, lev.: <aaaa>↲
↲
The corresponding error number is 11.↲
↲
where↲
╞ <aaaa> is the interrupt request level.↲
↲
Note that the default jumper settings in S6 giving flagbyte ↓
interrupt on IR4 is necessary to perform this test. (Consult ↓
hardware reference manual for strapping instructions).↲
↲
Failure to install this jumper will cause an error 5: "illegal ↓
interrupt".↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆12. Test 4 = iAPX186 Interrupt Test.↲
↲
↲
The iAPX186 Interrupt Test of the ETC601 SBC Selftest applies to ↓
the verification of the functionality of the on-chip interrupt ↓
controller.↲
↲
The procedure of the test is to start the internal timer 2 with a ↓
count value equal 1. It is tested that an interrupt is generated ↓
within a programmed time interval, and that the interrupt arrived ↓
on the expected level.↲
↲
If no interrupt has arrived within 4 mSec, a message is written ↓
like this:↲
↲
┆b0┆iAPX186 slave interrupt test: timeout↲
↲
The corresponding error number is 13.↲
↲
If an interrupt has arrived, but on an unexpected level, a ↓
message is written like this:↲
↲
┆b0┆iAPX186 slave interrupt test: illegal level serviced,↲
┆b0┆ lev.: <aaaa>↲
↲
The corresponding error number is 12.↲
↲
where↲
╞ <aaaa> is the actual level that interrupted.↲
↲
Both errors should be localized internal to the iAPX186 chip.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆13. Test 5 = Ethernet Test 2.↲
↲
↲
The ethernet test 2 applies to the verification of the 82586 co-↓
processor and its interface circuitry. The test makes an external ↓
data loopback test on the ethernet chip.↲
↲
First a software reset of the ethernet chip is made. This reset ↓
causes the ethernet controller to issue an interrupt when the ↓
reset is complete. If no interrupt is received an error message ↓
is generated like this:↲
↲
┆b0┆Ethernet test 2 : missing reset interrupt↲
↲
Corresponding error number is 61.↲
↲
Second a configure command is executed to the ethernet controller ↓
in order to select the external loopback mode. Again the sleftest ↓
awaits a configure complete interrupt, and if none is received an ↓
error message is generated like this:↲
↲
┆b0┆Ethernet test 2 : configuration command not accepted↲
↲
Corresponding error number is 58.↲
↲
Third a transmit frame command is executed. The ethernet address ↓
is the broadcast address and the message length is 14 bytes. If ↓
the transmit frame command is not accepted by the ethernet ↓
controller an error message is generated like this:↲
↲
┆b0┆Ethernet test 2 : transmit command not accepted↲
↲
corresponding error number is 59.↲
↲
Fourth, when the transmit frame command is completed the data ↓
sent is copared with the data received and if not the same an ↓
error message is generated otherwise the ethernet interface is ↓
said to be OK.↲
↲
┆8c┆┆83┆┆d4┆↓
┆b0┆Ethernet test 2 : data error add.:<aaaa>, exp.:<eeee>,↲
┆b0┆╞ ╞ ╞ ╞ rec.:<rrrr>↲
┆81┆↲
Corresponding error number is 60.↲
↲
where↲
add.:<aaaa> is offset address in the receive buffer↲
exp.:<eeee> is the expected value from the transmit buffer↲
rec.:<rrrr> is the received value in the receive buffer↲
↲
Another error message is written if the ethernet controller ↓
generates an interrupt without having reset the command just ↓
executed.↲
↲
┆b0┆Ethernet test 2 : interrupt but command word not cleared↲
↲
Corresponding error number is 48.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆14. Test 6 = 8274 ChA Test.↲
↲
↲
The 8274 test applies to the verification of the X.21 and V.24 ↓
interface build around the MPSC 8274 Channel A. This test is not ↓
part of the default power up test. It must be specially requsted ↓
by operator intervention. Before execution of the test it is ↓
necessary to install a loopback cable CBL 788(rear cabinet) or ↓
CBL 789 (card edge).↲
↲
The test examines the status signals for both the X.21 and the ↓
V.24 interface. A datatest in interrupt driven mode is made on ↓
both the X.21 and the V.24 interface. The capability of ↓
datatransport in DMA driven mode is tested on the V.24 interface.↲
↲
If no loopback cable is installed the test responds with this ↓
message:↲
↲
┆b0┆8274 CHA test : No testplug installed.↲
↲
Corresponding error number is 55.↲
↲
Note that this test rises the /RTS from the MPSC 8274 to test if ↓
the testplug is present. Therefore this error may be caused by a ↓
hardware error instead of missing testplug.↲
↲
If an error is detected during the status signal test an error ↓
message is written.↲
↲
┆b0┆8274 CHA test : V.24 status error exp.:<000e>, rec.:<000r>↲
↲
Corresponding error number is 53.↲
↲
OR↲
↲
┆b0┆8274 CHA test : X.21 status error exp.:<000e>, rec.:<000r>↲
┆82┆↲
Corresponding error number is 54.↲
↲
┆8c┆┆83┆┆d4┆↓
The received value holds the received CTS, DCD, CI ans DSR ↓
signals. In the V.24 status test the difference between expected ↓
and received must be interpreted like this:↲
↲
╞ expected bit 0 not equal received bit 0 = DCD error↲
╞ expected bit 2 not equal received bit 2 = CTS error↲
╞ expected bit 3 not equal received bit 3 = CI error↲
╞ expected bit 4 not equal received bit 4 = DSR error↲
↲
In the X.21 status test the difference between expected and ↓
received value must be intepreted like this:↲
↲
╞ expected bit 0 not equal received bit 0 = ┆84┆Clearing State ↓
┆19┆┆ae┆┄┄error (DCD)↲
╞ expected bit 2 not equal received bit 2 = ┆84┆Indication error ↓
┆19┆┆ae┆┄┄(CTS)↲
╞ expected bit 3 not equal received bit 3 = ┆84┆Clearing state ↓
┆19┆┆ae┆┄┄error (DCD)↲
╞ expected bit 4 not equal received bit 4 = ┆84┆Indication error ↓
┆19┆┆ae┆┄┄(CTS)↲
↲
↲
If an error is detected during the data test one of the following ↓
errormessages are produced:↲
↲
┆b0┆8274 CHA test : V.24 data error addr.:<aaaa>, exp.:<eeee>,↲
┆19┆┄┆81┆┆82┆╞ ╞ ╞ ╞ rec.:<rrrr>↲
┆81┆↲
Corresponding error number is 49.↲
↲
↲
┆b0┆8274 CHA test : X.21 data error addr.:<aaaa>, exp.:<eeee>,↲
┆b0┆╞ ╞ ╞ ╞ ╞ rec.:<rrrr>↲
┆81┆↲
Corresponding error number is 51.↲
↲
┆b0┆8274 CHA test : DMA data error addr.:<aaaa>, exp.:<eeee>,↲
┆b0┆╞ ╞ ╞ ╞ ╞ rec.:<rrrr>↲
┆8c┆┆83┆┆c8┆↓
┆81┆↲
Corresponding error number is 57.↲
↲
where↲
add.:<aaaa> is offset address in the receive buffer↲
exp.:<eeee> is the expected value from the transmit buffer↲
rec.:<rrrr> is the received value in the receive buffer↲
↲
The data test of the 8274 is executed with 8274 interrupts ↓
enabeled. If a exception interrupts is received during the ↓
data transfer an error message is produced.↲
↲
If the interrupt occur in the interrupt driven mode a message is ↓
generated like this:↲
↲
┆b0┆┆b0┆8274 CHA test : Interrupterror in interruptmode rec.:<rrrr>↲
↲
Corresponding error number is 52.↲
↲
If the interrupt occur in the DMA mode a message is generated ↓
like this:↲
↲
┆b0┆8274 CHA test : Interrupterror in DMA mode rec.:<rrrr>↲
↲
Corresponding error number is 56.↲
↲
Where↲
┆84┆rec.:<rrrr> holds the vectorcode related to the exception ↓
┆19┆┆85┆┄┄interrupt.↲
↲
If the data transfer is not completed within 250 ms. a timeout ↓
message is generated.↲
↲
┆b0┆8274 CHA test : Timeout↲
↲
Corresponding error number is 50.↲
↲
┆8c┆┆83┆┆bc┆↓
This message shoulæd indicate that the 8274 interrupt system ↓
failed.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆15. Test 7 = Floppy Test.↲
↲
↲
The floppy test applies to the verification of the functionality ↓
of the FDC601 controller and attached hardware. The FDC601 is a ↓
iSBX (Single Board eXtention) controller. The test should not be ↓
executed if no FDC601 is present.↲
↲
The test is an Extended test which is not executed by default ↓
after power on, but only when requested explicitely by an ↓
operator selecting loop in test no. 7, or setting the "boot after ↓
test" to "N".↲
↲
The procedure of the test is to write, read and compare a set of ↓
test pattern over a set of tracks on the floppy disk. The test ↓
use only sector one on the tracks, but both sides of the floppy ↓
disc are tested.↲
↲
↲
┆a1┆15.1 Test Results.↲
↲
↲
The floppy test will respond with one of the following texts to ↓
inform the operator about the outcome of the test.↲
↲
┆b0┆┆b0┆Floppy test : OK↲
↲
The result "OK" indicates a well succeded writing/reading and ↓
comparing for all sectors tested as well as proper functioning ↓
hardware, e.g. interrupt system and DMA transferring.↲
↲
┆b0┆Floppy test : FDC601 not installed↲
┆b0┆↲
Corresponding error number is 39.↲
↲
The result "FDC601 not installed" is evident, e.g. the SBX board ↓
FDC601 is not installed on top of the ETC601 board.↲
↲
┆8c┆┆83┆┆c8┆↓
┆b0┆Floppy test : drive not ready↲
↲
Corresponding error number is 31.↲
↲
The result "drive not ready" normally indicates that no disc is ↓
installed in the drive or the door is not closed. If these ↓
precautions are satisfied, a hard error exist, e.g. bad drive, ↓
bad FDC601 board, missing cables ti the drive, etc.↲
↲
┆b0┆Floppy test : write protect↲
┆b0┆↲
Corrosponding error number is 32.↲
↲
The result "write protect" is evident, e.g. the inserted floppy ↓
disk is write protected. Remove the disk protection for proper ↓
function.↲
↲
┆b0┆Floppy test : seek error↲
┆b0┆↲
Corresponding error number is 33.↲
↲
┆b0┆Floppy test : CRC error↲
┆b0┆↲
Corresponding error number is 34.↲
↲
┆b0┆Floppy test : record not found↲
┆b0┆↲
Corresponding error number is 35.↲
↲
The result "seek error", "CRC error" and "record not found" ↓
normally indicates a hard error on the inserted disk or that the ↓
disc is not formatted correct.↲
↲
┆b0┆Floppy test : lost data↲
┆b0┆↲
Corresponding error number is 36.↲
↲
┆8c┆┆83┆┆bc┆↓
The result "lost data" might indicate lack of data acknowledge ↓
from the FD1797 to the iAPX186 CPU within the DMA transfers, e.g. ↓
a strap on the ETC601 board.↲
↲
┆b0┆Floppy test : write fault↲
↲
Corresponding error number is 37.↲
↲
The result "write fault" might indicate hard errors on the ↓
inserted disk, but might also indicate hard errors within the ↓
hardware system.↲
↲
┆b0┆Floppy test : receive data error, reg:<aa>, exp: <ee>, rec: <rr>↲
↲
┆b0┆┆f0┆Corresponding error number is 38.↲
↲
The result "receive data error" indicates an inconsistence with ↓
┆19┆┄┆81┆┄respect to the data pattern read from the floppy disk. <aa> gives ↓
┆19┆┄┆81┆┄the local offset address in the received data block where the ↓
┆19┆┄┆81┆┄inconsistence was found, <ee> gives the expected value and <rr> ↓
┆19┆┄┆81┆┄gives the received value. This result could indicate a transfer ↓
┆19┆┄┆81┆┄error, due to speed variations.↲
↲
↲
┆a1┆15.2 The Test Disk.↲
↲
↲
Before the floppy test initiated, a formatted disk must be ↓
inserted in the floppy drive. The disk inserted must be double ↓
sided, double density, soft sectoring with track density of 96 ↓
TPI. The format of the disk corresponds with a CP/M format, e.g ↓
have 77 tracks where each track has 10 sectors of each 512 bytes ↓
length.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆16. Multibus Configuration and Test Monitor.↲
↲
↲
The socalled Multibus Test Monitor is deviced into two phases, an↓
automatic configuration with decoding of errors produced by the ↓
"test-slaves" and an interactive test phase, which must be ↓
requested by the operator.↲
↲
In the configuration phase the "test host" will produce a ↓
complete configuration table of the total RC3900 Multibus System.↲
↲
Example of the Multibus configuration:↲
┆0e┆↓
↲
╱04002d4e0a00060000000003014c3100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆a2┆┆05┆↲
Entry no. ,MB block ,state ,name ,RAM size * 64k, flag offset * 16k,err no.↲
┆a2┆┆05┆↲
00004 4000↲
00007 7000 ready COM601 00003 00004┆05┆00000 ↲
00010 A000 ready COM601 00001 00002 00002↲
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a00060000000003014c3100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆0f┆↓
↲
The interactive testphase, where it is possible to control the ↓
execution of tests on different "test-slaves", will only be ↓
entered, when requested by the operator (press <cntrl><S>) during ↓
the "test-master" selftest).↲
↲
↲
┆b0┆┆a1┆┆f0┆16.1 Automatic Configuration.↲
↲
↲
When a "test-master" has terminated its selftest, it will always ↓
perform an automatic Multibus configuration, in order to locate ↓
active "test-slaves" and eventually inactive memory areas.↲
↲
It is a convention that every "test-slave", when terminating its ↓
selftest will communicate with "test-master" by means of a ↓
predefined protocol.↲
↲
┆8c┆┆83┆┆bc┆↓
The configuration table will be shown on the console, and it is ↓
possible for the operator to decide, if it corresponds with the ↓
actual configuration. The entries, which has passed a handshake ↓
with the "test-master" will have the state "READY" and an ↓
identification name set in the configuration table.↲
↲
If one or more of the "test-slaves" have produced an error, the ↓
communication buffer for the related "test-slave" will contain ↓
some data and text, which will identify the error. The text in ↓
the buffer will be shown on the console as an errortext. About ↓
"test slave" errortexts, please consult the related manual.↲
↲
If the "test-master" has halted on one of these errors, it is ↓
possible to continue by typing <cntrl><Q>.↲
↲
↲
┆b0┆┆a1┆┆f0┆16.2 "Test Slave" Management.↲
↲
↲
The default action of the ETC601 SBC Selftest is to enter the ↓
bootloader when the configuration phase has been terminated. This ↓
can be overwritten by the operator typing <cntrl><S> during the ↓
"test-master" selftest.↲
↲
When the interactive test phase has been selected the following ↓
text will be written, when the automatic configuration has been ↓
terminated:↲
↲
┆b0┆>> Multibus monitoring↲
↲
Each of the connected "test slaves" has its own seperate set of ↓
parameters, which has the same format as those used by the CPU. ↓
↲
In the interative phase it is possible to start one or several ↓
"test-slaves" looping in the complete selftest or in a specific ↓
testprogram.↲
↲
┆8c┆┆83┆┆bc┆↓
Until a "test-slave" has received its first set of parameters, it ↓
will stay in an inactive mode.↲
↲
Every time "test-slave" recognizes an error, the related message ↓
will be written on the console.↲
↲
By typing <cntrl><S>, the configuration will be shown. When the ↓
interactive phase is selected new parameters for a "test-slave" ↓
may be entered after the configuration table has been written.↲
↲
An errormessage will be retyped on the console, when a change of ↓
parameters has been made.↲
↲
↲
┆b0┆┆a1┆┆f0┆16.3 Bootload.↲
↲
↲
Default action of the ETC601 SBC selftest is to enter the ↓
bootloader immediately after the configuration.↲
↲
When testing in the interactive phase the character <cntrl><Q> ↓
has two purposes.↲
↲
a) ┆84┆When the "test-master" has halted due to a "test slave" error, ↓
┆19┆┆83┆┄┄this "halt" can be quit by typing <entrl><Q>.↲
↲
b) ┆84┆When running in the interactive phase and typing <cntrl><Q>, ↓
┆19┆┆83┆┄┄this will force all the "test-slaves" and finally the "test- ↓
┆19┆┆83┆┄┄master" to enter the bootloader.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆17. ETC601 as a "Test-slave".↲
↲
↲
It is possible to configurate a ETC601 as a "test-slave" by the ↓
switch shown in fig. 9. This means that several ETC601 boards can ↓
be managed by one "test-master".↲
↲
Specialities:↲
↲
a) ┆84┆When looping in the memory test, the "test-slave" will ┆a1┆not┆e1┆ ↓
┆19┆┆83┆┄┄communicate with the "test-master".↲
↲
b) ┆84┆When both the parameters "suppress status check" and "suppress ↓
┆19┆┆83┆┄┄data check" is set to "Y", it will only communicate in case of ↓
┆19┆┆83┆┄┄errors.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆A. LAYOUT OF THE MASTER TO SLAVE COMMUNICATION BUFFER↲
╱04002d4e0a0006000000000201413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
↲
↲
┆a1┆┆05┆↲
!xxxx:FFFF ! id field ! !┆05┆!↲
┆a1┆! FFFE ! state ! !┆05┆!↲
! FFFD ! 'C' ! ! ┆05┆!↲
! FFFC ! 'O' ! ! !↲
! FFFB ! name 'M' ! ! !↲
! FFFA ! '6' ! ! ┆05┆!↲
! FFF9 ! '0' ! !┆05┆!↲
┆a1┆! FFF8 ! '1' ! ! !↲
! FFF7 ! ramsize ! !┆05┆!↲
! FFF6 ! flag_offset ! !┆05┆!↲
┆a1┆! FFF5 ! data pat ! !┆05┆!↲
! FFF4 ! switch ! ! ┆05┆!↲
┆a1┆! FFF3 ! test no ! !┆05┆!↲
┆a1┆! FFF2 ! param flag ! !┆05┆!↲
! FFF1 ! ! ! ┆05┆!↲
! FFF0 ! ! !┆05┆!↲
! **** ! slave error ! !┆05┆!↲
! **** ! text string ! !┆05┆!↲
! **** ! max 80 chars ! !┆05┆!↲
! FFA3 ! ! !┆05┆!↲
┆a1┆! FFA2 ! ! !┆05┆!↲
! FFA1 ! text length ! ! ┆05┆!↲
┆a1┆! FFA0 ! ! ! !↲
! FF9F ! aux3_data ! !┆05┆!↲
┆a1┆! FF9E ! ! !┆05┆!↲
! FF9D ! aux2_data ! !┆05┆!↲
┆a1┆! FF9C ! ! !┆05┆!↲
! FF9B ! aux1_data ! !┆05┆!↲
┆a1┆! FF9A ! ! !┆05┆!↲
! FF99 ! rec_data ! !┆05┆!↲
┆a1┆! FF98 ! ! !┆05┆!↲
! FF97 ! exp_data ! !┆05┆!↲
┆a1┆! FF96 ! ! !┆05┆!↲
! FF95 ! adr_data ! !┆05┆!↲
┆a1┆! FF94 ! ! !┆05┆!↲
! FF93 ! err_no ! !┆05┆!↲
┆a1┆! FF92 ! error flag ! !┆05┆!↲
┆1a┆┆1a┆onding error number i.↲
↲
┆b0┆Floppy test : drive not reagurat↓
┆b0┆ot found↲
┆b0┆↲
Corresponding error number i
0x0000…0020 (0,) 00 00 00 00 00 00 00 00 42 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0c 4e 00 00 00 ┆ B N ┆
0x0020…0040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
0x0040…0047 00 00 00 00 00 00 00 ┆ ┆
0x0047…0080 Params {
0x0047…0080 04 00 2d 4e 0c 00 06 00 00 00 00 03 01 48 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N H1` ┆
0x0047…0080 00 00 00 00 00 00 00 00 2d 37 41 4b 55 5f 69 73 7d 87 91 ff ff ff ff ff 04 ┆ -7AKU_iså ┆
0x0047…0080 }
0x0080…00a0 0d 0a 09 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 0d 0a 09 ┆ __________________________ ┆
0x00a0…00c0 45 64 69 74 69 6f 6e 3a 09 31 39 38 34 2e 31 31 2e 32 30 0d 0a 09 41 75 74 68 6f 72 3a 20 09 50 ┆Edition: 1984.11.20 Author: P┆
0x00c0…00e0 65 74 65 72 20 4c 75 6e 64 62 6f 0d 0a 09 52 43 53 4c 20 4e 6f 2e 3a 09 39 39 20 2d 20 31 20 2d ┆eter Lundbo RCSL No.: 99 - 1 -┆
0x00e0…0100 20 30 39 39 34 34 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ 09944 ┆
0x0100…0120 20 20 20 20 20 20 20 20 20 20 20 49 4e 54 45 52 4e 41 4c 20 44 4f 43 55 4d 45 4e 54 0d 0a 0d 0a ┆ INTERNAL DOCUMENT ┆
0x0120…0140 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f ┆ ______________________┆
0x0140…0160 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f ┆________________________________┆
0x0160…0180 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 0d 0a 0d 0a 54 69 74 6c 65 3a 0d 0a 0d 0a ┆__________________ Title: ┆
0x0180…01a0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 45 54 43 20 36 30 ┆ ETC 60┆
0x01a0…01c0 31 20 48 61 72 64 77 61 72 65 20 53 65 6c 66 74 65 73 74 0d 0a 20 20 20 20 20 20 20 20 20 20 20 ┆1 Hardware Selftest ┆
0x01c0…01e0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 55 73 65 72 27 73 20 4d 61 6e 75 ┆ User's Manu┆
0x01e0…0200 61 6c 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆al ┆
0x0200…0220 (1,) 20 20 20 20 56 65 72 73 69 6f 6e 20 31 2e 30 0d 0a 0d 0a 0d 0a 0d 0a 5f 5f 5f 5f 5f 5f 5f 5f 5f ┆ Version 1.0 _________┆
0x0220…0240 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f ┆________________________________┆
0x0240…0260 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 5f 0d ┆_______________________________ ┆
0x0260…0261 0a ┆ ┆
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[…0x1…]
0x02c0…02e0 0d 0a 4b 45 59 57 4f 52 44 53 20 3a 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 45 54 43 20 36 30 ┆ KEYWORDS : ETC 60┆
0x02e0…0300 31 2c 20 52 43 20 33 39 30 30 2c 20 49 6e 74 65 6c 2c 20 4d 75 6c 74 69 62 75 73 2c 20 48 61 72 ┆1, RC 3900, Intel, Multibus, Har┆
0x0300…0320 64 77 61 72 65 20 53 65 6c 66 74 65 73 74 2e 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 2d 2d 2d ┆dware Selftest. ---┆
0x0320…0340 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x0360…0380 2d 2d 2d 0d 0a 41 42 53 54 52 41 43 54 20 3a 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 84 54 68 ┆--- ABSTRACT : Th┆
0x0380…03a0 69 73 20 6d 61 6e 75 61 6c 20 63 6f 76 65 72 73 20 74 68 65 20 45 54 43 20 36 30 31 20 28 45 74 ┆is manual covers the ETC 601 (Et┆
0x03a0…03c0 68 65 72 6e 65 74 20 43 6f 6e 74 72 6f 6c 6c 65 72 29 20 48 61 72 64 77 61 72 65 20 0a 19 8a 80 ┆hernet Controller) Hardware ┆
0x03c0…03e0 80 53 65 6c 66 74 65 73 74 20 70 72 6f 67 72 61 6d 20 69 6e 73 74 61 6c 6c 65 64 20 69 6e 20 6f ┆ Selftest program installed in o┆
0x03e0…0400 6e 2d 62 6f 61 72 64 20 50 52 4f 4d 27 73 20 74 6f 67 65 74 68 65 72 20 77 69 74 68 20 0a 19 8a ┆n-board PROM's together with ┆
0x0400…0420 (2,) 80 80 74 68 65 20 62 6f 6f 74 6c 6f 61 64 65 72 2e 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 20 20 20 ┆ the bootloader. ┆
0x0420…043b 20 20 20 20 20 20 20 28 35 36 20 70 72 69 6e 74 65 64 20 70 61 67 65 73 29 0d 0a ┆ (56 printed pages) ┆
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0x0440…0460 69 0d 0a 0d 0a b0 a1 54 41 42 4c 45 20 4f 46 20 43 4f 4e 54 45 4e 54 53 05 50 41 47 45 0d 0a 0d ┆i TABLE OF CONTENTS PAGE ┆
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0x0461…049a }
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0x04d3…04e0 0a 0d 0a 0d 0a 31 2e 09 49 4e 54 52 4f ┆ 1. INTRO┆
0x04e0…0500 44 55 43 54 49 4f 4e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆DUCTION ........................┆
0x0500…0520 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 0d ┆........................... 1 ┆
0x0520…0540 0a 20 20 20 20 31 2e 31 20 20 54 68 65 20 4f 62 6a 65 63 74 20 6f 66 20 74 68 65 20 54 65 73 74 ┆ 1.1 The Object of the Test┆
0x0540…0560 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆s ..............................┆
0x0560…0580 2e 2e 2e 2e 2e 20 20 20 32 0d 0a 20 20 20 20 31 2e 32 20 20 41 75 74 6f 6d 61 74 69 63 20 43 6f ┆..... 2 1.2 Automatic Co┆
0x0580…05a0 6e 66 69 67 75 72 61 74 69 6f 6e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆nfiguration ....................┆
0x05a0…05c0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 32 0d 0a 20 20 20 20 31 2e 33 20 20 53 65 ┆............... 2 1.3 Se┆
0x05c0…05e0 6c 66 74 65 73 74 20 45 71 75 69 70 6d 65 6e 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆lftest Equipment ...............┆
0x05e0…0600 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 33 0d 0a 20 ┆......................... 3 ┆
0x0600…0620 (3,) 20 20 20 31 2e 34 20 20 4c 69 73 74 20 6f 66 20 49 6e 63 6c 75 64 65 64 20 54 65 73 74 73 20 2e ┆ 1.4 List of Included Tests .┆
0x0620…0640 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0640…0660 2e 2e 2e 20 20 20 33 0d 0a 0d 0a 32 2e 09 54 65 73 74 61 64 6d 69 6e 69 73 74 72 61 6f 72 20 2e ┆... 3 2. Testadministraor .┆
0x0660…0680 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0680…06a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 35 0d 0a 20 20 20 20 32 2e 31 20 20 4f 70 65 ┆.............. 5 2.1 Ope┆
0x06a0…06c0 72 61 74 6f 72 20 53 74 69 6d 75 6c 69 20 6f 66 20 74 68 65 20 53 65 6c 66 74 65 73 74 20 2e 2e ┆rator Stimuli of the Selftest ..┆
0x06c0…06e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 35 0d 0a 20 20 ┆........................ 5 ┆
0x06e0…0700 20 20 32 2e 32 20 20 50 61 72 61 6d 65 74 65 72 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ 2.2 Parameters ..............┆
0x0700…0720 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0720…0740 2e 2e 20 20 20 39 0d 0a 20 20 20 20 32 2e 33 20 20 54 65 73 74 20 4e 75 6d 62 65 72 73 20 2e 2e ┆.. 9 2.3 Test Numbers ..┆
0x0740…0760 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0760…0780 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 31 0d 0a 20 20 20 20 32 2e 34 20 20 4f 75 74 70 75 ┆............ 11 2.4 Outpu┆
0x0780…07a0 74 20 66 72 6f 6d 20 61 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆t from a Test ..................┆
0x07a0…07c0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 32 0d 0a 20 20 20 20 ┆...................... 12 ┆
0x07c0…07e0 32 2e 35 20 20 44 65 66 61 75 6c 74 20 49 6e 74 65 72 72 75 70 74 20 48 61 6e 64 6c 69 6e 67 20 ┆2.5 Default Interrupt Handling ┆
0x07e0…0800 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0800…0820 (4,) 20 20 31 32 0d 0a 20 20 20 20 20 20 20 20 20 32 2e 35 2e 31 20 20 49 6e 73 74 72 75 63 74 69 6f ┆ 12 2.5.1 Instructio┆
0x0820…0840 6e 20 45 78 63 65 70 74 69 6f 6e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆n Exception ....................┆
0x0840…0860 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 32 0d 0a 20 20 20 20 20 20 20 20 20 32 2e 35 2e 32 20 20 ┆.......... 12 2.5.2 ┆
0x0860…0880 49 6c 6c 65 67 61 6c 20 49 6e 74 65 72 72 75 70 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆Illegal Interrupt ..............┆
0x0880…08a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 33 0d 0a 0d 0a 33 2e 20 20 ┆.................... 13 3. ┆
0x08a0…08c0 49 2f 4f 20 50 72 6f 63 65 64 75 72 65 20 61 6e 64 20 54 61 62 6c 65 20 49 6e 64 65 78 69 6e 67 ┆I/O Procedure and Table Indexing┆
0x08c0…08e0 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ ...............................┆
0x08e0…0900 20 20 31 35 0d 0a 20 20 20 20 33 2e 31 20 20 49 6e 70 75 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ 15 3.1 Input ...........┆
0x0900…0920 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0920…0940 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 35 0d 0a 20 20 20 20 33 2e 32 20 20 4f 75 74 70 75 74 20 ┆.......... 15 3.2 Output ┆
0x0940…0960 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0960…0980 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 35 0d 0a 20 20 20 20 33 2e ┆.................... 15 3.┆
0x0980…09a0 33 20 20 54 65 73 74 20 53 65 6c 65 63 74 69 6f 6e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆3 Test Selection ..............┆
0x09a0…09c0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 ┆.............................. ┆
0x09c0…09e0 31 35 0d 0a 0d 0a 34 2e 20 20 53 65 6c 66 74 65 73 74 20 53 77 69 74 63 68 20 53 65 74 74 69 6e ┆15 4. Selftest Switch Settin┆
0x09e0…0a00 67 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆gs .............................┆
0x0a00…0a20 (5,) 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 37 0d 0a 0d 0a 35 2e 20 20 49 6e 69 74 69 61 6c 69 7a 61 ┆.......... 17 5. Initializa┆
0x0a20…0a40 74 69 6f 6e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆tion ...........................┆
0x0a40…0a60 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 38 0d 0a 20 20 20 20 ┆...................... 18 ┆
0x0a60…0a80 35 2e 31 20 20 57 61 69 74 20 53 74 61 74 65 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆5.1 Wait States ...............┆
0x0a80…0aa0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0aa0…0ac0 20 20 31 38 0d 0a 20 20 20 20 35 2e 32 20 20 69 41 50 58 31 38 36 20 49 6e 74 65 72 72 75 70 74 ┆ 18 5.2 iAPX186 Interrupt┆
0x0ac0…0ae0 20 43 6f 6e 74 72 6f 6c 6c 65 72 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ Controller ....................┆
0x0ae0…0b00 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 38 0d 0a 20 20 20 20 35 2e 33 20 20 50 72 6f 67 72 61 6d ┆.......... 18 5.3 Program┆
0x0b00…0b20 6d 61 62 6c 65 20 49 6e 74 65 72 72 75 70 74 20 43 6f 6e 74 72 6f 6c 6c 65 72 20 38 32 35 39 20 ┆mable Interrupt Controller 8259 ┆
0x0b20…0b40 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 39 0d 0a 20 20 20 20 35 2e ┆.................... 19 5.┆
0x0b40…0b60 34 20 20 69 41 50 58 31 38 36 20 54 69 6d 65 72 20 31 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆4 iAPX186 Timer 1 .............┆
0x0b60…0b80 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 ┆.............................. ┆
0x0b80…0ba0 31 39 0d 0a 20 20 20 20 35 2e 35 20 20 4d 50 53 43 20 38 32 37 34 20 43 68 2e 20 42 20 28 43 6f ┆19 5.5 MPSC 8274 Ch. B (Co┆
0x0ba0…0bc0 6e 73 6f 6c 65 20 49 6e 74 65 72 66 61 63 65 29 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆nsole Interface) ...............┆
0x0bc0…0be0 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 30 0d 0a 20 20 20 20 35 2e 36 20 20 42 75 73 74 65 73 74 2c 20 ┆........ 20 5.6 Bustest, ┆
0x0be0…0c00 43 68 69 70 20 53 65 6c 65 63 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆Chip Select ....................┆
0x0c00…0c20 (6,) 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 30 0d 0a 0d 0a 36 2e 20 20 41 75 ┆.................. 20 6. Au┆
0x0c20…0c40 74 6f 6d 61 74 69 63 20 42 61 75 64 20 52 61 74 65 20 44 65 74 65 72 6d 69 6e 61 74 69 6f 6e 20 ┆tomatic Baud Rate Determination ┆
0x0c40…0c60 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 ┆.............................. ┆
0x0c60…0c80 32 32 0d 0a 0d 0a 37 2e 09 54 68 65 20 53 65 6c 66 74 65 73 74 20 53 6e 6f 6f 70 65 72 20 2e 2e ┆22 7. The Selftest Snooper ..┆
0x0c80…0ca0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0ca0…0cc0 2e 2e 2e 2e 2e 2e 2e 2e 2e 09 20 32 33 0d 0a 20 20 20 20 37 2e 31 20 20 50 72 65 73 73 20 3c 52 ┆......... 23 7.1 Press <R┆
0x0cc0…0ce0 3e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆> ..............................┆
0x0ce0…0d00 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 34 0d 0a 20 20 20 20 37 2e 32 ┆................... 24 7.2┆
0x0d00…0d20 20 20 50 72 65 73 73 20 3c 53 3e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ Press <S> ....................┆
0x0d20…0d40 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 ┆............................. 2┆
0x0d40…0d45 34 0d 0a 0d 0a ┆4 ┆
0x0d45…0d48 FormFeed {
0x0d45…0d48 0c 83 f8 ┆ ┆
0x0d45…0d48 }
0x0d48…0d60 0a 06 20 69 69 0d 0a 0d 0a a1 b0 54 41 42 4c 45 20 4f 46 20 43 4f 4e 54 ┆ ii TABLE OF CONT┆
0x0d60…0d80 45 4e 54 53 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ENTS ┆
0x0d80…0da0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 50 41 47 45 09 0d 0a 0d 0a ┆ PAGE ┆
0x0da0…0dc0 20 20 20 20 37 2e 33 20 20 50 72 65 73 73 20 3c 49 3e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ 7.3 Press <I> .............┆
0x0dc0…0de0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0de0…0e00 2e 2e 2e 2e 20 20 32 35 0d 0a 20 20 20 20 37 2e 34 20 20 50 72 65 73 73 20 3c 4f 3e 20 2e 2e 2e ┆.... 25 7.4 Press <O> ...┆
0x0e00…0e20 (7,) 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0e20…0e40 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 35 0d 0a 0d 0a a1 e1 38 e1 2e 20 20 54 65 73 ┆.............. 25 8 . Tes┆
0x0e40…0e60 74 20 30 20 3d 20 4d 65 6d 6f 72 79 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆t 0 = Memory Test ..............┆
0x0e60…0e80 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 ┆............................. 2┆
0x0e80…0ea0 37 0d 0a 20 20 20 20 38 2e 31 20 20 50 52 4f 4d 20 43 68 65 63 6b 73 75 6d 20 54 65 73 74 20 2e ┆7 8.1 PROM Checksum Test .┆
0x0ea0…0ec0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0ec0…0ee0 2e 2e 2e 2e 2e 2e 2e 20 20 32 37 0d 0a 20 20 20 20 38 2e 32 20 20 52 41 4d 20 4d 65 6d 6f 72 79 ┆....... 27 8.2 RAM Memory┆
0x0ee0…0f00 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ Test ..........................┆
0x0f00…0f20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 38 0d 0a 20 20 20 20 20 20 20 20 20 ┆................. 28 ┆
0x0f20…0f40 38 2e 32 2e 32 20 20 4d 65 6d 6f 72 79 20 54 65 73 74 20 50 61 74 74 65 72 6e 20 2e 2e 2e 2e 2e ┆8.2.2 Memory Test Pattern .....┆
0x0f40…0f60 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 38 0d ┆........................... 28 ┆
0x0f60…0f80 0a 0d 0a 39 2e 20 20 54 65 73 74 20 31 20 3d 20 52 41 4d 20 52 65 66 72 65 73 68 20 54 65 73 74 ┆ 9. Test 1 = RAM Refresh Test┆
0x0f80…0fa0 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ ...............................┆
0x0fa0…0fc0 2e 2e 2e 2e 2e 2e 2e 20 20 33 30 0d 0a 0d 0a 31 30 2e 20 54 65 73 74 20 32 20 3d 20 69 41 50 58 ┆....... 30 10. Test 2 = iAPX┆
0x0fc0…0fe0 31 38 36 20 44 4d 41 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆186 DMA Test ...................┆
0x0fe0…1000 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 33 31 0d 0a 0d 0a 31 31 2e 20 54 ┆................... 31 11. T┆
0x1000…1020 (8,) 65 73 74 20 33 20 3d 20 50 49 43 20 28 38 32 35 39 29 20 49 6e 74 65 72 72 75 70 74 20 54 65 73 ┆est 3 = PIC (8259) Interrupt Tes┆
0x1020…1040 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 ┆t ............................. ┆
0x1040…1060 20 33 34 0d 0a 0d 0a 31 32 2e 20 54 65 73 74 20 34 20 3d 20 69 41 50 58 31 38 36 20 49 6e 74 65 ┆ 34 12. Test 4 = iAPX186 Inte┆
0x1060…1080 72 72 75 70 74 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆rrupt Test .....................┆
0x1080…10a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 33 35 0d 0a 0d 0a 31 33 2e 20 54 65 73 74 20 35 20 3d 20 ┆........... 35 13. Test 5 = ┆
0x10a0…10c0 45 74 68 65 72 6e 65 74 20 54 65 73 74 20 32 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆Ethernet Test 2 ................┆
0x10c0…10e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 33 36 0d 0a 0d 0a 31 ┆....................... 36 1┆
0x10e0…1100 34 2e 20 54 65 73 74 20 36 20 3d 20 38 32 37 34 20 43 68 41 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e ┆4. Test 6 = 8274 ChA Test ......┆
0x1100…1120 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x1120…1140 2e 2e 2e 20 20 33 38 0d 0a 0d 0a 31 35 2e 20 54 65 73 74 20 37 20 3d 20 46 6c 6f 70 70 79 20 54 ┆... 38 15. Test 7 = Floppy T┆
0x1140…1160 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆est ............................┆
0x1160…1180 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 34 32 0d 0a 09 31 35 2e 31 20 54 65 73 74 20 ┆............... 42 15.1 Test ┆
0x1180…11a0 52 65 73 75 6c 74 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆Results ........................┆
0x11a0…11c0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 34 32 0d 0a 20 20 20 20 ┆...................... 42 ┆
0x11c0…11e0 31 35 2e 32 20 54 68 65 20 54 65 73 74 20 44 69 73 6b 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆15.2 The Test Disk .............┆
0x11e0…1200 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x1200…1220 (9,) 20 20 34 34 0d 0a 0d 0a 31 36 2e 20 4d 75 6c 74 69 62 75 73 20 43 6f 6e 66 69 67 75 72 61 74 69 ┆ 44 16. Multibus Configurati┆
0x1220…1240 6f 6e 20 61 6e 64 20 54 65 73 74 20 4d 6f 6e 69 74 6f 72 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆on and Test Monitor ............┆
0x1240…1260 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 34 35 0d 0a 09 31 36 2e 31 20 41 75 74 6f 6d 61 74 69 ┆............ 45 16.1 Automati┆
0x1260…1280 63 20 43 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆c Configuration ................┆
0x1280…12a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 34 35 0d 0a 20 20 20 20 31 36 2e ┆................... 45 16.┆
0x12a0…12c0 32 20 22 54 65 73 74 20 53 6c 61 76 65 22 20 4d 61 6e 61 67 65 6d 65 6e 74 20 2e 2e 2e 2e 2e 2e ┆2 "Test Slave" Management ......┆
0x12c0…12e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 34 ┆............................. 4┆
0x12e0…1300 36 0d 0a 20 20 20 20 31 36 2e 33 20 42 6f 6f 74 6c 6f 61 64 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆6 16.3 Bootload ...........┆
0x1300…1320 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x1320…1340 2e 2e 2e 2e 2e 2e 2e 20 20 34 37 0d 0a 0d 0a 31 37 2e 20 45 54 43 36 30 31 20 61 73 20 61 20 22 ┆....... 47 17. ETC601 as a "┆
0x1340…1360 54 65 73 74 2d 53 6c 61 76 65 22 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆Test-Slave" ....................┆
0x1360…1380 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 34 38 0d 0a 0d 0a 0d 0a b0 a1 41 ┆................... 48 A┆
0x1380…13a0 50 50 45 4e 44 49 58 0d 0a 0d 0a 41 2e 20 20 4c 41 59 4f 55 54 20 4f 46 20 54 48 45 20 4d 41 53 ┆PPENDIX A. LAYOUT OF THE MAS┆
0x13a0…13c0 54 45 52 20 54 4f 20 53 4c 41 56 45 20 43 4f 4d 4d 55 4e 49 43 41 54 49 4f 4e 20 42 55 46 46 45 ┆TER TO SLAVE COMMUNICATION BUFFE┆
0x13c0…13d7 52 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 34 39 0d 0a 0d 0a ┆R ............ 49 ┆
0x13d7…13da FormFeed {
0x13d7…13da 0c 83 e0 ┆ ┆
0x13d7…13da }
0x13da…13e0 0a 14 b3 06 0b 0d ┆ ┆
0x13e0…1400 0a b0 a1 31 2e 20 49 6e 74 72 6f 64 75 63 74 69 6f 6e 2e 0d 0a 0d 0a 0d 0a 52 43 33 39 30 30 20 ┆ 1. Introduction. RC3900 ┆
0x1400…1420 (10,) 69 73 20 61 20 66 61 6d 69 6c 79 20 62 61 73 65 64 20 6f 6e 20 74 68 65 20 49 6e 74 65 6c 20 4d ┆is a family based on the Intel M┆
0x1420…1440 75 6c 74 69 62 75 73 20 63 61 72 64 20 66 6f 72 6d 61 74 2e 20 0a 41 6e 20 61 63 74 75 61 6c 20 ┆ultibus card format. An actual ┆
0x1440…1460 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 6d 61 79 20 63 6f 6e 73 69 73 74 73 20 6f 66 20 6f 6e ┆configuration may consists of on┆
0x1460…1480 65 20 6f 72 20 6d 6f 72 65 20 43 50 55 2d 62 6f 61 72 64 73 2c 20 0a 6f 6e 65 20 6f 72 20 6d 6f ┆e or more CPU-boards, one or mo┆
0x1480…14a0 72 65 20 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 63 6f 6e 74 72 6f 6c 6c 65 72 73 20 28 43 4f ┆re communication controllers (CO┆
0x14a0…14c0 4d 36 30 31 29 20 61 6e 64 20 61 20 6e 75 6d 62 65 72 20 6f 66 20 0a 6f 74 68 65 72 20 63 6f 6e ┆M601) and a number of other con┆
0x14c0…14e0 74 72 6f 6c 6c 65 72 73 2e 20 54 68 65 20 45 54 43 36 30 31 20 77 68 69 63 68 20 69 73 20 63 6f ┆trollers. The ETC601 which is co┆
0x14e0…1500 76 65 72 65 64 20 62 79 20 74 68 69 73 20 6d 61 6e 75 61 6c 20 6d 61 79 20 0a 69 6e 20 73 6f 6d ┆vered by this manual may in som┆
0x1500…1520 65 20 73 79 73 74 65 6d 20 62 65 20 74 68 65 20 6d 61 69 6e 20 43 50 55 20 62 6f 61 72 64 2c 20 ┆e system be the main CPU board, ┆
0x1520…1540 77 68 65 72 65 61 73 20 69 6e 20 6f 74 68 65 72 73 20 69 74 20 6d 61 79 20 62 65 20 0a 61 20 63 ┆whereas in others it may be a c┆
0x1540…1560 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 6f 6e 6c 79 2e 0d 0a 0d ┆ommunication controller only. ┆
0x1560…1580 0a 54 68 65 73 65 20 53 69 6e 67 6c 65 20 42 6f 61 72 64 20 43 6f 6d 70 75 74 65 72 73 20 28 53 ┆ These Single Board Computers (S┆
0x1580…15a0 42 43 29 20 6d 61 79 20 65 61 63 68 20 62 65 20 63 6f 6e 73 69 64 65 72 65 64 20 61 73 20 0a 69 ┆BC) may each be considered as i┆
0x15a0…15c0 6e 74 65 6c 6c 69 67 65 6e 74 20 75 6e 69 74 73 2e 20 53 6f 6d 65 20 77 69 74 68 20 74 68 65 20 ┆ntelligent units. Some with the ┆
0x15c0…15e0 72 6f 6c 65 20 61 73 20 70 6f 74 65 6e 74 69 6f 6e 61 6c 20 4d 75 6c 74 69 62 75 73 20 0a 6d 61 ┆role as potentional Multibus ma┆
0x15e0…1600 73 74 65 72 73 20 28 45 54 43 36 30 31 29 2c 20 61 6e 64 20 73 6f 6d 65 20 61 73 20 70 6f 74 65 ┆sters (ETC601), and some as pote┆
0x1600…1620 (11,) 6e 74 69 6f 6e 61 6c 20 73 6c 61 76 65 73 20 28 43 4f 4d 36 30 31 29 2e 0d 0a 0d 0a 45 76 65 72 ┆ntional slaves (COM601). Ever┆
0x1620…1640 79 20 52 43 2d 6d 61 6e 75 66 61 63 74 75 72 65 64 20 69 6e 74 65 6c 6c 69 67 65 6e 74 20 4d 75 ┆y RC-manufactured intelligent Mu┆
0x1640…1660 6c 74 69 62 75 73 20 53 42 43 20 77 69 6c 6c 20 63 6f 6e 74 61 69 6e 20 61 20 0a 62 75 69 6c 74 ┆ltibus SBC will contain a built┆
0x1660…1680 2d 69 6e 20 50 52 4f 4d 2d 62 61 73 65 64 20 73 65 6c 66 74 65 73 74 20 70 72 6f 67 72 61 6d 20 ┆-in PROM-based selftest program ┆
0x1680…16a0 77 68 69 63 68 20 63 61 6e 20 62 65 20 63 6f 6e 73 69 64 65 72 65 64 20 61 73 20 0a 61 6e 20 69 ┆which can be considered as an i┆
0x16a0…16c0 6e 74 65 67 72 61 74 65 64 20 70 61 72 74 20 6f 66 20 74 68 65 20 53 42 43 20 62 6f 6f 74 6c 6f ┆ntegrated part of the SBC bootlo┆
0x16c0…16e0 61 64 2d 66 61 63 69 6c 69 74 79 2e 20 49 6e 20 6f 74 68 65 72 20 77 6f 72 64 73 20 0a 74 68 65 ┆ad-facility. In other words the┆
0x16e0…1700 20 70 6f 77 65 72 20 75 70 20 6f 66 20 61 20 73 79 73 74 65 6d 20 63 6f 75 6c 64 20 62 65 20 64 ┆ power up of a system could be d┆
0x1700…1720 65 76 69 64 65 64 20 69 6e 74 6f 20 74 68 72 65 65 20 70 68 61 73 65 73 2e 20 54 68 65 20 0a 66 ┆evided into three phases. The f┆
0x1720…1740 69 72 73 74 20 77 6f 75 6c 64 20 62 65 20 61 6e 20 69 6e 69 74 69 61 6c 69 7a 61 74 69 6f 6e 20 ┆irst would be an initialization ┆
0x1740…1760 6f 66 20 74 68 65 20 6f 6e 62 6f 61 72 64 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 63 68 69 70 73 2e ┆of the onboard controller chips.┆
0x1760…1780 20 0a 53 65 63 6f 6e 64 20 77 6f 75 6c 64 20 62 65 20 61 20 73 65 6c 66 74 65 73 74 20 6f 66 20 ┆ Second would be a selftest of ┆
0x1780…17a0 65 61 63 68 20 53 42 43 2c 20 74 65 72 6d 69 6e 61 74 65 64 20 62 79 20 61 20 0a 63 65 6e 74 72 ┆each SBC, terminated by a centr┆
0x17a0…17c0 61 6c 6c 69 7a 61 74 69 6f 6e 20 6f 66 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 73 20 69 6e 20 6f 6e ┆allization of informations in on┆
0x17c0…17e0 65 20 6f 66 20 74 68 65 20 62 6f 61 72 64 73 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 0a 74 68 ┆e of the boards connected to th┆
0x17e0…1800 65 20 4d 75 6c 74 69 62 75 73 2c 20 6e 61 6d 65 6c 79 20 74 68 65 20 22 74 65 73 74 2d 6d 61 73 ┆e Multibus, namely the "test-mas┆
0x1800…1820 (12,) 74 65 72 22 2e 20 54 68 65 20 74 68 69 72 64 20 70 68 61 73 65 20 69 73 20 61 20 0a 63 6f 6d 6d ┆ter". The third phase is a comm┆
0x1820…1840 6f 6e 20 62 6f 6f 74 6c 6f 61 64 20 6f 66 20 61 6c 6c 20 62 6f 61 72 64 73 20 63 6f 6e 6e 65 63 ┆on bootload of all boards connec┆
0x1840…1860 74 65 64 20 74 6f 20 74 68 65 20 4d 75 6c 74 69 62 75 73 2e 0d 0a 0d 0a 49 6e 20 74 68 65 20 74 ┆ted to the Multibus. In the t┆
0x1860…1880 65 73 74 2d 70 68 61 73 65 2c 20 61 6e 20 52 43 33 39 30 30 20 73 79 73 74 65 6d 2c 20 6d 75 73 ┆est-phase, an RC3900 system, mus┆
0x1880…18a0 74 20 62 65 20 63 6f 6e 73 69 64 65 72 65 64 20 61 73 20 0a 63 6f 6e 73 69 73 74 69 6e 67 20 6f ┆t be considered as consisting o┆
0x18a0…18c0 66 20 6f 6e 65 20 61 6e 64 20 6f 6e 6c 79 20 6f 6e 65 20 22 74 65 73 74 2d 6d 61 73 74 65 72 22 ┆f one and only one "test-master"┆
0x18c0…18e0 20 63 61 72 64 20 61 6e 64 20 61 20 6e 75 6d 62 65 72 20 6f 66 20 0a 22 74 65 73 74 2d 73 6c 61 ┆ card and a number of "test-sla┆
0x18e0…1900 76 65 22 20 63 61 72 64 73 2e 20 41 66 74 65 72 20 70 6f 77 65 72 20 6f 6e 20 74 68 65 20 22 74 ┆ve" cards. After power on the "t┆
0x1900…1920 65 73 74 2d 6d 61 73 74 65 72 22 20 61 6e 64 20 22 74 65 73 74 2d 0a 73 6c 61 76 65 73 22 20 65 ┆est-master" and "test- slaves" e┆
0x1920…1940 78 65 63 75 74 65 20 74 68 65 69 72 20 73 65 6c 66 74 65 73 74 20 70 72 6f 67 72 61 6d 73 20 63 ┆xecute their selftest programs c┆
0x1940…1960 6f 6e 63 75 72 72 65 6e 74 6c 79 2e 20 57 68 65 6e 20 74 68 65 20 0a 22 74 65 73 74 2d 6d 61 73 ┆oncurrently. When the "test-mas┆
0x1960…1980 74 65 72 22 20 68 61 73 20 66 69 6e 69 73 68 65 64 20 69 74 27 73 20 6f 77 6e 20 73 65 6c 66 74 ┆ter" has finished it's own selft┆
0x1980…19a0 65 73 74 2c 20 69 74 20 77 69 6c 6c 20 62 65 20 61 62 6c 65 20 74 6f 20 0a 6d 6f 6e 69 74 6f 72 ┆est, it will be able to monitor┆
0x19a0…19c0 20 6d 65 73 73 61 67 65 73 20 66 72 6f 6d 20 74 68 65 20 22 74 65 73 74 2d 73 6c 61 76 65 73 22 ┆ messages from the "test-slaves"┆
0x19c0…19e0 2c 20 61 6e 64 20 74 6f 20 69 6e 66 6c 75 65 6e 63 65 20 74 68 65 73 65 20 0a 74 6f 20 69 2e 65 ┆, and to influence these to i.e┆
0x19e0…1a00 2e 20 6c 6f 6f 70 20 69 6e 20 61 20 73 70 65 63 69 66 69 63 20 74 65 73 74 20 73 65 76 65 72 61 ┆. loop in a specific test severa┆
0x1a00…1a20 (13,) 6c 20 74 69 6d 65 73 2e 20 54 68 69 73 20 6d 65 61 6e 73 2c 20 74 68 61 74 20 0a 74 68 65 20 22 ┆l times. This means, that the "┆
0x1a20…1a40 74 65 73 74 2d 6d 61 73 74 65 72 22 20 6d 61 79 20 61 63 74 20 61 73 20 61 6e 20 69 6e 74 65 6c ┆test-master" may act as an intel┆
0x1a40…1a60 6c 69 67 65 6e 74 20 6d 6f 6e 69 74 6f 72 20 66 6f 72 20 61 20 0a 64 65 62 75 67 67 69 6e 67 20 ┆ligent monitor for a debugging ┆
0x1a60…1a80 73 65 73 73 69 6f 6e 20 6f 6e 20 74 68 65 20 22 74 65 73 74 2d 73 6c 61 76 65 73 22 2e 0d 0a 0d ┆session on the "test-slaves". ┆
0x1a80…1a83 0a 0d 0a ┆ ┆
0x1a83…1a86 FormFeed {
0x1a83…1a86 0c 83 a4 ┆ ┆
0x1a83…1a86 }
0x1a86…1aa0 0a 81 b0 a1 f0 31 2e 31 20 54 68 65 20 4f 62 6a 65 63 74 20 6f 66 20 74 68 65 ┆ 1.1 The Object of the┆
0x1aa0…1ac0 20 54 65 73 74 73 2e 0d 0a 0d 0a 0d 0a 49 74 20 69 73 20 74 68 65 20 69 6e 74 65 6e 74 69 6f 6e ┆ Tests. It is the intention┆
0x1ac0…1ae0 20 6f 66 20 74 68 69 73 20 73 79 73 74 65 6d 20 6f 66 20 53 42 43 2d 73 65 6c 66 74 65 73 74 73 ┆ of this system of SBC-selftests┆
0x1ae0…1b00 20 74 6f 20 63 6f 76 65 72 20 0a 74 68 72 65 65 20 69 6e 20 74 68 65 20 6e 61 74 75 72 65 20 64 ┆ to cover three in the nature d┆
0x1b00…1b20 69 66 66 65 72 65 6e 74 20 6e 65 65 64 73 2e 0d 0a 0d 0a 0d 0a 61 29 20 84 54 68 65 20 52 43 33 ┆ifferent needs. a) The RC3┆
0x1b20…1b40 39 30 30 20 69 73 20 65 71 75 69 70 70 65 64 20 77 69 74 68 20 61 20 70 6f 77 65 72 20 75 70 20 ┆900 is equipped with a power up ┆
0x1b40…1b60 73 65 6c 66 74 65 73 74 2c 20 63 6f 6e 73 69 73 74 69 6e 67 20 6f 66 20 0a 19 83 80 80 61 20 73 ┆selftest, consisting of a s┆
0x1b60…1b80 65 71 75 65 6e 63 65 20 6f 66 20 64 69 66 66 65 72 65 6e 74 20 74 65 73 74 20 70 72 6f 67 72 61 ┆equence of different test progra┆
0x1b80…1ba0 6d 73 2e 20 54 68 65 73 65 20 74 65 73 74 73 20 61 72 65 20 0a 19 83 80 80 6f 72 67 61 6e 69 7a ┆ms. These tests are organiz┆
0x1ba0…1bc0 65 64 20 77 69 74 68 20 72 69 73 69 6e 67 20 63 6f 6d 70 6c 65 78 69 74 79 2c 20 73 6f 20 74 68 ┆ed with rising complexity, so th┆
0x1bc0…1be0 61 74 20 61 73 20 66 61 72 20 61 73 20 70 6f 73 73 69 62 6c 65 20 0a 19 83 80 80 6e 6f 20 70 61 ┆at as far as possible no pa┆
0x1be0…1c00 72 74 20 6f 66 20 74 68 65 20 68 61 72 64 77 61 72 65 20 69 73 20 75 73 65 64 2c 20 62 65 66 6f ┆rt of the hardware is used, befo┆
0x1c00…1c20 (14,) 72 65 20 69 74 20 69 73 20 74 65 73 74 65 64 2e 20 49 74 20 0a 19 83 80 80 73 68 6f 75 6c 64 20 ┆re it is tested. It should ┆
0x1c20…1c40 65 73 74 61 62 6c 69 73 68 20 61 20 62 61 73 69 63 20 6c 65 76 65 6c 20 6f 66 20 63 6f 6e 66 69 ┆establish a basic level of confi┆
0x1c40…1c60 64 65 6e 63 65 20 74 6f 20 74 68 65 20 68 61 72 64 77 61 72 65 20 0a 19 83 80 80 69 6e 63 6c 75 ┆dence to the hardware inclu┆
0x1c60…1c80 64 65 64 20 69 6e 20 74 68 65 20 52 43 33 39 30 30 20 73 79 73 74 65 6d 2e 20 49 74 20 72 65 71 ┆ded in the RC3900 system. It req┆
0x1c80…1ca0 75 69 72 65 73 20 6e 6f 20 69 6e 74 65 72 61 63 74 69 6f 6e 20 66 72 6f 6d 20 0a 19 83 80 80 74 ┆uires no interaction from t┆
0x1ca0…1cc0 68 65 20 6f 70 65 72 61 74 6f 72 2e 0d 0a 0d 0a 62 29 20 84 49 74 20 67 69 76 65 73 20 74 68 65 ┆he operator. b) It gives the┆
0x1cc0…1ce0 20 70 72 6f 64 75 63 74 69 6f 6e 20 64 65 70 61 72 74 6d 65 6e 74 20 74 68 65 20 70 6f 73 73 69 ┆ production department the possi┆
0x1ce0…1d00 62 69 6c 69 74 79 20 6f 66 20 75 73 69 6e 67 20 0a 19 83 80 80 74 68 65 20 73 61 6d 65 20 74 65 ┆bility of using the same te┆
0x1d00…1d20 73 74 20 70 72 6f 67 72 61 6d 73 20 61 73 20 61 20 62 75 72 6e 2d 69 6e 20 66 61 63 69 6c 69 74 ┆st programs as a burn-in facilit┆
0x1d20…1d40 79 2e 20 54 68 69 73 20 69 73 20 75 70 74 61 69 6e 65 64 20 0a 19 83 80 80 62 79 20 74 68 65 20 ┆y. This is uptained by the ┆
0x1d40…1d60 66 61 63 74 20 74 68 61 74 20 74 68 65 20 74 65 73 74 20 70 72 6f 67 72 61 6d 73 20 6d 61 79 20 ┆fact that the test programs may ┆
0x1d60…1d80 62 65 20 63 6f 6e 74 72 6f 6c 6c 65 64 20 66 72 6f 6d 20 61 20 0a 19 83 80 80 63 6f 6e 6e 65 63 ┆be controlled from a connec┆
0x1d80…1da0 74 65 64 20 63 6f 6e 73 6f 6c 65 2e 20 54 68 65 20 74 65 73 74 73 20 69 6e 20 74 68 65 20 45 54 ┆ted console. The tests in the ET┆
0x1da0…1dc0 43 36 30 31 20 6d 61 79 20 65 61 63 68 20 65 69 74 68 65 72 20 72 75 6e 20 0a 19 83 80 80 69 6e ┆C601 may each either run in┆
0x1dc0…1de0 20 6c 6f 6f 70 2d 6d 6f 64 65 2c 20 6f 72 20 69 6e 20 61 20 62 69 67 20 73 65 71 75 65 6e 63 69 ┆ loop-mode, or in a big sequenci┆
0x1de0…1e00 61 6c 20 6c 6f 6f 70 20 69 6e 63 6c 75 64 69 6e 67 20 61 6c 6c 20 74 65 73 74 73 2e 20 0a 19 83 ┆al loop including all tests. ┆
0x1e00…1e20 (15,) 80 80 46 75 72 74 68 65 72 6d 6f 72 65 20 74 68 65 72 65 20 69 73 20 61 20 70 6f 73 73 69 62 69 ┆ Furthermore there is a possibi┆
0x1e20…1e40 6c 69 74 79 20 6f 66 20 68 61 76 69 6e 67 20 73 65 76 65 72 61 6c 20 53 42 43 27 73 20 0a 19 83 ┆lity of having several SBC's ┆
0x1e40…1e60 80 80 72 75 6e 6e 69 6e 67 20 74 68 65 69 72 20 74 65 73 74 73 20 69 6e 20 70 61 72 61 6c 6c 65 ┆ running their tests in paralle┆
0x1e60…1e80 6c 2c 20 61 6e 64 20 6d 61 6b 65 20 74 68 65 6d 20 72 65 70 65 61 74 20 69 74 20 69 6e 20 0a 19 ┆l, and make them repeat it in ┆
0x1e80…1ea0 83 80 80 74 68 65 20 69 6e 66 69 6e 69 74 65 2c 20 75 6e 64 65 72 20 74 68 65 20 63 6f 6e 74 72 ┆ the infinite, under the contr┆
0x1ea0…1ec0 6f 6c 65 20 6f 66 20 61 20 22 74 65 73 74 2d 6d 61 73 74 65 72 22 2e 0d 0a 0d 0a 63 29 20 84 49 ┆ole of a "test-master". c) I┆
0x1ec0…1ee0 74 20 73 75 70 70 6c 69 65 73 20 74 68 65 20 54 65 63 68 6e 69 63 61 6c 20 53 65 72 76 69 63 65 ┆t supplies the Technical Service┆
0x1ee0…1f00 20 44 65 70 61 72 74 6d 65 6e 74 20 77 69 74 68 20 61 20 64 69 61 67 6e 6f 73 74 69 63 20 0a 19 ┆ Department with a diagnostic ┆
0x1f00…1f20 83 80 80 74 6f 6f 6c 2c 20 74 68 61 74 20 77 69 6c 6c 20 61 73 73 69 73 74 20 74 68 65 6d 20 64 ┆ tool, that will assist them d┆
0x1f20…1f40 75 72 69 6e 67 20 74 68 65 69 72 20 64 65 62 75 67 67 69 6e 67 20 73 65 73 73 69 6f 6e 73 2e 0d ┆uring their debugging sessions. ┆
0x1f40…1f60 0a 0d 0a 0d 0a b0 a1 f0 31 2e 32 20 41 75 74 6f 6d 61 74 69 63 20 43 6f 6e 66 69 67 75 72 61 74 ┆ 1.2 Automatic Configurat┆
0x1f60…1f80 69 6f 6e 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 73 65 6c 66 74 65 73 74 20 6f 66 20 74 68 65 20 45 54 ┆ion. The selftest of the ET┆
0x1f80…1fa0 43 36 30 31 20 63 6f 6e 73 69 73 74 73 20 6f 66 20 61 20 73 65 74 20 6f 66 20 64 69 66 66 65 72 ┆C601 consists of a set of differ┆
0x1fa0…1fc0 65 6e 74 20 0a 74 65 73 74 70 72 6f 67 72 61 6d 73 20 77 68 69 63 68 20 69 73 20 72 75 6e 20 69 ┆ent testprograms which is run i┆
0x1fc0…1fe0 6e 20 73 65 71 75 65 6e 63 65 2e 20 57 68 65 6e 20 74 68 65 20 73 65 6c 66 74 65 73 74 20 72 75 ┆n sequence. When the selftest ru┆
0x1fe0…2000 6e 73 20 69 6e 20 0a 74 68 65 20 64 65 66 61 75 6c 74 20 6d 6f 64 65 20 77 69 74 68 20 6e 6f 20 ┆ns in the default mode with no ┆
0x2000…2020 (16,) 6f 70 65 72 61 74 6f 72 20 69 6e 74 65 72 66 65 72 65 6e 63 65 2c 20 74 68 65 6e 20 74 68 65 20 ┆operator interference, then the ┆
0x2020…2040 73 65 6c 66 74 65 73 74 20 0a 74 65 72 6d 69 6e 61 74 65 73 20 62 79 20 70 65 72 66 6f 72 6d 69 ┆selftest terminates by performi┆
0x2040…2060 6e 67 20 61 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 6f 66 20 74 68 65 20 4d 75 6c 74 69 62 ┆ng a configuration of the Multib┆
0x2060…2080 75 73 20 61 64 64 72 65 73 73 2d 0a 73 70 61 63 65 2e 20 49 74 20 77 69 6c 6c 20 61 63 74 20 61 ┆us address- space. It will act a┆
0x2080…20a0 73 20 61 20 22 74 65 73 74 2d 6d 61 73 74 65 72 22 20 61 6e 64 20 63 6f 6c 6c 65 63 74 20 74 65 ┆s a "test-master" and collect te┆
0x20a0…20c0 73 74 20 72 65 73 75 6c 74 73 20 0a 66 72 6f 6d 20 61 6c 6c 20 63 6f 6e 6e 65 63 74 65 64 20 52 ┆st results from all connected R┆
0x20c0…20e0 43 2d 6d 61 6e 75 66 61 63 74 75 72 65 64 20 53 42 43 27 73 2e 20 49 66 20 6e 6f 6e 65 20 6f 66 ┆C-manufactured SBC's. If none of┆
0x20e0…2100 20 74 68 65 20 0a 63 6f 6e 6e 65 63 74 65 64 20 53 42 43 27 73 20 68 61 73 20 65 78 68 69 62 69 ┆ the connected SBC's has exhibi┆
0x2100…2120 74 65 64 20 61 6e 20 65 72 72 6f 72 20 64 75 72 69 6e 67 20 74 68 65 20 73 65 6c 66 74 65 73 74 ┆ted an error during the selftest┆
0x2120…2140 2c 20 74 68 65 6e 20 0a 74 68 65 20 63 6f 6d 70 6c 65 74 65 20 73 79 73 74 65 6d 20 77 69 6c 6c ┆, then the complete system will┆
0x2140…2160 20 65 6e 74 65 72 20 69 74 73 20 62 6f 6f 74 6c 6f 61 64 20 70 68 61 73 65 2e 0d 0a 0d 0a 8c 83 ┆ enter its bootload phase. ┆
0x2160…2180 e0 0a 49 74 20 69 73 20 70 6f 73 73 69 62 6c 65 20 62 79 20 6f 70 65 72 61 74 6f 72 20 69 6e 74 ┆ It is possible by operator int┆
0x2180…21a0 65 72 76 65 6e 74 69 6f 6e 20 74 6f 20 70 72 65 76 65 6e 74 20 74 68 65 20 73 79 73 74 65 6d 20 ┆ervention to prevent the system ┆
0x21a0…21c0 0a 66 72 6f 6d 20 65 6e 74 65 72 69 6e 67 20 74 68 65 20 62 6f 6f 74 6c 6f 61 64 20 70 68 61 73 ┆ from entering the bootload phas┆
0x21c0…21e0 65 2c 20 61 6e 64 20 69 6e 73 74 65 61 64 20 65 6e 74 65 72 20 61 6e 20 0a 69 6e 74 65 72 61 63 ┆e, and instead enter an interac┆
0x21e0…2200 74 69 76 65 20 74 65 73 74 20 6d 6f 64 65 2e 20 54 68 69 73 20 67 69 76 65 73 20 74 68 65 20 70 ┆tive test mode. This gives the p┆
0x2200…2220 (17,) 6f 73 73 69 62 69 6c 69 74 79 20 6f 66 20 6d 6f 6e 69 74 6f 72 69 6e 67 20 0a 74 65 73 74 73 20 ┆ossibility of monitoring tests ┆
0x2220…2240 65 78 65 63 75 74 65 64 20 63 75 6e 63 75 72 72 65 6e 74 6c 79 20 6f 6e 20 73 65 76 65 72 61 6c ┆executed cuncurrently on several┆
0x2240…2260 20 22 74 65 73 74 2d 73 6c 61 76 65 73 22 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 31 2e 33 20 53 65 6c 66 ┆ "test-slaves". 1.3 Self┆
0x2260…2280 74 65 73 74 20 45 71 75 69 70 6d 65 6e 74 2e 0d 0a 0d 0a 0d 0a 4f 6e 65 20 6f 66 20 74 68 65 20 ┆test Equipment. One of the ┆
0x2280…22a0 65 78 74 65 6e 64 65 64 20 74 65 73 74 73 2c 20 74 68 65 20 38 32 37 34 20 43 68 41 20 74 65 73 ┆extended tests, the 8274 ChA tes┆
0x22a0…22c0 74 20 28 6e 6f 74 20 72 75 6e 20 62 79 20 64 65 66 61 75 6c 74 29 20 0a 72 65 71 75 69 72 65 73 ┆t (not run by default) requires┆
0x22c0…22e0 20 61 20 6c 6f 6f 70 62 61 63 6b 20 63 61 62 6c 65 20 65 69 74 68 65 72 20 43 42 4c 20 37 38 38 ┆ a loopback cable either CBL 788┆
0x22e0…2300 20 28 72 65 61 72 20 63 61 62 69 6e 65 74 29 20 6f 72 20 43 42 4c 20 0a 37 38 39 20 28 63 61 72 ┆ (rear cabinet) or CBL 789 (car┆
0x2300…2320 64 20 65 64 67 65 29 20 74 6f 20 62 65 20 69 6e 73 74 61 6c 6c 65 64 2e 0d 0a 0d 0a 41 6e 6f 74 ┆d edge) to be installed. Anot┆
0x2320…2340 68 65 72 20 65 78 74 65 6e 64 65 64 20 74 65 73 74 20 74 68 65 20 66 6c 6f 70 70 79 20 74 65 73 ┆her extended test the floppy tes┆
0x2340…2360 74 20 72 65 71 75 69 72 65 73 20 61 6e 20 69 53 42 58 20 62 6f 61 72 64 20 0a 6e 61 6d 65 64 20 ┆t requires an iSBX board named ┆
0x2360…2380 46 44 43 36 30 31 20 74 6f 20 62 65 20 69 6e 73 74 61 6c 6c 65 64 20 61 6e 64 20 63 6f 6e 6e 65 ┆FDC601 to be installed and conne┆
0x2380…23a0 63 74 65 64 20 74 6f 20 61 20 35 20 31 2f 34 22 20 66 6c 6f 70 70 79 20 0a 64 69 73 6b 20 64 72 ┆cted to a 5 1/4" floppy disk dr┆
0x23a0…23c0 69 76 65 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 31 2e 34 20 4c 69 73 74 20 6f 66 20 49 6e 63 6c 75 64 65 ┆ive. 1.4 List of Include┆
0x23c0…23e0 64 20 54 65 73 74 73 2e 0d 0a 0d 0a 0d 0a 42 65 73 69 64 65 73 20 74 68 65 20 74 65 73 74 20 70 ┆d Tests. Besides the test p┆
0x23e0…2400 72 6f 67 72 61 6d 73 2c 20 74 68 65 20 52 43 33 39 30 30 2c 20 53 42 43 20 53 65 6c 66 74 65 73 ┆rograms, the RC3900, SBC Selftes┆
0x2400…2420 (18,) 74 73 20 69 6e 63 6c 75 64 65 73 20 61 20 0a 74 65 73 74 20 61 64 6d 69 6e 69 73 74 72 61 74 6f ┆ts includes a test administrato┆
0x2420…2440 72 20 61 6e 64 20 61 20 6c 69 62 72 61 72 79 20 6f 66 20 73 6f 6d 65 20 73 69 6d 70 6c 65 20 69 ┆r and a library of some simple i┆
0x2440…2460 6e 70 75 74 20 61 6e 64 20 6f 75 74 70 75 74 20 0a 72 6f 75 74 69 6e 65 73 2e 0d 0a 0d 0a 54 68 ┆nput and output routines. Th┆
0x2460…2480 65 20 73 69 6d 70 6c 65 20 74 65 73 74 20 61 64 6d 69 6e 69 73 74 72 61 74 6f 72 20 61 64 6d 69 ┆e simple test administrator admi┆
0x2480…24a0 6e 69 73 74 65 72 73 20 74 68 65 20 6d 6f 64 65 20 69 6e 20 77 68 69 63 68 20 61 20 0a 70 61 72 ┆nisters the mode in which a par┆
0x24a0…24c0 74 69 63 75 6c 61 72 20 74 65 73 74 20 69 73 20 72 75 6e 2e 20 44 69 66 66 65 72 65 6e 74 20 6d ┆ticular test is run. Different m┆
0x24c0…24e0 6f 64 65 73 20 69 73 20 64 65 74 65 72 6d 69 6e 65 64 20 62 79 20 0a 70 61 72 61 6d 65 74 65 72 ┆odes is determined by parameter┆
0x24e0…2500 20 73 65 74 74 69 6e 67 73 2e 20 53 65 65 20 63 68 61 70 74 65 72 20 32 2e 0d 0a 0d 0a 54 68 65 ┆ settings. See chapter 2. The┆
0x2500…2520 20 74 65 73 74 20 70 72 6f 67 72 61 6d 73 20 61 72 65 20 61 73 20 66 6f 6c 6c 6f 77 73 3a 0d 0a ┆ test programs are as follows: ┆
0x2520…2540 0d 0a 53 69 6d 70 6c 65 20 42 75 73 74 65 73 74 20 20 20 20 20 20 20 20 20 20 2d 20 84 61 20 70 ┆ Simple Bustest - a p┆
0x2540…2560 61 72 74 20 6f 66 20 74 68 65 20 69 6e 69 74 69 61 6c 69 7a 61 74 69 6f 6e 2e 20 54 68 69 73 20 ┆art of the initialization. This ┆
0x2560…2580 74 65 73 74 20 0a 19 9a 80 80 6d 61 79 20 62 65 20 73 65 6c 65 63 74 65 64 20 62 79 20 74 68 65 ┆test may be selected by the┆
0x2580…25a0 20 38 32 35 35 20 73 77 69 74 63 68 20 50 41 33 20 0a 19 9a 80 80 61 6e 64 20 69 73 20 69 6e 74 ┆ 8255 switch PA3 and is int┆
0x25a0…25c0 65 6e 64 65 64 20 74 6f 20 62 65 20 75 73 65 64 20 66 6f 72 20 63 6f 6d 70 6c 65 78 20 0a 19 9a ┆ended to be used for complex ┆
0x25c0…25e0 80 80 66 61 75 6c 74 20 66 69 6e 64 69 6e 67 20 6f 66 20 62 75 73 20 65 72 72 6f 72 73 2e 0d 0a ┆ fault finding of bus errors. ┆
0x25e0…2600 0d 0a 50 52 4f 4d 20 63 68 65 63 6b 73 75 6d 20 74 65 73 74 20 20 20 20 20 20 2d 20 84 61 20 73 ┆ PROM checksum test - a s┆
0x2600…2620 (19,) 69 6d 70 6c 65 20 50 52 4f 4d 20 63 68 65 63 6b 73 65 75 6d 20 69 73 20 63 61 6c 63 75 6c 61 74 ┆imple PROM checkseum is calculat┆
0x2620…2640 65 64 2e 20 0a 19 9a 80 80 49 74 20 69 73 20 6f 6e 6c 79 20 65 78 65 63 75 74 65 64 20 6f 6e 63 ┆ed. It is only executed onc┆
0x2640…2660 65 20 61 66 74 65 72 20 65 61 63 68 20 0a 19 9a 80 80 70 6f 77 65 72 20 75 70 20 75 6e 69 74 69 ┆e after each power up uniti┆
0x2660…2680 61 6c 69 7a 61 74 69 6f 6e 2e 0d 0a 0d 0a 8c 83 e0 0a 52 41 4d 20 6d 65 6d 6f 72 79 20 74 65 73 ┆alization. RAM memory tes┆
0x2680…26a0 74 20 20 20 20 20 20 20 20 20 2d 20 84 61 20 6d 6f 64 75 6c 75 73 20 33 20 70 61 74 74 65 72 6e ┆t - a modulus 3 pattern┆
0x26a0…26c0 20 74 65 73 74 20 6f 66 20 74 68 65 20 62 6f 61 72 64 20 0a 19 9a 80 80 72 65 73 69 64 65 6e 74 ┆ test of the board resident┆
0x26c0…26e0 20 52 41 4d 20 6d 65 6d 6f 72 79 2e 0d 0a 0d 0a 52 41 4d 20 72 65 66 72 65 73 68 20 74 65 73 74 ┆ RAM memory. RAM refresh test┆
0x26e0…2700 20 20 20 20 20 20 20 20 2d 20 84 61 20 74 65 73 74 20 6f 66 20 74 68 65 20 61 75 74 6f 6d 61 74 ┆ - a test of the automat┆
0x2700…2720 69 63 20 72 65 66 72 65 73 68 69 6e 67 20 6f 66 20 0a 19 9a 80 80 74 68 65 20 52 41 4d 2d 6d 65 ┆ic refreshing of the RAM-me┆
0x2720…2740 6d 6f 72 79 2e 0d 0a 0d 0a 69 41 50 58 31 38 36 20 44 4d 41 20 74 65 73 74 20 20 20 20 20 20 20 ┆mory. iAPX186 DMA test ┆
0x2740…2760 20 2d 20 84 61 20 74 65 73 74 20 6f 66 20 74 68 65 20 69 41 50 58 31 38 36 20 6f 6e 2d 63 68 69 ┆ - a test of the iAPX186 on-chi┆
0x2760…2780 70 20 44 4d 41 20 0a 19 9a 80 80 63 6f 6e 74 72 6f 6c 6c 65 72 2e 0d 0a 0d 0a 69 41 50 58 31 38 ┆p DMA controller. iAPX18┆
0x2780…27a0 36 20 69 6e 74 65 72 72 75 70 74 20 74 65 73 74 20 20 2d 20 84 61 20 74 65 73 74 20 6f 66 20 74 ┆6 interrupt test - a test of t┆
0x27a0…27c0 68 65 20 6f 6e 2d 63 68 69 70 20 69 6e 74 65 72 72 75 70 74 20 0a 19 9a 80 80 63 6f 6e 74 72 6f ┆he on-chip interrupt contro┆
0x27c0…27e0 6c 6c 65 72 20 61 6e 64 20 69 74 73 20 61 62 69 6c 69 74 79 20 74 6f 20 72 65 63 65 69 76 65 20 ┆ller and its ability to receive ┆
0x27e0…2800 0a 19 9a 80 80 69 6e 74 65 72 72 75 70 74 73 20 66 72 6f 6d 20 74 68 65 20 6f 6e 2d 63 68 69 70 ┆ interrupts from the on-chip┆
0x2800…2820 (20,) 20 74 69 6d 65 72 2e 0d 0a 0d 0a 38 32 35 39 20 69 6e 74 65 72 72 75 70 74 20 74 65 73 74 20 20 ┆ timer. 8259 interrupt test ┆
0x2820…2840 20 20 20 2d 20 84 61 20 74 65 73 74 20 6f 66 20 74 68 65 20 38 32 35 39 20 69 6e 74 65 72 72 75 ┆ - a test of the 8259 interru┆
0x2840…2860 70 74 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 0a 19 9a 80 80 61 6e 64 20 69 74 73 20 61 62 69 6c 69 ┆pt controller and its abili┆
0x2860…2880 74 79 20 74 6f 20 72 65 63 65 69 76 65 20 61 20 66 6c 61 67 62 79 74 65 20 0a 19 9a 80 80 69 6e ┆ty to receive a flagbyte in┆
0x2880…28a0 74 65 72 72 75 70 74 2e 0d 0a 0d 0a 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 09 2d 20 84 61 ┆terrupt. Ethernet test 2 - a┆
0x28a0…28c0 20 74 65 73 74 20 74 68 61 74 20 6d 61 6b 65 73 20 61 6e 20 65 78 74 65 72 6e 61 6c 20 6c 6f 6f ┆ test that makes an external loo┆
0x28c0…28e0 70 20 62 61 63 6b 20 0a 19 9a 80 80 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 77 69 74 68 20 ┆p back data transport with ┆
0x28e0…2900 74 68 65 20 45 74 68 65 72 6e 65 74 20 0a 19 9a 80 80 43 6f 6e 74 72 6f 6c 6c 65 72 2e 0d 0a 0d ┆the Ethernet Controller. ┆
0x2900…2920 0a 38 32 37 34 20 43 48 41 20 74 65 73 74 09 09 2d 20 84 61 20 74 65 73 74 20 74 68 61 74 20 6d ┆ 8274 CHA test - a test that m┆
0x2920…2940 61 6b 65 73 20 61 6e 20 65 78 74 65 72 6e 61 6c 20 6c 6f 6f 70 20 62 61 63 6b 20 0a 19 9a 80 80 ┆akes an external loop back ┆
0x2940…2960 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 6f 6e 20 74 68 65 20 38 32 37 34 20 4d 50 53 43 20 ┆data transport on the 8274 MPSC ┆
0x2960…2980 0a 19 9a 80 80 63 6f 6e 74 72 6f 6c 6c 65 72 20 63 68 61 6e 6e 65 6c 20 41 2e 0d 0a 0d 0a 46 6c ┆ controller channel A. Fl┆
0x2980…29a0 6f 70 70 79 20 74 65 73 74 09 09 2d 20 84 61 20 74 65 73 74 20 74 68 61 74 20 76 65 72 69 66 69 ┆oppy test - a test that verifi┆
0x29a0…29c0 65 73 20 74 68 65 20 69 53 42 58 20 69 6e 74 65 72 66 61 63 65 20 0a 19 9a 80 80 77 68 65 72 65 ┆es the iSBX interface where┆
0x29c0…29e0 20 61 20 46 44 43 36 30 31 20 46 6c 6f 70 70 79 20 44 69 73 63 20 43 6f 6e 74 72 6f 6c 6c 65 72 ┆ a FDC601 Floppy Disc Controller┆
0x29e0…2a00 20 0a 19 9a 80 80 73 68 6f 75 6c 64 20 62 65 20 61 74 74 61 63 68 65 64 2e 0d 0a 0d 0a 4d 75 6c ┆ should be attached. Mul┆
0x2a00…2a20 (21,) 74 69 62 75 73 20 54 65 73 74 20 4d 6f 6e 69 74 6f 72 20 20 20 2d 20 84 61 20 4d 6f 6e 69 74 6f ┆tibus Test Monitor - a Monito┆
0x2a20…2a40 72 20 74 68 61 74 20 73 75 70 70 6c 69 65 73 20 74 68 65 20 6f 70 65 72 61 74 6f 72 20 0a 19 9a ┆r that supplies the operator ┆
0x2a40…2a60 80 80 77 69 74 68 20 72 65 6d 6f 74 65 20 63 6f 6e 74 72 6f 6c 20 74 68 65 20 65 78 65 63 75 74 ┆ with remote control the execut┆
0x2a60…2a80 69 6f 6e 20 6f 66 20 0a 19 9a 80 80 6f 74 68 65 72 20 53 42 43 20 73 65 6c 66 74 65 73 74 73 2e ┆ion of other SBC selftests.┆
0x2a80…2aa0 0d 0a 0d 0a 4d 65 73 73 61 67 65 73 20 66 72 6f 6d 20 74 68 65 20 74 65 73 74 20 70 72 6f 67 72 ┆ Messages from the test progr┆
0x2aa0…2ac0 61 6d 73 20 61 72 65 20 65 78 70 6c 61 69 6e 65 64 20 61 6c 6f 6e 67 20 77 69 74 68 20 74 68 65 ┆ams are explained along with the┆
0x2ac0…2ae0 20 0a 64 65 73 63 72 69 70 74 69 6f 6e 20 6f 66 20 74 68 65 20 69 6e 64 69 76 69 64 75 61 6c 20 ┆ description of the individual ┆
0x2ae0…2b00 74 65 73 74 20 6c 6f 6f 70 73 2e 20 54 68 65 20 6d 65 73 73 61 67 65 20 22 4f 4b 22 20 69 73 20 ┆test loops. The message "OK" is ┆
0x2b00…2b20 0a 75 73 65 64 20 62 79 20 61 6c 6c 20 74 65 73 74 20 70 72 6f 67 72 61 6d 73 2c 20 61 6e 64 20 ┆ used by all test programs, and ┆
0x2b20…2b40 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 6e 6f 20 65 72 72 6f 72 20 68 61 73 20 62 65 65 6e ┆indicates that no error has been┆
0x2b40…2b4d 20 0a 64 65 74 65 63 74 65 64 2e 0d 0a ┆ detected. ┆
0x2b4d…2b50 FormFeed {
0x2b4d…2b50 0c 83 bc ┆ ┆
0x2b4d…2b50 }
0x2b50…2b60 0a b0 a1 32 2e 20 54 65 73 74 61 64 6d 69 6e 69 ┆ 2. Testadmini┆
0x2b60…2b80 73 74 72 61 74 6f 72 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c ┆strator. The ETC601 SBC Sel┆
0x2b80…2ba0 66 74 65 73 74 20 69 73 20 65 71 75 69 70 70 65 64 20 77 69 74 68 20 61 20 73 69 6d 70 6c 65 20 ┆ftest is equipped with a simple ┆
0x2ba0…2bc0 74 65 73 74 20 0a 61 64 6d 69 6e 69 73 74 72 61 74 6f 72 2c 20 74 68 61 74 20 61 64 6d 69 6e 69 ┆test administrator, that admini┆
0x2bc0…2be0 73 74 65 72 73 20 74 68 65 20 6d 6f 64 65 20 69 6e 20 77 68 69 63 68 20 61 20 70 61 72 74 69 63 ┆sters the mode in which a partic┆
0x2be0…2c00 75 6c 61 72 20 0a 74 65 73 74 20 69 73 20 65 78 65 63 75 74 65 64 2e 0d 0a 0d 0a 54 68 65 20 73 ┆ular test is executed. The s┆
0x2c00…2c20 (22,) 65 6c 66 74 65 73 74 20 63 6f 6e 73 69 73 74 73 20 6f 66 20 61 20 73 65 74 20 6f 66 20 74 65 73 ┆elftest consists of a set of tes┆
0x2c20…2c40 74 20 70 72 6f 67 72 61 6d 73 20 61 6e 64 20 61 20 4d 75 6c 74 69 62 75 73 20 0a 63 6f 6e 66 69 ┆t programs and a Multibus confi┆
0x2c40…2c60 67 75 72 61 74 69 6f 6e 20 6d 6f 64 75 6c 65 2e 20 42 79 20 64 65 66 61 75 6c 74 20 61 6c 6c 20 ┆guration module. By default all ┆
0x2c60…2c80 74 68 65 20 74 65 73 74 73 20 61 72 65 20 72 75 6e 20 73 65 71 75 65 6e 74 69 61 6c 20 0a 61 6e ┆the tests are run sequential an┆
0x2c80…2ca0 64 20 74 65 72 6d 69 6e 61 74 65 64 20 62 79 20 65 6e 74 65 72 69 6e 67 20 74 68 65 20 62 6f 6f ┆d terminated by entering the boo┆
0x2ca0…2cc0 74 6c 6f 61 64 65 72 2e 20 54 68 65 20 6d 61 69 6e 20 70 75 72 70 6f 73 65 20 6f 66 20 0a 74 68 ┆tloader. The main purpose of th┆
0x2cc0…2ce0 65 20 74 65 73 74 61 64 6d 69 6e 69 73 74 72 61 74 6f 72 20 69 73 20 74 6f 20 63 6f 6d 70 75 74 ┆e testadministrator is to comput┆
0x2ce0…2d00 65 20 74 68 65 20 61 64 64 72 65 73 73 20 6f 66 20 74 68 65 20 6e 65 78 74 20 74 65 73 74 20 0a ┆e the address of the next test ┆
0x2d00…2d20 69 6e 20 73 65 71 75 65 6e 63 65 20 61 6e 64 20 74 6f 20 67 65 6e 65 72 61 74 65 20 65 72 72 6f ┆in sequence and to generate erro┆
0x2d20…2d40 72 20 6d 65 73 73 61 67 65 73 20 74 6f 20 74 68 65 20 63 6f 6e 73 6f 6c 65 2e 0d 0a 0d 0a 54 68 ┆r messages to the console. Th┆
0x2d40…2d60 65 20 6d 6f 64 65 20 61 6e 64 20 73 65 71 75 65 6e 63 65 20 69 6e 20 77 68 69 63 68 20 74 68 65 ┆e mode and sequence in which the┆
0x2d60…2d80 20 74 65 73 74 73 20 61 72 65 20 65 78 65 63 75 74 65 64 20 6d 61 79 20 62 65 20 0a 63 6f 6e 74 ┆ tests are executed may be cont┆
0x2d80…2da0 72 6f 6c 6c 65 64 20 66 72 6f 6d 20 61 20 63 6f 6e 6e 65 63 74 65 64 20 63 6f 6e 73 6f 6c 65 2e ┆rolled from a connected console.┆
0x2da0…2dc0 0d 0a 0d 0a 4e 6f 74 65 20 74 68 61 74 20 74 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c ┆ Note that the ETC601 SBC Sel┆
0x2dc0…2de0 66 74 65 73 74 20 69 73 20 65 71 75 69 70 70 65 64 20 77 69 74 68 20 74 77 6f 20 76 65 72 73 69 ┆ftest is equipped with two versi┆
0x2de0…2e00 6f 6e 73 20 0a 6f 66 20 74 68 65 20 74 65 73 74 61 64 6d 69 6e 69 73 74 72 61 74 6f 72 2c 20 6f ┆ons of the testadministrator, o┆
0x2e00…2e20 (23,) 6e 65 20 77 68 65 6e 20 63 6f 6e 66 69 67 75 72 61 74 65 64 20 61 73 20 61 20 22 74 65 73 74 2d ┆ne when configurated as a "test-┆
0x2e20…2e40 0a 6d 61 73 74 65 72 22 20 61 6e 64 20 61 6e 6f 74 68 65 72 20 77 68 65 6e 20 63 6f 6e 66 69 67 ┆ master" and another when config┆
0x2e40…2e60 75 72 61 74 65 64 20 61 73 20 61 20 22 74 65 73 74 2d 73 6c 61 76 65 22 2e 20 57 68 69 63 68 20 ┆urated as a "test-slave". Which ┆
0x2e60…2e80 6f 66 20 0a 74 68 65 20 74 77 6f 20 74 68 61 74 20 69 73 20 61 63 74 69 76 65 20 69 73 20 64 65 ┆of the two that is active is de┆
0x2e80…2ea0 74 65 72 6d 69 6e 65 64 20 62 79 20 74 68 65 20 38 32 35 35 2c 20 50 41 32 20 73 74 72 61 70 20 ┆termined by the 8255, PA2 strap ┆
0x2ea0…2ec0 0a 28 53 32 33 29 2c 20 73 65 65 20 63 68 61 70 74 65 72 20 34 2e 0d 0a 0d 0a 54 68 65 20 64 65 ┆ (S23), see chapter 4. The de┆
0x2ec0…2ee0 73 63 72 69 70 74 69 6f 6e 20 6f 66 20 74 68 65 20 64 69 66 66 65 72 65 6e 63 65 73 20 69 6e 20 ┆scription of the differences in ┆
0x2ee0…2f00 74 68 65 20 74 65 73 74 61 64 6d 69 6e 69 73 74 72 61 74 6f 72 2c 20 77 68 65 6e 20 0a 69 6e 20 ┆the testadministrator, when in ┆
0x2f00…2f20 22 74 65 73 74 2d 73 6c 61 76 65 22 20 6d 6f 64 65 20 69 73 20 69 6e 20 63 68 61 70 74 65 72 20 ┆"test-slave" mode is in chapter ┆
0x2f20…2f40 31 37 2e 0d 0a 0d 0a 46 69 67 2e 20 31 20 67 69 76 65 73 20 61 20 73 69 6d 70 6c 65 20 6f 76 65 ┆17. Fig. 1 gives a simple ove┆
0x2f40…2f60 72 76 69 65 77 20 6f 66 20 74 68 65 20 53 65 6c 66 74 65 73 74 20 70 72 6f 67 72 61 6d 20 66 6c ┆rview of the Selftest program fl┆
0x2f60…2f80 6f 77 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 32 2e 31 20 4f 70 65 72 61 74 6f 72 20 53 74 69 6d 75 6c 69 ┆ow. 2.1 Operator Stimuli┆
0x2f80…2fa0 20 6f 66 20 74 68 65 20 53 65 6c 66 74 65 73 74 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 45 54 43 36 30 ┆ of the Selftest. The ETC60┆
0x2fa0…2fc0 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 72 65 63 6f 67 6e 69 7a 65 73 20 72 65 63 65 69 76 ┆1 SBC Selftest recognizes receiv┆
0x2fc0…2fe0 65 20 69 6e 74 65 72 72 75 70 74 73 20 66 72 6f 6d 20 74 68 65 20 0a 38 32 37 34 20 55 53 41 52 ┆e interrupts from the 8274 USAR┆
0x2fe0…3000 54 20 61 6e 64 20 72 65 61 64 73 20 74 68 65 20 63 6f 72 72 6f 73 70 6f 6e 64 69 6e 67 20 63 68 ┆T and reads the corrosponding ch┆
0x3000…3020 (24,) 61 72 61 63 74 65 72 2c 20 77 68 69 63 68 20 65 6e 61 62 6c 65 73 20 0a 6f 70 65 72 61 74 6f 72 ┆aracter, which enables operator┆
0x3020…3040 20 6d 61 6e 69 70 75 6c 61 74 69 6f 6e 20 6f 66 20 74 68 65 20 53 65 6c 66 74 65 73 74 20 66 6c ┆ manipulation of the Selftest fl┆
0x3040…3060 6f 77 2e 20 49 74 20 69 73 20 61 20 66 61 63 74 2c 20 74 68 61 74 20 0a 74 68 65 20 45 54 43 36 ┆ow. It is a fact, that the ETC6┆
0x3060…3080 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 69 73 20 64 65 73 69 67 6e 65 64 20 74 6f 20 65 ┆01 SBC Selftest is designed to e┆
0x3080…30a0 6e 73 75 72 65 20 22 6e 6f 20 73 74 6f 70 22 20 69 6e 20 74 68 65 20 0a 64 65 66 61 75 6c 74 20 ┆nsure "no stop" in the default ┆
0x30a0…30c0 70 6f 77 65 72 20 75 70 20 62 6f 6f 74 6c 6f 61 64 2e 20 54 68 65 72 65 66 6f 72 65 20 62 65 20 ┆power up bootload. Therefore be ┆
0x30c0…30e0 61 77 61 72 65 2c 20 74 68 61 74 20 69 66 20 61 6e 79 20 0a 6d 61 6e 69 70 75 6c 61 74 69 6f 6e ┆aware, that if any manipulation┆
0x30e0…3100 20 6f 66 20 74 68 65 20 74 65 73 74 20 66 6c 6f 77 20 69 73 20 77 61 6e 74 65 64 2c 20 74 68 61 ┆ of the test flow is wanted, tha┆
0x3100…3120 74 20 62 65 20 6c 6f 6f 70 69 6e 67 20 69 6e 20 74 68 65 20 0a 45 54 43 36 30 31 20 53 65 6c 66 ┆t be looping in the ETC601 Self┆
0x3120…3140 74 65 73 74 20 6f 72 20 6d 6f 6e 69 74 6f 72 69 6e 67 20 6f 66 20 22 74 65 73 74 2d 73 6c 61 76 ┆test or monitoring of "test-slav┆
0x3140…3160 65 73 22 2c 20 74 68 65 20 64 65 63 69 73 69 6f 6e 20 6d 75 73 74 20 0a 8c 83 c8 0a 62 65 20 74 ┆es", the decision must be t┆
0x3160…3180 61 6b 65 6e 20 62 65 66 6f 72 65 20 74 68 65 20 62 6f 6f 74 6c 6f 61 64 69 6e 67 20 69 73 20 73 ┆aken before the bootloading is s┆
0x3180…31a0 74 61 72 74 65 64 2c 20 65 6c 73 65 20 74 68 65 20 63 6f 6e 74 72 6f 6c 20 69 73 20 0a 6c 6f 73 ┆tarted, else the control is los┆
0x31a0…31a4 74 2e 0d 0a ┆t. ┆
0x31a4…31a7 FormFeed {
0x31a4…31a7 0c 80 98 ┆ ┆
0x31a4…31a7 }
0x31a7…31aa 0a 0d 0a ┆ ┆
0x31aa…31ad FormFeed {
0x31aa…31ad 0c 80 8c ┆ ┆
0x31aa…31ad }
0x31ad…31c0 0a 54 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c ┆ The ETC601 SBC Sel┆
0x31c0…31e0 66 74 65 73 74 20 69 73 20 73 65 6e 73 69 74 69 76 65 20 74 6f 20 73 65 76 65 72 61 6c 20 6b 69 ┆ftest is sensitive to several ki┆
0x31e0…3200 6e 64 73 20 6f 66 20 69 6e 70 75 74 73 2c 20 0a 77 68 69 63 68 20 68 61 73 20 64 69 66 66 65 72 ┆nds of inputs, which has differ┆
0x3200…3220 (25,) 65 6e 74 20 6d 65 61 6e 69 6e 67 73 3a 0d 0a 0d 0a 50 72 65 73 73 20 3c 65 73 63 3e 20 20 20 20 ┆ent meanings: Press <esc> ┆
0x3220…3240 20 20 3a 20 84 65 6e 61 62 6c 65 73 20 69 6e 74 65 72 61 63 74 69 76 65 20 63 68 61 6e 67 65 20 ┆ : enables interactive change ┆
0x3240…3260 6f 66 20 70 72 6f 67 72 61 6d 20 66 6c 6f 77 20 0a 19 93 80 80 70 61 72 61 6d 65 74 65 72 73 2e ┆of program flow parameters.┆
0x3260…3280 20 53 65 65 20 73 65 63 74 69 6f 6e 20 32 2e 32 2e 0d 0a 0d 0a 50 72 65 73 73 20 3c 63 6e 74 72 ┆ See section 2.2. Press <cntr┆
0x3280…32a0 6c 3e 3c 40 3e 20 3a 20 84 73 74 61 72 74 73 20 74 68 65 20 74 65 73 74 20 73 6e 6f 6f 70 65 72 ┆l><@> : starts the test snooper┆
0x32a0…32c0 20 66 61 63 69 6c 69 74 79 2e 20 53 65 65 20 63 68 61 70 74 65 72 20 0a 19 93 80 80 37 2e 0d 0a ┆ facility. See chapter 7. ┆
0x32c0…32e0 0d 0a 50 72 65 73 73 20 3c 63 6e 74 72 6c 3e 3c 51 3e 20 3a 20 84 71 75 69 74 20 70 72 65 73 65 ┆ Press <cntrl><Q> : quit prese┆
0x32e0…3300 6e 74 20 73 74 61 74 65 2e 20 54 68 69 73 20 63 6f 75 6c 64 20 62 65 20 61 6e 20 65 72 72 6f 72 ┆nt state. This could be an error┆
0x3300…3320 2d 0a 19 93 80 80 68 61 6c 74 20 63 6f 6e 64 69 74 69 6f 6e 20 6f 72 20 74 68 65 20 4d 75 6c 74 ┆- halt condition or the Mult┆
0x3320…3340 69 62 75 73 20 74 65 73 74 20 6d 6f 6e 69 74 6f 72 69 6e 67 20 0a 19 93 80 80 6f 66 20 22 74 65 ┆ibus test monitoring of "te┆
0x3340…3360 73 74 2d 73 6c 61 76 65 73 22 2e 0d 0a 0d 0a 50 72 65 73 73 20 3c 63 6e 74 72 6c 3e 3c 53 3e 20 ┆st-slaves". Press <cntrl><S> ┆
0x3360…3380 3a 20 84 72 65 71 75 65 73 74 20 4d 75 6c 74 69 62 75 73 20 74 65 73 74 20 6d 6f 6e 69 74 6f 72 ┆: request Multibus test monitor┆
0x3380…33a0 69 6e 67 20 6f 66 20 22 74 65 73 74 2d 0a 19 93 80 80 73 6c 61 76 65 73 22 20 61 74 20 74 68 65 ┆ing of "test- slaves" at the┆
0x33a0…33c0 20 65 6e 64 20 6f 66 20 74 68 65 20 45 54 43 36 30 31 20 73 65 6c 66 74 65 73 74 2e 0d 0a 0d 0a ┆ end of the ETC601 selftest. ┆
0x33c0…33e0 49 66 20 61 6e 79 20 6f 74 68 65 72 20 63 68 61 72 61 63 74 65 72 20 69 73 20 74 79 70 65 64 20 ┆If any other character is typed ┆
0x33e0…3400 74 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 77 69 6c 6c 20 0a 72 65 ┆the ETC601 SBC Selftest will re┆
0x3400…3420 (26,) 73 70 6f 6e 64 20 77 69 74 68 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 6d 65 6e 75 20 61 6e ┆spond with the following menu an┆
0x3420…3440 64 20 77 61 69 74 20 66 6f 72 20 79 65 74 20 61 6e 6f 74 68 65 72 20 0a 63 68 61 72 61 63 74 65 ┆d wait for yet another characte┆
0x3440…3460 72 20 74 6f 20 63 6f 6e 74 69 6e 75 65 2e 0d 0a 0d 0a f0 2d 2d 2d 2d 4d 45 4e 55 2d 2d 2d 2d 0d ┆r to continue. ----MENU---- ┆
0x3460…3480 0a 3c 65 73 63 3e 20 20 20 20 20 20 3a 20 63 68 61 6e 67 65 20 70 61 72 61 6d 65 74 65 72 73 0d ┆ <esc> : change parameters ┆
0x3480…34a0 0a 3c 63 6e 74 72 6c 3e 3c 40 3e 20 3a 20 65 6e 74 65 72 20 73 6e 6f 6f 70 65 72 0d 0a 3c 63 6e ┆ <cntrl><@> : enter snooper <cn┆
0x34a0…34c0 74 72 6c 3e 3c 51 3e 20 3a 20 71 75 69 74 20 70 72 65 73 65 6e 74 20 73 74 61 74 65 0d 0a 3c 63 ┆trl><Q> : quit present state <c┆
0x34c0…34e0 6e 74 72 6c 3e 3c 53 3e 20 3a 20 72 65 71 75 65 73 74 20 64 65 62 75 67 20 6f 66 20 74 65 73 74 ┆ntrl><S> : request debug of test┆
0x34e0…3500 20 73 6c 61 76 65 73 0d 0a 74 65 73 74 20 6e 6f 2e 3a 0d 0a 30 30 30 30 37 3a 20 46 6c 6f 70 70 ┆ slaves test no.: 00007: Flopp┆
0x3500…3520 79 20 74 65 73 74 0d 0a 30 30 30 30 36 3a 20 38 32 37 34 20 43 48 41 20 74 65 73 74 0d 0a 30 30 ┆y test 00006: 8274 CHA test 00┆
0x3520…3540 30 30 35 3a 20 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 0d 0a 30 30 30 30 34 3a 20 69 41 50 ┆005: Ethernet test 2 00004: iAP┆
0x3540…3560 58 31 38 36 20 73 6c 61 76 65 20 69 6e 74 65 72 72 75 70 74 20 74 65 73 74 0d 0a 30 30 30 30 33 ┆X186 slave interrupt test 00003┆
0x3560…3580 3a 20 50 49 43 20 74 65 73 74 0d 0a 30 30 30 30 32 3a 20 69 41 50 58 31 38 36 20 44 4d 41 20 74 ┆: PIC test 00002: iAPX186 DMA t┆
0x3580…35a0 65 73 74 0d 0a 30 30 30 30 31 3a 20 52 41 4d 20 72 65 66 72 65 73 68 20 74 65 73 74 0d 0a 30 30 ┆est 00001: RAM refresh test 00┆
0x35a0…35c0 30 30 30 3a 20 6d 65 6d 6f 72 79 20 74 65 73 74 0d 0a 2d 2d 2d 2d 4d 45 4e 55 2d 2d 2d 2d 0d 0a ┆000: memory test ----MENU---- ┆
0x35c0…35e0 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 46 69 67 75 72 65 20 ┆ Figure ┆
0x35e0…3600 32 3a 20 53 65 6c 66 74 65 73 74 20 6d 65 6e 75 2e 0d 0a 0d 0a 8c 83 c8 0a a1 32 2e 32 20 50 61 ┆2: Selftest menu. 2.2 Pa┆
0x3600…3620 (27,) 72 61 6d 65 74 65 72 73 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 66 6c 6f 77 20 6f 66 20 74 68 65 20 45 ┆rameters. The flow of the E┆
0x3620…3640 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 69 73 20 62 61 73 65 64 20 75 70 6f 6e ┆TC601 SBC Selftest is based upon┆
0x3640…3660 20 74 68 65 20 66 61 63 74 20 74 68 61 74 20 0a 65 61 63 68 20 74 65 73 74 20 70 72 6f 67 72 61 ┆ the fact that each test progra┆
0x3660…3680 6d 20 72 65 63 65 69 76 65 73 20 61 20 73 65 74 20 6f 66 20 70 61 72 61 6d 65 74 65 72 73 20 61 ┆m receives a set of parameters a┆
0x3680…36a0 73 20 69 6e 70 75 74 20 61 6e 64 20 0a 64 65 6c 69 76 65 72 65 73 20 61 20 62 75 66 66 65 72 20 ┆s input and deliveres a buffer ┆
0x36a0…36c0 6f 66 20 65 72 72 6f 72 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 73 20 61 73 20 6f 75 74 70 75 74 2e ┆of error informations as output.┆
0x36c0…36e0 0d 0a 0d 0a 54 68 65 20 70 61 72 61 6d 65 74 65 72 73 20 61 72 65 20 63 6f 6e 74 61 69 6e 65 64 ┆ The parameters are contained┆
0x36e0…3700 20 69 6e 20 61 20 31 36 20 62 69 74 20 77 6f 72 64 20 76 61 72 69 61 62 6c 65 2c 20 61 20 0a 73 ┆ in a 16 bit word variable, a s┆
0x3700…3720 6f 63 61 6c 6c 65 64 20 73 77 69 74 63 68 20 76 61 72 69 61 62 6c 65 2c 20 77 68 69 63 68 20 73 ┆ocalled switch variable, which s┆
0x3720…3740 75 72 76 69 76 65 73 20 74 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 69 6e 20 61 6e 20 0a 69 ┆urvives the memory test in an i┆
0x3740…3760 6e 74 65 72 6e 61 6c 20 69 41 50 58 31 38 36 20 43 50 55 20 72 65 67 69 73 74 65 72 2e 20 54 68 ┆nternal iAPX186 CPU register. Th┆
0x3760…3780 69 73 20 76 61 72 69 61 62 6c 65 20 63 6f 6e 74 61 69 6e 73 20 74 68 65 20 0a 69 6e 66 6f 72 6d ┆is variable contains the inform┆
0x3780…37a0 61 74 69 6f 6e 20 6e 65 63 65 73 73 61 72 79 20 66 6f 72 20 74 68 65 20 74 65 73 74 20 61 64 6d ┆ation necessary for the test adm┆
0x37a0…37c0 69 6e 69 73 74 72 61 74 6f 72 20 74 6f 20 6d 61 6e 61 67 65 20 74 68 65 20 0a 66 6c 6f 77 20 6f ┆inistrator to manage the flow o┆
0x37c0…37e0 66 20 74 68 65 20 74 65 73 74 20 70 72 6f 67 72 61 6d 2e 0d 0a 8c 81 90 0a 0e 0a 0d 0a a1 6e 61 ┆f the test program. na┆
0x37e0…3800 6d 65 20 20 20 20 20 20 20 69 6e 69 74 69 61 6c 20 76 61 6c 75 65 20 20 20 06 63 6f 6d 6d 65 6e ┆me initial value commen┆
0x3800…3820 (28,) 74 05 0d 0a 68 61 6c 74 20 62 69 74 20 20 20 20 20 20 20 20 31 20 20 20 20 20 20 20 20 20 20 20 ┆t halt bit 1 ┆
0x3820…3840 20 31 3a 20 84 68 61 6c 74 73 20 65 78 65 63 75 74 69 6f 6e 20 77 68 65 6e 20 61 6e 20 65 72 72 ┆ 1: halts execution when an err┆
0x3840…3860 6f 72 20 69 73 20 0a 19 a0 80 80 64 69 73 63 6f 76 65 72 65 64 2e 0d 0a 20 20 20 20 20 20 20 20 ┆or is discovered. ┆
0x3860…3880 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 30 3a 20 62 79 70 61 73 73 65 73 ┆ 0: bypasses┆
0x3880…38a0 20 65 72 72 6f 72 73 2e 0d 0a 0d 0a 6c 6f 6f 70 20 62 69 74 20 20 20 20 20 20 20 20 30 20 20 20 ┆ errors. loop bit 0 ┆
0x38a0…38c0 20 20 20 20 20 20 20 20 20 31 3a 20 84 72 65 70 65 61 74 73 20 74 68 65 20 73 65 6c 65 63 74 69 ┆ 1: repeats the selecti┆
0x38c0…38e0 6f 6e 20 6f 66 20 74 68 65 20 74 65 73 74 20 0a 19 a0 80 80 73 70 65 63 69 66 69 65 64 2e 0d 0a ┆on of the test specified. ┆
0x38e0…3900 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 30 3a 20 ┆ 0: ┆
0x3900…3920 73 65 71 75 65 6e 74 69 61 6c 20 66 6c 6f 77 2e 0d 0a 0d 0a 77 61 69 74 20 62 69 74 20 20 20 20 ┆sequential flow. wait bit ┆
0x3920…3940 20 20 20 20 30 20 20 20 20 20 20 20 20 20 20 20 20 31 3a 20 84 75 73 65 64 20 69 6e 20 74 68 65 ┆ 0 1: used in the┆
0x3940…3960 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 70 68 61 73 65 20 0a 19 a0 80 80 62 79 20 74 68 65 ┆ configuration phase by the┆
0x3960…3980 20 22 74 65 73 74 20 73 6c 61 76 65 73 22 2e 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ "test slaves". ┆
0x3980…39a0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 30 3a 20 84 72 65 6c 65 61 73 65 20 22 74 65 73 74 2d ┆ 0: release "test-┆
0x39a0…39c0 73 6c 61 76 65 73 22 20 28 6f 6e 6c 79 20 0a 19 a0 80 80 69 6e 74 65 72 6e 61 6c 29 2e 0d 0a 0d ┆slaves" (only internal). ┆
0x39c0…39e0 0a 62 6f 6f 74 20 62 69 74 20 20 20 20 20 20 20 20 31 20 20 20 20 20 20 20 20 20 20 20 20 31 3a ┆ boot bit 1 1:┆
0x39e0…3a00 20 84 63 6f 6e 66 69 67 75 72 61 74 65 20 61 6e 64 20 62 6f 6f 74 6c 6f 61 64 20 61 66 74 65 72 ┆ configurate and bootload after┆
0x3a00…3a20 (29,) 20 0a 19 a0 80 80 65 6e 64 20 6f 66 20 73 65 6c 66 74 65 73 74 2e 0d 0a 20 20 20 20 20 20 20 20 ┆ end of selftest. ┆
0x3a20…3a40 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 30 3a 20 72 65 70 65 61 74 20 6f ┆ 0: repeat o┆
0x3a40…3a60 77 6e 20 73 65 6c 66 74 65 73 74 2e 0d 0a 0d 0a 73 74 61 74 75 73 20 62 69 74 20 20 20 20 20 20 ┆wn selftest. status bit ┆
0x3a60…3a80 30 20 20 20 20 20 20 20 20 20 20 20 20 31 3a 20 84 73 75 70 70 72 65 73 73 20 73 74 61 74 75 73 ┆0 1: suppress status┆
0x3a80…3aa0 20 63 68 65 63 6b 2e 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ check. ┆
0x3aa0…3ac0 20 20 20 20 20 20 30 3a 20 70 65 72 66 6f 72 6d 20 73 74 61 74 75 73 20 63 68 65 63 6b 2e 0d 0a ┆ 0: perform status check. ┆
0x3ac0…3ae0 0d 0a 64 61 74 61 20 62 69 74 20 20 20 20 20 20 20 20 30 20 20 20 20 20 20 20 20 20 20 20 20 31 ┆ data bit 0 1┆
0x3ae0…3b00 3a 20 73 75 70 70 72 65 73 73 20 64 61 74 61 20 63 68 65 63 6b 2e 0d 0a 20 20 20 20 20 20 20 20 ┆: suppress data check. ┆
0x3b00…3b20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 30 3a 20 70 65 72 66 6f 72 6d 20 ┆ 0: perform ┆
0x3b20…3b40 64 61 74 61 20 63 68 65 63 6b 2e 0d 0a 0d 0a 6e 6f 74 20 75 73 65 64 20 20 20 20 20 20 20 20 30 ┆data check. not used 0┆
0x3b40…3b60 0d 0a 0d 0a a1 6e 6f 74 20 75 73 65 64 20 20 20 20 20 20 20 20 30 20 05 0d 0a a1 74 65 73 74 2e ┆ not used 0 test.┆
0x3b60…3b80 6e 6f 2e 20 20 20 20 20 20 20 30 30 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 69 64 65 6e 74 ┆no. 00 ident┆
0x3b80…3ba0 69 66 69 63 61 74 69 6f 6e 20 6f 66 20 74 65 73 74 20 70 72 6f 67 72 61 6d 05 0d 0a 0d 0a 20 20 ┆ification of test program ┆
0x3ba0…3bc0 20 20 20 20 20 20 20 20 20 20 20 20 46 69 67 75 72 65 20 33 3a 20 54 65 73 74 20 70 61 72 61 6d ┆ Figure 3: Test param┆
0x3bc0…3be0 65 74 65 72 20 76 61 72 69 61 62 6c 65 2e 0d 0a 0f 0a 0d 0a 49 74 20 69 73 20 70 6f 73 73 69 62 ┆eter variable. It is possib┆
0x3be0…3c00 6c 65 20 66 6f 72 20 74 68 65 20 6f 70 65 72 61 74 6f 72 20 74 6f 20 6d 61 6e 69 70 75 6c 61 74 ┆le for the operator to manipulat┆
0x3c00…3c20 (30,) 65 20 74 68 65 73 65 20 70 61 72 61 6d 65 74 65 72 73 20 62 79 20 0a 74 79 70 69 6e 67 20 3c 65 ┆e these parameters by typing <e┆
0x3c20…3c40 73 63 3e 2e 20 74 68 69 73 20 77 69 6c 6c 20 63 61 75 73 65 20 74 68 65 20 66 6f 6c 6c 6f 77 69 ┆sc>. this will cause the followi┆
0x3c40…3c60 6e 67 20 71 75 65 73 74 69 6f 6e 73 2c 20 77 68 69 63 68 20 6d 75 73 74 20 0a 62 65 20 61 6e 73 ┆ng questions, which must be ans┆
0x3c60…3c80 77 65 72 65 64 20 6f 6e 65 20 62 79 20 6f 6e 65 2c 20 74 6f 20 61 70 70 65 61 72 20 6f 6e 20 74 ┆wered one by one, to appear on t┆
0x3c80…3ca0 68 65 20 73 63 72 65 65 6e 2e 0d 0a 0d 0a 3d 3d 3d 3d 3d 3d 3d 3d 3d 3d 3d 3d 3d 3d 20 4f 6e 62 ┆he screen. ============== Onb┆
0x3ca0…3cc0 6f 61 72 64 20 6d 65 6d 6f 72 79 20 73 69 7a 65 20 28 6b 20 62 79 74 65 73 29 3a 20 30 30 32 35 ┆oard memory size (k bytes): 0025┆
0x3cc0…3ce0 36 0d 0a 68 61 6c 74 20 6f 6e 20 65 72 72 6f 72 20 20 20 20 20 20 20 20 20 3f 20 3c 59 2f 4e 3e ┆6 halt on error ? <Y/N>┆
0x3ce0…3d00 2c 20 59 2f 0d 0a 8c 83 c8 0a 6c 6f 6f 70 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆, Y/ loop ┆
0x3d00…3d20 3f 20 3c 59 2f 4e 3e 2c 20 4e 2f 0d 0a 62 6f 6f 74 20 61 66 74 65 72 20 74 65 73 74 20 20 20 20 ┆? <Y/N>, N/ boot after test ┆
0x3d20…3d40 20 20 20 3f 20 3c 59 2f 4e 3e 2c 20 59 2f 0d 0a 73 75 70 70 72 65 73 73 20 73 74 61 74 75 73 20 ┆ ? <Y/N>, Y/ suppress status ┆
0x3d40…3d60 63 68 65 63 6b 20 3f 20 3c 59 2f 4e 3e 2c 20 4e 2f 0d 0a 73 75 70 70 72 65 73 73 20 64 61 74 61 ┆check ? <Y/N>, N/ suppress data┆
0x3d60…3d80 20 63 68 65 63 6b 20 20 20 3f 20 3c 59 2f 4e 3e 2c 20 4e 2f 0d 0a 74 65 73 74 20 6e 6f 2e 3a 20 ┆ check ? <Y/N>, N/ test no.: ┆
0x3d80…3da0 30 30 30 30 30 2f 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 46 69 67 75 72 65 ┆00000/ Figure┆
0x3da0…3dc0 20 34 3a 20 70 61 72 61 6d 65 74 65 72 20 73 65 74 74 69 6e 67 2e 0d 0a 0d 0a 54 68 65 20 61 6e ┆ 4: parameter setting. The an┆
0x3dc0…3de0 73 77 65 72 73 20 74 6f 20 74 68 65 20 22 3c 59 2f 4e 3e 22 20 71 75 65 73 74 69 6f 6e 73 20 61 ┆swers to the "<Y/N>" questions a┆
0x3de0…3e00 72 65 20 22 59 22 2c 20 22 4e 22 20 6f 72 20 63 61 72 72 69 61 67 65 20 0a 72 65 74 75 72 6e 2e ┆re "Y", "N" or carriage return.┆
0x3e00…3e20 (31,) 0d 0a 0d 0a 54 68 65 20 61 6e 73 77 65 72 20 74 6f 20 74 68 65 20 22 74 65 73 74 20 6e 6f 2e 3a ┆ The answer to the "test no.:┆
0x3e20…3e40 22 20 71 75 65 73 74 69 6f 6e 20 69 73 20 61 20 6c 65 67 61 6c 20 74 65 73 74 20 6e 75 6d 62 65 ┆" question is a legal test numbe┆
0x3e40…3e60 72 20 0a 61 6e 64 2f 6f 72 20 63 61 72 72 69 61 67 65 20 72 65 74 75 72 6e 2e 0d 0a 0d 0a 0d 0a ┆r and/or carriage return. ┆
0x3e60…3e80 b0 a1 f0 32 2e 33 20 54 65 73 74 20 4e 75 6d 62 65 72 73 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 72 65 ┆ 2.3 Test Numbers. The re┆
0x3e80…3ea0 6c 61 74 69 6f 6e 73 68 69 70 20 62 65 74 77 65 65 6e 20 74 65 73 74 20 6e 75 6d 62 65 72 73 20 ┆lationship between test numbers ┆
0x3ea0…3ec0 61 6e 64 20 61 63 74 75 61 6c 20 74 65 73 74 20 70 72 6f 67 72 61 6d 73 20 0a 61 72 65 20 61 73 ┆and actual test programs are as┆
0x3ec0…3ee0 20 66 6f 6c 6c 6f 77 73 3a 0d 0a 0e 0a 0d 0a a2 e2 a1 54 65 73 74 20 4e 6f 20 20 20 54 65 73 74 ┆ follows: Test No Test┆
0x3ee0…3f00 20 6e 61 6d 65 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 0d 0a 20 30 20 20 20 20 ┆ name 0 ┆
0x3f00…3f20 20 20 20 20 6d 65 6d 6f 72 79 20 74 65 73 74 0d 0a 20 31 20 20 20 20 20 20 20 20 52 41 4d 20 72 ┆ memory test 1 RAM r┆
0x3f20…3f40 65 66 72 65 73 68 20 74 65 73 74 0d 0a 20 32 20 20 20 20 20 20 20 20 69 41 50 58 31 38 36 20 44 ┆efresh test 2 iAPX186 D┆
0x3f40…3f60 4d 41 20 74 65 73 74 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 70 6f 77 65 72 20 75 70 0d 0a ┆MA test power up ┆
0x3f60…3f80 20 33 20 20 20 20 20 20 20 20 50 49 43 20 74 65 73 74 09 09 20 20 20 20 20 20 20 74 65 73 74 73 ┆ 3 PIC test tests┆
0x3f80…3fa0 0d 0a a1 20 34 20 20 20 20 20 20 20 20 69 41 50 58 31 38 36 20 73 6c 61 76 65 20 69 6e 74 65 72 ┆ 4 iAPX186 slave inter┆
0x3fa0…3fc0 72 75 70 74 20 74 65 73 74 0d 0a a1 e1 20 35 20 20 20 20 20 20 20 20 45 74 68 65 72 6e 65 74 20 ┆rupt test 5 Ethernet ┆
0x3fc0…3fe0 74 65 73 74 20 32 0d 0a 20 36 20 20 20 20 20 20 20 20 38 32 37 34 20 43 48 41 20 74 65 73 74 09 ┆test 2 6 8274 CHA test ┆
0x3fe0…4000 09 20 20 20 20 20 20 20 65 78 74 65 6e 64 65 64 0d 0a a1 20 37 09 20 20 20 20 20 20 46 6c 6f 70 ┆ extended 7 Flop┆
0x4000…4020 (32,) 70 79 20 74 65 73 74 e1 09 09 20 20 20 20 20 20 20 74 65 73 74 73 0d 0a 0f 0a 0d 0a 54 68 65 20 ┆py test tests The ┆
0x4020…4040 74 65 73 74 73 20 6e 75 6d 62 65 72 65 64 20 35 2d 37 20 61 72 65 20 6e 6f 74 20 72 75 6e 20 69 ┆tests numbered 5-7 are not run i┆
0x4040…4060 6e 20 74 68 65 20 64 65 66 61 75 6c 74 20 70 6f 77 65 72 20 75 70 20 0a 73 65 71 75 65 6e 63 65 ┆n the default power up sequence┆
0x4060…4080 2e 20 54 68 65 79 20 61 72 65 20 69 6e 63 6c 75 64 65 64 20 61 73 20 65 78 74 65 6e 64 65 64 20 ┆. They are included as extended ┆
0x4080…40a0 74 65 73 74 73 20 61 6e 64 20 6d 75 73 74 20 62 65 20 0a 72 65 71 75 65 73 74 65 64 20 65 78 70 ┆tests and must be requested exp┆
0x40a0…40c0 6c 69 63 69 74 20 62 79 20 6f 70 65 72 61 74 6f 72 20 69 6e 74 65 72 76 65 6e 74 69 6f 6e 2e 0d ┆licit by operator intervention. ┆
0x40c0…40c5 0a 0d 0a 0d 0a ┆ ┆
0x40c5…40c8 FormFeed {
0x40c5…40c8 0c 83 b0 ┆ ┆
0x40c5…40c8 }
0x40c8…40e0 0a b0 a1 f0 32 2e 34 20 4f 75 74 70 75 74 20 46 72 6f 6d 20 61 20 54 65 ┆ 2.4 Output From a Te┆
0x40e0…4100 73 74 2e 0d 0a 0d 0a 0d 0a 41 74 20 74 68 65 20 65 6e 64 20 6f 66 20 65 76 65 72 79 20 74 65 73 ┆st. At the end of every tes┆
0x4100…4120 74 20 70 72 6f 67 72 61 6d 2c 20 74 68 65 20 73 65 6c 66 74 65 73 74 20 77 69 6c 6c 20 69 6e 66 ┆t program, the selftest will inf┆
0x4120…4140 6f 72 6d 20 61 62 6f 75 74 20 0a 69 74 73 20 73 74 61 74 65 2c 20 6f 6b 20 6f 72 20 65 72 72 6f ┆orm about its state, ok or erro┆
0x4140…4160 72 2c 20 74 6f 20 74 68 65 20 6f 70 65 72 61 74 6f 72 20 76 69 61 20 74 68 65 20 63 6f 6e 6e 65 ┆r, to the operator via the conne┆
0x4160…4180 63 74 65 64 20 0a 63 6f 6e 73 6f 6c 65 2e 20 54 68 65 20 66 6f 72 6d 61 74 20 77 69 6c 6c 20 6e ┆cted console. The format will n┆
0x4180…419a 6f 72 6d 61 6c 6c 79 20 6c 6f 6f 6b 20 61 73 20 66 6f 6c 6c 6f 77 73 3a 0d 0a ┆ormally look as follows: ┆
0x419a…41d3 Params {
0x419a…41d3 04 00 2d 4e 0a 00 06 00 00 00 00 02 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0x419a…41d3 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x419a…41d3 }
0x41d3…420c Params {
0x41d3…420c 04 00 2d 4e 0c 00 06 00 00 00 00 03 01 48 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N H1` ┆
0x41d3…420c 00 00 00 00 00 00 00 00 05 0a 0f 17 46 4b 55 5f 69 73 7d ff ff ff ff ff 04 ┆ FKU_iså ┆
0x41d3…420c }
0x420c…4220 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x4220…4240 20 20 20 3c 4f 4b 3e 0d 0a 20 3c 74 65 73 74 20 6e 61 6d 65 3a 3e 20 20 20 2c 20 20 20 20 20 20 ┆ <OK> <test name:> , ┆
0x4240…4260 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x4260…4280 20 20 20 20 4e 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 3c 65 72 72 6f ┆ N <erro┆
0x4280…42a0 72 20 74 79 70 65 3e 20 20 20 2c 20 20 20 3c 74 65 78 74 3e 3c 65 72 72 6f 72 20 64 61 74 61 3e ┆r type> , <text><error data>┆
0x42a0…42c0 20 20 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x42c0…42e0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 30 ┆ 0┆
0x42e0…42e2 0d 0a ┆ ┆
0x42e2…431b Params {
0x42e2…431b 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0x42e2…431b 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x42e2…431b }
0x431b…4354 Params {
0x431b…4354 04 00 2d 4e 0a 00 06 00 00 00 00 02 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0x431b…4354 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x431b…4354 }
0x4354…4360 0a 0d 0a 3c 65 72 72 6f 72 20 74 79 ┆ <error ty┆
0x4360…4380 70 65 3e 20 69 73 20 61 20 70 72 69 6d 61 72 79 20 65 72 72 6f 72 74 65 78 74 20 69 6e 66 6f 72 ┆pe> is a primary errortext infor┆
0x4380…43a0 6d 69 6e 67 20 61 62 6f 75 74 20 74 68 65 20 73 70 65 63 69 66 69 63 20 0a 65 72 72 6f 72 2e 20 ┆ming about the specific error. ┆
0x43a0…43c0 3c 74 65 78 74 3e 20 69 73 20 6f 66 20 74 68 65 20 6b 69 6e 64 20 22 61 64 64 72 3a 22 2c 20 22 ┆<text> is of the kind "addr:", "┆
0x43c0…43e0 65 78 70 3a 22 20 61 6e 64 20 74 68 65 20 6c 69 6b 65 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 32 2e 35 20 ┆exp:" and the like. 2.5 ┆
0x43e0…4400 44 65 66 61 75 6c 74 20 49 6e 74 65 72 72 75 70 74 20 48 61 6e 64 6c 69 6e 67 2e 0d 0a 0d 0a 0d ┆Default Interrupt Handling. ┆
0x4400…4420 (34,) 0a 57 68 65 6e 20 74 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 68 61 ┆ When the ETC601 SBC Selftest ha┆
0x4420…4440 73 20 66 69 6e 69 73 68 65 64 20 74 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 2c 20 61 20 73 65 ┆s finished the memory test, a se┆
0x4440…4460 74 20 0a 6f 66 20 64 65 66 61 75 6c 74 20 69 6e 74 65 72 72 75 70 74 20 76 65 63 74 6f 72 73 20 ┆t of default interrupt vectors ┆
0x4460…4480 61 72 65 20 70 6c 61 63 65 64 20 69 6e 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 76 65 63 74 ┆are placed in the interrupt vect┆
0x4480…44a0 6f 72 20 0a 74 61 62 6c 65 2e 20 54 68 65 73 65 20 76 65 63 74 6f 72 73 20 61 72 65 20 70 72 69 ┆or table. These vectors are pri┆
0x44a0…44c0 6d 61 72 69 6c 79 20 75 73 65 64 20 74 6f 20 68 61 6e 64 6c 65 20 75 6e 65 78 70 65 63 74 65 64 ┆marily used to handle unexpected┆
0x44c0…44e0 20 0a 69 6e 74 65 72 72 75 70 74 73 2e 20 54 68 65 72 65 20 61 72 65 20 74 77 6f 20 6b 69 6e 64 ┆ interrupts. There are two kind┆
0x44e0…4500 73 20 6f 66 20 75 6e 65 78 70 65 63 74 65 64 20 69 6e 74 65 72 72 75 70 74 73 2e 20 54 68 65 20 ┆s of unexpected interrupts. The ┆
0x4500…4520 0a 66 69 72 73 74 20 69 73 20 68 61 6e 64 6c 65 64 20 62 79 20 74 68 65 20 69 6e 74 65 72 72 75 ┆ first is handled by the interru┆
0x4520…4540 70 74 20 70 72 6f 63 65 64 75 72 65 20 66 6f 72 20 69 6e 74 65 72 6e 61 6c 20 69 41 50 58 31 38 ┆pt procedure for internal iAPX18┆
0x4540…4560 36 20 0a 69 6e 73 74 72 75 63 74 69 6f 6e 20 69 6e 74 65 72 72 75 70 74 73 20 61 6e 64 20 74 68 ┆6 instruction interrupts and th┆
0x4560…4580 65 20 73 65 63 6f 6e 64 20 69 73 20 68 61 6e 64 6c 65 64 20 62 79 20 74 68 65 20 69 6e 74 65 72 ┆e second is handled by the inter┆
0x4580…45a0 72 75 70 74 20 0a 70 72 6f 63 65 64 75 72 65 20 66 6f 72 20 69 6c 6c 65 67 61 6c 20 64 65 76 69 ┆rupt procedure for illegal devi┆
0x45a0…45c0 63 65 20 69 6e 74 65 72 72 75 70 74 73 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 32 2e 35 2e 31 20 49 6e 73 ┆ce interrupts. 2.5.1 Ins┆
0x45c0…45e0 74 72 75 63 74 69 6f 6e 20 45 78 63 65 70 74 69 6f 6e 2e 0d 0a 0d 0a 0d 0a 49 66 20 61 6e 20 49 ┆truction Exception. If an I┆
0x45e0…4600 6e 73 74 72 75 63 74 69 6f 6e 20 45 78 63 65 70 74 69 6f 6e 20 69 6e 74 65 72 72 75 70 74 20 6f ┆nstruction Exception interrupt o┆
0x4600…4620 (35,) 63 63 75 72 73 2c 20 69 74 20 69 73 20 6c 69 6b 65 6c 79 20 74 6f 20 0a 62 65 6c 69 65 76 65 20 ┆ccurs, it is likely to believe ┆
0x4620…4640 74 68 61 74 20 74 68 69 73 20 77 61 73 20 63 61 75 73 65 64 20 62 79 20 61 20 6d 61 6c 66 75 6e ┆that this was caused by a malfun┆
0x4640…4660 63 74 69 6f 6e 20 6f 66 20 74 68 65 20 69 41 50 58 31 38 36 2c 20 0a 62 65 63 61 75 73 65 20 74 ┆ction of the iAPX186, because t┆
0x4660…4680 68 69 73 20 69 6e 74 65 72 72 75 70 74 20 69 73 20 72 65 6c 61 74 65 64 20 74 6f 20 73 6f 6d 65 ┆his interrupt is related to some┆
0x4680…46a0 20 43 50 55 20 69 6e 73 74 72 75 63 74 69 6f 6e 73 2e 0d 0a 0d 0a 49 66 20 74 68 69 73 20 65 72 ┆ CPU instructions. If this er┆
0x46a0…46c0 72 6f 72 20 73 68 6f 75 6c 64 20 6f 63 63 75 72 20 69 74 20 77 69 6c 6c 20 70 72 6f 64 75 63 65 ┆ror should occur it will produce┆
0x46c0…46e0 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 0a 65 72 72 6f 72 74 65 78 74 3a 0d 0a 0d 0a b0 09 ┆ the following errortext: ┆
0x46e0…4700 09 22 3e 3e 20 69 6e 73 74 72 75 63 74 69 6f 6e 20 65 78 63 65 70 74 69 6f 6e 22 0d 0a 0d 0a 54 ┆ ">> instruction exception" T┆
0x4700…4720 68 65 20 63 6f 72 72 6f 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 ┆he corrosponding error number is┆
0x4720…4740 20 38 2e 0d 0a 0d 0a 0d 0a 8c 83 f0 0a b0 a1 f0 32 2e 35 2e 32 20 49 6c 6c 65 67 61 6c 20 49 6e ┆ 8. 2.5.2 Illegal In┆
0x4740…4760 74 65 72 72 75 70 74 2e 0d 0a 0d 0a 0d 0a 41 74 20 74 68 65 20 65 6e 64 20 6f 66 20 65 76 65 72 ┆terrupt. At the end of ever┆
0x4760…4780 79 20 74 65 73 74 20 6c 6f 6f 70 20 74 68 65 20 72 65 63 65 70 74 69 6f 6e 20 6f 66 20 69 6e 74 ┆y test loop the reception of int┆
0x4780…47a0 65 72 72 75 70 74 73 20 61 72 65 20 0a 65 6e 61 62 6c 65 64 2e 20 4f 6e 6c 79 20 74 77 6f 20 6f ┆errupts are enabled. Only two o┆
0x47a0…47c0 66 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 72 65 71 75 65 73 74 20 6c 69 6e 65 73 20 77 69 ┆f the interrupt request lines wi┆
0x47c0…47e0 6c 6c 20 62 65 20 75 73 65 64 20 69 6e 20 0a 74 68 65 20 53 65 6c 66 74 65 73 74 2e 20 54 68 69 ┆ll be used in the Selftest. Thi┆
0x47e0…4800 73 20 69 73 20 74 68 65 20 4d 50 53 43 20 38 32 37 34 20 72 65 63 65 69 76 65 20 69 6e 74 65 72 ┆s is the MPSC 8274 receive inter┆
0x4800…4820 (36,) 72 75 70 74 20 77 68 69 63 68 20 69 73 20 0a 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 74 68 65 20 ┆rupt which is connected to the ┆
0x4820…4840 38 30 31 38 36 20 69 6e 74 65 72 72 75 70 74 20 72 65 71 75 65 73 74 20 49 4e 54 31 20 61 6e 64 ┆80186 interrupt request INT1 and┆
0x4840…4860 20 74 68 65 20 70 61 72 69 74 79 20 0a 69 6e 74 65 72 72 75 70 74 20 77 68 69 63 68 20 69 73 20 ┆ the parity interrupt which is ┆
0x4860…4880 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 74 68 65 20 38 32 35 39 20 69 6e 74 65 72 72 75 70 74 20 ┆connected to the 8259 interrupt ┆
0x4880…48a0 72 65 71 75 65 73 74 20 49 52 33 2e 0d 0a 0d 0a 0d 0a 41 6c 6c 20 6f 74 68 65 72 20 69 6e 74 65 ┆request IR3. All other inte┆
0x48a0…48c0 72 72 75 70 74 20 72 65 71 75 65 73 74 73 20 77 69 6c 6c 20 62 65 20 64 65 63 6f 64 65 64 20 61 ┆rrupt requests will be decoded a┆
0x48c0…48e0 73 20 69 6c 6c 65 67 61 6c 20 0a 69 6e 74 65 72 72 75 70 74 73 20 61 6e 64 20 77 69 6c 6c 20 70 ┆s illegal interrupts and will p┆
0x48e0…4900 72 6f 64 75 63 65 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 65 72 72 6f 72 74 65 78 74 3a 0d ┆roduce the following errortext: ┆
0x4900…4920 0a 0d 0a b0 09 09 22 69 6c 6c 65 67 61 6c 20 69 6e 74 65 72 72 75 70 74 22 0d 0a 0d 0a 66 6f 6c ┆ "illegal interrupt" fol┆
0x4920…4940 6c 6f 77 65 64 20 62 79 20 74 68 65 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 20 61 62 6f 75 74 2c 20 ┆lowed by the information about, ┆
0x4940…4960 77 68 69 63 68 20 6c 65 76 65 6c 20 77 61 73 20 69 73 73 75 69 6e 67 20 74 68 65 20 0a 69 6e 74 ┆which level was issuing the int┆
0x4960…4980 65 72 72 75 70 74 2e 0d 0a 0d 0a 54 68 65 20 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 ┆errupt. The corresponding err┆
0x4980…49a0 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 35 2e 0d 0a 0d 0a 0d 0a 49 6e 20 74 68 65 20 50 49 43 20 ┆or number is 5. In the PIC ┆
0x49a0…49c0 69 6e 74 65 72 72 75 70 74 20 74 65 73 74 20 61 6e 64 20 74 68 65 20 4d 75 6c 74 69 62 75 73 20 ┆interrupt test and the Multibus ┆
0x49c0…49e0 69 6e 74 65 72 72 75 70 74 20 74 65 73 74 20 61 6e 20 0a 22 69 6c 6c 65 67 61 6c 20 69 6e 74 65 ┆interrupt test an "illegal inte┆
0x49e0…4a00 72 72 75 70 74 22 20 65 72 72 6f 72 20 69 73 20 70 72 6f 64 75 63 65 64 20 69 66 20 69 74 20 69 ┆rrupt" error is produced if it i┆
0x4a00…4a20 (37,) 73 20 69 6d 70 6f 73 73 69 62 6c 65 20 74 6f 20 0a 63 6c 65 61 72 20 74 68 65 20 69 6e 74 65 72 ┆s impossible to clear the inter┆
0x4a20…4a40 72 75 70 74 20 66 6f 6c 6c 6f 77 69 6e 67 20 74 68 65 20 74 65 73 74 2e 20 54 68 69 73 20 6d 61 ┆rupt following the test. This ma┆
0x4a40…4a60 79 20 68 61 70 70 65 6e 20 69 66 20 61 20 0a 6a 75 6d 70 65 72 20 69 6e 20 74 68 65 20 69 6e 74 ┆y happen if a jumper in the int┆
0x4a60…4a80 65 72 72 75 70 74 20 73 74 72 61 70 20 61 72 65 61 20 53 36 20 69 73 20 6d 69 73 73 69 6e 67 2e ┆errupt strap area S6 is missing.┆
0x4a80…4aa0 0d 0a 8c 82 ac 0a 0e 0a 0d 0a a1 49 6e 74 65 72 72 75 70 74 20 6e 61 6d 65 20 20 20 20 56 65 63 ┆ Interrupt name Vec┆
0x4aa0…4ac0 74 6f 72 20 74 79 70 65 20 20 20 52 65 6c 61 74 65 64 20 69 6e 73 74 72 75 63 74 69 6f 6e 73 05 ┆tor type Related instructions ┆
0x4ac0…4ae0 0d 0a 44 69 76 69 64 65 20 45 72 72 6f 72 20 20 20 20 20 20 20 20 20 20 30 20 20 20 20 20 20 20 ┆ Divide Error 0 ┆
0x4ae0…4b00 20 20 44 49 56 2c 20 49 44 49 56 0d 0a 53 69 6e 67 6c 65 20 73 74 65 70 20 20 20 20 20 20 20 20 ┆ DIV, IDIV Single step ┆
0x4b00…4b20 20 20 20 31 20 20 20 20 20 20 20 20 20 41 4c 4c 0d 0a 4e 4d 49 20 20 20 20 20 20 20 20 20 20 20 ┆ 1 ALL NMI ┆
0x4b20…4b40 20 20 20 20 20 20 20 20 32 20 20 20 20 20 20 20 20 20 41 4c 4c 0d 0a 42 72 65 61 6b 70 6f 69 6e ┆ 2 ALL Breakpoin┆
0x4b40…4b60 74 20 20 20 20 20 20 20 20 20 20 20 20 33 20 20 20 20 20 20 20 20 20 49 4e 54 0d 0a 49 4e 54 30 ┆t 3 INT INT0┆
0x4b60…4b80 20 44 65 74 65 63 74 65 64 20 20 20 20 20 20 20 20 20 34 20 20 20 20 20 20 20 20 20 49 4e 54 30 ┆ Detected 4 INT0┆
0x4b80…4ba0 0d 0a 6f 76 65 72 66 6c 6f 77 0d 0a 41 72 72 61 79 20 42 6f 75 6e 64 73 20 20 20 20 20 20 20 20 ┆ overflow Array Bounds ┆
0x4ba0…4bc0 20 20 35 20 20 20 20 20 20 20 20 20 42 4f 55 4e 44 0d 0a 55 6e 75 73 65 64 20 4f 70 63 6f 64 65 ┆ 5 BOUND Unused Opcode┆
0x4bc0…4be0 20 20 20 20 20 20 20 20 20 36 20 20 20 20 20 20 20 20 20 55 6e 64 65 66 69 6e 65 64 20 4f 70 63 ┆ 6 Undefined Opc┆
0x4be0…4c00 6f 64 65 73 0d 0a a1 45 53 43 20 4f 70 63 6f 64 65 20 20 20 20 20 20 20 20 20 20 20 20 37 20 20 ┆odes ESC Opcode 7 ┆
0x4c00…4c20 (38,) 20 20 20 20 20 20 20 45 53 43 20 4f 70 63 6f 64 65 73 05 0d 0a a1 49 6e 74 65 72 72 75 70 74 20 ┆ ESC Opcodes Interrupt ┆
0x4c20…4c40 6e 61 6d 65 20 20 20 20 56 65 63 74 6f 72 20 74 79 70 65 20 20 20 52 65 6c 61 74 65 64 20 69 6e ┆name Vector type Related in┆
0x4c40…4c60 74 65 72 72 75 70 74 20 6c 65 76 65 6c 05 0d 0a 54 69 6d 65 72 20 30 20 49 6e 74 65 72 72 75 70 ┆terrupt level Timer 0 Interrup┆
0x4c60…4c80 74 20 20 20 20 20 38 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 38 0d 0a 52 65 73 65 72 76 65 ┆t 8 8 Reserve┆
0x4c80…4ca0 64 20 20 20 20 20 20 20 20 20 20 20 20 20 20 39 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2d ┆d 9 -┆
0x4ca0…4cc0 0d 0a 44 4d 41 20 30 20 49 6e 74 65 72 72 75 70 74 20 20 20 20 20 20 31 30 20 20 20 20 20 20 20 ┆ DMA 0 Interrupt 10 ┆
0x4cc0…4ce0 20 20 20 20 20 20 20 31 30 0d 0a 44 4d 41 20 31 20 49 6e 74 65 72 72 75 70 74 20 20 20 20 20 20 ┆ 10 DMA 1 Interrupt ┆
0x4ce0…4d00 31 31 20 20 20 20 20 20 20 20 20 20 20 20 20 20 31 31 0d 0a 49 4e 54 30 20 49 6e 74 65 72 72 75 ┆11 11 INT0 Interru┆
0x4d00…4d20 70 74 20 20 20 20 20 20 20 31 32 2a 20 20 20 20 20 20 20 20 20 20 20 20 20 31 32 0d 0a 49 4e 54 ┆pt 12* 12 INT┆
0x4d20…4d40 31 20 49 6e 74 65 72 72 75 70 74 20 20 20 20 20 20 20 31 33 2a 2a 20 20 20 20 20 20 20 20 20 20 ┆1 Interrupt 13** ┆
0x4d40…4d60 20 20 31 33 0d 0a 49 4e 54 32 20 49 6e 74 65 72 72 75 70 74 20 20 20 20 20 20 20 31 34 2a 20 20 ┆ 13 INT2 Interrupt 14* ┆
0x4d60…4d80 20 20 20 20 20 20 20 20 20 20 20 31 34 0d 0a 49 4e 54 33 20 49 6e 74 65 72 72 75 70 74 20 20 20 ┆ 14 INT3 Interrupt ┆
0x4d80…4da0 20 20 20 20 31 35 2a 2a 20 20 20 20 20 20 20 20 20 20 20 20 31 35 0d 0a 54 69 6d 65 72 20 31 20 ┆ 15** 15 Timer 1 ┆
0x4da0…4dc0 49 6e 74 65 72 72 75 70 74 20 20 20 20 31 38 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 38 0d ┆Interrupt 18 8 ┆
0x4dc0…4de0 0a a1 54 69 6d 65 72 20 32 20 49 6e 74 65 72 72 75 70 74 20 20 20 20 31 39 20 20 20 20 20 20 20 ┆ Timer 2 Interrupt 19 ┆
0x4de0…4e00 20 20 20 20 20 20 20 20 38 05 0d 0a 38 32 35 39 20 49 52 30 20 20 20 20 20 20 20 20 20 20 20 20 ┆ 8 8259 IR0 ┆
0x4e00…4e20 (39,) 20 32 30 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 30 0d 0a 38 32 35 39 20 49 52 31 20 20 20 ┆ 20 20 8259 IR1 ┆
0x4e20…4e40 20 20 20 20 20 20 20 20 20 20 32 31 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 31 0d 0a 38 32 ┆ 21 21 82┆
0x4e40…4e60 35 39 20 49 52 32 20 20 20 20 20 20 20 20 20 20 20 20 20 32 32 20 20 20 20 20 20 20 20 20 20 20 ┆59 IR2 22 ┆
0x4e60…4e80 20 20 20 32 32 0d 0a 50 61 72 2d 69 6e 74 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 33 20 20 ┆ 22 Par-int 23 ┆
0x4e80…4ea0 20 20 20 20 20 20 20 20 20 20 20 20 32 33 0d 0a 38 32 35 39 20 49 52 34 20 20 20 20 20 20 20 20 ┆ 23 8259 IR4 ┆
0x4ea0…4ec0 20 20 20 20 20 32 34 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 34 0d 0a 38 32 35 39 20 49 52 ┆ 24 24 8259 IR┆
0x4ec0…4ee0 35 20 20 20 20 20 20 20 20 20 20 20 20 20 32 35 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 35 ┆5 25 25┆
0x4ee0…4f00 0d 0a 38 32 35 39 20 49 52 36 20 20 20 20 20 20 20 20 20 20 20 20 20 32 36 20 20 20 20 20 20 20 ┆ 8259 IR6 26 ┆
0x4f00…4f20 20 20 20 20 20 20 20 32 36 0d 0a 38 32 35 39 20 49 52 37 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ 26 8259 IR7 ┆
0x4f20…4f40 32 37 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 37 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 ┆27 27 ┆
0x4f40…4f60 20 20 20 20 46 69 67 75 72 65 20 35 3a 20 49 6e 74 65 72 72 75 70 74 20 4c 65 76 65 6c 20 54 61 ┆ Figure 5: Interrupt Level Ta┆
0x4f60…4f80 62 6c 65 2e 0d 0a 0d 0a 2a 20 49 4e 54 30 20 61 6e 64 20 49 4e 54 32 20 61 72 65 20 75 73 65 64 ┆ble. * INT0 and INT2 are used┆
0x4f80…4fa0 20 61 73 20 49 4e 54 30 20 61 6e 64 20 49 4e 54 41 30 20 66 6f 72 20 74 68 65 20 38 32 35 39 2e ┆ as INT0 and INTA0 for the 8259.┆
0x4fa0…4fc0 0d 0a 2a 2a 20 49 4e 54 31 20 61 6e 64 20 49 4e 54 33 20 61 72 65 20 75 73 65 64 20 61 73 20 49 ┆ ** INT1 and INT3 are used as I┆
0x4fc0…4fe0 4e 54 31 20 61 6e 64 20 49 4e 54 41 32 20 66 6f 72 20 74 68 65 20 38 32 37 34 20 4d 50 53 43 2e ┆NT1 and INTA2 for the 8274 MPSC.┆
0x4fe0…4fe4 0d 0a 0f 0a ┆ ┆
0x4fe4…4fe7 FormFeed {
0x4fe4…4fe7 0c 83 a4 ┆ ┆
0x4fe4…4fe7 }
0x4fe7…5000 0a b0 a1 b0 33 2e 20 49 2f 4f 20 50 72 6f 63 65 64 75 72 65 73 20 61 6e 64 ┆ 3. I/O Procedures and┆
0x5000…5020 (40,) 20 54 61 62 6c 65 20 49 6e 64 65 78 69 6e 67 2e 0a 0d 0a 0d 0a 49 6e 63 6c 75 64 65 64 20 69 6e ┆ Table Indexing. Included in┆
0x5020…5040 20 74 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 69 73 20 61 20 72 61 ┆ the ETC601 SBC Selftest is a ra┆
0x5040…5060 74 68 65 72 20 73 69 6d 70 6c 65 20 68 61 6e 64 6c 69 6e 67 20 0a 6f 66 20 63 6f 6e 73 6f 6c 65 ┆ther simple handling of console┆
0x5060…5080 20 69 6e 70 75 74 20 61 6e 64 20 6f 75 74 70 75 74 2e 20 46 75 72 74 68 65 72 6d 6f 72 65 20 69 ┆ input and output. Furthermore i┆
0x5080…50a0 74 20 75 73 65 73 20 61 72 72 61 79 20 74 61 62 6c 65 73 20 74 6f 20 0a 64 65 63 69 64 65 20 77 ┆t uses array tables to decide w┆
0x50a0…50c0 68 69 63 68 20 74 65 73 74 20 69 73 20 74 6f 20 62 65 20 73 74 61 72 74 65 64 20 61 6e 64 20 77 ┆hich test is to be started and w┆
0x50c0…50e0 68 69 63 68 20 65 72 72 6f 72 74 65 78 74 20 69 73 20 74 6f 20 62 65 20 0a 77 72 69 74 74 65 6e ┆hich errortext is to be written┆
0x50e0…5100 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 33 2e 31 20 49 6e 70 75 74 2e 0d 0a 0d 0a 0d 0a 49 6e 70 75 74 20 ┆. 3.1 Input. Input ┆
0x5100…5120 69 73 20 68 61 6e 64 6c 65 64 20 69 6e 20 74 68 65 20 6d 6f 73 74 20 73 69 6d 70 6c 65 20 77 61 ┆is handled in the most simple wa┆
0x5120…5140 79 20 70 6f 73 73 69 62 6c 65 2e 20 49 74 20 77 6f 72 6b 73 20 0a 6f 70 65 72 61 74 6f 72 20 69 ┆y possible. It works operator i┆
0x5140…5160 6e 74 65 72 61 63 74 69 76 65 20 75 73 69 6e 67 20 74 68 65 20 6f 6e 65 20 63 68 61 72 61 63 74 ┆nteractive using the one charact┆
0x5160…5180 65 72 20 62 75 66 66 65 72 20 69 6e 20 74 68 65 20 55 53 41 52 54 20 0a 69 74 73 65 6c 66 2e 0d ┆er buffer in the USART itself. ┆
0x5180…51a0 0a 0d 0a 55 53 41 52 54 20 72 65 63 65 69 76 65 20 69 6e 74 65 72 72 75 70 74 73 20 69 73 20 6f ┆ USART receive interrupts is o┆
0x51a0…51c0 6e 6c 79 20 75 73 65 64 20 74 6f 20 67 69 76 65 20 64 69 66 66 65 72 65 6e 74 20 0a 61 74 74 65 ┆nly used to give different atte┆
0x51c0…51e0 6e 74 69 6f 6e 73 20 74 6f 20 74 68 65 20 73 65 6c 66 74 65 73 74 2e 20 54 68 65 73 65 20 61 72 ┆ntions to the selftest. These ar┆
0x51e0…5200 65 20 3c 65 73 63 3e 2c 20 3c 63 6e 74 72 6c 3e 3c 40 3e 2c 20 0a 3c 63 6e 74 72 6c 3e 3c 51 3e ┆e <esc>, <cntrl><@>, <cntrl><Q>┆
0x5200…5220 (41,) 2c 20 61 6e 64 20 3c 63 6e 74 72 6c 3e 3c 53 3e 2e 20 53 65 65 20 73 65 63 74 69 6f 6e 20 32 2e ┆, and <cntrl><S>. See section 2.┆
0x5220…5240 31 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 33 2e 32 20 4f 75 74 70 75 74 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 ┆1. 3.2 Output. The ┆
0x5240…5260 74 65 73 74 6f 75 74 70 75 74 20 66 72 6f 6d 20 74 68 65 20 73 65 6c 66 74 65 73 74 20 69 73 20 ┆testoutput from the selftest is ┆
0x5260…5280 61 20 63 68 61 72 61 63 74 65 72 20 62 79 20 63 68 61 72 61 63 74 65 72 20 0a 6f 75 74 70 75 74 ┆a character by character output┆
0x5280…52a0 20 77 69 74 68 6f 75 74 20 61 6e 79 20 69 6e 74 65 72 72 75 70 74 20 67 65 6e 65 72 61 74 69 6f ┆ without any interrupt generatio┆
0x52a0…52c0 6e 2e 20 54 68 65 20 63 6f 6e 64 69 74 69 6f 6e 20 66 6f 72 20 0a 73 65 6e 64 69 6e 67 20 61 20 ┆n. The condition for sending a ┆
0x52c0…52e0 63 68 61 72 61 63 74 65 72 20 74 6f 20 74 68 65 20 4d 50 53 43 20 38 32 37 34 20 69 73 20 74 68 ┆character to the MPSC 8274 is th┆
0x52e0…5300 65 20 73 74 61 74 75 73 2c 20 74 72 61 6e 73 6d 69 74 74 65 72 20 0a 62 75 66 66 65 72 20 65 6d ┆e status, transmitter buffer em┆
0x5300…5320 70 74 79 2e 0d 0a 0d 0a b0 a1 f0 33 2e 33 20 54 65 73 74 20 53 65 6c 65 63 74 69 6f 6e 2e 0d 0a ┆pty. 3.3 Test Selection. ┆
0x5320…5340 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 6e 75 6d 62 65 72 20 66 69 65 6c 64 20 6f 66 20 74 68 65 ┆ The test number field of the┆
0x5340…5360 20 74 65 73 74 20 70 61 72 61 6d 65 74 65 72 20 73 77 69 74 63 68 20 28 73 65 65 20 66 69 67 2e ┆ test parameter switch (see fig.┆
0x5360…5380 20 33 29 20 0a 69 73 20 75 73 65 64 20 74 6f 20 73 65 6c 65 63 74 20 74 68 65 20 6e 65 78 74 20 ┆ 3) is used to select the next ┆
0x5380…53a0 74 65 73 74 20 74 6f 20 62 65 20 72 75 6e 2e 20 54 68 69 73 20 6e 75 6d 62 65 72 20 69 73 20 61 ┆test to be run. This number is a┆
0x53a0…53c0 6e 20 0a 69 6e 64 65 78 20 69 6e 20 61 6e 20 61 72 72 61 79 2c 20 77 68 69 63 68 20 66 6f 72 20 ┆n index in an array, which for ┆
0x53c0…53e0 65 76 65 72 79 20 74 65 73 74 20 63 6f 6e 74 61 69 6e 73 20 74 68 65 20 6f 66 66 73 65 74 20 74 ┆every test contains the offset t┆
0x53e0…5400 6f 20 0a 74 68 65 20 69 6e 74 72 6f 64 75 63 74 69 6f 6e 20 74 65 78 74 20 61 6e 64 20 74 68 65 ┆o the introduction text and the┆
0x5400…5420 (42,) 20 73 74 61 72 74 69 6e 67 20 61 64 64 72 65 73 73 2e 0d 0a 0d 0a 8c 83 bc 0a 54 68 65 20 45 54 ┆ starting address. The ET┆
0x5420…5440 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 77 69 6c 6c 20 61 6c 77 61 79 73 20 77 72 ┆C601 SBC Selftest will always wr┆
0x5440…5460 69 74 65 20 74 68 65 20 74 65 73 74 20 69 6e 74 72 6f 64 75 63 74 69 6f 6e 20 0a 74 65 78 74 20 ┆ite the test introduction text ┆
0x5460…547d 62 65 66 6f 72 65 20 74 68 65 20 74 65 73 74 20 69 73 20 73 74 61 72 74 65 64 2e 0d 0a ┆before the test is started. ┆
0x547d…5480 FormFeed {
0x547d…5480 0c 80 98 ┆ ┆
0x547d…5480 }
0x5480…54a0 0a b0 a1 34 a1 2e 20 53 65 6c 66 74 65 73 74 20 53 77 69 74 63 68 20 53 65 74 74 69 6e 67 73 2e ┆ 4 . Selftest Switch Settings.┆
0x54a0…54c0 0d 0a 0d 0a 0d 0a 54 68 65 20 45 54 43 36 30 31 20 69 73 20 65 71 75 69 70 70 65 64 20 77 69 74 ┆ The ETC601 is equipped wit┆
0x54c0…54e0 68 20 61 20 53 65 6c 66 74 65 73 74 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 73 77 69 74 63 ┆h a Selftest configuration switc┆
0x54e0…5500 68 20 0a 28 53 32 33 29 2c 20 77 68 69 63 68 20 69 73 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 ┆h (S23), which is connected to ┆
0x5500…5520 74 68 65 20 38 32 35 35 2c 20 50 41 20 70 6f 72 74 2e 0d 0a 0d 0a 50 41 2c 20 62 69 74 20 30 2d ┆the 8255, PA port. PA, bit 0-┆
0x5520…5540 31 20 3a 20 84 54 68 65 73 65 20 62 69 74 73 20 61 72 65 20 75 73 65 64 20 62 79 20 74 68 65 20 ┆1 : These bits are used by the ┆
0x5540…5560 6d 65 6d 6f 72 79 20 74 65 73 74 20 74 6f 20 64 65 74 65 72 6d 69 6e 65 20 0a 19 8e 80 80 74 68 ┆memory test to determine th┆
0x5560…5580 65 20 6f 6e 62 6f 61 72 64 20 6d 65 6d 6f 72 79 20 73 69 7a 65 2e 0d 0a 0d 0a 50 41 2c 20 62 69 ┆e onboard memory size. PA, bi┆
0x5580…55a0 74 20 32 20 20 20 3a 20 84 74 68 69 73 20 62 69 74 20 69 73 20 75 73 65 64 20 74 6f 20 63 6f 6e ┆t 2 : this bit is used to con┆
0x55a0…55c0 66 69 67 75 72 61 74 65 20 74 68 65 20 43 50 55 20 61 73 20 61 20 22 74 65 73 74 2d 0a 19 8e 80 ┆figurate the CPU as a "test- ┆
0x55c0…55e0 80 68 6f 73 74 22 20 6f 72 20 22 74 65 73 74 2d 73 6c 61 76 65 22 2e 0d 0a 0d 0a 50 41 2c 20 62 ┆ host" or "test-slave". PA, b┆
0x55e0…5600 69 74 20 33 20 20 20 3a 20 84 54 68 69 73 20 62 69 74 2c 20 69 66 20 22 31 22 2c 20 77 69 6c 6c ┆it 3 : This bit, if "1", will┆
0x5600…5620 (43,) 20 63 61 75 73 65 20 74 68 65 20 53 65 6c 66 74 65 73 74 20 74 6f 20 0a 19 8e 80 80 63 6f 6e 74 ┆ cause the Selftest to cont┆
0x5620…5640 69 6e 6f 75 73 6c 79 20 72 75 6e 20 69 6e 20 61 20 6c 6f 6f 70 20 74 68 61 74 20 69 73 20 74 65 ┆inously run in a loop that is te┆
0x5640…5660 73 74 69 6e 67 20 74 68 65 20 43 50 55 20 0a 19 8e 80 80 74 6f 20 6d 65 6d 6f 72 79 20 62 75 73 ┆sting the CPU to memory bus┆
0x5660…5680 20 61 6e 64 20 67 65 6e 65 72 61 74 65 20 63 68 69 70 20 73 65 6c 65 63 74 20 6f 6e 20 61 6c 6c ┆ and generate chip select on all┆
0x5680…56a0 20 0a 19 8e 80 80 6f 6e 62 6f 61 72 64 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 63 68 69 70 73 2e 20 ┆ onboard controller chips. ┆
0x56a0…56c0 53 65 65 20 63 68 61 70 74 65 72 20 37 2e 20 54 68 69 73 20 69 73 20 0a 19 8e 80 80 69 6e 74 65 ┆See chapter 7. This is inte┆
0x56c0…56e0 6e 64 65 64 20 66 6f 72 20 63 6f 6d 70 6c 65 78 20 66 61 75 6c 74 20 66 69 6e 64 69 6e 67 2e 0d ┆nded for complex fault finding. ┆
0x56e0…5700 0a 0d 0a 50 41 2c 20 62 69 74 20 34 20 20 20 3a 20 84 74 68 69 73 20 62 69 74 2c 20 69 66 20 22 ┆ PA, bit 4 : this bit, if "┆
0x5700…5720 31 22 20 6d 61 6b 65 73 20 74 68 65 20 74 65 73 74 70 72 6f 67 72 61 6d 20 74 6f 20 61 73 73 75 ┆1" makes the testprogram to assu┆
0x5720…5740 6d 65 20 61 6e 20 0a 19 8e 80 80 38 20 4d 48 7a 20 43 50 55 20 69 6e 73 74 61 6c 6c 65 64 2e 20 ┆me an 8 MHz CPU installed. ┆
0x5740…5760 54 68 69 73 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 20 69 73 20 75 73 65 64 20 74 6f 20 0a 19 8e 80 ┆This information is used to ┆
0x5760…5780 80 63 6f 6e 74 72 6f 6c 20 74 68 65 20 6f 6e 2d 63 68 69 70 20 74 69 6d 65 72 20 75 73 65 64 20 ┆ control the on-chip timer used ┆
0x5780…57a0 61 73 20 62 61 75 64 72 61 74 65 20 0a 19 8e 80 80 67 65 6e 65 72 61 74 6f 72 2e 0d 0a 0d 0a 09 ┆as baudrate generator. ┆
0x57a0…57c0 09 09 09 09 30 30 20 3a 20 31 32 38 20 4b 62 79 74 65 73 20 52 41 4d 0d 0a 20 20 20 20 2e 20 2e ┆ 00 : 128 Kbytes RAM . .┆
0x57c0…57e0 20 2e 20 2e 20 2e 09 09 09 09 30 31 20 3a 20 32 35 36 20 4b 62 79 74 65 73 20 52 41 4d 0d 0a 20 ┆ . . . 01 : 256 Kbytes RAM ┆
0x57e0…5800 20 20 31 b0 2e f0 20 2e 20 2e 20 2e 20 2e 09 09 09 09 31 30 20 3a 20 35 31 32 20 4b 62 79 74 65 ┆ 1 . . . . . 10 : 512 Kbyte┆
0x5800…5820 (44,) 73 20 52 41 4d 0d 0a 20 20 20 20 21 20 21 20 21 20 a1 21 20 21 20 20 20 20 20 20 20 20 20 20 20 ┆s RAM ! ! ! ! ! ┆
0x5820…5840 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 31 31 20 3a 20 31 20 4d 62 79 74 65 ┆ 11 : 1 Mbyte┆
0x5840…5860 73 20 52 41 4d 20 20 20 09 0d 0a 20 20 20 20 21 20 21 20 21 0d 0a 20 20 20 20 21 20 21 20 21 09 ┆s RAM ! ! ! ! ! ! ┆
0x5860…5880 09 09 09 20 30 20 3a 20 4d 61 73 74 65 72 20 45 54 43 36 30 31 0d 0a 20 20 20 20 21 20 21 20 21 ┆ 0 : Master ETC601 ! ! !┆
0x5880…58a0 a2 a1 e2 20 20 20 09 09 09 09 20 31 20 3a 20 53 6c 61 76 65 20 45 54 43 36 30 31 20 20 20 20 0d ┆ 1 : Slave ETC601 ┆
0x58a0…58c0 0a 20 20 20 20 21 20 21 0d 0a 20 20 20 20 21 20 21 09 09 09 09 20 30 20 3a 20 4e 6f 72 6d 61 6c ┆ ! ! ! ! 0 : Normal┆
0x58c0…58e0 20 6d 6f 64 65 0d 0a 20 20 20 20 21 20 21 a1 09 09 09 09 20 31 20 3a 20 43 68 69 70 20 73 65 6c ┆ mode ! ! 1 : Chip sel┆
0x58e0…5900 65 63 74 20 6d 6f 64 65 20 0d 0a 20 20 20 20 21 0d 0a 20 20 20 20 21 09 09 09 09 20 30 20 3a 20 ┆ect mode ! ! 0 : ┆
0x5900…5920 36 20 4d 48 7a 20 69 41 50 58 31 38 36 20 0d 0a 20 20 20 20 21 a1 20 09 09 09 09 20 31 20 3a 20 ┆6 MHz iAPX186 ! 1 : ┆
0x5920…5940 38 20 4d 48 7a 20 69 41 50 58 31 38 36 20 20 20 20 0d 0a 0d 0a a1 e1 e1 e1 0d 0a 20 20 20 20 20 ┆8 MHz iAPX186 ┆
0x5940…5960 20 20 20 20 20 20 20 20 20 a1 46 69 67 75 72 65 20 38 20 3a 20 54 68 65 20 53 32 33 20 6a 75 6d ┆ Figure 8 : The S23 jum┆
0x5960…596b 70 65 72 20 61 72 65 61 2e 0d 0a ┆per area. ┆
0x596b…596e FormFeed {
0x596b…596e 0c 83 d4 ┆ ┆
0x596b…596e }
0x596e…5980 0a b0 a1 35 2e 20 49 6e 69 74 69 61 6c 69 7a 61 74 69 ┆ 5. Initializati┆
0x5980…59a0 6f 6e 2e 0d 0a 0d 0a 0d 0a 41 66 74 65 72 20 70 6f 77 65 72 20 75 70 2f 72 65 73 65 74 20 74 68 ┆on. After power up/reset th┆
0x59a0…59c0 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 77 69 6c 6c 20 70 65 72 66 6f ┆e ETC601 SBC Selftest will perfo┆
0x59c0…59e0 72 6d 20 73 6f 6d 65 20 0a 69 6e 69 74 69 61 6c 69 7a 61 74 69 6f 6e 73 20 6f 66 20 74 68 65 20 ┆rm some initializations of the ┆
0x59e0…5a00 6f 6e 62 6f 61 72 64 20 63 6f 6e 74 72 6f 6c 6c 65 72 73 2e 0d 0a 0d 0a 54 68 65 20 69 6e 69 74 ┆onboard controllers. The init┆
0x5a00…5a20 (45,) 69 61 6c 69 7a 61 74 69 6f 6e 73 20 61 72 65 20 63 6f 6d 6d 6f 6e 20 66 6f 72 20 74 68 65 20 53 ┆ializations are common for the S┆
0x5a20…5a40 65 6c 66 74 65 73 74 20 61 6e 64 20 74 68 65 20 0a 62 6f 6f 74 6c 6f 61 64 65 72 2e 0d 0a 0d 0a ┆elftest and the bootloader. ┆
0x5a40…5a60 0d 0a b0 a1 f0 35 2e 31 20 57 61 69 74 20 53 74 61 74 65 73 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 50 ┆ 5.1 Wait States. The P┆
0x5a60…5a80 52 4f 4d 20 61 6e 64 20 52 41 4d 20 6d 65 6d 6f 72 79 20 77 69 6c 6c 20 68 61 76 65 20 30 20 77 ┆ROM and RAM memory will have 0 w┆
0x5a80…5aa0 61 69 74 20 73 74 61 74 65 73 2e 0d 0a 0d 0a 50 68 65 72 69 70 68 65 72 61 6c 73 20 6f 6e 20 50 ┆ait states. Pheripherals on P┆
0x5aa0…5ac0 43 53 20 30 2d 33 20 77 69 6c 6c 20 68 61 76 65 20 31 20 77 61 69 74 20 73 74 61 74 65 0d 0a 50 ┆CS 0-3 will have 1 wait state P┆
0x5ac0…5ae0 68 65 72 69 70 68 65 72 61 6c 73 20 6f 6e 20 50 43 53 20 34 2d 36 20 77 69 6c 6c 20 68 61 76 65 ┆heripherals on PCS 4-6 will have┆
0x5ae0…5b00 20 32 20 77 61 69 74 20 73 74 61 74 65 73 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 35 2e 32 20 69 41 50 58 ┆ 2 wait states. 5.2 iAPX┆
0x5b00…5b20 31 38 36 20 49 6e 74 65 72 72 75 70 74 20 43 6f 6e 74 72 6f 6c 6c 65 72 2e 0d 0a 0d 0a 0d 0a 54 ┆186 Interrupt Controller. T┆
0x5b20…5b40 68 65 20 69 6e 74 65 72 72 75 70 74 20 76 65 63 74 6f 72 20 66 6f 72 20 74 68 65 20 69 41 50 58 ┆he interrupt vector for the iAPX┆
0x5b40…5b60 31 38 36 20 63 6f 6e 74 72 6f 6c 6c 65 72 73 20 69 73 20 74 69 65 64 20 74 6f 20 0a 73 70 65 63 ┆186 controllers is tied to spec┆
0x5b60…5b80 69 66 69 63 20 6d 65 6d 6f 72 79 20 6c 6f 63 61 74 69 6f 6e 73 2c 20 65 71 75 61 6c 20 74 6f 20 ┆ific memory locations, equal to ┆
0x5b80…5ba0 74 68 65 20 6c 6f 63 61 74 69 6f 6e 20 32 30 48 20 66 6f 72 20 74 68 65 20 0a 66 69 72 73 74 20 ┆the location 20H for the first ┆
0x5ba0…5bc0 76 65 63 74 6f 72 20 69 6e 20 74 68 65 20 74 61 62 6c 65 2e 20 53 65 65 20 73 65 63 74 69 6f 6e ┆vector in the table. See section┆
0x5bc0…5be0 20 32 2e 35 2e 0d 0a 0d 0a 09 1f a1 49 4e 54 30 2f 49 4e 54 32 3a 0d 0a 20 20 20 20 20 20 20 20 ┆ 2.5. INT0/INT2: ┆
0x5be0…5c00 20 50 6f 72 74 20 20 3a 20 46 46 33 38 48 0d 0a 20 20 20 20 20 20 20 20 20 56 61 6c 75 65 20 3a ┆ Port : FF38H Value :┆
0x5c00…5c20 (46,) 20 33 37 48 0d 0a 0d 0a 54 68 65 73 65 20 74 77 6f 20 70 69 6e 73 20 6f 66 20 74 68 65 20 69 41 ┆ 37H These two pins of the iA┆
0x5c20…5c40 50 58 31 38 36 20 69 73 20 75 73 65 64 20 66 6f 72 20 63 61 73 63 61 64 69 6e 67 20 74 6f 20 74 ┆PX186 is used for cascading to t┆
0x5c40…5c60 68 65 20 65 78 74 65 72 6e 20 0a 69 6e 74 65 72 72 75 70 74 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 ┆he extern interrupt controller ┆
0x5c60…5c80 38 32 35 39 2e 0d 0a 0d 0a 09 a1 49 4e 54 31 2f 49 4e 54 33 3a 0d 0a 20 20 20 20 20 20 20 20 50 ┆8259. INT1/INT3: P┆
0x5c80…5ca0 6f 72 74 20 20 3a 20 46 46 33 41 48 0d 0a 20 20 20 20 20 20 20 20 56 61 6c 75 65 20 3a 20 33 37 ┆ort : FF3AH Value : 37┆
0x5ca0…5cc0 48 0d 0a 0d 0a 8c 83 bc 0a 54 68 65 73 65 20 74 77 6f 20 70 69 6e 73 20 6f 66 20 74 68 65 20 69 ┆H These two pins of the i┆
0x5cc0…5ce0 41 50 58 38 30 31 38 36 20 69 73 20 75 73 65 64 20 66 6f 72 20 63 61 73 63 61 64 69 6e 67 20 74 ┆APX80186 is used for cascading t┆
0x5ce0…5d00 6f 20 74 68 65 20 4d 50 53 43 20 0a 38 32 37 34 2e 0d 0a 0d 0a 09 a1 4d 61 73 6b 20 52 65 67 69 ┆o the MPSC 8274. Mask Regi┆
0x5d00…5d20 73 74 65 72 3a 0d 0a 20 20 20 20 20 20 20 20 50 6f 72 74 20 20 3a 20 46 46 32 38 48 0d 0a 20 20 ┆ster: Port : FF28H ┆
0x5d20…5d40 20 20 20 20 20 20 56 61 6c 75 65 20 3a 20 46 44 48 0d 0a 0d 0a 57 68 69 63 68 20 77 69 6c 6c 20 ┆ Value : FDH Which will ┆
0x5d40…5d60 6d 61 73 6b 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 3a 0d 0a 0d 0a 09 49 33 20 20 3a 20 31 09 ┆mask the following: I3 : 1 ┆
0x5d60…5d80 3b 20 49 4e 54 33 0d 0a 09 49 32 20 20 3a 20 31 09 3b 20 49 4e 54 32 0d 0a 09 49 31 20 20 3a 20 ┆; INT3 I2 : 1 ; INT2 I1 : ┆
0x5d80…5da0 31 09 3b 20 49 4e 54 31 0d 0a 09 49 30 20 20 3a 20 30 09 3b 20 49 4e 54 30 0d 0a 09 44 31 20 20 ┆1 ; INT1 I0 : 0 ; INT0 D1 ┆
0x5da0…5dc0 3a 20 31 09 3b 20 44 4d 41 31 0d 0a 09 44 30 20 20 3a 20 31 09 3b 20 44 4d 41 30 0d 0a 09 54 52 ┆: 1 ; DMA1 D0 : 1 ; DMA0 TR┆
0x5dc0…5de0 4d 20 3a 20 31 09 3b 20 54 69 6d 65 72 73 0d 0a 0d 0a 0d 0a b0 a1 f0 35 2e 33 20 50 72 6f 67 72 ┆M : 1 ; Timers 5.3 Progr┆
0x5de0…5e00 61 6d 61 62 6c 65 20 49 6e 74 65 72 72 75 70 74 20 43 6f 6e 74 72 6f 6c 6c 65 72 20 38 32 35 39 ┆amable Interrupt Controller 8259┆
0x5e00…5e20 (47,) 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 69 ┆. The ETC601 SBC Selftest i┆
0x5e20…5e40 73 20 63 6f 6e 66 69 67 75 72 61 74 65 64 20 77 69 74 68 20 55 53 41 52 54 20 70 61 72 69 74 79 ┆s configurated with USART parity┆
0x5e40…5e60 20 0a 69 6e 74 65 72 72 75 70 74 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 49 52 33 2e 0d 0a 0d ┆ interrupt connected to IR3. ┆
0x5e60…5e80 0a 09 a1 38 32 35 39 20 73 65 74 75 70 3a 0d 0a 20 20 20 20 20 20 20 20 49 43 57 20 31 20 3a 20 ┆ 8259 setup: ICW 1 : ┆
0x5e80…5ea0 31 42 48 20 20 3b 20 6c 65 76 65 6c 20 74 72 69 67 67 65 72 65 64 20 69 6e 70 75 74 2c 20 73 69 ┆1BH ; level triggered input, si┆
0x5ea0…5ec0 6e 67 6c 65 20 6d 6f 64 65 0d 0a 20 20 20 20 20 20 20 20 49 43 57 20 32 20 3a 20 32 30 48 20 20 ┆ngle mode ICW 2 : 20H ┆
0x5ec0…5ee0 3b 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 76 65 63 74 6f 72 20 74 61 62 6c 65 20 73 74 61 ┆; the interrupt vector table sta┆
0x5ee0…5f00 72 74 73 20 69 6e 20 38 30 48 0d 0a 20 20 20 20 20 20 20 20 49 43 57 20 34 20 3a 20 31 44 48 20 ┆rts in 80H ICW 4 : 1DH ┆
0x5f00…5f20 20 84 3b 20 6e 6f 6e 20 62 75 66 66 65 72 20 6d 6f 64 65 2c 20 6e 6f 72 6d 61 6c 20 45 4f 49 20 ┆ ; non buffer mode, normal EOI ┆
0x5f20…5f40 61 6e 64 20 6e 6f 74 20 66 75 6c 6c 79 20 0a 19 95 80 80 3b 20 6e 65 73 74 65 64 2e 0d 0a 20 20 ┆and not fully ; nested. ┆
0x5f40…5f60 20 20 20 20 20 20 4d 41 53 4b 20 20 3a 20 46 37 48 20 20 3b 20 65 6e 61 62 6c 65 20 70 61 72 69 ┆ MASK : F7H ; enable pari┆
0x5f60…5f80 74 79 20 69 6e 74 65 72 72 75 70 74 20 6f 6e 20 49 52 33 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 35 2e 34 ┆ty interrupt on IR3. 5.4┆
0x5f80…5fa0 20 69 41 50 58 31 38 36 20 54 69 6d 65 72 20 31 2e 0d 0a 0d 0a 0d 0a 54 69 6d 65 72 20 31 20 69 ┆ iAPX186 Timer 1. Timer 1 i┆
0x5fa0…5fc0 73 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 61 73 20 61 20 62 61 75 64 72 61 74 65 20 67 65 6e 65 ┆s initialized as a baudrate gene┆
0x5fc0…5fe0 72 61 74 6f 72 20 69 6e 20 61 6c 74 65 72 6e 61 74 69 6e 67 20 0a 6d 6f 64 65 20 77 69 74 68 20 ┆rator in alternating mode with ┆
0x5fe0…6000 65 76 65 6e 20 64 75 74 79 20 63 79 63 6c 65 2e 20 49 66 20 6e 6f 20 63 6f 6e 73 6f 6c 65 20 69 ┆even duty cycle. If no console i┆
0x6000…6020 (48,) 73 20 63 6f 6e 6e 65 63 74 65 64 20 74 68 65 20 0a 62 61 75 64 72 61 74 65 20 69 73 20 73 65 74 ┆s connected the baudrate is set┆
0x6020…6040 20 74 6f 20 39 36 30 30 20 62 61 75 64 2c 20 6f 74 68 65 72 77 69 73 65 20 74 68 65 20 42 61 75 ┆ to 9600 baud, otherwise the Bau┆
0x6040…6060 64 20 52 61 74 65 20 0a 44 65 74 65 72 6d 69 6e 61 74 69 6f 6e 20 70 72 6f 63 65 64 75 72 65 20 ┆d Rate Determination procedure ┆
0x6060…6080 69 73 20 65 6e 74 65 72 65 64 20 73 65 65 20 63 68 61 70 74 65 72 20 36 2e 0d 0a 0d 0a 0d 0a 8c ┆is entered see chapter 6. ┆
0x6080…60a0 83 ec 0a b0 a1 f0 35 2e 35 20 4d 50 53 43 20 38 32 37 34 20 43 68 2e 20 42 20 28 43 6f 6e 73 6f ┆ 5.5 MPSC 8274 Ch. B (Conso┆
0x60a0…60c0 6c 65 20 49 6e 74 65 72 66 61 63 65 29 2e 0d 0a 0d 0a 0d 0a 42 61 75 64 72 61 74 65 20 66 61 63 ┆le Interface). Baudrate fac┆
0x60c0…60e0 74 6f 72 20 20 3a 20 58 31 36 0d 0a 43 68 61 72 61 63 74 65 72 20 6c 65 6e 67 74 68 20 3a 20 38 ┆tor : X16 Character length : 8┆
0x60e0…6100 20 62 69 74 73 0d 0a 50 61 72 69 74 79 20 20 20 20 20 20 20 20 20 20 20 3a 20 6e 6f 6e 65 0d 0a ┆ bits Parity : none ┆
0x6100…6120 53 74 6f 70 20 62 69 74 73 20 20 20 20 20 20 20 20 3a 20 32 0d 0a 4d 6f 64 65 20 20 20 20 20 20 ┆Stop bits : 2 Mode ┆
0x6120…6140 20 20 20 20 20 20 20 3a 20 61 73 79 6e 63 68 72 6f 6e 6f 75 73 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 35 ┆ : asynchronous. 5┆
0x6140…6160 2e 36 20 42 75 73 74 65 73 74 2c 20 43 68 69 70 20 53 65 6c 65 63 74 2e 0d 0a 0d 0a 0d 0a 54 6f ┆.6 Bustest, Chip Select. To┆
0x6160…6180 20 65 61 73 65 20 63 6f 6d 70 6c 65 78 20 64 65 62 75 67 67 69 6e 67 2c 20 61 20 43 50 55 20 74 ┆ ease complex debugging, a CPU t┆
0x6180…61a0 6f 20 6d 65 6d 6f 72 79 20 62 75 73 74 65 73 74 20 61 6e 64 20 61 20 63 68 69 70 20 0a 73 65 6c ┆o memory bustest and a chip sel┆
0x61a0…61c0 65 63 74 20 6c 6f 6f 70 20 61 72 65 20 73 75 70 70 6c 69 65 64 20 61 73 20 61 20 66 75 6e 63 74 ┆ect loop are supplied as a funct┆
0x61c0…61e0 69 6f 6e 20 6f 66 20 74 68 65 20 38 32 35 35 20 50 41 33 20 62 69 74 2e 0d 0a 0d 0a 49 66 20 74 ┆ion of the 8255 PA3 bit. If t┆
0x61e0…6200 68 65 20 38 32 35 35 20 50 41 33 20 62 69 74 20 69 73 20 73 65 74 20 74 6f 20 22 31 22 20 62 6f ┆he 8255 PA3 bit is set to "1" bo┆
0x6200…6220 (49,) 74 68 20 74 68 65 20 62 75 73 74 65 73 74 20 61 6e 64 20 74 68 65 20 63 68 69 70 20 0a 73 65 6c ┆th the bustest and the chip sel┆
0x6220…6240 65 63 74 20 6c 6f 6f 70 20 61 72 65 20 65 78 65 63 75 74 65 64 2e 20 46 69 72 73 74 20 74 68 65 ┆ect loop are executed. First the┆
0x6240…6260 72 65 20 77 69 6c 6c 20 62 65 20 70 65 72 66 6f 72 6d 65 64 20 69 6e 70 75 74 20 0a 69 6e 73 74 ┆re will be performed input inst┆
0x6260…6280 72 75 63 74 69 6f 6e 73 20 6f 6e 20 61 6c 6c 20 72 65 6c 65 76 61 6e 74 20 49 2f 4f 2d 64 65 76 ┆ructions on all relevant I/O-dev┆
0x6280…62a0 69 63 65 73 2e 20 54 68 65 73 65 20 61 72 65 3a 0d 0a 0d 0a 50 6f 72 74 20 30 2c 20 38 30 48 2c ┆ices. These are: Port 0, 80H,┆
0x62a0…62c0 20 31 30 30 48 2c 20 31 38 30 48 2c 20 31 38 32 48 2c 20 31 38 34 48 2c 20 31 38 36 48 2c 20 31 ┆ 100H, 180H, 182H, 184H, 186H, 1┆
0x62c0…62e0 39 30 48 2c 20 31 43 30 48 2c 20 31 43 32 48 2c 20 0a 32 30 30 48 2c 20 32 38 30 48 20 61 6e 64 ┆90H, 1C0H, 1C2H, 200H, 280H and┆
0x62e0…6300 20 33 30 30 48 2e 0d 0a 0d 0a 54 68 69 73 20 6d 69 67 68 74 20 62 65 20 75 73 65 64 20 66 6f 72 ┆ 300H. This might be used for┆
0x6300…6320 20 6d 65 61 73 75 72 65 6d 65 6e 74 73 2e 0d 0a 0d 0a 53 65 63 6f 6e 64 6c 79 20 61 20 43 50 55 ┆ measurements. Secondly a CPU┆
0x6320…6340 20 74 6f 20 6d 65 6d 6f 72 79 20 62 75 73 74 65 73 74 20 69 73 20 70 65 72 66 6f 72 6d 65 64 2e ┆ to memory bustest is performed.┆
0x6340…6360 20 54 68 69 73 20 6c 6f 6f 70 20 77 69 6c 6c 20 75 73 65 20 0a 6f 6e 65 20 77 6f 72 64 20 69 6e ┆ This loop will use one word in┆
0x6360…6380 20 74 68 65 20 52 41 4d 2d 6d 65 6d 6f 72 79 2e 20 54 68 69 73 20 77 6f 72 64 20 69 73 20 69 6e ┆ the RAM-memory. This word is in┆
0x6380…63a0 69 74 69 61 6c 69 7a 65 64 20 77 69 74 68 20 61 20 7a 65 72 6f 2c 20 0a 77 68 65 72 65 61 66 74 ┆itialized with a zero, whereaft┆
0x63a0…63c0 65 72 20 61 20 6f 6e 65 2d 62 69 74 20 69 73 20 73 68 69 66 74 65 64 20 66 72 6f 6d 20 74 68 65 ┆er a one-bit is shifted from the┆
0x63c0…63e0 20 4c 53 42 20 74 6f 77 61 72 64 73 20 74 68 65 20 4d 53 42 2e 20 46 6f 72 20 0a 65 76 65 72 79 ┆ LSB towards the MSB. For every┆
0x63e0…6400 20 73 68 69 66 74 2c 20 74 68 65 20 70 61 74 74 65 72 6e 20 69 73 20 72 65 61 64 20 61 6e 64 20 ┆ shift, the pattern is read and ┆
0x6400…6420 (50,) 63 68 65 63 6b 65 64 2e 20 53 68 6f 75 6c 64 20 69 74 20 6f 63 63 75 72 2c 20 0a 74 68 61 74 20 ┆checked. Should it occur, that ┆
0x6420…6440 74 68 65 20 70 61 74 74 65 72 6e 20 77 61 73 20 6e 6f 74 20 77 72 69 74 74 65 6e 2c 20 74 68 65 ┆the pattern was not written, the┆
0x6440…6460 20 70 72 6f 67 72 61 6d 20 77 69 6c 6c 20 6c 6f 6f 70 20 0a 63 6f 6e 74 69 6e 6f 75 73 6c 79 20 ┆ program will loop continously ┆
0x6460…6480 74 72 79 69 6e 67 20 74 6f 20 72 65 61 64 20 74 68 65 20 63 6f 72 72 65 63 74 20 70 61 74 74 65 ┆trying to read the correct patte┆
0x6480…64a0 72 6e 2e 20 54 68 69 73 20 6d 65 61 6e 73 2c 20 74 68 61 74 20 0a 69 66 20 74 68 65 20 62 75 73 ┆rn. This means, that if the bus┆
0x64a0…64c0 20 73 69 67 6e 61 6c 73 20 61 72 65 20 63 68 65 63 6b 65 64 20 62 79 20 61 6e 20 6f 73 63 69 6c ┆ signals are checked by an oscil┆
0x64c0…64e0 6c 6f 73 63 6f 70 65 20 61 6e 64 20 74 68 65 20 77 6f 72 64 20 0a 72 65 61 64 20 69 73 20 66 6f ┆loscope and the word read is fo┆
0x64e0…6500 75 6e 64 20 74 6f 20 68 61 76 65 20 74 68 65 20 62 69 74 73 20 30 20 61 6e 64 20 31 20 74 6f 20 ┆und to have the bits 0 and 1 to ┆
0x6500…6520 74 68 65 20 6f 6e 65 20 6c 65 76 65 6c 20 61 6e 64 20 74 68 65 20 0a 72 65 73 74 20 74 6f 20 74 ┆the one level and the rest to t┆
0x6520…6540 68 65 20 7a 65 72 6f 20 6c 65 76 65 6c 2c 20 69 74 20 6d 75 73 74 20 62 65 20 62 69 74 20 32 2c ┆he zero level, it must be bit 2,┆
0x6540…6560 20 74 68 61 74 20 63 6f 6e 74 61 69 6e 73 20 74 68 65 20 0a 65 72 72 6f 72 2e 0d 0a 0d 0a 57 68 ┆ that contains the error. Wh┆
0x6560…6580 65 6e 20 74 68 65 20 6f 6e 65 2d 62 69 74 20 68 61 73 20 62 65 65 6e 20 73 68 69 66 74 65 64 20 ┆en the one-bit has been shifted ┆
0x6580…65a0 74 68 72 6f 75 67 68 20 74 68 65 20 65 6e 74 69 72 65 20 77 6f 72 64 2c 20 74 68 69 73 20 0a 77 ┆through the entire word, this w┆
0x65a0…65c0 6f 72 64 20 69 73 20 72 65 69 6e 69 74 69 61 6c 69 7a 65 64 20 74 6f 20 61 6c 6c 20 6f 6e 65 73 ┆ord is reinitialized to all ones┆
0x65c0…65e0 20 61 6e 64 20 61 20 7a 65 72 6f 2d 62 69 74 20 69 73 20 73 68 69 66 74 65 64 20 0a 74 68 72 6f ┆ and a zero-bit is shifted thro┆
0x65e0…6600 75 67 68 20 69 74 2e 0d 0a 0d 0a 8c 83 e0 0a 49 66 20 74 68 65 20 38 32 35 35 20 50 41 33 20 62 ┆ugh it. If the 8255 PA3 b┆
0x6600…6620 (51,) 69 74 20 69 73 20 73 74 72 61 70 70 65 64 20 74 6f 20 22 30 22 2c 20 74 68 65 73 65 20 6d 65 61 ┆it is strapped to "0", these mea┆
0x6620…6640 73 75 72 65 6d 65 6e 74 20 6c 6f 6f 70 73 20 0a 61 72 65 20 62 79 70 61 73 73 65 64 20 77 68 65 ┆surement loops are bypassed whe┆
0x6640…6650 6e 20 70 6f 77 65 72 69 6e 67 20 75 70 2e 0d 0a ┆n powering up. ┆
0x6650…6653 FormFeed {
0x6650…6653 0c 80 98 ┆ ┆
0x6650…6653 }
0x6653…6660 0a a1 b0 36 2e 20 41 75 74 6f 6d 61 74 ┆ 6. Automat┆
0x6660…6680 69 63 20 42 61 75 64 20 52 61 74 65 20 44 65 74 65 72 6d 69 6e 61 74 69 6f 6e 2e 0d 0a 0d 0a 0d ┆ic Baud Rate Determination. ┆
0x6680…66a0 0a 41 66 74 65 72 20 70 6f 77 65 72 20 6f 6e 20 6f 72 20 65 78 74 65 72 6e 61 6c 20 72 65 73 65 ┆ After power on or external rese┆
0x66a0…66c0 74 20 74 68 65 20 73 65 6c 66 74 65 73 74 20 64 65 74 65 72 6d 69 6e 65 73 20 77 68 65 74 68 65 ┆t the selftest determines whethe┆
0x66c0…66e0 72 20 0a 61 20 63 6f 6e 73 6f 6c 65 20 69 73 20 70 72 65 73 65 6e 74 20 6f 72 20 6e 6f 74 20 62 ┆r a console is present or not b┆
0x66e0…6700 79 20 73 61 6d 70 6c 69 6e 67 20 74 68 65 20 44 53 52 20 73 69 67 6e 61 6c 2e 0d 0a 0d 0a 49 66 ┆y sampling the DSR signal. If┆
0x6700…6720 20 61 20 63 6f 6e 73 6f 6c 65 20 69 73 20 70 72 65 73 65 6e 74 20 74 68 65 6e 20 74 68 65 20 73 ┆ a console is present then the s┆
0x6720…6740 65 6c 66 74 65 73 74 20 65 6e 74 65 72 73 20 74 68 65 20 41 75 74 6f 6d 61 74 69 63 20 0a 42 61 ┆elftest enters the Automatic Ba┆
0x6740…6760 75 64 20 52 61 74 65 20 64 65 74 65 72 6d 69 6e 61 74 69 6f 6e 20 70 68 61 73 65 2c 20 6f 74 68 ┆ud Rate determination phase, oth┆
0x6760…6780 65 72 77 69 73 65 20 74 68 65 20 62 61 75 64 20 72 61 74 65 20 69 73 20 73 65 74 20 74 6f 20 0a ┆erwise the baud rate is set to ┆
0x6780…67a0 39 36 30 30 20 42 61 75 64 20 61 6e 64 20 74 68 65 20 73 65 6c 66 74 65 73 74 20 70 72 6f 63 65 ┆9600 Baud and the selftest proce┆
0x67a0…67c0 65 64 73 2e 0d 0a 0d 0a 49 6e 20 74 68 65 20 41 75 74 6f 6d 61 74 69 63 20 42 61 75 64 20 52 61 ┆eds. In the Automatic Baud Ra┆
0x67c0…67e0 74 65 20 44 65 74 65 72 6d 69 6e 61 74 69 6f 6e 20 70 68 61 73 65 20 74 68 65 20 74 65 73 74 20 ┆te Determination phase the test ┆
0x67e0…6800 70 72 6f 67 72 61 6d 20 0a 69 6e 69 74 69 61 6c 69 7a 65 73 20 74 68 65 20 63 6f 6e 73 6f 6c 65 ┆program initializes the console┆
0x6800…6820 (52,) 20 74 6f 20 39 36 30 30 20 42 61 75 64 2c 20 61 6e 64 20 73 74 61 72 74 73 20 74 6f 20 77 72 69 ┆ to 9600 Baud, and starts to wri┆
0x6820…6840 74 65 20 2a 20 0a 28 73 74 61 72 73 29 20 74 6f 20 74 68 65 20 63 6f 6e 73 6f 6c 65 2e 20 4e 6f ┆te * (stars) to the console. No┆
0x6840…6860 74 65 20 74 68 61 74 20 74 68 65 20 61 70 70 65 61 72 61 6e 63 65 20 6f 6e 20 74 68 65 20 6f 70 ┆te that the appearance on the op┆
0x6860…6880 65 72 61 74 6f 72 20 0a 63 6f 6e 73 6f 6c 65 20 6d 61 79 20 6e 6f 74 20 62 65 20 73 74 61 72 73 ┆erator console may not be stars┆
0x6880…68a0 2c 20 77 6f 72 73 74 20 63 61 73 65 20 6e 6f 74 68 69 6e 67 20 69 73 20 73 65 65 6e 20 61 74 20 ┆, worst case nothing is seen at ┆
0x68a0…68c0 61 6c 6c 2e 20 54 68 65 20 0a 73 65 6c 66 74 65 73 74 20 77 61 69 74 73 20 66 6f 72 20 74 68 65 ┆all. The selftest waits for the┆
0x68c0…68e0 20 6f 70 65 72 61 74 6f 72 20 74 6f 20 74 79 70 65 20 6f 6e 65 20 6f 72 20 74 77 6f 20 75 70 70 ┆ operator to type one or two upp┆
0x68e0…6900 65 72 20 63 61 73 65 20 55 2c 20 0a 74 68 69 73 20 77 69 6c 6c 20 61 6c 6c 6f 77 20 74 68 65 20 ┆er case U, this will allow the ┆
0x6900…6920 73 65 6c 66 74 65 73 74 20 74 6f 20 64 65 74 65 72 6d 69 6e 65 20 74 68 65 20 62 61 75 64 20 72 ┆selftest to determine the baud r┆
0x6920…6940 61 74 65 20 6f 66 20 74 68 65 20 0a 61 74 74 61 63 68 65 64 20 63 6f 6e 73 6f 6c 65 2e 20 41 66 ┆ate of the attached console. Af┆
0x6940…6960 74 65 72 20 74 68 65 20 64 65 74 65 72 6d 69 6e 61 74 69 6f 6e 20 6f 66 20 74 68 65 20 62 61 75 ┆ter the determination of the bau┆
0x6960…6980 64 20 72 61 74 65 20 74 68 65 20 0a 74 65 73 74 20 70 72 6f 63 65 65 64 73 2e 20 42 61 75 64 20 ┆d rate the test proceeds. Baud ┆
0x6980…69a0 72 61 74 65 20 72 65 63 6f 67 6e 69 7a 65 64 20 61 72 65 20 33 30 30 2c 20 36 30 30 2c 20 31 32 ┆rate recognized are 300, 600, 12┆
0x69a0…69c0 30 30 2c 20 32 34 30 30 2c 20 0a 34 38 30 30 20 61 6e 64 20 39 36 30 30 20 42 61 75 64 2e 0d 0a ┆00, 2400, 4800 and 9600 Baud. ┆
0x69c0…69c3 FormFeed {
0x69c0…69c3 0c 81 e4 ┆ ┆
0x69c0…69c3 }
0x69c3…69e0 0a b0 a1 37 2e 20 54 68 65 20 53 65 6c 66 74 65 73 74 20 53 6e 6f 6f 70 65 72 2e 0d 0a ┆ 7. The Selftest Snooper. ┆
0x69e0…6a00 0d 0a 0d 0a 54 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 69 73 20 65 ┆ The ETC601 SBC Selftest is e┆
0x6a00…6a20 (53,) 71 75 69 70 70 65 64 20 77 69 74 68 20 61 20 73 6f 63 61 6c 6c 65 64 20 53 6e 6f 6f 70 65 72 20 ┆quipped with a socalled Snooper ┆
0x6a20…6a40 0a 66 61 63 69 6c 69 74 79 2c 20 77 68 69 63 68 20 65 6e 61 62 6c 65 73 20 74 68 65 20 75 73 65 ┆ facility, which enables the use┆
0x6a40…6a60 72 20 74 6f 20 6d 61 6e 69 70 75 6c 61 74 65 20 77 69 74 68 20 52 41 4d 20 64 61 74 61 20 61 6e ┆r to manipulate with RAM data an┆
0x6a60…6a80 64 20 0a 69 6e 70 75 74 2c 20 6f 75 74 70 75 74 20 70 6f 72 74 73 2e 20 49 74 20 69 73 20 65 6e ┆d input, output ports. It is en┆
0x6a80…6aa0 76 6f 6b 65 64 20 62 79 20 65 6e 74 65 72 69 6e 67 20 61 66 20 3c 63 6e 74 72 6c 3e 3c 40 3e 20 ┆voked by entering af <cntrl><@> ┆
0x6aa0…6ac0 6f 6e 20 0a 74 68 65 20 63 6f 6e 6e 65 63 74 65 64 20 63 6f 6e 73 6f 6c 65 2e 0d 0a 0d 0a 54 68 ┆on the connected console. Th┆
0x6ac0…6ae0 65 20 53 6e 6f 6f 70 65 72 20 63 61 6e 20 62 65 20 65 6e 74 65 72 65 64 20 61 74 20 74 68 65 20 ┆e Snooper can be entered at the ┆
0x6ae0…6b00 74 65 72 6d 69 6e 61 74 69 6f 6e 20 6f 66 20 61 6e 79 20 6f 66 20 74 68 65 20 74 65 73 74 20 0a ┆termination of any of the test ┆
0x6b00…6b20 70 72 6f 67 72 61 6d 73 2e 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 53 6e 6f 6f 70 65 72 20 69 73 ┆programs. When the Snooper is┆
0x6b20…6b40 20 65 6e 74 65 72 65 64 2c 20 69 74 20 77 69 6c 6c 20 72 65 73 70 6f 6e 64 20 77 69 74 68 20 74 ┆ entered, it will respond with t┆
0x6b40…6b60 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 0a 6d 65 6e 75 3a 0d 0a 0d 0a 3e 3e 20 53 6e 6f 6f 70 65 ┆he following menu: >> Snoope┆
0x6b60…6b80 72 0d 0a 0d 0a 3c 52 3e 20 3a 20 64 69 73 70 6c 61 79 20 6d 65 6d 6f 72 79 0d 0a 3c 53 3e 20 3a ┆r <R> : display memory <S> :┆
0x6b80…6ba0 20 73 75 62 73 74 69 74 75 74 65 20 77 6f 72 64 0d 0a 3c 49 3e 20 3a 20 69 6e 70 75 74 20 66 72 ┆ substitute word <I> : input fr┆
0x6ba0…6bc0 6f 6d 20 70 6f 72 74 0d 0a 3c 4f 3e 20 3a 20 6f 75 74 70 75 74 20 74 6f 20 70 6f 72 74 0d 0a 3c ┆om port <O> : output to port <┆
0x6bc0…6be0 2c 3e 20 3a 20 63 6f 6e 74 69 6e 75 65 20 73 65 6c 65 63 74 65 64 0d 0a 3c 58 3e 20 3a 20 65 78 ┆,> : continue selected <X> : ex┆
0x6be0…6c00 69 74 20 66 72 6f 6d 20 73 6e 6f 6f 70 65 72 0d 0a 0d 0a 2a 2a 2a 20 4e 6f 74 65 3a 20 84 74 68 ┆it from snooper *** Note: th┆
0x6c00…6c20 (54,) 61 74 20 63 61 6e 67 69 6e 67 20 74 68 65 20 63 6f 6e 74 65 6e 74 20 6f 66 20 52 41 4d 20 6d 65 ┆at canging the content of RAM me┆
0x6c20…6c40 6d 6f 72 79 20 77 6f 72 64 73 20 6f 72 20 0a 19 8a 80 80 70 65 72 66 6f 72 6d 69 6e 67 20 6f 75 ┆mory words or performing ou┆
0x6c40…6c60 74 70 75 74 20 74 6f 20 64 65 76 69 63 65 73 20 6d 61 79 20 68 61 76 65 20 73 6f 6d 20 64 72 61 ┆tput to devices may have som dra┆
0x6c60…6c80 73 74 69 63 20 0a 19 8a 80 80 65 66 66 65 63 74 20 74 6f 20 74 68 65 20 53 65 6c 66 74 65 73 74 ┆stic effect to the Selftest┆
0x6c80…6ca0 20 73 79 73 74 65 6d 2e 0d 0a 0d 0a 57 68 65 6e 20 65 6e 74 65 72 69 6e 67 20 74 68 65 20 63 68 ┆ system. When entering the ch┆
0x6ca0…6cc0 61 72 61 63 74 65 72 20 22 58 22 20 6f 6e 20 74 68 65 20 63 6f 6e 6e 65 63 74 65 64 20 63 6f 6e ┆aracter "X" on the connected con┆
0x6cc0…6ce0 73 6f 6c 65 2c 20 74 68 65 20 0a 53 6e 6f 6f 70 65 72 20 77 69 6c 6c 20 72 65 74 75 72 6e 20 63 ┆sole, the Snooper will return c┆
0x6ce0…6d00 6f 6e 74 72 6f 6c 20 74 6f 20 74 68 65 20 53 65 6c 66 74 65 73 74 2c 20 77 68 69 63 68 20 77 69 ┆ontrol to the Selftest, which wi┆
0x6d00…6d20 6c 6c 20 70 72 6f 63 65 65 64 20 0a 69 74 73 20 6f 70 65 72 61 74 69 6f 6e 2e 0d 0a 0d 0a 54 68 ┆ll proceed its operation. Th┆
0x6d20…6d40 65 20 53 6e 6f 6f 70 65 72 20 77 6f 72 6b 73 20 69 6e 20 61 6e 20 69 6e 74 65 72 72 75 70 74 20 ┆e Snooper works in an interrupt ┆
0x6d40…6d54 64 69 73 61 62 6c 65 64 20 6d 6f 64 65 2e 0d 0a 0d 0a 0d 0a ┆disabled mode. ┆
0x6d54…6d57 FormFeed {
0x6d54…6d57 0c 83 98 ┆ ┆
0x6d54…6d57 }
0x6d57…6d60 0a b0 a1 f0 37 2e 31 20 50 ┆ 7.1 P┆
0x6d60…6d80 72 65 73 73 20 3c 52 3e 2e 0d 0a 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 63 68 61 72 61 63 74 65 ┆ress <R>. When the characte┆
0x6d80…6da0 72 20 22 52 22 20 68 61 73 20 62 65 65 6e 20 73 65 6c 65 63 74 65 64 2c 20 74 68 65 20 66 6f 6c ┆r "R" has been selected, the fol┆
0x6da0…6dc0 6c 6f 77 69 6e 67 20 74 77 6f 20 0a 71 75 65 73 74 69 6f 6e 73 20 63 6f 6e 63 65 72 6e 69 6e 67 ┆lowing two questions concerning┆
0x6dc0…6de0 20 74 68 65 20 61 64 64 72 65 73 73 20 77 69 6c 6c 20 62 65 20 61 73 6b 65 64 3a 0d 0a 0d 0a 53 ┆ the address will be asked: S┆
0x6de0…6e00 65 67 6d 2e 3a 20 5f 20 5f 20 5f 20 5f 20 41 64 64 72 2e 3a 20 5f 20 5f 20 5f 20 5f 0d 0a 0d 0a ┆egm.: _ _ _ _ Addr.: _ _ _ _ ┆
0x6e00…6e20 (55,) 54 68 65 73 65 20 71 75 65 73 74 69 6f 6e 73 20 6d 75 73 74 20 62 65 20 61 6e 73 77 65 72 65 64 ┆These questions must be answered┆
0x6e20…6e40 20 77 69 74 68 20 74 68 65 20 61 64 64 72 65 73 73 20 6f 66 20 74 68 65 20 66 69 72 73 74 20 0a ┆ with the address of the first ┆
0x6e40…6e60 6d 65 6d 6f 72 79 20 77 6f 72 64 20 74 6f 20 62 65 20 64 69 73 70 6c 61 79 65 64 2e 0d 0a 0d 0a ┆memory word to be displayed. ┆
0x6e60…6e80 57 68 65 6e 20 74 68 65 20 61 64 64 72 65 73 73 20 68 61 73 20 62 65 65 6e 20 73 65 6c 65 63 74 ┆When the address has been select┆
0x6e80…6ea0 65 64 2c 20 31 30 30 20 2d 20 31 36 20 62 69 74 20 77 6f 72 64 73 20 77 69 6c 6c 20 62 65 20 0a ┆ed, 100 - 16 bit words will be ┆
0x6ea0…6ec0 73 68 6f 77 6e 20 6f 6e 20 74 68 65 20 64 69 73 70 6c 61 79 20 6f 66 20 74 68 65 20 63 6f 6e 6e ┆shown on the display of the conn┆
0x6ec0…6ee0 65 63 74 65 64 20 63 6f 6e 73 6f 6c 65 2e 20 54 68 65 20 66 6f 72 6d 61 74 20 6f 66 20 74 68 65 ┆ected console. The format of the┆
0x6ee0…6f00 20 0a 6f 75 74 70 75 74 20 69 73 20 32 30 20 6c 69 6e 65 73 20 65 61 63 68 20 77 69 74 68 20 74 ┆ output is 20 lines each with t┆
0x6f00…6f20 68 65 20 63 6f 6e 74 65 6e 74 20 6f 66 20 35 20 77 6f 72 64 73 2e 20 49 74 20 69 73 20 73 68 6f ┆he content of 5 words. It is sho┆
0x6f20…6f40 77 6e 20 0a 69 6e 20 68 65 78 61 64 65 63 69 6d 61 6c 20 61 6e 64 20 69 6e 20 61 73 63 69 69 2e ┆wn in hexadecimal and in ascii.┆
0x6f40…6f60 0d 0a 0d 0a 54 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 31 30 30 20 77 6f 72 64 73 20 77 69 6c 6c ┆ The following 100 words will┆
0x6f60…6f80 20 62 65 20 64 69 73 70 6c 61 79 65 64 20 69 66 20 61 20 22 2c 22 20 69 73 20 65 6e 74 65 72 65 ┆ be displayed if a "," is entere┆
0x6f80…6fa0 64 2e 0d 0a 0d 0a 41 20 6e 65 77 20 66 69 72 73 74 20 61 64 64 72 65 73 73 20 63 61 6e 20 62 65 ┆d. A new first address can be┆
0x6fa0…6fc0 20 73 65 6c 65 63 74 65 64 20 62 79 20 72 65 65 6e 74 65 72 69 6e 67 20 74 68 65 20 63 68 61 72 ┆ selected by reentering the char┆
0x6fc0…6fe0 61 63 74 65 72 20 0a 22 52 22 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 37 2e 32 20 50 72 65 73 73 20 3c 53 ┆acter "R". 7.2 Press <S┆
0x6fe0…7000 3e 2e 0d 0a 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 63 68 61 72 61 63 74 65 72 20 22 53 22 20 68 ┆>. When the character "S" h┆
0x7000…7020 (56,) 61 73 20 62 65 65 6e 20 73 65 6c 65 63 74 65 64 2c 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 ┆as been selected, the following ┆
0x7020…7040 74 77 6f 20 0a 71 75 65 73 74 69 6f 6e 73 20 63 6f 6e 63 65 72 6e 69 6e 67 20 74 68 65 20 61 64 ┆two questions concerning the ad┆
0x7040…7060 64 72 65 73 73 20 77 69 6c 6c 20 62 65 20 61 73 6b 65 64 3a 0d 0a 0d 0a 53 65 67 6d 2e 3a 20 5f ┆dress will be asked: Segm.: _┆
0x7060…7080 20 5f 20 5f 20 5f 20 41 64 64 72 2e 3a 20 5f 20 5f 20 5f 20 5f 0d 0a 0d 0a 54 68 65 73 65 20 71 ┆ _ _ _ Addr.: _ _ _ _ These q┆
0x7080…70a0 75 65 73 74 69 6f 6e 73 20 6d 75 73 74 20 62 65 20 61 6e 73 77 65 72 65 64 20 77 69 74 68 20 74 ┆uestions must be answered with t┆
0x70a0…70c0 68 65 20 61 64 64 72 65 73 73 20 6f 66 20 74 68 65 20 66 69 72 73 74 20 0a 77 6f 72 64 20 74 6f ┆he address of the first word to┆
0x70c0…70e0 20 62 65 20 63 68 61 6e 67 65 64 2e 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 61 64 64 72 65 73 73 ┆ be changed. When the address┆
0x70e0…7100 20 68 61 73 20 62 65 65 6e 20 73 65 6c 65 63 74 65 64 2c 20 74 68 65 20 66 69 72 73 74 20 77 6f ┆ has been selected, the first wo┆
0x7100…7120 72 64 20 69 73 20 64 69 73 70 6c 61 79 65 64 2e 0a 4e 6f 77 20 74 68 65 72 65 20 61 72 65 20 74 ┆rd is displayed. Now there are t┆
0x7120…7140 77 6f 20 70 6f 73 73 69 62 69 6c 69 74 69 65 73 2c 20 65 69 74 68 65 72 20 74 6f 20 66 69 6c 6c ┆wo possibilities, either to fill┆
0x7140…7160 20 69 6e 20 61 20 6e 65 77 20 76 61 6c 75 65 20 6f 72 0a 74 6f 20 70 72 65 73 73 20 22 2c 22 2e ┆ in a new value or to press ",".┆
0x7160…7180 0d 0a 0d 0a 41 20 6e 65 77 20 76 61 6c 75 65 20 6d 61 79 20 63 6f 6e 73 69 73 74 20 6f 66 20 66 ┆ A new value may consist of f┆
0x7180…71a0 72 6f 6d 20 6f 6e 65 20 75 70 20 74 6f 20 66 6f 75 72 20 64 69 67 69 74 73 2e 20 49 66 20 6c 65 ┆rom one up to four digits. If le┆
0x71a0…71c0 73 73 0a 74 68 61 6e 20 66 6f 75 72 20 64 69 67 69 74 73 20 69 73 20 69 6e 70 75 74 2c 20 74 68 ┆ss than four digits is input, th┆
0x71c0…71e0 65 20 6e 75 6d 62 65 72 20 77 69 6c 6c 20 62 65 20 65 6e 74 65 72 65 64 20 62 79 20 70 72 65 73 ┆e number will be entered by pres┆
0x71e0…7200 73 69 6e 67 0a 22 72 65 74 75 72 6e 22 2e 0d 0a 0d 0a 8c 83 ec 0a 57 68 65 6e 20 61 20 6e 65 77 ┆sing "return". When a new┆
0x7200…7220 (57,) 20 76 61 6c 75 65 20 68 61 73 20 62 65 65 6e 20 65 6e 74 65 72 65 64 2c 20 74 68 65 20 76 61 6c ┆ value has been entered, the val┆
0x7220…7240 75 65 20 6f 66 20 74 68 65 20 6e 65 78 74 20 77 6f 72 64 20 69 73 20 0a 73 68 6f 77 6e 2e 0d 0a ┆ue of the next word is shown. ┆
0x7240…7260 b0 a1 0d 0a 49 66 20 74 68 65 20 63 68 61 72 61 63 74 65 72 20 22 2c 22 20 69 73 20 65 6e 74 65 ┆ If the character "," is ente┆
0x7260…7280 72 65 64 2c 20 74 68 65 20 6d 65 6d 6f 72 79 20 77 6f 72 64 20 64 69 73 70 6c 61 79 65 64 20 69 ┆red, the memory word displayed i┆
0x7280…72a0 73 20 0a 6c 65 66 74 20 75 6e 63 68 61 6e 67 65 64 2c 20 61 6e 64 20 74 68 65 20 6e 65 78 74 20 ┆s left unchanged, and the next ┆
0x72a0…72c0 77 6f 72 64 20 69 73 20 64 69 73 70 6c 61 79 65 64 2e 0d 0a 0d 0a 54 68 65 20 77 61 79 20 74 6f ┆word is displayed. The way to┆
0x72c0…72e0 20 65 73 63 61 70 65 20 74 68 65 20 73 75 62 73 74 69 74 75 74 65 20 73 65 73 73 69 6f 6e 2c 20 ┆ escape the substitute session, ┆
0x72e0…7300 69 73 20 74 6f 20 73 65 6c 65 63 74 20 61 20 6e 65 77 20 0a 66 75 6e 63 74 69 6f 6e 20 6f 72 20 ┆is to select a new function or ┆
0x7300…7320 74 6f 20 65 78 69 74 20 74 68 65 20 73 6e 6f 6f 70 65 72 2e 0d 0a 0d 0a 49 74 20 69 73 20 70 6f ┆to exit the snooper. It is po┆
0x7320…7340 73 73 69 62 6c 65 20 74 6f 20 66 69 6c 6c 20 61 6e 20 61 6d 6f 75 6e 74 20 6f 66 20 69 2e 65 2e ┆ssible to fill an amount of i.e.┆
0x7340…7360 20 74 68 65 20 44 4d 41 2d 74 72 61 6e 73 6d 69 74 20 62 75 66 66 65 72 20 0a 77 69 74 68 20 61 ┆ the DMA-transmit buffer with a┆
0x7360…7380 20 63 65 72 74 61 69 6e 20 64 61 74 61 20 70 61 74 74 65 72 6e 20 62 79 20 70 72 65 73 73 69 6e ┆ certain data pattern by pressin┆
0x7380…73a0 67 20 72 65 70 65 61 74 20 61 6e 64 20 74 68 65 20 64 61 74 61 20 28 65 2e 67 2e 20 0a 30 2d 46 ┆g repeat and the data (e.g. 0-F┆
0x73a0…73c0 29 2e 20 54 68 69 73 20 69 73 20 64 75 65 20 74 6f 20 74 68 65 20 66 61 63 74 20 74 68 61 74 20 ┆). This is due to the fact that ┆
0x73c0…73e0 65 6e 74 65 72 69 6e 67 20 34 20 64 69 67 69 74 73 2c 20 77 69 6c 6c 20 0a 61 75 74 6f 6d 61 74 ┆entering 4 digits, will automat┆
0x73e0…7400 69 63 61 6c 6c 79 20 65 6e 74 65 72 20 74 68 65 73 65 20 64 61 74 61 20 69 6e 74 6f 20 74 68 65 ┆ically enter these data into the┆
0x7400…7420 (58,) 20 77 6f 72 64 20 61 6e 64 20 63 6f 6e 74 69 6e 75 65 20 77 69 74 68 20 0a 74 68 65 20 6e 65 78 ┆ word and continue with the nex┆
0x7420…7440 74 20 77 6f 72 64 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 37 2e 33 20 50 72 65 73 73 20 3c 49 3e 2e 0d 0a ┆t word. 7.3 Press <I>. ┆
0x7440…7460 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 63 68 61 72 61 63 74 65 72 20 22 49 22 20 68 61 73 20 62 ┆ When the character "I" has b┆
0x7460…7480 65 65 6e 20 73 65 6c 65 63 74 65 64 20 74 68 65 20 53 6e 6f 6f 70 65 72 20 77 69 6c 6c 20 72 65 ┆een selected the Snooper will re┆
0x7480…74a0 73 70 6f 6e 64 20 0a 77 69 74 68 20 74 68 65 20 71 75 65 73 74 69 6f 6e 3a 0d 0a 0d 0a 70 6f 72 ┆spond with the question: por┆
0x74a0…74c0 74 3a 20 5f 20 5f 20 5f 20 5f 0d 0a 0d 0a 57 68 65 6e 20 61 20 70 6f 72 74 20 6e 75 6d 62 65 72 ┆t: _ _ _ _ When a port number┆
0x74c0…74e0 20 68 61 73 20 62 65 65 6e 20 65 6e 74 65 72 65 64 2c 20 74 68 65 20 31 36 20 62 69 74 20 77 6f ┆ has been entered, the 16 bit wo┆
0x74e0…7500 72 64 20 63 6f 6e 74 61 69 6e 65 64 20 69 6e 20 0a 74 68 69 73 20 70 6f 72 74 20 69 73 20 73 68 ┆rd contained in this port is sh┆
0x7500…7520 6f 77 6e 2e 20 49 66 20 74 68 65 20 70 6f 72 74 20 69 73 20 61 6e 20 38 20 62 69 74 20 74 79 70 ┆own. If the port is an 8 bit typ┆
0x7520…7540 65 2c 20 69 74 20 69 73 20 74 68 65 20 38 20 0a 4c 53 42 2c 20 74 68 61 74 20 69 73 20 73 69 67 ┆e, it is the 8 LSB, that is sig┆
0x7540…7560 6e 69 66 69 63 61 6e 74 2e 0d 0a 0d 0a 0d 0a b0 a1 b0 f0 37 2e 34 20 50 72 65 73 73 20 3c 4f 3e ┆nificant. 7.4 Press <O>┆
0x7560…7580 2e 0d 0a 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 63 68 61 72 61 63 74 65 72 20 22 4f 22 20 68 61 ┆. When the character "O" ha┆
0x7580…75a0 73 20 62 65 65 6e 20 73 65 6c 65 63 74 65 64 20 74 68 65 20 53 6e 6f 6f 70 65 72 20 77 69 6c 6c ┆s been selected the Snooper will┆
0x75a0…75c0 20 72 65 73 70 6f 6e 64 20 0a 77 69 74 68 20 74 68 65 20 71 75 65 73 74 69 6f 6e 3a 0d 0a 0d 0a ┆ respond with the question: ┆
0x75c0…75d1 70 6f 72 74 3a 20 5f 20 5f 20 5f 20 5f 0d 0a 0d 0a ┆port: _ _ _ _ ┆
0x75d1…75d4 FormFeed {
0x75d1…75d4 0c 83 bc ┆ ┆
0x75d1…75d4 }
0x75d4…75e0 0a 57 68 65 6e 20 61 20 70 6f 72 74 ┆ When a port┆
0x75e0…7600 20 6e 75 6d 62 65 72 20 68 61 73 20 62 65 65 6e 20 65 6e 74 65 72 65 64 2c 20 74 68 65 20 31 36 ┆ number has been entered, the 16┆
0x7600…7620 (59,) 20 62 69 74 20 77 6f 72 64 20 74 6f 20 62 65 20 73 65 6e 64 2c 20 0a 6d 75 73 74 20 62 65 20 65 ┆ bit word to be send, must be e┆
0x7620…7640 6e 74 65 72 65 64 2e 20 49 66 20 74 68 65 20 70 6f 72 74 20 69 73 20 61 6e 20 38 20 62 69 74 20 ┆ntered. If the port is an 8 bit ┆
0x7640…7660 74 79 70 65 2c 20 69 74 20 69 73 20 74 68 65 20 38 20 4c 53 42 2c 20 0a 74 68 61 74 20 69 73 20 ┆type, it is the 8 LSB, that is ┆
0x7660…766e 73 69 67 6e 69 66 69 63 61 6e 74 2e 0d 0a ┆significant. ┆
0x766e…7671 FormFeed {
0x766e…7671 0c 80 a4 ┆ ┆
0x766e…7671 }
0x7671…7680 0a b0 a1 38 2e 20 54 65 73 74 20 30 20 3d 20 ┆ 8. Test 0 = ┆
0x7680…76a0 4d 65 6d 6f 72 79 20 54 65 73 74 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 ┆Memory Test. The memory tes┆
0x76a0…76c0 74 20 6f 66 20 74 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 63 6f 6e ┆t of the ETC601 SBC Selftest con┆
0x76c0…76e0 73 69 73 74 73 20 6f 66 20 74 77 6f 20 0a 70 61 72 74 73 2c 20 61 20 50 52 4f 4d 20 63 68 65 63 ┆sists of two parts, a PROM chec┆
0x76e0…7700 6b 73 75 6d 20 74 65 73 74 20 61 6e 64 20 61 20 52 41 4d 20 6d 65 6d 6f 72 79 20 74 65 73 74 2e ┆ksum test and a RAM memory test.┆
0x7700…7720 20 54 68 65 20 50 52 4f 4d 20 0a 63 68 65 63 6b 73 75 6d 20 74 65 73 74 20 69 73 20 6f 6e 6c 79 ┆ The PROM checksum test is only┆
0x7720…7740 20 72 75 6e 20 6f 6e 63 65 20 61 74 20 70 6f 77 65 72 20 75 70 2c 20 77 68 65 72 65 61 73 20 74 ┆ run once at power up, whereas t┆
0x7740…7760 68 65 20 52 41 4d 20 0a 6d 65 6d 6f 72 79 20 74 65 73 74 20 6d 61 79 20 62 65 20 72 75 6e 20 73 ┆he RAM memory test may be run s┆
0x7760…7780 65 76 65 72 61 6c 20 74 69 6d 65 73 2c 20 69 66 20 72 65 71 75 65 73 74 65 64 20 62 79 20 74 68 ┆everal times, if requested by th┆
0x7780…77a0 65 20 0a 6f 70 65 72 61 74 6f 72 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 38 2e 31 20 50 52 4f 4d 20 43 68 ┆e operator. 8.1 PROM Ch┆
0x77a0…77c0 65 63 6b 73 75 6d 20 54 65 73 74 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 63 6f 6e 74 65 6e 74 20 6f 66 ┆ecksum Test. The content of┆
0x77c0…77e0 20 74 68 65 20 74 77 6f 20 50 52 4f 4d 27 73 2c 20 6c 6f 63 61 74 65 64 20 69 6e 20 55 33 34 20 ┆ the two PROM's, located in U34 ┆
0x77e0…7800 61 6e 64 20 55 33 35 2c 20 61 72 65 20 0a 73 75 6d 6d 61 72 69 78 65 64 20 69 6e 64 65 70 65 6e ┆and U35, are summarixed indepen┆
0x7800…7820 (60,) 64 65 6e 74 6c 79 20 6f 66 20 65 61 63 68 20 6f 74 68 65 72 2e 20 54 68 65 20 73 75 6d 6d 61 74 ┆dently of each other. The summat┆
0x7820…7840 69 6f 6e 20 66 6f 72 20 65 61 63 68 20 0a 50 52 4f 4d 20 6d 75 73 74 20 72 65 73 75 6c 74 20 69 ┆ion for each PROM must result i┆
0x7840…7860 6e 20 61 20 7a 65 72 6f 2e 20 46 6f 72 20 74 68 61 74 20 72 65 61 73 6f 6e 20 65 61 63 68 20 6f ┆n a zero. For that reason each o┆
0x7860…7880 66 20 74 68 65 20 50 52 4f 4d 27 73 20 0a 63 6f 6e 74 61 69 6e 73 20 61 20 63 6f 6d 70 65 6e 73 ┆f the PROM's contains a compens┆
0x7880…78a0 61 74 69 6f 6e 20 62 79 74 65 2e 0d 0a 0d 0a 55 33 34 20 63 6f 6e 74 61 69 6e 73 20 61 6c 6c 20 ┆ation byte. U34 contains all ┆
0x78a0…78c0 74 68 65 20 65 76 65 6e 20 62 79 74 65 73 20 61 6e 64 20 55 33 35 20 61 6c 6c 20 74 68 65 20 6f ┆the even bytes and U35 all the o┆
0x78c0…78e0 64 64 20 62 79 74 65 73 2e 0d 0a 0d 0a 49 66 20 74 68 65 20 73 75 6d 6d 61 74 69 6f 6e 20 69 73 ┆dd bytes. If the summation is┆
0x78e0…7900 20 64 69 66 66 65 72 65 6e 74 20 66 72 6f 6d 20 7a 65 72 6f 20 74 68 65 20 66 6f 6c 6c 6f 77 69 ┆ different from zero the followi┆
0x7900…7920 6e 67 20 65 72 72 6f 72 2d 0a 6d 65 73 73 61 67 65 20 77 69 6c 6c 20 62 65 20 6f 75 74 70 75 74 ┆ng error- message will be output┆
0x7920…7940 20 74 6f 20 74 68 65 20 63 6f 6e 73 6f 6c 65 3a 0d 0a 0d 0a b0 63 68 65 63 6b 73 75 6d 3a 20 3c ┆ to the console: checksum: <┆
0x7940…7960 30 30 3e 3c 45 45 3e 20 65 72 72 6f 72 0d 0a 0d 0a 77 68 65 72 65 20 3c 30 30 3e 20 69 73 20 74 ┆00><EE> error where <00> is t┆
0x7960…7980 68 65 20 38 20 62 69 74 20 73 75 6d 20 6f 66 20 55 33 35 2c 20 61 6e 64 20 3c 45 45 3e 20 69 73 ┆he 8 bit sum of U35, and <EE> is┆
0x7980…79a0 20 74 68 65 20 38 20 62 69 74 20 73 75 6d 20 6f 66 20 0a 55 33 34 2e 0d 0a 0d 0a 54 68 69 73 20 ┆ the 8 bit sum of U34. This ┆
0x79a0…79c0 65 72 72 6f 72 20 6d 65 61 6e 73 20 74 68 61 74 20 74 68 65 20 63 6f 6e 74 65 6e 74 20 6f 66 20 ┆error means that the content of ┆
0x79c0…79e0 74 68 65 20 70 72 6f 67 72 61 6d 20 50 52 4f 4d 27 73 20 68 61 73 20 62 65 65 6e 20 0a 64 61 6d ┆the program PROM's has been dam┆
0x79e0…7a00 61 67 65 64 20 61 6e 64 20 74 68 61 74 20 74 68 65 20 50 52 4f 4d 27 73 20 6d 75 73 74 20 62 65 ┆aged and that the PROM's must be┆
0x7a00…7a20 (61,) 20 63 68 61 6e 67 65 64 2e 0d 0a 0d 0a 54 68 65 20 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 ┆ changed. The corresponding e┆
0x7a20…7a37 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 31 2e 0d 0a 0d 0a 0d 0a ┆rror number is 1. ┆
0x7a37…7a3a FormFeed {
0x7a37…7a3a 0c 83 98 ┆ ┆
0x7a37…7a3a }
0x7a3a…7a40 0a b0 a1 f0 38 2e ┆ 8.┆
0x7a40…7a60 32 20 52 41 4d 20 4d 65 6d 6f 72 79 20 54 65 73 74 2e 0d 0a 0d 0a 54 68 65 20 52 41 4d 20 6d 65 ┆2 RAM Memory Test. The RAM me┆
0x7a60…7a80 6d 6f 72 79 20 74 65 73 74 20 6f 66 20 74 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 ┆mory test of the ETC601 SBC Self┆
0x7a80…7aa0 74 65 73 74 20 76 65 72 69 66 69 65 73 20 74 68 65 20 0a 6f 6e 62 6f 61 72 64 20 6d 65 6d 6f 72 ┆test verifies the onboard memor┆
0x7aa0…7ac0 79 2e 0d 0a 0d 0a 54 68 65 20 52 41 4d 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 69 73 20 61 62 6c ┆y. The RAM memory test is abl┆
0x7ac0…7ae0 65 20 74 6f 20 74 65 73 74 20 6f 6e 62 6f 61 72 64 20 6d 65 6d 6f 72 79 20 6f 66 20 66 6f 75 72 ┆e to test onboard memory of four┆
0x7ae0…7b00 20 0a 64 69 66 66 65 72 65 6e 74 20 73 69 7a 65 73 2e 20 54 68 65 73 65 20 61 72 65 20 31 32 38 ┆ different sizes. These are 128┆
0x7b00…7b20 20 6b 2d 2c 20 32 35 36 20 6b 2d 2c 20 35 31 32 20 6b 2d 62 79 74 65 73 2c 20 6f 72 20 31 20 0a ┆ k-, 256 k-, 512 k-bytes, or 1 ┆
0x7b20…7b40 4d 62 79 74 65 73 2e 0d 0a 0d 0a 54 68 65 20 73 69 7a 65 20 6f 66 20 74 68 65 20 6d 65 6d 6f 72 ┆Mbytes. The size of the memor┆
0x7b40…7b60 79 20 69 73 20 63 6f 6e 66 69 67 75 72 61 74 65 64 20 69 6e 20 74 68 65 20 53 32 33 20 73 74 72 ┆y is configurated in the S23 str┆
0x7b60…7b80 61 70 2c 20 50 41 20 62 69 74 20 30 20 0a 61 6e 64 20 31 2c 20 73 65 65 20 63 68 61 70 74 65 72 ┆ap, PA bit 0 and 1, see chapter┆
0x7b80…7ba0 20 34 20 66 69 67 2e 20 38 2e 0d 0a 0d 0a 54 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 69 73 ┆ 4 fig. 8. The memory test is┆
0x7ba0…7bc0 20 61 20 72 65 67 69 73 74 65 72 20 62 61 73 65 64 20 74 65 73 74 20 6e 6f 74 20 75 73 69 6e 67 ┆ a register based test not using┆
0x7bc0…7be0 20 6d 65 6d 6f 72 79 20 0a 76 61 72 69 61 62 6c 65 73 20 61 74 20 61 6c 6c 2c 20 6e 65 69 74 68 ┆ memory variables at all, neith┆
0x7be0…7c00 65 72 20 66 6f 72 20 76 61 6c 75 65 73 20 6e 6f 72 20 73 74 61 63 6b 2e 20 49 74 20 69 73 20 74 ┆er for values nor stack. It is t┆
0x7c00…7c20 (62,) 65 73 74 69 6e 67 20 0a 65 76 65 72 79 20 73 69 6e 67 6c 65 20 62 79 74 65 20 6f 66 20 74 68 65 ┆esting every single byte of the┆
0x7c20…7c40 20 6f 6e 62 6f 61 72 64 20 6d 65 6d 6f 72 79 2e 0d 0a 0d 0a 54 68 69 73 20 66 61 63 74 20 6c 65 ┆ onboard memory. This fact le┆
0x7c40…7c60 61 76 65 73 20 6f 6e 6c 79 20 74 77 6f 20 72 65 67 69 73 74 65 72 73 20 66 6f 72 20 76 61 72 69 ┆aves only two registers for vari┆
0x7c60…7c80 61 62 6c 65 73 20 74 68 61 74 20 63 61 6e 20 0a 73 75 72 76 69 76 65 20 74 68 65 20 6d 65 6d 6f ┆ables that can survive the memo┆
0x7c80…7ca0 72 79 20 74 65 73 74 2c 20 61 20 70 61 73 73 2d 63 6f 75 6e 74 65 72 20 61 6e 64 20 74 68 65 20 ┆ry test, a pass-counter and the ┆
0x7ca0…7cc0 70 61 72 61 6d 65 74 65 72 20 77 6f 72 64 2e 20 0a 49 74 20 67 69 76 65 73 20 73 6f 6d 65 20 6f ┆parameter word. It gives some o┆
0x7cc0…7ce0 66 20 74 68 65 20 65 78 70 6c 61 6e 61 74 69 6f 6e 20 66 6f 72 20 74 68 65 20 73 69 6d 70 6c 65 ┆f the explanation for the simple┆
0x7ce0…7d00 20 73 74 72 75 63 74 75 72 65 20 6f 66 20 74 68 65 20 0a 73 65 6c 66 74 65 73 74 20 74 65 73 74 ┆ structure of the selftest test┆
0x7d00…7d20 61 64 6d 69 6e 69 73 74 72 61 74 6f 72 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 38 2e 32 2e 32 20 4d 65 6d ┆administrator. 8.2.2 Mem┆
0x7d20…7d40 6f 72 79 20 54 65 73 74 20 50 61 74 74 65 72 6e 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 6f 6e 62 6f 61 ┆ory Test Pattern. The onboa┆
0x7d40…7d60 72 64 20 44 75 61 6c 20 50 6f 72 74 20 52 41 4d 20 6d 65 6d 6f 72 79 20 63 6f 6e 73 69 73 74 73 ┆rd Dual Port RAM memory consists┆
0x7d60…7d80 20 6f 66 20 6d 65 6d 6f 72 79 20 63 68 69 70 73 20 6f 66 20 31 20 0a 62 69 74 20 78 20 36 34 20 ┆ of memory chips of 1 bit x 64 ┆
0x7d80…7da0 6b 2e 20 74 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 65 78 65 63 75 74 65 73 20 34 20 70 61 ┆k. the memory test executes 4 pa┆
0x7da0…7dc0 73 73 65 73 20 74 68 72 6f 75 67 68 20 74 68 65 20 65 6e 74 69 72 65 20 0a 6d 65 6d 6f 72 79 2c ┆sses through the entire memory,┆
0x7dc0…7de0 20 74 77 6f 20 74 69 6d 65 73 20 77 72 69 74 69 6e 67 20 61 6e 64 20 74 77 6f 20 74 69 6d 65 73 ┆ two times writing and two times┆
0x7de0…7e00 20 72 65 61 64 69 6e 67 2e 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 73 74 61 72 74 73 20 69 6e 20 ┆ reading. The test starts in ┆
0x7e00…7e20 (63,) 74 68 65 20 68 69 67 68 65 73 74 20 61 64 64 72 65 73 73 2c 20 64 65 72 69 76 65 64 20 66 72 6f ┆the highest address, derived fro┆
0x7e20…7e40 6d 20 74 68 65 20 53 32 33 20 0a 73 74 72 61 70 2c 20 61 6e 64 20 69 6e 73 65 72 74 73 20 74 68 ┆m the S23 strap, and inserts th┆
0x7e40…7e60 65 20 70 61 74 74 65 72 6e 20 74 6f 77 61 72 64 73 20 6c 6f 77 65 72 20 61 64 64 72 65 73 73 65 ┆e pattern towards lower addresse┆
0x7e60…7e80 73 2e 0d 0a 0d 0a 57 68 65 6e 20 61 6c 6c 20 6d 65 6d 6f 72 79 20 77 6f 72 64 73 20 68 61 76 65 ┆s. When all memory words have┆
0x7e80…7ea0 20 62 65 65 6e 20 77 72 69 74 74 65 6e 20 61 6e 64 20 74 65 73 74 65 64 2c 20 74 68 65 79 20 61 ┆ been written and tested, they a┆
0x7ea0…7ec0 72 65 20 0a 74 65 73 74 65 64 20 61 67 61 69 6e 20 77 69 74 68 20 74 68 65 20 69 6e 76 65 72 73 ┆re tested again with the invers┆
0x7ec0…7ee0 65 64 20 70 61 74 74 65 72 6e 2c 20 74 68 69 73 20 6d 65 61 6e 73 2c 20 61 6c 6c 20 62 69 74 73 ┆ed pattern, this means, all bits┆
0x7ee0…7f00 20 61 72 65 20 0a 74 65 73 74 65 64 20 66 6f 72 20 22 7a 65 72 6f 22 20 61 6e 64 20 22 6f 6e 65 ┆ are tested for "zero" and "one┆
0x7f00…7f20 22 20 69 6e 73 65 72 74 69 6f 6e 2e 0d 0a 0d 0a 49 66 20 61 6e 20 65 72 72 6f 72 20 6f 63 63 75 ┆" insertion. If an error occu┆
0x7f20…7f40 72 73 2c 20 61 20 6d 65 73 73 61 67 65 20 77 69 6c 6c 20 62 65 20 77 72 69 74 74 65 6e 20 61 73 ┆rs, a message will be written as┆
0x7f40…7f4d 20 66 6f 6c 6c 6f 77 73 3a 0d 0a 0d 0a ┆ follows: ┆
0x7f4d…7f86 Params {
0x7f4d…7f86 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 45 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N E1 ┆
0x7f4d…7f86 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x7f4d…7f86 }
0x7f86…7fbf Params {
0x7f86…7fbf 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0x7f86…7fbf 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x7f86…7fbf }
0x7fbf…7fc0 0a ┆ ┆
0x7fc0…7fe0 b0 6d 65 6d 6f 72 79 20 74 65 73 74 3a 20 65 72 72 6f 72 2c 20 61 64 64 72 2e 3a 20 3c 73 73 73 ┆ memory test: error, addr.: <sss┆
0x7fe0…8000 73 3e 3a 3c 61 61 61 61 3e 2c 20 65 78 70 2e 3a 20 3c 65 65 65 65 3e 2c 72 65 63 2e 3a 20 3c 72 ┆s>:<aaaa>, exp.: <eeee>,rec.: <r┆
0x8000…8006 (64,) 72 72 72 3e 0d 0a ┆rrr> ┆
0x8006…803f Params {
0x8006…803f 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0x8006…803f 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x8006…803f }
0x803f…8078 Params {
0x803f…8078 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 45 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N E1 ┆
0x803f…8078 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x803f…8078 }
0x8078…8080 0a 0d 0a 8c 83 e0 0a 57 ┆ W┆
0x8080…80a0 68 65 72 65 20 0d 0a 09 3c 73 73 73 73 3e 20 69 73 20 74 68 65 20 73 65 67 6d 65 6e 74 20 61 64 ┆here <ssss> is the segment ad┆
0x80a0…80c0 64 72 65 73 73 0d 0a 09 3c 61 61 61 61 3e 20 69 73 20 74 68 65 20 6f 66 66 73 65 74 20 61 64 64 ┆dress <aaaa> is the offset add┆
0x80c0…80e0 72 65 73 73 0d 0a 20 09 3c 65 65 65 65 3e 20 69 73 20 74 68 65 20 65 78 70 65 63 74 65 64 20 70 ┆ress <eeee> is the expected p┆
0x80e0…8100 61 74 74 65 72 6e 0d 0a 09 3c 72 72 72 72 3e 20 69 73 20 74 68 65 20 72 65 63 65 69 76 65 64 20 ┆attern <rrrr> is the received ┆
0x8100…8120 70 61 74 74 65 72 6e 2e 0d 0a 0d 0a 49 6e 20 63 61 73 65 20 6f 66 20 61 6e 20 65 72 72 6f 72 20 ┆pattern. In case of an error ┆
0x8120…8140 74 68 65 20 74 65 73 74 61 64 6d 69 6e 69 73 74 72 61 74 6f 72 20 70 61 73 73 2d 63 6f 75 6e 74 ┆the testadministrator pass-count┆
0x8140…815c 65 72 20 77 69 6c 6c 20 62 65 20 0a 64 65 73 74 72 6f 79 65 64 2e 0d 0a 0d 0a 0d 0a ┆er will be destroyed. ┆
0x815c…815f FormFeed {
0x815c…815f 0c 80 f8 ┆ ┆
0x815c…815f }
0x815f…8160 0a ┆ ┆
0x8160…8180 b0 a1 39 2e 20 54 65 73 74 20 31 20 3d 20 52 41 4d 20 52 65 66 72 65 73 68 20 54 65 73 74 2e 0d ┆ 9. Test 1 = RAM Refresh Test. ┆
0x8180…81a0 0a 0d 0a 0d 0a 54 68 65 20 52 41 4d 20 72 65 66 72 65 73 68 20 74 65 73 74 20 6f 66 20 74 68 65 ┆ The RAM refresh test of the┆
0x81a0…81c0 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 61 73 73 69 73 74 20 69 6e 20 74 ┆ ETC601 SBC Selftest assist in t┆
0x81c0…81e0 68 65 20 0a 76 65 72 69 66 69 63 61 74 69 6f 6e 20 6f 66 20 74 68 65 20 6d 65 6d 6f 72 79 20 63 ┆he verification of the memory c┆
0x81e0…8200 6f 6e 74 72 6f 6c 20 6c 6f 67 69 63 20 66 75 6e 63 74 69 6f 6e 61 6c 69 74 79 2e 20 54 68 65 20 ┆ontrol logic functionality. The ┆
0x8200…8220 (65,) 6d 61 69 6e 20 0a 70 75 72 70 6f 73 65 20 69 73 20 74 6f 20 64 69 73 63 6f 76 65 72 20 74 68 65 ┆main purpose is to discover the┆
0x8220…8240 20 64 65 63 61 79 20 6f 66 20 64 61 74 61 20 63 61 75 73 65 64 20 62 79 20 61 20 6d 61 6c 66 75 ┆ decay of data caused by a malfu┆
0x8240…8260 6e 63 74 69 6f 6e 20 0a 6f 66 20 74 68 65 20 52 41 4d 20 72 65 66 72 65 73 68 20 63 69 72 63 75 ┆nction of the RAM refresh circu┆
0x8260…8280 69 74 72 79 2e 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 70 61 74 74 65 72 6e 20 77 72 69 74 74 65 ┆itry. The test pattern writte┆
0x8280…82a0 6e 20 69 73 20 61 20 63 6f 75 6e 74 69 6e 67 20 70 61 74 74 65 72 6e 20 61 6e 64 20 74 68 65 20 ┆n is a counting pattern and the ┆
0x82a0…82c0 73 69 7a 65 20 6f 66 20 0a 74 68 65 20 74 65 73 74 20 62 75 66 66 65 72 20 69 73 20 34 20 4b 2c ┆size of the test buffer is 4 K,┆
0x82c0…82e0 20 31 36 20 62 69 74 20 77 6f 72 64 73 2e 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 70 61 74 74 65 ┆ 16 bit words. When the patte┆
0x82e0…8300 72 6e 20 68 61 73 20 62 65 65 6e 20 77 72 69 74 74 65 6e 20 74 68 65 20 74 65 73 74 20 70 72 6f ┆rn has been written the test pro┆
0x8300…8320 67 72 61 6d 20 65 6e 74 65 72 73 20 61 20 0a 77 61 69 74 69 6e 67 20 6c 6f 6f 70 20 66 6f 72 20 ┆gram enters a waiting loop for ┆
0x8320…8340 61 70 70 72 6f 78 69 6d 61 74 65 20 35 20 73 65 63 2e 2c 20 69 6e 20 77 68 69 63 68 20 74 68 65 ┆approximate 5 sec., in which the┆
0x8340…8360 20 43 50 55 20 77 69 6c 6c 20 6e 6f 74 20 0a 61 63 63 65 73 73 20 74 68 65 20 52 41 4d 20 6d 65 ┆ CPU will not access the RAM me┆
0x8360…8380 6d 6f 72 79 2e 20 41 66 74 65 72 20 74 68 65 20 64 65 6c 61 79 2c 20 74 68 65 20 62 75 66 66 65 ┆mory. After the delay, the buffe┆
0x8380…83a0 72 20 77 69 6c 6c 20 62 65 20 0a 63 68 65 63 6b 65 64 20 74 6f 20 64 69 73 63 6f 76 65 72 20 61 ┆r will be checked to discover a┆
0x83a0…83c0 6e 79 20 64 65 63 61 79 2e 0d 0a 0d 0a 49 66 20 64 65 63 61 79 20 69 73 20 66 6f 75 6e 64 2c 20 ┆ny decay. If decay is found, ┆
0x83c0…83e0 61 20 6d 65 73 73 61 67 65 20 69 73 20 77 72 69 74 74 65 6e 20 6c 69 6b 65 20 74 68 69 73 3a 0d ┆a message is written like this: ┆
0x83e0…83e3 0a 0d 0a ┆ ┆
0x83e3…841c Params {
0x83e3…841c 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 45 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N E1 ┆
0x83e3…841c 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x83e3…841c }
0x841c…8455 Params {
0x841c…8455 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0x841c…8455 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x841c…8455 }
0x8455…8460 0a b0 52 41 4d 20 72 65 66 72 65 ┆ RAM refre┆
0x8460…8480 73 68 20 74 65 73 74 3a 20 65 72 72 6f 72 2c 20 61 64 64 72 2e 3a 20 3c 61 61 61 61 3e 2c 20 65 ┆sh test: error, addr.: <aaaa>, e┆
0x8480…849b 78 70 2e 3a 20 3c 65 65 65 65 3e 2c 20 72 65 63 2e 3a 20 3c 72 72 72 72 3e 0d 0a ┆xp.: <eeee>, rec.: <rrrr> ┆
0x849b…84d4 Params {
0x849b…84d4 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0x849b…84d4 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x849b…84d4 }
0x84d4…850d Params {
0x84d4…850d 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 45 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N E1 ┆
0x84d4…850d 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x84d4…850d }
0x850d…8520 0a 0d 0a 57 68 65 72 65 0d 0a 09 3c 61 61 61 61 3e 20 84 ┆ Where <aaaa> ┆
0x8520…8540 69 73 20 74 68 65 20 6f 66 66 73 65 74 20 61 64 64 72 65 73 73 20 72 65 6c 61 74 69 76 65 20 74 ┆is the offset address relative t┆
0x8540…8560 6f 20 74 68 65 20 73 74 61 72 74 20 6f 66 20 74 68 65 20 0a 19 8b 80 80 74 65 73 74 20 62 75 66 ┆o the start of the test buf┆
0x8560…8580 66 65 72 2e 0d 0a 20 20 20 20 3c 65 65 65 65 3e 20 69 73 20 74 68 65 20 70 61 74 74 65 72 6e 20 ┆fer. <eeee> is the pattern ┆
0x8580…85a0 77 72 69 74 74 65 6e 20 69 6e 20 74 68 69 73 20 77 6f 72 64 2e 0d 0a 09 3c 72 72 72 72 3e 20 69 ┆written in this word. <rrrr> i┆
0x85a0…85c0 73 20 74 68 65 20 70 61 74 74 65 72 6e 20 72 65 61 64 20 66 72 6f 6d 20 74 68 69 73 20 77 6f 72 ┆s the pattern read from this wor┆
0x85c0…85e0 64 2e 0d 0a 0d 0a 54 68 65 20 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 ┆d. The corresponding error nu┆
0x85e0…85ec 6d 62 65 72 20 69 73 20 39 2e 0d 0a ┆mber is 9. ┆
0x85ec…85ef FormFeed {
0x85ec…85ef 0c 82 c4 ┆ ┆
0x85ec…85ef }
0x85ef…8600 0a b0 a1 31 30 2e 20 54 65 73 74 20 32 20 3d 20 69 ┆ 10. Test 2 = i┆
0x8600…8620 (67,) 41 50 58 31 38 36 20 44 4d 41 20 54 65 73 74 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 69 41 50 58 31 38 ┆APX186 DMA Test. The iAPX18┆
0x8620…8640 36 20 44 4d 41 20 54 65 73 74 20 6f 66 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 ┆6 DMA Test of ETC601 SBC Selftes┆
0x8640…8660 74 20 61 70 70 6c 69 65 73 20 74 6f 20 74 68 65 20 0a 76 65 72 69 66 69 63 61 74 69 6f 6e 20 6f ┆t applies to the verification o┆
0x8660…8680 66 20 74 68 65 20 66 75 6e 63 74 69 6f 6e 61 6c 69 74 79 20 6f 66 20 74 68 65 20 74 77 6f 20 6f ┆f the functionality of the two o┆
0x8680…86a0 6e 2d 63 68 69 70 20 69 41 50 58 31 38 36 20 44 4d 41 20 0a 63 68 61 6e 6e 65 6c 73 2e 0d 0a 0d ┆n-chip iAPX186 DMA channels. ┆
0x86a0…86c0 0a 42 6f 74 68 20 44 4d 41 20 63 68 61 6e 6e 65 6c 73 20 61 72 65 20 69 6e 69 74 69 61 6c 69 7a ┆ Both DMA channels are initializ┆
0x86c0…86e0 65 64 20 74 6f 20 6d 65 6d 6f 72 79 20 74 6f 20 6d 65 6d 6f 72 79 20 74 72 61 6e 73 70 6f 72 74 ┆ed to memory to memory transport┆
0x86e0…8700 73 2e 20 0a 43 68 61 6e 6e 65 6c 20 30 20 77 69 6c 6c 20 74 72 61 6e 73 66 65 72 20 74 6f 20 74 ┆s. Channel 0 will transfer to t┆
0x8700…8720 68 65 20 6c 6f 77 65 73 74 20 61 64 64 72 65 73 73 20 6f 66 20 69 74 73 20 72 65 63 65 69 76 65 ┆he lowest address of its receive┆
0x8720…8740 20 0a 62 75 66 66 65 72 20 66 69 72 73 74 2c 20 61 6e 64 20 63 68 61 6e 6e 65 6c 20 31 20 77 69 ┆ buffer first, and channel 1 wi┆
0x8740…8760 6c 6c 20 74 72 61 6e 73 66 65 72 20 74 6f 20 74 68 65 20 68 69 67 68 65 73 74 20 61 64 64 72 65 ┆ll transfer to the highest addre┆
0x8760…8780 73 73 20 0a 6f 66 20 69 74 73 20 72 65 63 65 69 76 65 20 62 75 66 66 65 72 20 66 69 72 73 74 2e ┆ss of its receive buffer first.┆
0x8780…87a0 0d 0a 0d 0a 42 6f 74 68 20 63 68 61 6e 6e 65 6c 73 20 61 72 65 20 73 74 61 72 74 65 64 20 61 6e ┆ Both channels are started an┆
0x87a0…87c0 64 20 77 69 6c 6c 20 74 72 61 6e 73 66 65 72 20 62 79 74 65 73 20 73 69 6d 75 6c 74 61 6e 65 6f ┆d will transfer bytes simultaneo┆
0x87c0…87e0 75 73 6c 79 2e 20 0a 54 68 65 20 70 72 6f 63 65 64 75 72 65 20 6f 66 20 74 68 65 20 74 65 73 74 ┆usly. The procedure of the test┆
0x87e0…8800 20 69 73 20 74 6f 20 63 68 65 63 6b 20 74 68 61 74 20 74 68 65 20 74 72 61 6e 73 66 65 72 20 63 ┆ is to check that the transfer c┆
0x8800…8820 (68,) 6f 75 6e 74 20 0a 72 65 61 63 68 65 73 20 7a 65 72 6f 20 62 65 66 6f 72 65 20 61 20 70 72 6f 67 ┆ount reaches zero before a prog┆
0x8820…8840 72 61 6d 6d 65 64 20 74 69 6d 65 2d 69 6e 74 65 72 76 61 6c 20 65 6c 61 70 73 65 73 2e 20 54 68 ┆rammed time-interval elapses. Th┆
0x8840…8860 65 20 0a 74 69 6d 65 6f 75 74 20 69 73 20 61 70 70 72 6f 78 69 6d 61 74 65 20 32 30 30 6d 53 2e ┆e timeout is approximate 200mS.┆
0x8860…8880 0d 0a 0d 0a 49 66 20 62 6f 74 68 20 63 68 61 6e 6e 65 6c 73 20 68 61 76 65 20 74 72 61 6e 73 66 ┆ If both channels have transf┆
0x8880…88a0 65 72 72 65 64 20 74 68 65 20 74 65 73 74 20 62 75 66 66 65 72 20 6f 66 20 38 20 6b 20 62 79 74 ┆erred the test buffer of 8 k byt┆
0x88a0…88c0 65 73 20 0a 65 61 63 68 20 77 69 74 68 6f 75 74 20 74 69 6d 65 6f 75 74 2c 20 61 20 64 61 74 61 ┆es each without timeout, a data┆
0x88c0…88e0 63 68 65 63 6b 20 6f 66 20 62 6f 74 68 20 72 65 63 65 69 76 65 20 62 75 66 66 65 72 73 20 69 73 ┆check of both receive buffers is┆
0x88e0…8900 20 0a 70 65 72 66 6f 72 6d 65 64 2e 20 54 68 65 20 64 61 74 61 20 63 6f 6d 70 61 72 65 20 72 6f ┆ performed. The data compare ro┆
0x8900…8920 75 74 69 6e 65 20 69 73 20 62 61 73 65 64 20 75 70 6f 6e 20 61 20 73 74 72 69 6e 67 20 0a 63 6f ┆utine is based upon a string co┆
0x8920…8940 6d 70 61 72 65 20 69 6e 73 74 72 75 63 74 69 6f 6e 2e 20 49 66 20 61 20 64 69 66 66 65 72 65 6e ┆mpare instruction. If a differen┆
0x8940…8960 63 65 20 62 65 74 77 65 65 6e 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 61 6e 64 20 0a 72 65 63 ┆ce between the transmit and rec┆
0x8960…8980 65 69 76 65 20 62 75 66 66 65 72 20 69 73 20 64 69 73 63 6f 76 65 72 65 64 2c 20 74 68 65 20 31 ┆eive buffer is discovered, the 1┆
0x8980…89a0 36 20 62 69 74 20 77 6f 72 64 20 69 6e 20 71 75 65 73 74 69 6f 6e 20 69 73 20 0a 66 65 74 63 68 ┆6 bit word in question is fetch┆
0x89a0…89c0 65 64 20 66 72 6f 6d 20 6d 65 6d 6f 72 79 20 61 6e 64 20 73 68 6f 77 6e 20 61 73 20 61 6e 20 65 ┆ed from memory and shown as an e┆
0x89c0…89e0 72 72 6f 72 6d 65 73 73 61 67 65 2e 20 49 6e 20 6f 74 68 65 72 20 77 6f 72 64 73 2c 20 0a 74 68 ┆rrormessage. In other words, th┆
0x89e0…8a00 65 20 65 72 72 6f 72 6e 65 6f 75 73 20 77 6f 72 64 20 69 73 20 66 65 74 63 68 65 73 20 69 6e 20 ┆e errorneous word is fetches in ┆
0x8a00…8a20 (69,) 62 6f 74 68 20 74 68 65 20 73 74 72 69 6e 67 20 63 6f 6d 70 61 72 65 20 0a 69 6e 73 74 72 75 63 ┆both the string compare instruc┆
0x8a20…8a40 74 69 6f 6e 20 61 6e 64 20 66 6f 72 20 74 68 65 20 65 72 72 6f 72 6d 65 73 73 61 67 65 2e 20 54 ┆tion and for the errormessage. T┆
0x8a40…8a60 68 69 73 20 63 6f 75 6c 64 20 6d 65 61 6e 2c 20 74 68 61 74 20 69 66 20 0a 74 68 65 20 64 69 73 ┆his could mean, that if the dis┆
0x8a60…8a80 63 6f 76 65 72 65 64 20 65 72 72 6f 72 20 77 61 73 20 64 75 65 20 74 6f 20 61 20 73 70 6f 72 61 ┆covered error was due to a spora┆
0x8a80…8aa0 64 69 63 20 6d 65 6d 6f 72 79 20 65 72 72 6f 72 2c 20 74 68 65 20 0a 73 68 6f 77 6e 20 65 78 70 ┆dic memory error, the shown exp┆
0x8aa0…8ac0 65 63 74 65 64 20 61 6e 64 20 72 65 63 65 69 76 65 64 20 76 61 6c 75 65 73 20 63 6f 75 6c 64 20 ┆ected and received values could ┆
0x8ac0…8ae0 74 75 72 6e 20 6f 75 74 20 74 6f 20 62 65 20 65 71 75 61 6c 2e 0d 0a 0d 0a 74 68 65 20 63 6f 6e ┆turn out to be equal. the con┆
0x8ae0…8b00 74 72 6f 6c 20 77 6f 72 64 20 6f 66 20 63 68 61 6e 6e 65 6c 20 30 20 69 73 20 69 6e 69 74 69 61 ┆trol word of channel 0 is initia┆
0x8b00…8b20 6c 69 7a 65 64 20 74 6f 20 42 36 30 36 48 20 61 6e 64 20 74 68 65 20 0a 63 6f 6e 74 72 6f 6c 20 ┆lized to B606H and the control ┆
0x8b20…8b40 77 6f 72 64 20 6f 66 20 63 68 61 6e 6e 65 6c 20 31 20 69 73 20 69 6e 69 74 69 61 6c 69 7a 65 64 ┆word of channel 1 is initialized┆
0x8b40…8b60 20 74 6f 20 44 41 30 36 48 2e 0d 0a 8c 82 e8 0a 0e 0a 0d 0a 3c 20 20 20 20 20 20 20 20 20 20 20 ┆ to DA06H. < ┆
0x8b60…8b80 20 20 20 20 20 20 20 20 20 20 20 20 20 20 a1 20 20 20 52 65 67 69 73 74 65 72 20 41 64 64 72 65 ┆ Register Addre┆
0x8b80…8ba0 73 73 20 0d 0a a1 20 52 65 67 69 73 74 65 72 20 6e 61 6d 65 20 20 20 20 20 20 20 20 20 20 20 20 ┆ss Register name ┆
0x8ba0…8bc0 43 68 2e 20 30 20 20 20 20 43 68 2e 31 20 20 20 20 20 20 0d 0a 20 43 6f 6e 74 72 6f 6c 20 57 6f ┆Ch. 0 Ch.1 Control Wo┆
0x8bc0…8be0 72 64 20 20 20 20 20 20 20 20 20 20 20 20 20 46 46 43 41 48 20 20 20 20 46 46 44 41 48 0d 0a 20 ┆rd FFCAH FFDAH ┆
0x8be0…8c00 54 72 61 6e 73 66 65 72 20 43 6f 75 6e 74 20 20 20 20 20 20 20 20 20 20 20 46 46 43 38 48 20 20 ┆Transfer Count FFC8H ┆
0x8c00…8c20 (70,) 20 20 46 46 44 38 48 0d 0a 20 44 65 73 74 69 6e 61 74 69 6f 6e 20 50 6f 69 6e 74 65 72 20 20 20 ┆ FFD8H Destination Pointer ┆
0x8c20…8c40 20 20 20 46 46 43 36 48 20 20 20 20 46 46 44 36 48 0d 0a 20 28 75 70 70 65 72 20 34 20 62 69 74 ┆ FFC6H FFD6H (upper 4 bit┆
0x8c40…8c60 73 29 0d 0a 20 44 65 73 74 69 6e 61 74 69 6f 6e 20 50 6f 69 6e 74 65 72 20 20 20 20 20 20 46 46 ┆s) Destination Pointer FF┆
0x8c60…8c80 43 34 48 20 20 20 20 46 46 44 34 48 0d 0a 20 53 6f 75 72 63 65 20 50 6f 69 6e 74 65 72 20 20 20 ┆C4H FFD4H Source Pointer ┆
0x8c80…8ca0 20 20 20 20 20 20 20 20 46 46 43 32 48 20 20 20 20 46 46 44 32 48 0d 0a 20 28 75 70 70 65 72 20 ┆ FFC2H FFD2H (upper ┆
0x8ca0…8cc0 34 20 62 69 74 73 29 0d 0a a1 20 53 6f 75 72 63 65 20 50 6f 69 6e 74 65 72 20 20 20 20 20 20 20 ┆4 bits) Source Pointer ┆
0x8cc0…8ce0 20 20 20 20 46 46 43 30 48 20 20 20 20 46 46 43 30 48 20 20 20 20 20 0d 0a 0d 0a 20 20 20 20 20 ┆ FFC0H FFC0H ┆
0x8ce0…8d00 20 20 20 20 20 20 20 20 46 69 67 75 72 65 20 31 33 3a 20 44 4d 41 20 43 6f 6e 74 72 6f 6c 20 42 ┆ Figure 13: DMA Control B┆
0x8d00…8d20 6c 6f 63 6b 20 46 6f 72 6d 61 74 2e 0d 0a 0f 0a 0d 0a 49 66 20 74 68 65 20 54 72 61 6e 73 66 65 ┆lock Format. If the Transfe┆
0x8d20…8d40 72 20 43 6f 75 6e 74 20 6f 66 20 6f 6e 65 20 6f 66 20 74 68 65 20 63 68 61 6e 6e 65 6c 73 20 64 ┆r Count of one of the channels d┆
0x8d40…8d60 6f 65 73 20 6e 6f 74 20 72 65 61 63 68 20 7a 65 72 6f 20 0a 62 65 66 6f 72 65 20 74 69 6d 65 6f ┆oes not reach zero before timeo┆
0x8d60…8d80 75 74 2c 20 61 20 6d 65 73 73 61 67 65 20 61 73 20 66 6f 6c 6c 6f 77 73 20 77 69 6c 6c 20 62 65 ┆ut, a message as follows will be┆
0x8d80…8da0 20 77 72 69 74 74 65 6e 3a 0d 0a 0d 0a b0 69 41 50 58 31 38 36 20 44 4d 41 20 74 65 73 74 3a 20 ┆ written: iAPX186 DMA test: ┆
0x8da0…8dc0 74 72 61 6e 73 66 65 72 20 63 6f 75 6e 74 20 65 72 72 6f 72 2c 20 72 65 67 2e 3a 3c 61 61 61 61 ┆transfer count error, reg.:<aaaa┆
0x8dc0…8de0 3e 2c 20 65 78 70 2e 3a 3c 65 65 65 65 3e 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 09 09 ┆>, exp.:<eeee> ┆
0x8de0…8e00 09 20 20 20 20 20 20 20 20 20 b0 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 0d 0a 54 68 65 20 63 6f ┆ rec.:<rrrr> The co┆
0x8e00…8e20 (71,) 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 34 2e 0d 0a ┆rresponding error number is 4. ┆
0x8e20…8e40 0d 0a 77 68 65 72 65 0d 0a 09 3c 61 61 61 61 3e 20 69 73 20 74 68 65 20 72 65 6c 61 74 65 64 20 ┆ where <aaaa> is the related ┆
0x8e40…8e60 54 72 61 6e 73 66 65 72 20 43 6f 75 6e 74 20 52 65 67 69 73 74 65 72 2e 0d 0a 09 3c 65 65 65 65 ┆Transfer Count Register. <eeee┆
0x8e60…8e80 3e 20 69 73 20 74 68 65 20 65 78 70 65 63 74 65 64 20 76 61 6c 75 65 2c 20 61 6c 77 61 79 73 20 ┆> is the expected value, always ┆
0x8e80…8ea0 7a 65 72 6f 2e 0d 0a 09 3c 72 72 72 72 3e 20 69 73 20 74 68 65 20 63 6f 6e 74 65 6e 74 20 6f 66 ┆zero. <rrrr> is the content of┆
0x8ea0…8ec0 20 74 68 65 20 54 72 61 6e 73 66 65 72 20 43 6f 75 6e 74 20 52 65 67 69 73 74 65 72 2e 0d 0a 0d ┆ the Transfer Count Register. ┆
0x8ec0…8ee0 0a 49 66 20 61 20 64 61 74 61 20 65 72 72 6f 72 20 69 73 20 64 69 73 63 6f 76 65 72 65 64 2c 20 ┆ If a data error is discovered, ┆
0x8ee0…8f00 61 20 6d 65 73 73 61 67 65 20 61 73 20 66 6f 6c 6c 6f 77 73 20 77 69 6c 6c 20 62 65 20 0a 77 72 ┆a message as follows will be wr┆
0x8f00…8f20 69 74 74 65 6e 2e 0d 0a 0d 0a b0 69 41 50 58 31 38 36 20 44 4d 41 20 74 65 73 74 3a 20 64 61 74 ┆itten. iAPX186 DMA test: dat┆
0x8f20…8f40 61 20 65 72 72 6f 72 2c 20 61 64 64 72 2e 3a 3c 61 61 61 61 3e 2c 20 65 78 70 2e 3a 3c 65 65 65 ┆a error, addr.:<aaaa>, exp.:<eee┆
0x8f40…8f60 65 3e 2c 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 b0 20 20 20 20 20 20 20 20 ┆e>, ┆
0x8f60…8f80 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 72 65 63 2e 3a 20 3c 72 72 72 72 3e 0d 0a 0d ┆ rec.: <rrrr> ┆
0x8f80…8fa0 0a 54 68 65 20 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 ┆ The corresponding error number ┆
0x8fa0…8fc0 69 73 20 33 2e 0d 0a 0d 0a 77 68 65 72 65 0d 0a 09 3c 61 61 61 61 3e 20 69 73 20 74 68 65 20 6f ┆is 3. where <aaaa> is the o┆
0x8fc0…8fe0 66 66 73 65 74 20 61 64 64 72 65 73 73 20 69 6e 20 74 68 65 20 72 65 63 65 69 76 65 20 62 75 66 ┆ffset address in the receive buf┆
0x8fe0…9000 66 65 72 2e 0d 0a 09 3c 65 65 65 65 3e 20 69 73 20 74 68 65 20 31 36 20 62 69 74 20 77 6f 72 64 ┆fer. <eeee> is the 16 bit word┆
0x9000…9020 (72,) 20 69 6e 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 62 75 66 66 65 72 2e 0d 0a 8c 83 c8 0a 09 3c ┆ in the transmit buffer. <┆
0x9020…9040 72 72 72 72 3e 20 69 73 20 74 68 65 20 31 36 20 62 69 74 20 77 6f 72 64 20 69 6e 20 74 68 65 20 ┆rrrr> is the 16 bit word in the ┆
0x9040…9060 72 65 63 65 69 76 65 64 20 62 75 66 66 65 72 2e 0d 0a 0d 0a 42 6f 74 68 20 65 72 72 6f 72 73 20 ┆received buffer. Both errors ┆
0x9060…9080 6d 69 67 68 74 20 62 65 20 69 6e 74 65 72 6e 61 6c 20 74 6f 20 74 68 65 20 69 41 50 58 31 38 36 ┆might be internal to the iAPX186┆
0x9080…9088 20 63 68 69 70 2e 20 0a ┆ chip. ┆
0x9088…908b FormFeed {
0x9088…908b 0c 80 a4 ┆ ┆
0x9088…908b }
0x908b…90a0 0a b0 a1 31 31 2e 20 54 65 73 74 20 33 20 3d 20 50 49 43 20 28 ┆ 11. Test 3 = PIC (┆
0x90a0…90c0 38 32 35 39 29 20 49 6e 74 65 72 72 75 70 74 20 54 65 73 74 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 50 ┆8259) Interrupt Test. The P┆
0x90c0…90e0 49 43 20 28 38 32 35 39 29 20 49 6e 74 65 72 72 75 70 74 20 54 65 73 74 20 6f 66 20 74 68 65 20 ┆IC (8259) Interrupt Test of the ┆
0x90e0…9100 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 61 70 70 6c 69 65 73 20 0a 74 6f 20 ┆ETC601 SBC Selftest applies to ┆
0x9100…9120 74 68 65 20 76 65 72 69 66 69 63 61 74 69 6f 6e 20 6f 66 20 74 68 65 20 66 75 6e 63 74 69 6f 6e ┆the verification of the function┆
0x9120…9140 61 6c 69 74 79 20 6f 66 20 74 68 65 20 38 32 35 39 20 69 6e 74 65 72 72 75 70 74 20 0a 63 6f 6e ┆ality of the 8259 interrupt con┆
0x9140…9160 74 72 6f 6c 6c 65 72 2e 0d 0a 0d 0a 54 68 65 20 70 72 6f 63 65 64 75 72 65 20 6f 66 20 74 68 65 ┆troller. The procedure of the┆
0x9160…9180 20 74 65 73 74 20 69 73 20 74 68 61 74 20 74 68 65 20 43 50 55 20 77 72 69 74 65 73 20 74 68 65 ┆ test is that the CPU writes the┆
0x9180…91a0 20 66 6c 61 67 62 79 74 65 2e 20 0a 54 68 69 73 20 77 69 6c 6c 20 63 61 75 73 65 20 61 6e 20 69 ┆ flagbyte. This will cause an i┆
0x91a0…91c0 6e 74 65 72 72 75 70 74 20 72 65 71 75 65 73 74 20 6f 6e 20 74 68 65 20 50 49 43 20 6c 65 76 65 ┆nterrupt request on the PIC leve┆
0x91c0…91e0 6c 20 49 52 34 2e 20 49 74 20 69 73 20 0a 76 65 72 69 66 69 65 64 20 74 68 61 74 20 74 68 65 20 ┆l IR4. It is verified that the ┆
0x91e0…9200 69 6e 74 65 72 72 75 70 74 20 69 73 20 67 65 6e 65 72 61 74 65 64 20 77 69 74 68 69 6e 20 61 20 ┆interrupt is generated within a ┆
0x9200…9220 (73,) 70 72 6f 67 72 61 6d 6d 65 64 20 74 69 6d 65 20 0a 69 6e 74 65 72 76 61 6c 2c 20 61 6e 64 20 74 ┆programmed time interval, and t┆
0x9220…9240 68 61 74 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 61 72 72 69 76 65 64 20 6f 6e 20 74 68 65 ┆hat the interrupt arrived on the┆
0x9240…9260 20 65 78 70 65 63 74 65 64 20 6c 65 76 65 6c 2e 20 0d 0a 49 66 20 6e 6f 20 69 6e 74 65 72 72 75 ┆ expected level. If no interru┆
0x9260…9280 70 74 20 68 61 73 20 61 72 72 69 76 65 64 20 77 69 74 68 69 6e 20 74 68 65 20 34 20 6d 53 65 63 ┆pt has arrived within the 4 mSec┆
0x9280…92a0 2e 20 61 20 6d 65 73 73 61 67 65 20 69 73 20 0a 77 72 69 74 74 65 6e 20 6c 69 6b 65 20 74 68 69 ┆. a message is written like thi┆
0x92a0…92c0 73 3a 0d 0a 0d 0a b0 50 49 43 20 74 65 73 74 3a 20 69 6e 74 65 72 72 75 70 74 20 74 69 6d 65 6f ┆s: PIC test: interrupt timeo┆
0x92c0…92e0 75 74 2e 0d 0a 0d 0a 54 68 65 20 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e ┆ut. The corresponding error n┆
0x92e0…9300 75 6d 62 65 72 20 69 73 20 36 2e 0d 0a 49 66 20 61 6e 20 69 6e 74 65 72 72 75 70 74 20 68 61 73 ┆umber is 6. If an interrupt has┆
0x9300…9320 20 61 72 72 69 76 65 64 2c 20 62 75 74 20 6f 6e 20 61 6e 20 75 6e 65 78 70 65 63 74 65 64 20 6c ┆ arrived, but on an unexpected l┆
0x9320…9340 65 76 65 6c 2c 20 61 20 0a 6d 65 73 73 61 67 65 20 69 73 20 77 72 69 74 74 65 6e 20 6c 69 6b 65 ┆evel, a message is written like┆
0x9340…9360 20 74 68 69 73 3a 0d 0a 0d 0a b0 50 49 43 20 74 65 73 74 3a 20 69 6c 6c 65 67 61 6c 20 69 6e 74 ┆ this: PIC test: illegal int┆
0x9360…9380 65 72 72 75 70 74 20 73 65 72 76 69 63 65 64 2c 20 6c 65 76 2e 3a 20 3c 61 61 61 61 3e 0d 0a 0d ┆errupt serviced, lev.: <aaaa> ┆
0x9380…93a0 0a 54 68 65 20 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 ┆ The corresponding error number ┆
0x93a0…93c0 69 73 20 31 31 2e 0d 0a 0d 0a 77 68 65 72 65 0d 0a 09 3c 61 61 61 61 3e 20 69 73 20 74 68 65 20 ┆is 11. where <aaaa> is the ┆
0x93c0…93e0 69 6e 74 65 72 72 75 70 74 20 72 65 71 75 65 73 74 20 6c 65 76 65 6c 2e 0d 0a 0d 0a 4e 6f 74 65 ┆interrupt request level. Note┆
0x93e0…9400 20 74 68 61 74 20 74 68 65 20 64 65 66 61 75 6c 74 20 6a 75 6d 70 65 72 20 73 65 74 74 69 6e 67 ┆ that the default jumper setting┆
0x9400…9420 (74,) 73 20 69 6e 20 53 36 20 67 69 76 69 6e 67 20 66 6c 61 67 62 79 74 65 20 0a 69 6e 74 65 72 72 75 ┆s in S6 giving flagbyte interru┆
0x9420…9440 70 74 20 6f 6e 20 49 52 34 20 69 73 20 6e 65 63 65 73 73 61 72 79 20 74 6f 20 70 65 72 66 6f 72 ┆pt on IR4 is necessary to perfor┆
0x9440…9460 6d 20 74 68 69 73 20 74 65 73 74 2e 20 28 43 6f 6e 73 75 6c 74 20 0a 68 61 72 64 77 61 72 65 20 ┆m this test. (Consult hardware ┆
0x9460…9480 72 65 66 65 72 65 6e 63 65 20 6d 61 6e 75 61 6c 20 66 6f 72 20 73 74 72 61 70 70 69 6e 67 20 69 ┆reference manual for strapping i┆
0x9480…94a0 6e 73 74 72 75 63 74 69 6f 6e 73 29 2e 0d 0a 0d 0a 46 61 69 6c 75 72 65 20 74 6f 20 69 6e 73 74 ┆nstructions). Failure to inst┆
0x94a0…94c0 61 6c 6c 20 74 68 69 73 20 6a 75 6d 70 65 72 20 77 69 6c 6c 20 63 61 75 73 65 20 61 6e 20 65 72 ┆all this jumper will cause an er┆
0x94c0…94de 72 6f 72 20 35 3a 20 22 69 6c 6c 65 67 61 6c 20 0a 69 6e 74 65 72 72 75 70 74 22 2e 0d 0a ┆ror 5: "illegal interrupt". ┆
0x94de…94e1 FormFeed {
0x94de…94e1 0c 83 8c ┆ ┆
0x94de…94e1 }
0x94e1…9500 0a b0 a1 31 32 2e 20 54 65 73 74 20 34 20 3d 20 69 41 50 58 31 38 36 20 49 6e 74 65 72 72 75 ┆ 12. Test 4 = iAPX186 Interru┆
0x9500…9520 70 74 20 54 65 73 74 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 69 41 50 58 31 38 36 20 49 6e 74 65 72 72 ┆pt Test. The iAPX186 Interr┆
0x9520…9540 75 70 74 20 54 65 73 74 20 6f 66 20 74 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 ┆upt Test of the ETC601 SBC Selft┆
0x9540…9560 65 73 74 20 61 70 70 6c 69 65 73 20 74 6f 20 0a 74 68 65 20 76 65 72 69 66 69 63 61 74 69 6f 6e ┆est applies to the verification┆
0x9560…9580 20 6f 66 20 74 68 65 20 66 75 6e 63 74 69 6f 6e 61 6c 69 74 79 20 6f 66 20 74 68 65 20 6f 6e 2d ┆ of the functionality of the on-┆
0x9580…95a0 63 68 69 70 20 69 6e 74 65 72 72 75 70 74 20 0a 63 6f 6e 74 72 6f 6c 6c 65 72 2e 0d 0a 0d 0a 54 ┆chip interrupt controller. T┆
0x95a0…95c0 68 65 20 70 72 6f 63 65 64 75 72 65 20 6f 66 20 74 68 65 20 74 65 73 74 20 69 73 20 74 6f 20 73 ┆he procedure of the test is to s┆
0x95c0…95e0 74 61 72 74 20 74 68 65 20 69 6e 74 65 72 6e 61 6c 20 74 69 6d 65 72 20 32 20 77 69 74 68 20 61 ┆tart the internal timer 2 with a┆
0x95e0…9600 20 0a 63 6f 75 6e 74 20 76 61 6c 75 65 20 65 71 75 61 6c 20 31 2e 20 49 74 20 69 73 20 74 65 73 ┆ count value equal 1. It is tes┆
0x9600…9620 (75,) 74 65 64 20 74 68 61 74 20 61 6e 20 69 6e 74 65 72 72 75 70 74 20 69 73 20 67 65 6e 65 72 61 74 ┆ted that an interrupt is generat┆
0x9620…9640 65 64 20 0a 77 69 74 68 69 6e 20 61 20 70 72 6f 67 72 61 6d 6d 65 64 20 74 69 6d 65 20 69 6e 74 ┆ed within a programmed time int┆
0x9640…9660 65 72 76 61 6c 2c 20 61 6e 64 20 74 68 61 74 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 61 72 ┆erval, and that the interrupt ar┆
0x9660…9680 72 69 76 65 64 20 0a 6f 6e 20 74 68 65 20 65 78 70 65 63 74 65 64 20 6c 65 76 65 6c 2e 0d 0a 0d ┆rived on the expected level. ┆
0x9680…96a0 0a 49 66 20 6e 6f 20 69 6e 74 65 72 72 75 70 74 20 68 61 73 20 61 72 72 69 76 65 64 20 77 69 74 ┆ If no interrupt has arrived wit┆
0x96a0…96c0 68 69 6e 20 34 20 6d 53 65 63 2c 20 61 20 6d 65 73 73 61 67 65 20 69 73 20 77 72 69 74 74 65 6e ┆hin 4 mSec, a message is written┆
0x96c0…96e0 20 0a 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a b0 69 41 50 58 31 38 36 20 73 6c 61 76 65 20 69 ┆ like this: iAPX186 slave i┆
0x96e0…9700 6e 74 65 72 72 75 70 74 20 74 65 73 74 3a 20 74 69 6d 65 6f 75 74 0d 0a 0d 0a 54 68 65 20 63 6f ┆nterrupt test: timeout The co┆
0x9700…9720 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 31 33 2e 0d ┆rresponding error number is 13. ┆
0x9720…9740 0a 0d 0a 49 66 20 61 6e 20 69 6e 74 65 72 72 75 70 74 20 68 61 73 20 61 72 72 69 76 65 64 2c 20 ┆ If an interrupt has arrived, ┆
0x9740…9760 62 75 74 20 6f 6e 20 61 6e 20 75 6e 65 78 70 65 63 74 65 64 20 6c 65 76 65 6c 2c 20 61 20 0a 6d ┆but on an unexpected level, a m┆
0x9760…9780 65 73 73 61 67 65 20 69 73 20 77 72 69 74 74 65 6e 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a ┆essage is written like this: ┆
0x9780…97a0 b0 69 41 50 58 31 38 36 20 73 6c 61 76 65 20 69 6e 74 65 72 72 75 70 74 20 74 65 73 74 3a 20 69 ┆ iAPX186 slave interrupt test: i┆
0x97a0…97c0 6c 6c 65 67 61 6c 20 6c 65 76 65 6c 20 73 65 72 76 69 63 65 64 2c 0d 0a 20 20 20 20 20 20 20 20 ┆llegal level serviced, ┆
0x97c0…97e0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 b0 20 20 20 20 20 20 20 20 20 ┆ ┆
0x97e0…9800 20 20 6c 65 76 2e 3a 20 3c 61 61 61 61 3e 0d 0a 0d 0a 54 68 65 20 63 6f 72 72 65 73 70 6f 6e 64 ┆ lev.: <aaaa> The correspond┆
0x9800…9820 (76,) 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 31 32 2e 0d 0a 0d 0a 77 68 65 72 65 ┆ing error number is 12. where┆
0x9820…9840 0d 0a 09 3c 61 61 61 61 3e 20 69 73 20 74 68 65 20 61 63 74 75 61 6c 20 6c 65 76 65 6c 20 74 68 ┆ <aaaa> is the actual level th┆
0x9840…9860 61 74 20 69 6e 74 65 72 72 75 70 74 65 64 2e 0d 0a 0d 0a 42 6f 74 68 20 65 72 72 6f 72 73 20 73 ┆at interrupted. Both errors s┆
0x9860…9880 68 6f 75 6c 64 20 62 65 20 6c 6f 63 61 6c 69 7a 65 64 20 69 6e 74 65 72 6e 61 6c 20 74 6f 20 74 ┆hould be localized internal to t┆
0x9880…9892 68 65 20 69 41 50 58 31 38 36 20 63 68 69 70 2e 0d 0a ┆he iAPX186 chip. ┆
0x9892…9895 FormFeed {
0x9892…9895 0c 82 f4 ┆ ┆
0x9892…9895 }
0x9895…98a0 0a b0 a1 31 33 2e 20 54 65 73 74 ┆ 13. Test┆
0x98a0…98c0 20 35 20 3d 20 45 74 68 65 72 6e 65 74 20 54 65 73 74 20 32 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 65 ┆ 5 = Ethernet Test 2. The e┆
0x98c0…98e0 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 20 61 70 70 6c 69 65 73 20 74 6f 20 74 68 65 20 76 65 ┆thernet test 2 applies to the ve┆
0x98e0…9900 72 69 66 69 63 61 74 69 6f 6e 20 6f 66 20 74 68 65 20 38 32 35 38 36 20 63 6f 2d 0a 70 72 6f 63 ┆rification of the 82586 co- proc┆
0x9900…9920 65 73 73 6f 72 20 61 6e 64 20 69 74 73 20 69 6e 74 65 72 66 61 63 65 20 63 69 72 63 75 69 74 72 ┆essor and its interface circuitr┆
0x9920…9940 79 2e 20 54 68 65 20 74 65 73 74 20 6d 61 6b 65 73 20 61 6e 20 65 78 74 65 72 6e 61 6c 20 0a 64 ┆y. The test makes an external d┆
0x9940…9960 61 74 61 20 6c 6f 6f 70 62 61 63 6b 20 74 65 73 74 20 6f 6e 20 74 68 65 20 65 74 68 65 72 6e 65 ┆ata loopback test on the etherne┆
0x9960…9980 74 20 63 68 69 70 2e 0d 0a 0d 0a 46 69 72 73 74 20 61 20 73 6f 66 74 77 61 72 65 20 72 65 73 65 ┆t chip. First a software rese┆
0x9980…99a0 74 20 6f 66 20 74 68 65 20 65 74 68 65 72 6e 65 74 20 63 68 69 70 20 69 73 20 6d 61 64 65 2e 20 ┆t of the ethernet chip is made. ┆
0x99a0…99c0 54 68 69 73 20 72 65 73 65 74 20 0a 63 61 75 73 65 73 20 74 68 65 20 65 74 68 65 72 6e 65 74 20 ┆This reset causes the ethernet ┆
0x99c0…99e0 63 6f 6e 74 72 6f 6c 6c 65 72 20 74 6f 20 69 73 73 75 65 20 61 6e 20 69 6e 74 65 72 72 75 70 74 ┆controller to issue an interrupt┆
0x99e0…9a00 20 77 68 65 6e 20 74 68 65 20 0a 72 65 73 65 74 20 69 73 20 63 6f 6d 70 6c 65 74 65 2e 20 49 66 ┆ when the reset is complete. If┆
0x9a00…9a20 (77,) 20 6e 6f 20 69 6e 74 65 72 72 75 70 74 20 69 73 20 72 65 63 65 69 76 65 64 20 61 6e 20 65 72 72 ┆ no interrupt is received an err┆
0x9a20…9a40 6f 72 20 6d 65 73 73 61 67 65 20 0a 69 73 20 67 65 6e 65 72 61 74 65 64 20 6c 69 6b 65 20 74 68 ┆or message is generated like th┆
0x9a40…9a60 69 73 3a 0d 0a 0d 0a b0 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 20 3a 20 6d 69 73 73 69 6e ┆is: Ethernet test 2 : missin┆
0x9a60…9a80 67 20 72 65 73 65 74 20 69 6e 74 65 72 72 75 70 74 0d 0a 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 ┆g reset interrupt Correspondi┆
0x9a80…9aa0 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 36 31 2e 0d 0a 0d 0a 53 65 63 6f 6e 64 ┆ng error number is 61. Second┆
0x9aa0…9ac0 20 61 20 63 6f 6e 66 69 67 75 72 65 20 63 6f 6d 6d 61 6e 64 20 69 73 20 65 78 65 63 75 74 65 64 ┆ a configure command is executed┆
0x9ac0…9ae0 20 74 6f 20 74 68 65 20 65 74 68 65 72 6e 65 74 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 0a 69 6e 20 ┆ to the ethernet controller in ┆
0x9ae0…9b00 6f 72 64 65 72 20 74 6f 20 73 65 6c 65 63 74 20 74 68 65 20 65 78 74 65 72 6e 61 6c 20 6c 6f 6f ┆order to select the external loo┆
0x9b00…9b20 70 62 61 63 6b 20 6d 6f 64 65 2e 20 41 67 61 69 6e 20 74 68 65 20 73 6c 65 66 74 65 73 74 20 0a ┆pback mode. Again the sleftest ┆
0x9b20…9b40 61 77 61 69 74 73 20 61 20 63 6f 6e 66 69 67 75 72 65 20 63 6f 6d 70 6c 65 74 65 20 69 6e 74 65 ┆awaits a configure complete inte┆
0x9b40…9b60 72 72 75 70 74 2c 20 61 6e 64 20 69 66 20 6e 6f 6e 65 20 69 73 20 72 65 63 65 69 76 65 64 20 61 ┆rrupt, and if none is received a┆
0x9b60…9b80 6e 20 0a 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 20 6c 69 ┆n error message is generated li┆
0x9b80…9ba0 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a b0 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 20 3a 20 63 ┆ke this: Ethernet test 2 : c┆
0x9ba0…9bc0 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 63 6f 6d 6d 61 6e 64 20 6e 6f 74 20 61 63 63 65 70 74 65 ┆onfiguration command not accepte┆
0x9bc0…9be0 64 0d 0a 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 ┆d Corresponding error number ┆
0x9be0…9c00 69 73 20 35 38 2e 0d 0a 0d 0a 54 68 69 72 64 20 61 20 74 72 61 6e 73 6d 69 74 20 66 72 61 6d 65 ┆is 58. Third a transmit frame┆
0x9c00…9c20 (78,) 20 63 6f 6d 6d 61 6e 64 20 69 73 20 65 78 65 63 75 74 65 64 2e 20 54 68 65 20 65 74 68 65 72 6e ┆ command is executed. The ethern┆
0x9c20…9c40 65 74 20 61 64 64 72 65 73 73 20 0a 69 73 20 74 68 65 20 62 72 6f 61 64 63 61 73 74 20 61 64 64 ┆et address is the broadcast add┆
0x9c40…9c60 72 65 73 73 20 61 6e 64 20 74 68 65 20 6d 65 73 73 61 67 65 20 6c 65 6e 67 74 68 20 69 73 20 31 ┆ress and the message length is 1┆
0x9c60…9c80 34 20 62 79 74 65 73 2e 20 49 66 20 0a 74 68 65 20 74 72 61 6e 73 6d 69 74 20 66 72 61 6d 65 20 ┆4 bytes. If the transmit frame ┆
0x9c80…9ca0 63 6f 6d 6d 61 6e 64 20 69 73 20 6e 6f 74 20 61 63 63 65 70 74 65 64 20 62 79 20 74 68 65 20 65 ┆command is not accepted by the e┆
0x9ca0…9cc0 74 68 65 72 6e 65 74 20 0a 63 6f 6e 74 72 6f 6c 6c 65 72 20 61 6e 20 65 72 72 6f 72 20 6d 65 73 ┆thernet controller an error mes┆
0x9cc0…9ce0 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a ┆sage is generated like this: ┆
0x9ce0…9d00 b0 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 20 3a 20 74 72 61 6e 73 6d 69 74 20 63 6f 6d 6d ┆ Ethernet test 2 : transmit comm┆
0x9d00…9d20 61 6e 64 20 20 6e 6f 74 20 61 63 63 65 70 74 65 64 0d 0a 0d 0a 63 6f 72 72 65 73 70 6f 6e 64 69 ┆and not accepted correspondi┆
0x9d20…9d40 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 35 39 2e 0d 0a 0d 0a 46 6f 75 72 74 68 ┆ng error number is 59. Fourth┆
0x9d40…9d60 2c 20 77 68 65 6e 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 66 72 61 6d 65 20 63 6f 6d 6d 61 6e ┆, when the transmit frame comman┆
0x9d60…9d80 64 20 69 73 20 63 6f 6d 70 6c 65 74 65 64 20 74 68 65 20 64 61 74 61 20 0a 73 65 6e 74 20 69 73 ┆d is completed the data sent is┆
0x9d80…9da0 20 63 6f 70 61 72 65 64 20 77 69 74 68 20 74 68 65 20 64 61 74 61 20 72 65 63 65 69 76 65 64 20 ┆ copared with the data received ┆
0x9da0…9dc0 61 6e 64 20 69 66 20 6e 6f 74 20 74 68 65 20 73 61 6d 65 20 61 6e 20 0a 65 72 72 6f 72 20 6d 65 ┆and if not the same an error me┆
0x9dc0…9de0 73 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 20 6f 74 68 65 72 77 69 73 65 20 74 68 65 ┆ssage is generated otherwise the┆
0x9de0…9e00 20 65 74 68 65 72 6e 65 74 20 69 6e 74 65 72 66 61 63 65 20 69 73 20 0a 73 61 69 64 20 74 6f 20 ┆ ethernet interface is said to ┆
0x9e00…9e20 (79,) 62 65 20 4f 4b 2e 0d 0a 0d 0a 8c 83 d4 0a b0 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 20 3a ┆be OK. Ethernet test 2 :┆
0x9e20…9e40 20 64 61 74 61 20 65 72 72 6f 72 20 20 61 64 64 2e 3a 3c 61 61 61 61 3e 2c 20 65 78 70 2e 3a 3c ┆ data error add.:<aaaa>, exp.:<┆
0x9e40…9e60 65 65 65 65 3e 2c 0d 0a b0 09 09 09 09 20 20 20 20 20 20 20 20 20 72 65 63 2e 3a 3c 72 72 72 72 ┆eeee>, rec.:<rrrr┆
0x9e60…9e80 3e 0d 0a 81 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 ┆> Corresponding error number┆
0x9e80…9ea0 20 69 73 20 36 30 2e 0d 0a 0d 0a 77 68 65 72 65 0d 0a 20 20 20 20 20 61 64 64 2e 3a 3c 61 61 61 ┆ is 60. where add.:<aaa┆
0x9ea0…9ec0 61 3e 20 69 73 20 6f 66 66 73 65 74 20 61 64 64 72 65 73 73 20 69 6e 20 74 68 65 20 72 65 63 65 ┆a> is offset address in the rece┆
0x9ec0…9ee0 69 76 65 20 62 75 66 66 65 72 0d 0a 20 20 20 20 20 65 78 70 2e 3a 3c 65 65 65 65 3e 20 69 73 20 ┆ive buffer exp.:<eeee> is ┆
0x9ee0…9f00 74 68 65 20 65 78 70 65 63 74 65 64 20 76 61 6c 75 65 20 66 72 6f 6d 20 74 68 65 20 74 72 61 6e ┆the expected value from the tran┆
0x9f00…9f20 73 6d 69 74 20 62 75 66 66 65 72 0d 0a 20 20 20 20 20 72 65 63 2e 3a 3c 72 72 72 72 3e 20 69 73 ┆smit buffer rec.:<rrrr> is┆
0x9f20…9f40 20 74 68 65 20 72 65 63 65 69 76 65 64 20 76 61 6c 75 65 20 69 6e 20 74 68 65 20 72 65 63 65 69 ┆ the received value in the recei┆
0x9f40…9f60 76 65 20 62 75 66 66 65 72 0d 0a 0d 0a 41 6e 6f 74 68 65 72 20 65 72 72 6f 72 20 6d 65 73 73 61 ┆ve buffer Another error messa┆
0x9f60…9f80 67 65 20 69 73 20 77 72 69 74 74 65 6e 20 69 66 20 74 68 65 20 65 74 68 65 72 6e 65 74 20 63 6f ┆ge is written if the ethernet co┆
0x9f80…9fa0 6e 74 72 6f 6c 6c 65 72 20 0a 67 65 6e 65 72 61 74 65 73 20 61 6e 20 69 6e 74 65 72 72 75 70 74 ┆ntroller generates an interrupt┆
0x9fa0…9fc0 20 77 69 74 68 6f 75 74 20 68 61 76 69 6e 67 20 72 65 73 65 74 20 74 68 65 20 63 6f 6d 6d 61 6e ┆ without having reset the comman┆
0x9fc0…9fe0 64 20 6a 75 73 74 20 0a 65 78 65 63 75 74 65 64 2e 0d 0a 0d 0a b0 45 74 68 65 72 6e 65 74 20 74 ┆d just executed. Ethernet t┆
0x9fe0…a000 65 73 74 20 32 20 3a 20 69 6e 74 65 72 72 75 70 74 20 62 75 74 20 63 6f 6d 6d 61 6e 64 20 77 6f ┆est 2 : interrupt but command wo┆
0xa000…a020 (80,) 72 64 20 6e 6f 74 20 63 6c 65 61 72 65 64 0d 0a 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 ┆rd not cleared Corresponding ┆
0xa020…a035 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 34 38 2e 0d 0a ┆error number is 48. ┆
0xa035…a038 FormFeed {
0xa035…a038 0c 81 cc ┆ ┆
0xa035…a038 }
0xa038…a040 0a b0 a1 31 34 2e 20 54 ┆ 14. T┆
0xa040…a060 65 73 74 20 36 20 3d 20 38 32 37 34 20 43 68 41 20 54 65 73 74 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 ┆est 6 = 8274 ChA Test. The ┆
0xa060…a080 38 32 37 34 20 74 65 73 74 20 61 70 70 6c 69 65 73 20 74 6f 20 74 68 65 20 76 65 72 69 66 69 63 ┆8274 test applies to the verific┆
0xa080…a0a0 61 74 69 6f 6e 20 6f 66 20 74 68 65 20 58 2e 32 31 20 61 6e 64 20 56 2e 32 34 20 0a 69 6e 74 65 ┆ation of the X.21 and V.24 inte┆
0xa0a0…a0c0 72 66 61 63 65 20 62 75 69 6c 64 20 61 72 6f 75 6e 64 20 74 68 65 20 4d 50 53 43 20 38 32 37 34 ┆rface build around the MPSC 8274┆
0xa0c0…a0e0 20 43 68 61 6e 6e 65 6c 20 41 2e 20 54 68 69 73 20 74 65 73 74 20 69 73 20 6e 6f 74 20 0a 70 61 ┆ Channel A. This test is not pa┆
0xa0e0…a100 72 74 20 6f 66 20 74 68 65 20 64 65 66 61 75 6c 74 20 70 6f 77 65 72 20 75 70 20 74 65 73 74 2e ┆rt of the default power up test.┆
0xa100…a120 20 49 74 20 6d 75 73 74 20 62 65 20 73 70 65 63 69 61 6c 6c 79 20 72 65 71 75 73 74 65 64 20 0a ┆ It must be specially requsted ┆
0xa120…a140 62 79 20 6f 70 65 72 61 74 6f 72 20 69 6e 74 65 72 76 65 6e 74 69 6f 6e 2e 20 42 65 66 6f 72 65 ┆by operator intervention. Before┆
0xa140…a160 20 65 78 65 63 75 74 69 6f 6e 20 6f 66 20 74 68 65 20 74 65 73 74 20 69 74 20 69 73 20 0a 6e 65 ┆ execution of the test it is ne┆
0xa160…a180 63 65 73 73 61 72 79 20 74 6f 20 69 6e 73 74 61 6c 6c 20 61 20 6c 6f 6f 70 62 61 63 6b 20 63 61 ┆cessary to install a loopback ca┆
0xa180…a1a0 62 6c 65 20 43 42 4c 20 37 38 38 28 72 65 61 72 20 63 61 62 69 6e 65 74 29 20 6f 72 20 0a 43 42 ┆ble CBL 788(rear cabinet) or CB┆
0xa1a0…a1c0 4c 20 37 38 39 20 28 63 61 72 64 20 65 64 67 65 29 2e 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 65 ┆L 789 (card edge). The test e┆
0xa1c0…a1e0 78 61 6d 69 6e 65 73 20 74 68 65 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 73 20 66 6f 72 20 62 ┆xamines the status signals for b┆
0xa1e0…a200 6f 74 68 20 74 68 65 20 58 2e 32 31 20 61 6e 64 20 74 68 65 20 0a 56 2e 32 34 20 69 6e 74 65 72 ┆oth the X.21 and the V.24 inter┆
0xa200…a220 (81,) 66 61 63 65 2e 20 41 20 64 61 74 61 74 65 73 74 20 69 6e 20 69 6e 74 65 72 72 75 70 74 20 64 72 ┆face. A datatest in interrupt dr┆
0xa220…a240 69 76 65 6e 20 6d 6f 64 65 20 69 73 20 6d 61 64 65 20 6f 6e 20 0a 62 6f 74 68 20 74 68 65 20 58 ┆iven mode is made on both the X┆
0xa240…a260 2e 32 31 20 61 6e 64 20 74 68 65 20 56 2e 32 34 20 69 6e 74 65 72 66 61 63 65 2e 20 54 68 65 20 ┆.21 and the V.24 interface. The ┆
0xa260…a280 63 61 70 61 62 69 6c 69 74 79 20 6f 66 20 0a 64 61 74 61 74 72 61 6e 73 70 6f 72 74 20 69 6e 20 ┆capability of datatransport in ┆
0xa280…a2a0 44 4d 41 20 64 72 69 76 65 6e 20 6d 6f 64 65 20 69 73 20 74 65 73 74 65 64 20 6f 6e 20 74 68 65 ┆DMA driven mode is tested on the┆
0xa2a0…a2c0 20 56 2e 32 34 20 69 6e 74 65 72 66 61 63 65 2e 0d 0a 0d 0a 49 66 20 6e 6f 20 6c 6f 6f 70 62 61 ┆ V.24 interface. If no loopba┆
0xa2c0…a2e0 63 6b 20 63 61 62 6c 65 20 69 73 20 69 6e 73 74 61 6c 6c 65 64 20 74 68 65 20 74 65 73 74 20 72 ┆ck cable is installed the test r┆
0xa2e0…a300 65 73 70 6f 6e 64 73 20 77 69 74 68 20 74 68 69 73 20 0a 6d 65 73 73 61 67 65 3a 0d 0a 0d 0a b0 ┆esponds with this message: ┆
0xa300…a320 38 32 37 34 20 43 48 41 20 74 65 73 74 20 3a 20 4e 6f 20 74 65 73 74 70 6c 75 67 20 69 6e 73 74 ┆8274 CHA test : No testplug inst┆
0xa320…a340 61 6c 6c 65 64 2e 0d 0a 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 ┆alled. Corresponding error nu┆
0xa340…a360 6d 62 65 72 20 69 73 20 35 35 2e 0d 0a 0d 0a 4e 6f 74 65 20 74 68 61 74 20 74 68 69 73 20 74 65 ┆mber is 55. Note that this te┆
0xa360…a380 73 74 20 72 69 73 65 73 20 74 68 65 20 2f 52 54 53 20 66 72 6f 6d 20 74 68 65 20 4d 50 53 43 20 ┆st rises the /RTS from the MPSC ┆
0xa380…a3a0 38 32 37 34 20 74 6f 20 74 65 73 74 20 69 66 20 0a 74 68 65 20 74 65 73 74 70 6c 75 67 20 69 73 ┆8274 to test if the testplug is┆
0xa3a0…a3c0 20 70 72 65 73 65 6e 74 2e 20 54 68 65 72 65 66 6f 72 65 20 74 68 69 73 20 65 72 72 6f 72 20 6d ┆ present. Therefore this error m┆
0xa3c0…a3e0 61 79 20 62 65 20 63 61 75 73 65 64 20 62 79 20 61 20 0a 68 61 72 64 77 61 72 65 20 65 72 72 6f ┆ay be caused by a hardware erro┆
0xa3e0…a400 72 20 69 6e 73 74 65 61 64 20 6f 66 20 6d 69 73 73 69 6e 67 20 74 65 73 74 70 6c 75 67 2e 0d 0a ┆r instead of missing testplug. ┆
0xa400…a420 (82,) 0d 0a 49 66 20 61 6e 20 65 72 72 6f 72 20 69 73 20 64 65 74 65 63 74 65 64 20 64 75 72 69 6e 67 ┆ If an error is detected during┆
0xa420…a440 20 74 68 65 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 20 74 65 73 74 20 61 6e 20 65 72 72 6f 72 ┆ the status signal test an error┆
0xa440…a460 20 0a 6d 65 73 73 61 67 65 20 69 73 20 77 72 69 74 74 65 6e 2e 0d 0a 0d 0a b0 38 32 37 34 20 43 ┆ message is written. 8274 C┆
0xa460…a480 48 41 20 74 65 73 74 20 3a 20 56 2e 32 34 20 73 74 61 74 75 73 20 65 72 72 6f 72 20 20 65 78 70 ┆HA test : V.24 status error exp┆
0xa480…a4a0 2e 3a 3c 30 30 30 65 3e 2c 20 72 65 63 2e 3a 3c 30 30 30 72 3e 0d 0a 0d 0a 43 6f 72 72 65 73 70 ┆.:<000e>, rec.:<000r> Corresp┆
0xa4a0…a4c0 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 35 33 2e 0d 0a 0d 0a 4f 52 ┆onding error number is 53. OR┆
0xa4c0…a4e0 0d 0a 0d 0a b0 38 32 37 34 20 43 48 41 20 74 65 73 74 20 3a 20 58 2e 32 31 20 73 74 61 74 75 73 ┆ 8274 CHA test : X.21 status┆
0xa4e0…a500 20 65 72 72 6f 72 20 20 65 78 70 2e 3a 3c 30 30 30 65 3e 2c 20 72 65 63 2e 3a 3c 30 30 30 72 3e ┆ error exp.:<000e>, rec.:<000r>┆
0xa500…a520 0d 0a 82 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 ┆ Corresponding error number ┆
0xa520…a540 69 73 20 35 34 2e 0d 0a 0d 0a 8c 83 d4 0a 54 68 65 20 72 65 63 65 69 76 65 64 20 76 61 6c 75 65 ┆is 54. The received value┆
0xa540…a560 20 68 6f 6c 64 73 20 74 68 65 20 72 65 63 65 69 76 65 64 20 43 54 53 2c 20 44 43 44 2c 20 43 49 ┆ holds the received CTS, DCD, CI┆
0xa560…a580 20 61 6e 73 20 44 53 52 20 0a 73 69 67 6e 61 6c 73 2e 20 49 6e 20 74 68 65 20 56 2e 32 34 20 73 ┆ ans DSR signals. In the V.24 s┆
0xa580…a5a0 74 61 74 75 73 20 74 65 73 74 20 74 68 65 20 64 69 66 66 65 72 65 6e 63 65 20 62 65 74 77 65 65 ┆tatus test the difference betwee┆
0xa5a0…a5c0 6e 20 65 78 70 65 63 74 65 64 20 0a 61 6e 64 20 72 65 63 65 69 76 65 64 20 6d 75 73 74 20 62 65 ┆n expected and received must be┆
0xa5c0…a5e0 20 69 6e 74 65 72 70 72 65 74 65 64 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a 09 65 78 70 65 ┆ interpreted like this: expe┆
0xa5e0…a600 63 74 65 64 20 62 69 74 20 30 20 6e 6f 74 20 65 71 75 61 6c 20 72 65 63 65 69 76 65 64 20 62 69 ┆cted bit 0 not equal received bi┆
0xa600…a620 (83,) 74 20 30 20 3d 20 44 43 44 20 65 72 72 6f 72 0d 0a 09 65 78 70 65 63 74 65 64 20 62 69 74 20 32 ┆t 0 = DCD error expected bit 2┆
0xa620…a640 20 6e 6f 74 20 65 71 75 61 6c 20 72 65 63 65 69 76 65 64 20 62 69 74 20 32 20 3d 20 43 54 53 20 ┆ not equal received bit 2 = CTS ┆
0xa640…a660 65 72 72 6f 72 0d 0a 09 65 78 70 65 63 74 65 64 20 62 69 74 20 33 20 6e 6f 74 20 65 71 75 61 6c ┆error expected bit 3 not equal┆
0xa660…a680 20 72 65 63 65 69 76 65 64 20 62 69 74 20 33 20 3d 20 43 49 20 65 72 72 6f 72 0d 0a 09 65 78 70 ┆ received bit 3 = CI error exp┆
0xa680…a6a0 65 63 74 65 64 20 62 69 74 20 34 20 6e 6f 74 20 65 71 75 61 6c 20 72 65 63 65 69 76 65 64 20 62 ┆ected bit 4 not equal received b┆
0xa6a0…a6c0 69 74 20 34 20 3d 20 44 53 52 20 65 72 72 6f 72 0d 0a 0d 0a 49 6e 20 74 68 65 20 58 2e 32 31 20 ┆it 4 = DSR error In the X.21 ┆
0xa6c0…a6e0 73 74 61 74 75 73 20 74 65 73 74 20 74 68 65 20 64 69 66 66 65 72 65 6e 63 65 20 62 65 74 77 65 ┆status test the difference betwe┆
0xa6e0…a700 65 6e 20 65 78 70 65 63 74 65 64 20 61 6e 64 20 0a 72 65 63 65 69 76 65 64 20 76 61 6c 75 65 20 ┆en expected and received value ┆
0xa700…a720 6d 75 73 74 20 62 65 20 69 6e 74 65 70 72 65 74 65 64 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d ┆must be intepreted like this: ┆
0xa720…a740 0a 09 65 78 70 65 63 74 65 64 20 62 69 74 20 30 20 6e 6f 74 20 65 71 75 61 6c 20 72 65 63 65 69 ┆ expected bit 0 not equal recei┆
0xa740…a760 76 65 64 20 62 69 74 20 30 20 3d 20 84 43 6c 65 61 72 69 6e 67 20 53 74 61 74 65 20 0a 19 ae 80 ┆ved bit 0 = Clearing State ┆
0xa760…a780 80 65 72 72 6f 72 20 28 44 43 44 29 0d 0a 09 65 78 70 65 63 74 65 64 20 62 69 74 20 32 20 6e 6f ┆ error (DCD) expected bit 2 no┆
0xa780…a7a0 74 20 65 71 75 61 6c 20 72 65 63 65 69 76 65 64 20 62 69 74 20 32 20 3d 20 84 49 6e 64 69 63 61 ┆t equal received bit 2 = Indica┆
0xa7a0…a7c0 74 69 6f 6e 20 65 72 72 6f 72 20 0a 19 ae 80 80 28 43 54 53 29 0d 0a 09 65 78 70 65 63 74 65 64 ┆tion error (CTS) expected┆
0xa7c0…a7e0 20 62 69 74 20 33 20 6e 6f 74 20 65 71 75 61 6c 20 72 65 63 65 69 76 65 64 20 62 69 74 20 33 20 ┆ bit 3 not equal received bit 3 ┆
0xa7e0…a800 3d 20 84 43 6c 65 61 72 69 6e 67 20 73 74 61 74 65 20 0a 19 ae 80 80 65 72 72 6f 72 20 28 44 43 ┆= Clearing state error (DC┆
0xa800…a820 (84,) 44 29 0d 0a 09 65 78 70 65 63 74 65 64 20 62 69 74 20 34 20 6e 6f 74 20 65 71 75 61 6c 20 72 65 ┆D) expected bit 4 not equal re┆
0xa820…a840 63 65 69 76 65 64 20 62 69 74 20 34 20 3d 20 84 49 6e 64 69 63 61 74 69 6f 6e 20 65 72 72 6f 72 ┆ceived bit 4 = Indication error┆
0xa840…a860 20 0a 19 ae 80 80 28 43 54 53 29 0d 0a 0d 0a 0d 0a 49 66 20 61 6e 20 65 72 72 6f 72 20 69 73 20 ┆ (CTS) If an error is ┆
0xa860…a880 64 65 74 65 63 74 65 64 20 64 75 72 69 6e 67 20 74 68 65 20 64 61 74 61 20 74 65 73 74 20 6f 6e ┆detected during the data test on┆
0xa880…a8a0 65 20 6f 66 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 0a 65 72 72 6f 72 6d 65 73 73 61 67 65 ┆e of the following errormessage┆
0xa8a0…a8c0 73 20 61 72 65 20 70 72 6f 64 75 63 65 64 3a 0d 0a 0d 0a b0 38 32 37 34 20 43 48 41 20 74 65 73 ┆s are produced: 8274 CHA tes┆
0xa8c0…a8e0 74 20 3a 20 56 2e 32 34 20 64 61 74 61 20 65 72 72 6f 72 20 20 61 64 64 72 2e 3a 3c 61 61 61 61 ┆t : V.24 data error addr.:<aaaa┆
0xa8e0…a900 3e 2c 20 65 78 70 2e 3a 3c 65 65 65 65 3e 2c 0d 0a 19 80 81 82 09 09 09 09 20 20 20 20 20 20 20 ┆>, exp.:<eeee>, ┆
0xa900…a920 20 20 20 20 20 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 81 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 ┆ rec.:<rrrr> Correspond┆
0xa920…a940 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 34 39 2e 0d 0a 0d 0a 0d 0a b0 38 32 ┆ing error number is 49. 82┆
0xa940…a960 37 34 20 43 48 41 20 74 65 73 74 20 3a 20 58 2e 32 31 20 64 61 74 61 20 65 72 72 6f 72 20 20 61 ┆74 CHA test : X.21 data error a┆
0xa960…a980 64 64 72 2e 3a 3c 61 61 61 61 3e 2c 20 65 78 70 2e 3a 3c 65 65 65 65 3e 2c 0d 0a b0 09 09 09 09 ┆ddr.:<aaaa>, exp.:<eeee>, ┆
0xa980…a9a0 09 20 20 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 81 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e ┆ rec.:<rrrr> Correspondin┆
0xa9a0…a9c0 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 35 31 2e 0d 0a 0d 0a b0 38 32 37 34 20 43 ┆g error number is 51. 8274 C┆
0xa9c0…a9e0 48 41 20 74 65 73 74 20 3a 20 44 4d 41 20 64 61 74 61 20 65 72 72 6f 72 20 20 61 64 64 72 2e 3a ┆HA test : DMA data error addr.:┆
0xa9e0…aa00 3c 61 61 61 61 3e 2c 20 65 78 70 2e 3a 3c 65 65 65 65 3e 2c 0d 0a b0 09 09 09 09 09 20 20 72 65 ┆<aaaa>, exp.:<eeee>, re┆
0xaa00…aa20 (85,) 63 2e 3a 3c 72 72 72 72 3e 0d 0a 8c 83 c8 0a 81 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 ┆c.:<rrrr> Corresponding ┆
0xaa20…aa40 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 35 37 2e 0d 0a 0d 0a 77 68 65 72 65 0d 0a 20 20 ┆error number is 57. where ┆
0xaa40…aa60 20 20 20 61 64 64 2e 3a 3c 61 61 61 61 3e 20 69 73 20 6f 66 66 73 65 74 20 61 64 64 72 65 73 73 ┆ add.:<aaaa> is offset address┆
0xaa60…aa80 20 69 6e 20 74 68 65 20 72 65 63 65 69 76 65 20 62 75 66 66 65 72 0d 0a 20 20 20 20 20 65 78 70 ┆ in the receive buffer exp┆
0xaa80…aaa0 2e 3a 3c 65 65 65 65 3e 20 69 73 20 74 68 65 20 65 78 70 65 63 74 65 64 20 76 61 6c 75 65 20 66 ┆.:<eeee> is the expected value f┆
0xaaa0…aac0 72 6f 6d 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 62 75 66 66 65 72 0d 0a 20 20 20 20 20 72 65 ┆rom the transmit buffer re┆
0xaac0…aae0 63 2e 3a 3c 72 72 72 72 3e 20 69 73 20 74 68 65 20 72 65 63 65 69 76 65 64 20 76 61 6c 75 65 20 ┆c.:<rrrr> is the received value ┆
0xaae0…ab00 69 6e 20 74 68 65 20 72 65 63 65 69 76 65 20 62 75 66 66 65 72 0d 0a 0d 0a 54 68 65 20 64 61 74 ┆in the receive buffer The dat┆
0xab00…ab20 61 20 74 65 73 74 20 6f 66 20 74 68 65 20 38 32 37 34 20 69 73 20 65 78 65 63 75 74 65 64 20 77 ┆a test of the 8274 is executed w┆
0xab20…ab40 69 74 68 20 38 32 37 34 20 69 6e 74 65 72 72 75 70 74 73 20 0a 65 6e 61 62 65 6c 65 64 2e 20 49 ┆ith 8274 interrupts enabeled. I┆
0xab40…ab60 66 20 61 20 65 78 63 65 70 74 69 6f 6e 20 69 6e 74 65 72 72 75 70 74 73 20 69 73 20 72 65 63 65 ┆f a exception interrupts is rece┆
0xab60…ab80 69 76 65 64 20 64 75 72 69 6e 67 20 74 68 65 20 0a 64 61 74 61 20 74 72 61 6e 73 66 65 72 20 61 ┆ived during the data transfer a┆
0xab80…aba0 6e 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 69 73 20 70 72 6f 64 75 63 65 64 2e 0d 0a 0d 0a ┆n error message is produced. ┆
0xaba0…abc0 49 66 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 6f 63 63 75 72 20 69 6e 20 74 68 65 20 69 6e ┆If the interrupt occur in the in┆
0xabc0…abe0 74 65 72 72 75 70 74 20 64 72 69 76 65 6e 20 6d 6f 64 65 20 61 20 6d 65 73 73 61 67 65 20 69 73 ┆terrupt driven mode a message is┆
0xabe0…ac00 20 0a 67 65 6e 65 72 61 74 65 64 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a b0 b0 38 32 37 34 ┆ generated like this: 8274┆
0xac00…ac20 (86,) 20 43 48 41 20 74 65 73 74 20 3a 20 49 6e 74 65 72 72 75 70 74 65 72 72 6f 72 20 69 6e 20 69 6e ┆ CHA test : Interrupterror in in┆
0xac20…ac40 74 65 72 72 75 70 74 6d 6f 64 65 20 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 0d 0a 43 6f 72 72 ┆terruptmode rec.:<rrrr> Corr┆
0xac40…ac60 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 35 32 2e 0d 0a 0d ┆esponding error number is 52. ┆
0xac60…ac80 0a 49 66 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 6f 63 63 75 72 20 69 6e 20 74 68 65 20 44 ┆ If the interrupt occur in the D┆
0xac80…aca0 4d 41 20 6d 6f 64 65 20 61 20 6d 65 73 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 20 0a ┆MA mode a message is generated ┆
0xaca0…acc0 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a b0 38 32 37 34 20 43 48 41 20 74 65 73 74 20 3a 20 49 ┆like this: 8274 CHA test : I┆
0xacc0…ace0 6e 74 65 72 72 75 70 74 65 72 72 6f 72 20 69 6e 20 44 4d 41 20 6d 6f 64 65 20 20 72 65 63 2e 3a ┆nterrupterror in DMA mode rec.:┆
0xace0…ad00 3c 72 72 72 72 3e 0d 0a 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 ┆<rrrr> Corresponding error nu┆
0xad00…ad20 6d 62 65 72 20 69 73 20 35 36 2e 0d 0a 0d 0a 57 68 65 72 65 0d 0a 20 20 20 20 20 84 72 65 63 2e ┆mber is 56. Where rec.┆
0xad20…ad40 3a 3c 72 72 72 72 3e 20 68 6f 6c 64 73 20 74 68 65 20 76 65 63 74 6f 72 63 6f 64 65 20 72 65 6c ┆:<rrrr> holds the vectorcode rel┆
0xad40…ad60 61 74 65 64 20 74 6f 20 74 68 65 20 65 78 63 65 70 74 69 6f 6e 20 0a 19 85 80 80 69 6e 74 65 72 ┆ated to the exception inter┆
0xad60…ad80 72 75 70 74 2e 0d 0a 0d 0a 49 66 20 74 68 65 20 64 61 74 61 20 74 72 61 6e 73 66 65 72 20 69 73 ┆rupt. If the data transfer is┆
0xad80…ada0 20 6e 6f 74 20 63 6f 6d 70 6c 65 74 65 64 20 77 69 74 68 69 6e 20 32 35 30 20 6d 73 2e 20 61 20 ┆ not completed within 250 ms. a ┆
0xada0…adc0 74 69 6d 65 6f 75 74 20 0a 6d 65 73 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 2e 0d 0a ┆timeout message is generated. ┆
0xadc0…ade0 0d 0a b0 38 32 37 34 20 43 48 41 20 74 65 73 74 20 3a 20 54 69 6d 65 6f 75 74 0d 0a 0d 0a 43 6f ┆ 8274 CHA test : Timeout Co┆
0xade0…ae00 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 35 30 2e 0d ┆rresponding error number is 50. ┆
0xae00…ae20 (87,) 0a 0d 0a 8c 83 bc 0a 54 68 69 73 20 6d 65 73 73 61 67 65 20 73 68 6f 75 6c 7b 64 20 69 6e 64 69 ┆ This message shoulæd indi┆
0xae20…ae40 63 61 74 65 20 74 68 61 74 20 74 68 65 20 38 32 37 34 20 69 6e 74 65 72 72 75 70 74 20 73 79 73 ┆cate that the 8274 interrupt sys┆
0xae40…ae4e 74 65 6d 20 0a 66 61 69 6c 65 64 2e 0d 0a ┆tem failed. ┆
0xae4e…ae51 FormFeed {
0xae4e…ae51 0c 80 98 ┆ ┆
0xae4e…ae51 }
0xae51…ae60 0a b0 a1 31 35 2e 20 54 65 73 74 20 37 20 3d ┆ 15. Test 7 =┆
0xae60…ae80 20 46 6c 6f 70 70 79 20 54 65 73 74 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 66 6c 6f 70 70 79 20 74 65 ┆ Floppy Test. The floppy te┆
0xae80…aea0 73 74 20 61 70 70 6c 69 65 73 20 74 6f 20 74 68 65 20 76 65 72 69 66 69 63 61 74 69 6f 6e 20 6f ┆st applies to the verification o┆
0xaea0…aec0 66 20 74 68 65 20 66 75 6e 63 74 69 6f 6e 61 6c 69 74 79 20 0a 6f 66 20 74 68 65 20 46 44 43 36 ┆f the functionality of the FDC6┆
0xaec0…aee0 30 31 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 61 6e 64 20 61 74 74 61 63 68 65 64 20 68 61 72 64 77 ┆01 controller and attached hardw┆
0xaee0…af00 61 72 65 2e 20 54 68 65 20 46 44 43 36 30 31 20 69 73 20 61 20 0a 69 53 42 58 20 28 53 69 6e 67 ┆are. The FDC601 is a iSBX (Sing┆
0xaf00…af20 6c 65 20 42 6f 61 72 64 20 65 58 74 65 6e 74 69 6f 6e 29 20 63 6f 6e 74 72 6f 6c 6c 65 72 2e 20 ┆le Board eXtention) controller. ┆
0xaf20…af40 54 68 65 20 74 65 73 74 20 73 68 6f 75 6c 64 20 6e 6f 74 20 62 65 20 0a 65 78 65 63 75 74 65 64 ┆The test should not be executed┆
0xaf40…af60 20 69 66 20 6e 6f 20 46 44 43 36 30 31 20 69 73 20 70 72 65 73 65 6e 74 2e 0d 0a 0d 0a 54 68 65 ┆ if no FDC601 is present. The┆
0xaf60…af80 20 74 65 73 74 20 69 73 20 61 6e 20 45 78 74 65 6e 64 65 64 20 74 65 73 74 20 77 68 69 63 68 20 ┆ test is an Extended test which ┆
0xaf80…afa0 69 73 20 6e 6f 74 20 65 78 65 63 75 74 65 64 20 62 79 20 64 65 66 61 75 6c 74 20 0a 61 66 74 65 ┆is not executed by default afte┆
0xafa0…afc0 72 20 70 6f 77 65 72 20 6f 6e 2c 20 62 75 74 20 6f 6e 6c 79 20 77 68 65 6e 20 72 65 71 75 65 73 ┆r power on, but only when reques┆
0xafc0…afe0 74 65 64 20 65 78 70 6c 69 63 69 74 65 6c 79 20 62 79 20 61 6e 20 0a 6f 70 65 72 61 74 6f 72 20 ┆ted explicitely by an operator ┆
0xafe0…b000 73 65 6c 65 63 74 69 6e 67 20 6c 6f 6f 70 20 69 6e 20 74 65 73 74 20 6e 6f 2e 20 37 2c 20 6f 72 ┆selecting loop in test no. 7, or┆
0xb000…b020 (88,) 20 73 65 74 74 69 6e 67 20 74 68 65 20 22 62 6f 6f 74 20 61 66 74 65 72 20 0a 74 65 73 74 22 20 ┆ setting the "boot after test" ┆
0xb020…b040 74 6f 20 22 4e 22 2e 0d 0a 0d 0a 54 68 65 20 70 72 6f 63 65 64 75 72 65 20 6f 66 20 74 68 65 20 ┆to "N". The procedure of the ┆
0xb040…b060 74 65 73 74 20 69 73 20 74 6f 20 77 72 69 74 65 2c 20 72 65 61 64 20 61 6e 64 20 63 6f 6d 70 61 ┆test is to write, read and compa┆
0xb060…b080 72 65 20 61 20 73 65 74 20 6f 66 20 0a 74 65 73 74 20 70 61 74 74 65 72 6e 20 6f 76 65 72 20 61 ┆re a set of test pattern over a┆
0xb080…b0a0 20 73 65 74 20 6f 66 20 74 72 61 63 6b 73 20 6f 6e 20 74 68 65 20 66 6c 6f 70 70 79 20 64 69 73 ┆ set of tracks on the floppy dis┆
0xb0a0…b0c0 6b 2e 20 54 68 65 20 74 65 73 74 20 0a 75 73 65 20 6f 6e 6c 79 20 73 65 63 74 6f 72 20 6f 6e 65 ┆k. The test use only sector one┆
0xb0c0…b0e0 20 6f 6e 20 74 68 65 20 74 72 61 63 6b 73 2c 20 62 75 74 20 62 6f 74 68 20 73 69 64 65 73 20 6f ┆ on the tracks, but both sides o┆
0xb0e0…b100 66 20 74 68 65 20 66 6c 6f 70 70 79 20 0a 64 69 73 63 20 61 72 65 20 74 65 73 74 65 64 2e 0d 0a ┆f the floppy disc are tested. ┆
0xb100…b120 0d 0a 0d 0a a1 31 35 2e 31 20 54 65 73 74 20 52 65 73 75 6c 74 73 2e 0d 0a 0d 0a 0d 0a 54 68 65 ┆ 15.1 Test Results. The┆
0xb120…b140 20 66 6c 6f 70 70 79 20 74 65 73 74 20 77 69 6c 6c 20 72 65 73 70 6f 6e 64 20 77 69 74 68 20 6f ┆ floppy test will respond with o┆
0xb140…b160 6e 65 20 6f 66 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 74 65 78 74 73 20 74 6f 20 0a 69 6e ┆ne of the following texts to in┆
0xb160…b180 66 6f 72 6d 20 74 68 65 20 6f 70 65 72 61 74 6f 72 20 61 62 6f 75 74 20 74 68 65 20 6f 75 74 63 ┆form the operator about the outc┆
0xb180…b1a0 6f 6d 65 20 6f 66 20 74 68 65 20 74 65 73 74 2e 0d 0a 0d 0a b0 b0 46 6c 6f 70 70 79 20 74 65 73 ┆ome of the test. Floppy tes┆
0xb1a0…b1c0 74 20 3a 20 4f 4b 0d 0a 0d 0a 54 68 65 20 72 65 73 75 6c 74 20 22 4f 4b 22 20 69 6e 64 69 63 61 ┆t : OK The result "OK" indica┆
0xb1c0…b1e0 74 65 73 20 61 20 77 65 6c 6c 20 73 75 63 63 65 64 65 64 20 77 72 69 74 69 6e 67 2f 72 65 61 64 ┆tes a well succeded writing/read┆
0xb1e0…b200 69 6e 67 20 61 6e 64 20 0a 63 6f 6d 70 61 72 69 6e 67 20 66 6f 72 20 61 6c 6c 20 73 65 63 74 6f ┆ing and comparing for all secto┆
0xb200…b220 (89,) 72 73 20 74 65 73 74 65 64 20 61 73 20 77 65 6c 6c 20 61 73 20 70 72 6f 70 65 72 20 66 75 6e 63 ┆rs tested as well as proper func┆
0xb220…b240 74 69 6f 6e 69 6e 67 20 0a 68 61 72 64 77 61 72 65 2c 20 65 2e 67 2e 20 69 6e 74 65 72 72 75 70 ┆tioning hardware, e.g. interrup┆
0xb240…b260 74 20 73 79 73 74 65 6d 20 61 6e 64 20 44 4d 41 20 74 72 61 6e 73 66 65 72 72 69 6e 67 2e 0d 0a ┆t system and DMA transferring. ┆
0xb260…b280 0d 0a b0 46 6c 6f 70 70 79 20 74 65 73 74 20 3a 20 46 44 43 36 30 31 20 6e 6f 74 20 69 6e 73 74 ┆ Floppy test : FDC601 not inst┆
0xb280…b2a0 61 6c 6c 65 64 0d 0a b0 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 ┆alled Corresponding error nu┆
0xb2a0…b2c0 6d 62 65 72 20 69 73 20 33 39 2e 0d 0a 0d 0a 54 68 65 20 72 65 73 75 6c 74 20 22 46 44 43 36 30 ┆mber is 39. The result "FDC60┆
0xb2c0…b2e0 31 20 6e 6f 74 20 69 6e 73 74 61 6c 6c 65 64 22 20 69 73 20 65 76 69 64 65 6e 74 2c 20 65 2e 67 ┆1 not installed" is evident, e.g┆
0xb2e0…b300 2e 20 74 68 65 20 53 42 58 20 62 6f 61 72 64 20 0a 46 44 43 36 30 31 20 69 73 20 6e 6f 74 20 69 ┆. the SBX board FDC601 is not i┆
0xb300…b320 6e 73 74 61 6c 6c 65 64 20 6f 6e 20 74 6f 70 20 6f 66 20 74 68 65 20 45 54 43 36 30 31 20 62 6f ┆nstalled on top of the ETC601 bo┆
0xb320…b340 61 72 64 2e 0d 0a 0d 0a 8c 83 c8 0a b0 46 6c 6f 70 70 79 20 74 65 73 74 20 3a 20 64 72 69 76 65 ┆ard. Floppy test : drive┆
0xb340…b360 20 6e 6f 74 20 72 65 61 64 79 0d 0a 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f ┆ not ready Corresponding erro┆
0xb360…b380 72 20 6e 75 6d 62 65 72 20 69 73 20 33 31 2e 0d 0a 0d 0a 54 68 65 20 72 65 73 75 6c 74 20 22 64 ┆r number is 31. The result "d┆
0xb380…b3a0 72 69 76 65 20 6e 6f 74 20 72 65 61 64 79 22 20 6e 6f 72 6d 61 6c 6c 79 20 69 6e 64 69 63 61 74 ┆rive not ready" normally indicat┆
0xb3a0…b3c0 65 73 20 74 68 61 74 20 6e 6f 20 64 69 73 63 20 69 73 20 0a 69 6e 73 74 61 6c 6c 65 64 20 69 6e ┆es that no disc is installed in┆
0xb3c0…b3e0 20 74 68 65 20 64 72 69 76 65 20 6f 72 20 74 68 65 20 64 6f 6f 72 20 69 73 20 6e 6f 74 20 63 6c ┆ the drive or the door is not cl┆
0xb3e0…b400 6f 73 65 64 2e 20 49 66 20 74 68 65 73 65 20 0a 70 72 65 63 61 75 74 69 6f 6e 73 20 61 72 65 20 ┆osed. If these precautions are ┆
0xb400…b420 (90,) 73 61 74 69 73 66 69 65 64 2c 20 61 20 68 61 72 64 20 65 72 72 6f 72 20 65 78 69 73 74 2c 20 65 ┆satisfied, a hard error exist, e┆
0xb420…b440 2e 67 2e 20 62 61 64 20 64 72 69 76 65 2c 20 0a 62 61 64 20 46 44 43 36 30 31 20 62 6f 61 72 64 ┆.g. bad drive, bad FDC601 board┆
0xb440…b460 2c 20 6d 69 73 73 69 6e 67 20 63 61 62 6c 65 73 20 74 69 20 74 68 65 20 64 72 69 76 65 2c 20 65 ┆, missing cables ti the drive, e┆
0xb460…b480 74 63 2e 0d 0a 0d 0a b0 46 6c 6f 70 70 79 20 74 65 73 74 20 3a 20 77 72 69 74 65 20 70 72 6f 74 ┆tc. Floppy test : write prot┆
0xb480…b4a0 65 63 74 0d 0a b0 0d 0a 43 6f 72 72 6f 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 ┆ect Corrosponding error numb┆
0xb4a0…b4c0 65 72 20 69 73 20 33 32 2e 0d 0a 0d 0a 54 68 65 20 72 65 73 75 6c 74 20 22 77 72 69 74 65 20 70 ┆er is 32. The result "write p┆
0xb4c0…b4e0 72 6f 74 65 63 74 22 20 69 73 20 65 76 69 64 65 6e 74 2c 20 65 2e 67 2e 20 74 68 65 20 69 6e 73 ┆rotect" is evident, e.g. the ins┆
0xb4e0…b500 65 72 74 65 64 20 66 6c 6f 70 70 79 20 0a 64 69 73 6b 20 69 73 20 77 72 69 74 65 20 70 72 6f 74 ┆erted floppy disk is write prot┆
0xb500…b520 65 63 74 65 64 2e 20 52 65 6d 6f 76 65 20 74 68 65 20 64 69 73 6b 20 70 72 6f 74 65 63 74 69 6f ┆ected. Remove the disk protectio┆
0xb520…b540 6e 20 66 6f 72 20 70 72 6f 70 65 72 20 0a 66 75 6e 63 74 69 6f 6e 2e 0d 0a 0d 0a b0 46 6c 6f 70 ┆n for proper function. Flop┆
0xb540…b560 70 79 20 74 65 73 74 20 3a 20 73 65 65 6b 20 65 72 72 6f 72 0d 0a b0 0d 0a 43 6f 72 72 65 73 70 ┆py test : seek error Corresp┆
0xb560…b580 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 33 33 2e 0d 0a 0d 0a b0 46 ┆onding error number is 33. F┆
0xb580…b5a0 6c 6f 70 70 79 20 74 65 73 74 20 3a 20 43 52 43 20 65 72 72 6f 72 0d 0a b0 0d 0a 43 6f 72 72 65 ┆loppy test : CRC error Corre┆
0xb5a0…b5c0 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 33 34 2e 0d 0a 0d 0a ┆sponding error number is 34. ┆
0xb5c0…b5e0 b0 46 6c 6f 70 70 79 20 74 65 73 74 20 3a 20 72 65 63 6f 72 64 20 6e 6f 74 20 66 6f 75 6e 64 0d ┆ Floppy test : record not found ┆
0xb5e0…b600 0a b0 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 ┆ Corresponding error number i┆
0xb600…b620 (91,) 73 20 33 35 2e 0d 0a 0d 0a 54 68 65 20 72 65 73 75 6c 74 20 22 73 65 65 6b 20 65 72 72 6f 72 22 ┆s 35. The result "seek error"┆
0xb620…b640 2c 20 22 43 52 43 20 65 72 72 6f 72 22 20 61 6e 64 20 22 72 65 63 6f 72 64 20 6e 6f 74 20 66 6f ┆, "CRC error" and "record not fo┆
0xb640…b660 75 6e 64 22 20 0a 6e 6f 72 6d 61 6c 6c 79 20 69 6e 64 69 63 61 74 65 73 20 61 20 68 61 72 64 20 ┆und" normally indicates a hard ┆
0xb660…b680 65 72 72 6f 72 20 6f 6e 20 74 68 65 20 69 6e 73 65 72 74 65 64 20 64 69 73 6b 20 6f 72 20 74 68 ┆error on the inserted disk or th┆
0xb680…b6a0 61 74 20 74 68 65 20 0a 64 69 73 63 20 69 73 20 6e 6f 74 20 66 6f 72 6d 61 74 74 65 64 20 63 6f ┆at the disc is not formatted co┆
0xb6a0…b6c0 72 72 65 63 74 2e 0d 0a 0d 0a b0 46 6c 6f 70 70 79 20 74 65 73 74 20 3a 20 6c 6f 73 74 20 64 61 ┆rrect. Floppy test : lost da┆
0xb6c0…b6e0 74 61 0d 0a b0 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 ┆ta Corresponding error numbe┆
0xb6e0…b700 72 20 69 73 20 33 36 2e 0d 0a 0d 0a 8c 83 bc 0a 54 68 65 20 72 65 73 75 6c 74 20 22 6c 6f 73 74 ┆r is 36. The result "lost┆
0xb700…b720 20 64 61 74 61 22 20 6d 69 67 68 74 20 69 6e 64 69 63 61 74 65 20 6c 61 63 6b 20 6f 66 20 64 61 ┆ data" might indicate lack of da┆
0xb720…b740 74 61 20 61 63 6b 6e 6f 77 6c 65 64 67 65 20 0a 66 72 6f 6d 20 74 68 65 20 46 44 31 37 39 37 20 ┆ta acknowledge from the FD1797 ┆
0xb740…b760 74 6f 20 74 68 65 20 69 41 50 58 31 38 36 20 43 50 55 20 77 69 74 68 69 6e 20 74 68 65 20 44 4d ┆to the iAPX186 CPU within the DM┆
0xb760…b780 41 20 74 72 61 6e 73 66 65 72 73 2c 20 65 2e 67 2e 20 0a 61 20 73 74 72 61 70 20 6f 6e 20 74 68 ┆A transfers, e.g. a strap on th┆
0xb780…b7a0 65 20 45 54 43 36 30 31 20 62 6f 61 72 64 2e 0d 0a 0d 0a b0 46 6c 6f 70 70 79 20 74 65 73 74 20 ┆e ETC601 board. Floppy test ┆
0xb7a0…b7c0 3a 20 77 72 69 74 65 20 66 61 75 6c 74 0d 0a 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 ┆: write fault Corresponding e┆
0xb7c0…b7e0 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 33 37 2e 0d 0a 0d 0a 54 68 65 20 72 65 73 75 6c 74 ┆rror number is 37. The result┆
0xb7e0…b800 20 22 77 72 69 74 65 20 66 61 75 6c 74 22 20 6d 69 67 68 74 20 69 6e 64 69 63 61 74 65 20 68 61 ┆ "write fault" might indicate ha┆
0xb800…b820 (92,) 72 64 20 65 72 72 6f 72 73 20 6f 6e 20 74 68 65 20 0a 69 6e 73 65 72 74 65 64 20 64 69 73 6b 2c ┆rd errors on the inserted disk,┆
0xb820…b840 20 62 75 74 20 6d 69 67 68 74 20 61 6c 73 6f 20 69 6e 64 69 63 61 74 65 20 68 61 72 64 20 65 72 ┆ but might also indicate hard er┆
0xb840…b860 72 6f 72 73 20 77 69 74 68 69 6e 20 74 68 65 20 0a 68 61 72 64 77 61 72 65 20 73 79 73 74 65 6d ┆rors within the hardware system┆
0xb860…b880 2e 0d 0a 0d 0a b0 46 6c 6f 70 70 79 20 74 65 73 74 20 3a 20 72 65 63 65 69 76 65 20 64 61 74 61 ┆. Floppy test : receive data┆
0xb880…b8a0 20 65 72 72 6f 72 2c 20 72 65 67 3a 3c 61 61 3e 2c 20 65 78 70 3a 20 3c 65 65 3e 2c 20 72 65 63 ┆ error, reg:<aa>, exp: <ee>, rec┆
0xb8a0…b8c0 3a 20 3c 72 72 3e 0d 0a 0d 0a b0 f0 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 ┆: <rr> Corresponding error ┆
0xb8c0…b8e0 6e 75 6d 62 65 72 20 69 73 20 33 38 2e 0d 0a 0d 0a 54 68 65 20 72 65 73 75 6c 74 20 22 72 65 63 ┆number is 38. The result "rec┆
0xb8e0…b900 65 69 76 65 20 64 61 74 61 20 65 72 72 6f 72 22 20 69 6e 64 69 63 61 74 65 73 20 61 6e 20 69 6e ┆eive data error" indicates an in┆
0xb900…b920 63 6f 6e 73 69 73 74 65 6e 63 65 20 77 69 74 68 20 0a 19 80 81 80 72 65 73 70 65 63 74 20 74 6f ┆consistence with respect to┆
0xb920…b940 20 74 68 65 20 64 61 74 61 20 70 61 74 74 65 72 6e 20 72 65 61 64 20 66 72 6f 6d 20 74 68 65 20 ┆ the data pattern read from the ┆
0xb940…b960 66 6c 6f 70 70 79 20 64 69 73 6b 2e 20 3c 61 61 3e 20 67 69 76 65 73 20 0a 19 80 81 80 74 68 65 ┆floppy disk. <aa> gives the┆
0xb960…b980 20 6c 6f 63 61 6c 20 6f 66 66 73 65 74 20 61 64 64 72 65 73 73 20 69 6e 20 74 68 65 20 72 65 63 ┆ local offset address in the rec┆
0xb980…b9a0 65 69 76 65 64 20 64 61 74 61 20 62 6c 6f 63 6b 20 77 68 65 72 65 20 74 68 65 20 0a 19 80 81 80 ┆eived data block where the ┆
0xb9a0…b9c0 69 6e 63 6f 6e 73 69 73 74 65 6e 63 65 20 77 61 73 20 66 6f 75 6e 64 2c 20 3c 65 65 3e 20 67 69 ┆inconsistence was found, <ee> gi┆
0xb9c0…b9e0 76 65 73 20 74 68 65 20 65 78 70 65 63 74 65 64 20 76 61 6c 75 65 20 61 6e 64 20 3c 72 72 3e 20 ┆ves the expected value and <rr> ┆
0xb9e0…ba00 0a 19 80 81 80 67 69 76 65 73 20 74 68 65 20 72 65 63 65 69 76 65 64 20 76 61 6c 75 65 2e 20 54 ┆ gives the received value. T┆
0xba00…ba20 (93,) 68 69 73 20 72 65 73 75 6c 74 20 63 6f 75 6c 64 20 69 6e 64 69 63 61 74 65 20 61 20 74 72 61 6e ┆his result could indicate a tran┆
0xba20…ba40 73 66 65 72 20 0a 19 80 81 80 65 72 72 6f 72 2c 20 64 75 65 20 74 6f 20 73 70 65 65 64 20 76 61 ┆sfer error, due to speed va┆
0xba40…ba60 72 69 61 74 69 6f 6e 73 2e 0d 0a 0d 0a 0d 0a a1 31 35 2e 32 20 54 68 65 20 54 65 73 74 20 44 69 ┆riations. 15.2 The Test Di┆
0xba60…ba80 73 6b 2e 0d 0a 0d 0a 0d 0a 42 65 66 6f 72 65 20 74 68 65 20 66 6c 6f 70 70 79 20 74 65 73 74 20 ┆sk. Before the floppy test ┆
0xba80…baa0 69 6e 69 74 69 61 74 65 64 2c 20 61 20 66 6f 72 6d 61 74 74 65 64 20 64 69 73 6b 20 6d 75 73 74 ┆initiated, a formatted disk must┆
0xbaa0…bac0 20 62 65 20 0a 69 6e 73 65 72 74 65 64 20 69 6e 20 74 68 65 20 66 6c 6f 70 70 79 20 64 72 69 76 ┆ be inserted in the floppy driv┆
0xbac0…bae0 65 2e 20 54 68 65 20 64 69 73 6b 20 69 6e 73 65 72 74 65 64 20 6d 75 73 74 20 62 65 20 64 6f 75 ┆e. The disk inserted must be dou┆
0xbae0…bb00 62 6c 65 20 0a 73 69 64 65 64 2c 20 64 6f 75 62 6c 65 20 64 65 6e 73 69 74 79 2c 20 73 6f 66 74 ┆ble sided, double density, soft┆
0xbb00…bb20 20 73 65 63 74 6f 72 69 6e 67 20 77 69 74 68 20 74 72 61 63 6b 20 64 65 6e 73 69 74 79 20 6f 66 ┆ sectoring with track density of┆
0xbb20…bb40 20 39 36 20 0a 54 50 49 2e 20 54 68 65 20 66 6f 72 6d 61 74 20 6f 66 20 74 68 65 20 64 69 73 6b ┆ 96 TPI. The format of the disk┆
0xbb40…bb60 20 63 6f 72 72 65 73 70 6f 6e 64 73 20 77 69 74 68 20 61 20 43 50 2f 4d 20 66 6f 72 6d 61 74 2c ┆ corresponds with a CP/M format,┆
0xbb60…bb80 20 65 2e 67 20 0a 68 61 76 65 20 37 37 20 74 72 61 63 6b 73 20 77 68 65 72 65 20 65 61 63 68 20 ┆ e.g have 77 tracks where each ┆
0xbb80…bba0 74 72 61 63 6b 20 68 61 73 20 31 30 20 73 65 63 74 6f 72 73 20 6f 66 20 65 61 63 68 20 35 31 32 ┆track has 10 sectors of each 512┆
0xbba0…bbb1 20 62 79 74 65 73 20 0a 6c 65 6e 67 74 68 2e 0d 0a ┆ bytes length. ┆
0xbbb1…bbb4 FormFeed {
0xbbb1…bbb4 0c 83 8c ┆ ┆
0xbbb1…bbb4 }
0xbbb4…bbc0 0a b0 a1 31 36 2e 20 4d 75 6c 74 69 ┆ 16. Multi┆
0xbbc0…bbe0 62 75 73 20 43 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 61 6e 64 20 54 65 73 74 20 4d 6f 6e 69 74 ┆bus Configuration and Test Monit┆
0xbbe0…bc00 6f 72 2e 0d 0a 0d 0a 0d 0a 54 68 65 20 73 6f 63 61 6c 6c 65 64 20 4d 75 6c 74 69 62 75 73 20 54 ┆or. The socalled Multibus T┆
0xbc00…bc20 (94,) 65 73 74 20 4d 6f 6e 69 74 6f 72 20 69 73 20 64 65 76 69 63 65 64 20 69 6e 74 6f 20 74 77 6f 20 ┆est Monitor is deviced into two ┆
0xbc20…bc40 70 68 61 73 65 73 2c 20 61 6e 0a 61 75 74 6f 6d 61 74 69 63 20 63 6f 6e 66 69 67 75 72 61 74 69 ┆phases, an automatic configurati┆
0xbc40…bc60 6f 6e 20 77 69 74 68 20 64 65 63 6f 64 69 6e 67 20 6f 66 20 65 72 72 6f 72 73 20 70 72 6f 64 75 ┆on with decoding of errors produ┆
0xbc60…bc80 63 65 64 20 62 79 20 74 68 65 20 0a 22 74 65 73 74 2d 73 6c 61 76 65 73 22 20 61 6e 64 20 61 6e ┆ced by the "test-slaves" and an┆
0xbc80…bca0 20 69 6e 74 65 72 61 63 74 69 76 65 20 74 65 73 74 20 70 68 61 73 65 2c 20 77 68 69 63 68 20 6d ┆ interactive test phase, which m┆
0xbca0…bcc0 75 73 74 20 62 65 20 0a 72 65 71 75 65 73 74 65 64 20 62 79 20 74 68 65 20 6f 70 65 72 61 74 6f ┆ust be requested by the operato┆
0xbcc0…bce0 72 2e 0d 0a 0d 0a 49 6e 20 74 68 65 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 70 68 61 73 65 ┆r. In the configuration phase┆
0xbce0…bd00 20 74 68 65 20 22 74 65 73 74 20 68 6f 73 74 22 20 77 69 6c 6c 20 70 72 6f 64 75 63 65 20 61 20 ┆ the "test host" will produce a ┆
0xbd00…bd20 0a 63 6f 6d 70 6c 65 74 65 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 74 61 62 6c 65 20 6f 66 ┆ complete configuration table of┆
0xbd20…bd40 20 74 68 65 20 74 6f 74 61 6c 20 52 43 33 39 30 30 20 4d 75 6c 74 69 62 75 73 20 53 79 73 74 65 ┆ the total RC3900 Multibus Syste┆
0xbd40…bd60 6d 2e 0d 0a 0d 0a 45 78 61 6d 70 6c 65 20 6f 66 20 74 68 65 20 4d 75 6c 74 69 62 75 73 20 63 6f ┆m. Example of the Multibus co┆
0xbd60…bd72 6e 66 69 67 75 72 61 74 69 6f 6e 3a 0d 0a 0e 0a 0d 0a ┆nfiguration: ┆
0xbd72…bdab Params {
0xbd72…bdab 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 4c 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N L1 ┆
0xbd72…bdab 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0xbd72…bdab }
0xbdab…bde4 Params {
0xbdab…bde4 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0xbdab…bde4 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0xbdab…bde4 }
0xbde4…be00 0a a2 05 0d 0a 45 6e 74 72 79 20 6e 6f 2e 20 2c 4d 42 20 62 6c 6f 63 6b 20 2c 73 74 ┆ Entry no. ,MB block ,st┆
0xbe00…be20 (95,) 61 74 65 20 2c 6e 61 6d 65 20 2c 52 41 4d 20 73 69 7a 65 20 2a 20 36 34 6b 2c 20 66 6c 61 67 20 ┆ate ,name ,RAM size * 64k, flag ┆
0xbe20…be40 6f 66 66 73 65 74 20 2a 20 31 36 6b 2c 65 72 72 20 6e 6f 2e 0d 0a a2 05 0d 0a 20 30 30 30 30 34 ┆offset * 16k,err no. 00004┆
0xbe40…be60 20 20 20 20 20 20 20 34 30 30 30 0d 0a 20 30 30 30 30 37 20 20 20 20 20 20 20 37 30 30 30 20 20 ┆ 4000 00007 7000 ┆
0xbe60…be80 20 20 72 65 61 64 79 20 43 4f 4d 36 30 31 20 20 20 20 20 30 30 30 30 33 20 20 20 20 20 20 20 20 ┆ ready COM601 00003 ┆
0xbe80…bea0 20 20 20 20 30 30 30 30 34 05 30 30 30 30 30 20 20 0d 0a 20 30 30 30 31 30 20 20 20 20 20 20 20 ┆ 00004 00000 00010 ┆
0xbea0…bec0 41 30 30 30 20 20 20 20 72 65 61 64 79 20 43 4f 4d 36 30 31 20 20 20 20 20 30 30 30 30 31 20 20 ┆A000 ready COM601 00001 ┆
0xbec0…bedf 20 20 20 20 20 20 20 20 20 20 30 30 30 30 32 20 20 20 20 20 20 20 20 20 30 30 30 30 32 0d 0a ┆ 00002 00002 ┆
0xbedf…bf18 Params {
0xbedf…bf18 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0xbedf…bf18 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0xbedf…bf18 }
0xbf18…bf51 Params {
0xbf18…bf51 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 4c 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N L1 ┆
0xbf18…bf51 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0xbf18…bf51 }
0xbf51…bf60 0a 0f 0a 0d 0a 54 68 65 20 69 6e 74 65 72 61 ┆ The intera┆
0xbf60…bf80 63 74 69 76 65 20 74 65 73 74 70 68 61 73 65 2c 20 77 68 65 72 65 20 69 74 20 69 73 20 70 6f 73 ┆ctive testphase, where it is pos┆
0xbf80…bfa0 73 69 62 6c 65 20 74 6f 20 63 6f 6e 74 72 6f 6c 20 74 68 65 20 0a 65 78 65 63 75 74 69 6f 6e 20 ┆sible to control the execution ┆
0xbfa0…bfc0 6f 66 20 74 65 73 74 73 20 6f 6e 20 64 69 66 66 65 72 65 6e 74 20 22 74 65 73 74 2d 73 6c 61 76 ┆of tests on different "test-slav┆
0xbfc0…bfe0 65 73 22 2c 20 77 69 6c 6c 20 6f 6e 6c 79 20 62 65 20 0a 65 6e 74 65 72 65 64 2c 20 77 68 65 6e ┆es", will only be entered, when┆
0xbfe0…c000 20 72 65 71 75 65 73 74 65 64 20 62 79 20 74 68 65 20 6f 70 65 72 61 74 6f 72 20 28 70 72 65 73 ┆ requested by the operator (pres┆
0xc000…c020 (96,) 73 20 3c 63 6e 74 72 6c 3e 3c 53 3e 29 20 64 75 72 69 6e 67 20 0a 74 68 65 20 22 74 65 73 74 2d ┆s <cntrl><S>) during the "test-┆
0xc020…c040 6d 61 73 74 65 72 22 20 73 65 6c 66 74 65 73 74 29 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 31 36 2e 31 20 ┆master" selftest). 16.1 ┆
0xc040…c060 41 75 74 6f 6d 61 74 69 63 20 43 6f 6e 66 69 67 75 72 61 74 69 6f 6e 2e 0d 0a 0d 0a 0d 0a 57 68 ┆Automatic Configuration. Wh┆
0xc060…c080 65 6e 20 61 20 22 74 65 73 74 2d 6d 61 73 74 65 72 22 20 68 61 73 20 74 65 72 6d 69 6e 61 74 65 ┆en a "test-master" has terminate┆
0xc080…c0a0 64 20 69 74 73 20 73 65 6c 66 74 65 73 74 2c 20 69 74 20 77 69 6c 6c 20 61 6c 77 61 79 73 20 0a ┆d its selftest, it will always ┆
0xc0a0…c0c0 70 65 72 66 6f 72 6d 20 61 6e 20 61 75 74 6f 6d 61 74 69 63 20 4d 75 6c 74 69 62 75 73 20 63 6f ┆perform an automatic Multibus co┆
0xc0c0…c0e0 6e 66 69 67 75 72 61 74 69 6f 6e 2c 20 69 6e 20 6f 72 64 65 72 20 74 6f 20 6c 6f 63 61 74 65 20 ┆nfiguration, in order to locate ┆
0xc0e0…c100 0a 61 63 74 69 76 65 20 22 74 65 73 74 2d 73 6c 61 76 65 73 22 20 61 6e 64 20 65 76 65 6e 74 75 ┆ active "test-slaves" and eventu┆
0xc100…c120 61 6c 6c 79 20 69 6e 61 63 74 69 76 65 20 6d 65 6d 6f 72 79 20 61 72 65 61 73 2e 0d 0a 0d 0a 49 ┆ally inactive memory areas. I┆
0xc120…c140 74 20 69 73 20 61 20 63 6f 6e 76 65 6e 74 69 6f 6e 20 74 68 61 74 20 65 76 65 72 79 20 22 74 65 ┆t is a convention that every "te┆
0xc140…c160 73 74 2d 73 6c 61 76 65 22 2c 20 77 68 65 6e 20 74 65 72 6d 69 6e 61 74 69 6e 67 20 69 74 73 20 ┆st-slave", when terminating its ┆
0xc160…c180 0a 73 65 6c 66 74 65 73 74 20 77 69 6c 6c 20 63 6f 6d 6d 75 6e 69 63 61 74 65 20 77 69 74 68 20 ┆ selftest will communicate with ┆
0xc180…c1a0 22 74 65 73 74 2d 6d 61 73 74 65 72 22 20 62 79 20 6d 65 61 6e 73 20 6f 66 20 61 20 0a 70 72 65 ┆"test-master" by means of a pre┆
0xc1a0…c1c0 64 65 66 69 6e 65 64 20 70 72 6f 74 6f 63 6f 6c 2e 0d 0a 0d 0a 8c 83 bc 0a 54 68 65 20 63 6f 6e ┆defined protocol. The con┆
0xc1c0…c1e0 66 69 67 75 72 61 74 69 6f 6e 20 74 61 62 6c 65 20 77 69 6c 6c 20 62 65 20 73 68 6f 77 6e 20 6f ┆figuration table will be shown o┆
0xc1e0…c200 6e 20 74 68 65 20 63 6f 6e 73 6f 6c 65 2c 20 61 6e 64 20 69 74 20 69 73 20 0a 70 6f 73 73 69 62 ┆n the console, and it is possib┆
0xc200…c220 (97,) 6c 65 20 66 6f 72 20 74 68 65 20 6f 70 65 72 61 74 6f 72 20 74 6f 20 64 65 63 69 64 65 2c 20 69 ┆le for the operator to decide, i┆
0xc220…c240 66 20 69 74 20 63 6f 72 72 65 73 70 6f 6e 64 73 20 77 69 74 68 20 74 68 65 20 0a 61 63 74 75 61 ┆f it corresponds with the actua┆
0xc240…c260 6c 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 2e 20 54 68 65 20 65 6e 74 72 69 65 73 2c 20 77 68 ┆l configuration. The entries, wh┆
0xc260…c280 69 63 68 20 68 61 73 20 70 61 73 73 65 64 20 61 20 68 61 6e 64 73 68 61 6b 65 20 0a 77 69 74 68 ┆ich has passed a handshake with┆
0xc280…c2a0 20 74 68 65 20 22 74 65 73 74 2d 6d 61 73 74 65 72 22 20 77 69 6c 6c 20 68 61 76 65 20 74 68 65 ┆ the "test-master" will have the┆
0xc2a0…c2c0 20 73 74 61 74 65 20 22 52 45 41 44 59 22 20 61 6e 64 20 61 6e 20 0a 69 64 65 6e 74 69 66 69 63 ┆ state "READY" and an identific┆
0xc2c0…c2e0 61 74 69 6f 6e 20 6e 61 6d 65 20 73 65 74 20 69 6e 20 74 68 65 20 63 6f 6e 66 69 67 75 72 61 74 ┆ation name set in the configurat┆
0xc2e0…c300 69 6f 6e 20 74 61 62 6c 65 2e 0d 0a 0d 0a 49 66 20 6f 6e 65 20 6f 72 20 6d 6f 72 65 20 6f 66 20 ┆ion table. If one or more of ┆
0xc300…c320 74 68 65 20 22 74 65 73 74 2d 73 6c 61 76 65 73 22 20 68 61 76 65 20 70 72 6f 64 75 63 65 64 20 ┆the "test-slaves" have produced ┆
0xc320…c340 61 6e 20 65 72 72 6f 72 2c 20 74 68 65 20 0a 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 62 75 66 ┆an error, the communication buf┆
0xc340…c360 66 65 72 20 66 6f 72 20 74 68 65 20 72 65 6c 61 74 65 64 20 22 74 65 73 74 2d 73 6c 61 76 65 22 ┆fer for the related "test-slave"┆
0xc360…c380 20 77 69 6c 6c 20 63 6f 6e 74 61 69 6e 20 0a 73 6f 6d 65 20 64 61 74 61 20 61 6e 64 20 74 65 78 ┆ will contain some data and tex┆
0xc380…c3a0 74 2c 20 77 68 69 63 68 20 77 69 6c 6c 20 69 64 65 6e 74 69 66 79 20 74 68 65 20 65 72 72 6f 72 ┆t, which will identify the error┆
0xc3a0…c3c0 2e 20 54 68 65 20 74 65 78 74 20 69 6e 20 0a 74 68 65 20 62 75 66 66 65 72 20 77 69 6c 6c 20 62 ┆. The text in the buffer will b┆
0xc3c0…c3e0 65 20 73 68 6f 77 6e 20 6f 6e 20 74 68 65 20 63 6f 6e 73 6f 6c 65 20 61 73 20 61 6e 20 65 72 72 ┆e shown on the console as an err┆
0xc3e0…c400 6f 72 74 65 78 74 2e 20 41 62 6f 75 74 20 0a 22 74 65 73 74 20 73 6c 61 76 65 22 20 65 72 72 6f ┆ortext. About "test slave" erro┆
0xc400…c420 (98,) 72 74 65 78 74 73 2c 20 70 6c 65 61 73 65 20 63 6f 6e 73 75 6c 74 20 74 68 65 20 72 65 6c 61 74 ┆rtexts, please consult the relat┆
0xc420…c440 65 64 20 6d 61 6e 75 61 6c 2e 0d 0a 0d 0a 49 66 20 74 68 65 20 22 74 65 73 74 2d 6d 61 73 74 65 ┆ed manual. If the "test-maste┆
0xc440…c460 72 22 20 68 61 73 20 68 61 6c 74 65 64 20 6f 6e 20 6f 6e 65 20 6f 66 20 74 68 65 73 65 20 65 72 ┆r" has halted on one of these er┆
0xc460…c480 72 6f 72 73 2c 20 69 74 20 69 73 20 0a 70 6f 73 73 69 62 6c 65 20 74 6f 20 63 6f 6e 74 69 6e 75 ┆rors, it is possible to continu┆
0xc480…c4a0 65 20 62 79 20 74 79 70 69 6e 67 20 3c 63 6e 74 72 6c 3e 3c 51 3e 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 ┆e by typing <cntrl><Q>. ┆
0xc4a0…c4c0 31 36 2e 32 20 22 54 65 73 74 20 53 6c 61 76 65 22 20 4d 61 6e 61 67 65 6d 65 6e 74 2e 0d 0a 0d ┆16.2 "Test Slave" Management. ┆
0xc4c0…c4e0 0a 0d 0a 54 68 65 20 64 65 66 61 75 6c 74 20 61 63 74 69 6f 6e 20 6f 66 20 74 68 65 20 45 54 43 ┆ The default action of the ETC┆
0xc4e0…c500 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 69 73 20 74 6f 20 65 6e 74 65 72 20 74 68 65 ┆601 SBC Selftest is to enter the┆
0xc500…c520 20 0a 62 6f 6f 74 6c 6f 61 64 65 72 20 77 68 65 6e 20 74 68 65 20 63 6f 6e 66 69 67 75 72 61 74 ┆ bootloader when the configurat┆
0xc520…c540 69 6f 6e 20 70 68 61 73 65 20 68 61 73 20 62 65 65 6e 20 74 65 72 6d 69 6e 61 74 65 64 2e 20 54 ┆ion phase has been terminated. T┆
0xc540…c560 68 69 73 20 0a 63 61 6e 20 62 65 20 6f 76 65 72 77 72 69 74 74 65 6e 20 62 79 20 74 68 65 20 6f ┆his can be overwritten by the o┆
0xc560…c580 70 65 72 61 74 6f 72 20 74 79 70 69 6e 67 20 3c 63 6e 74 72 6c 3e 3c 53 3e 20 64 75 72 69 6e 67 ┆perator typing <cntrl><S> during┆
0xc580…c5a0 20 74 68 65 20 0a 22 74 65 73 74 2d 6d 61 73 74 65 72 22 20 73 65 6c 66 74 65 73 74 2e 0d 0a 0d ┆ the "test-master" selftest. ┆
0xc5a0…c5c0 0a 57 68 65 6e 20 74 68 65 20 69 6e 74 65 72 61 63 74 69 76 65 20 74 65 73 74 20 70 68 61 73 65 ┆ When the interactive test phase┆
0xc5c0…c5e0 20 68 61 73 20 62 65 65 6e 20 73 65 6c 65 63 74 65 64 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 ┆ has been selected the following┆
0xc5e0…c600 20 0a 74 65 78 74 20 77 69 6c 6c 20 62 65 20 77 72 69 74 74 65 6e 2c 20 77 68 65 6e 20 74 68 65 ┆ text will be written, when the┆
0xc600…c620 (99,) 20 61 75 74 6f 6d 61 74 69 63 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 68 61 73 20 62 65 65 ┆ automatic configuration has bee┆
0xc620…c640 6e 20 0a 74 65 72 6d 69 6e 61 74 65 64 3a 0d 0a 0d 0a b0 3e 3e 20 4d 75 6c 74 69 62 75 73 20 6d ┆n terminated: >> Multibus m┆
0xc640…c660 6f 6e 69 74 6f 72 69 6e 67 0d 0a 0d 0a 45 61 63 68 20 6f 66 20 74 68 65 20 63 6f 6e 6e 65 63 74 ┆onitoring Each of the connect┆
0xc660…c680 65 64 20 22 74 65 73 74 20 73 6c 61 76 65 73 22 20 68 61 73 20 69 74 73 20 6f 77 6e 20 73 65 70 ┆ed "test slaves" has its own sep┆
0xc680…c6a0 65 72 61 74 65 20 73 65 74 20 6f 66 20 0a 70 61 72 61 6d 65 74 65 72 73 2c 20 77 68 69 63 68 20 ┆erate set of parameters, which ┆
0xc6a0…c6c0 68 61 73 20 74 68 65 20 73 61 6d 65 20 66 6f 72 6d 61 74 20 61 73 20 74 68 6f 73 65 20 75 73 65 ┆has the same format as those use┆
0xc6c0…c6e0 64 20 62 79 20 74 68 65 20 43 50 55 2e 20 0a 0d 0a 49 6e 20 74 68 65 20 69 6e 74 65 72 61 74 69 ┆d by the CPU. In the interati┆
0xc6e0…c700 76 65 20 70 68 61 73 65 20 69 74 20 69 73 20 70 6f 73 73 69 62 6c 65 20 74 6f 20 73 74 61 72 74 ┆ve phase it is possible to start┆
0xc700…c720 20 6f 6e 65 20 6f 72 20 73 65 76 65 72 61 6c 20 0a 22 74 65 73 74 2d 73 6c 61 76 65 73 22 20 6c ┆ one or several "test-slaves" l┆
0xc720…c740 6f 6f 70 69 6e 67 20 69 6e 20 74 68 65 20 63 6f 6d 70 6c 65 74 65 20 73 65 6c 66 74 65 73 74 20 ┆ooping in the complete selftest ┆
0xc740…c760 6f 72 20 69 6e 20 61 20 73 70 65 63 69 66 69 63 20 0a 74 65 73 74 70 72 6f 67 72 61 6d 2e 0d 0a ┆or in a specific testprogram. ┆
0xc760…c780 0d 0a 8c 83 bc 0a 55 6e 74 69 6c 20 61 20 22 74 65 73 74 2d 73 6c 61 76 65 22 20 68 61 73 20 72 ┆ Until a "test-slave" has r┆
0xc780…c7a0 65 63 65 69 76 65 64 20 69 74 73 20 66 69 72 73 74 20 73 65 74 20 6f 66 20 70 61 72 61 6d 65 74 ┆eceived its first set of paramet┆
0xc7a0…c7c0 65 72 73 2c 20 69 74 20 0a 77 69 6c 6c 20 73 74 61 79 20 69 6e 20 61 6e 20 69 6e 61 63 74 69 76 ┆ers, it will stay in an inactiv┆
0xc7c0…c7e0 65 20 6d 6f 64 65 2e 0d 0a 0d 0a 45 76 65 72 79 20 74 69 6d 65 20 22 74 65 73 74 2d 73 6c 61 76 ┆e mode. Every time "test-slav┆
0xc7e0…c800 65 22 20 72 65 63 6f 67 6e 69 7a 65 73 20 61 6e 20 65 72 72 6f 72 2c 20 74 68 65 20 72 65 6c 61 ┆e" recognizes an error, the rela┆
0xc800…c820 (100,) 74 65 64 20 6d 65 73 73 61 67 65 20 0a 77 69 6c 6c 20 62 65 20 77 72 69 74 74 65 6e 20 6f 6e 20 ┆ted message will be written on ┆
0xc820…c840 74 68 65 20 63 6f 6e 73 6f 6c 65 2e 0d 0a 0d 0a 42 79 20 74 79 70 69 6e 67 20 3c 63 6e 74 72 6c ┆the console. By typing <cntrl┆
0xc840…c860 3e 3c 53 3e 2c 20 74 68 65 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 77 69 6c 6c 20 62 65 20 ┆><S>, the configuration will be ┆
0xc860…c880 73 68 6f 77 6e 2e 20 57 68 65 6e 20 74 68 65 20 0a 69 6e 74 65 72 61 63 74 69 76 65 20 70 68 61 ┆shown. When the interactive pha┆
0xc880…c8a0 73 65 20 69 73 20 73 65 6c 65 63 74 65 64 20 6e 65 77 20 70 61 72 61 6d 65 74 65 72 73 20 66 6f ┆se is selected new parameters fo┆
0xc8a0…c8c0 72 20 61 20 22 74 65 73 74 2d 73 6c 61 76 65 22 20 0a 6d 61 79 20 62 65 20 65 6e 74 65 72 65 64 ┆r a "test-slave" may be entered┆
0xc8c0…c8e0 20 61 66 74 65 72 20 74 68 65 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 74 61 62 6c 65 20 68 ┆ after the configuration table h┆
0xc8e0…c900 61 73 20 62 65 65 6e 20 77 72 69 74 74 65 6e 2e 0d 0a 0d 0a 41 6e 20 65 72 72 6f 72 6d 65 73 73 ┆as been written. An errormess┆
0xc900…c920 61 67 65 20 77 69 6c 6c 20 62 65 20 72 65 74 79 70 65 64 20 6f 6e 20 74 68 65 20 63 6f 6e 73 6f ┆age will be retyped on the conso┆
0xc920…c940 6c 65 2c 20 77 68 65 6e 20 61 20 63 68 61 6e 67 65 20 6f 66 20 0a 70 61 72 61 6d 65 74 65 72 73 ┆le, when a change of parameters┆
0xc940…c960 20 68 61 73 20 62 65 65 6e 20 6d 61 64 65 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 31 36 2e 33 20 42 6f 6f ┆ has been made. 16.3 Boo┆
0xc960…c980 74 6c 6f 61 64 2e 0d 0a 0d 0a 0d 0a 44 65 66 61 75 6c 74 20 61 63 74 69 6f 6e 20 6f 66 20 74 68 ┆tload. Default action of th┆
0xc980…c9a0 65 20 45 54 43 36 30 31 20 53 42 43 20 73 65 6c 66 74 65 73 74 20 69 73 20 74 6f 20 65 6e 74 65 ┆e ETC601 SBC selftest is to ente┆
0xc9a0…c9c0 72 20 74 68 65 20 0a 62 6f 6f 74 6c 6f 61 64 65 72 20 69 6d 6d 65 64 69 61 74 65 6c 79 20 61 66 ┆r the bootloader immediately af┆
0xc9c0…c9e0 74 65 72 20 74 68 65 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 2e 0d 0a 0d 0a 57 68 65 6e 20 74 ┆ter the configuration. When t┆
0xc9e0…ca00 65 73 74 69 6e 67 20 69 6e 20 74 68 65 20 69 6e 74 65 72 61 63 74 69 76 65 20 70 68 61 73 65 20 ┆esting in the interactive phase ┆
0xca00…ca20 (101,) 74 68 65 20 63 68 61 72 61 63 74 65 72 20 3c 63 6e 74 72 6c 3e 3c 51 3e 20 0a 68 61 73 20 74 77 ┆the character <cntrl><Q> has tw┆
0xca20…ca40 6f 20 70 75 72 70 6f 73 65 73 2e 0d 0a 0d 0a 61 29 20 84 57 68 65 6e 20 74 68 65 20 22 74 65 73 ┆o purposes. a) When the "tes┆
0xca40…ca60 74 2d 6d 61 73 74 65 72 22 20 68 61 73 20 68 61 6c 74 65 64 20 64 75 65 20 74 6f 20 61 20 22 74 ┆t-master" has halted due to a "t┆
0xca60…ca80 65 73 74 20 73 6c 61 76 65 22 20 65 72 72 6f 72 2c 20 0a 19 83 80 80 74 68 69 73 20 22 68 61 6c ┆est slave" error, this "hal┆
0xca80…caa0 74 22 20 63 61 6e 20 62 65 20 71 75 69 74 20 62 79 20 74 79 70 69 6e 67 20 3c 65 6e 74 72 6c 3e ┆t" can be quit by typing <entrl>┆
0xcaa0…cac0 3c 51 3e 2e 0d 0a 0d 0a 62 29 20 84 57 68 65 6e 20 72 75 6e 6e 69 6e 67 20 69 6e 20 74 68 65 20 ┆<Q>. b) When running in the ┆
0xcac0…cae0 69 6e 74 65 72 61 63 74 69 76 65 20 70 68 61 73 65 20 61 6e 64 20 74 79 70 69 6e 67 20 3c 63 6e ┆interactive phase and typing <cn┆
0xcae0…cb00 74 72 6c 3e 3c 51 3e 2c 20 0a 19 83 80 80 74 68 69 73 20 77 69 6c 6c 20 66 6f 72 63 65 20 61 6c ┆trl><Q>, this will force al┆
0xcb00…cb20 6c 20 74 68 65 20 22 74 65 73 74 2d 73 6c 61 76 65 73 22 20 61 6e 64 20 66 69 6e 61 6c 6c 79 20 ┆l the "test-slaves" and finally ┆
0xcb20…cb40 74 68 65 20 22 74 65 73 74 2d 20 0a 19 83 80 80 6d 61 73 74 65 72 22 20 74 6f 20 65 6e 74 65 72 ┆the "test- master" to enter┆
0xcb40…cb52 20 74 68 65 20 62 6f 6f 74 6c 6f 61 64 65 72 2e 0d 0a ┆ the bootloader. ┆
0xcb52…cb55 FormFeed {
0xcb52…cb55 0c 82 dc ┆ ┆
0xcb52…cb55 }
0xcb55…cb60 0a b0 a1 31 37 2e 20 45 54 43 36 ┆ 17. ETC6┆
0xcb60…cb80 30 31 20 61 73 20 61 20 22 54 65 73 74 2d 73 6c 61 76 65 22 2e 0d 0a 0d 0a 0d 0a 49 74 20 69 73 ┆01 as a "Test-slave". It is┆
0xcb80…cba0 20 70 6f 73 73 69 62 6c 65 20 74 6f 20 63 6f 6e 66 69 67 75 72 61 74 65 20 61 20 45 54 43 36 30 ┆ possible to configurate a ETC60┆
0xcba0…cbc0 31 20 61 73 20 61 20 22 74 65 73 74 2d 73 6c 61 76 65 22 20 62 79 20 74 68 65 20 0a 73 77 69 74 ┆1 as a "test-slave" by the swit┆
0xcbc0…cbe0 63 68 20 73 68 6f 77 6e 20 69 6e 20 66 69 67 2e 20 39 2e 20 54 68 69 73 20 6d 65 61 6e 73 20 74 ┆ch shown in fig. 9. This means t┆
0xcbe0…cc00 68 61 74 20 73 65 76 65 72 61 6c 20 45 54 43 36 30 31 20 62 6f 61 72 64 73 20 63 61 6e 20 0a 62 ┆hat several ETC601 boards can b┆
0xcc00…cc20 (102,) 65 20 6d 61 6e 61 67 65 64 20 62 79 20 6f 6e 65 20 22 74 65 73 74 2d 6d 61 73 74 65 72 22 2e 0d ┆e managed by one "test-master". ┆
0xcc20…cc40 0a 0d 0a 53 70 65 63 69 61 6c 69 74 69 65 73 3a 0d 0a 0d 0a 61 29 20 84 57 68 65 6e 20 6c 6f 6f ┆ Specialities: a) When loo┆
0xcc40…cc60 70 69 6e 67 20 69 6e 20 74 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 2c 20 74 68 65 20 22 74 65 ┆ping in the memory test, the "te┆
0xcc60…cc80 73 74 2d 73 6c 61 76 65 22 20 77 69 6c 6c 20 a1 6e 6f 74 e1 20 0a 19 83 80 80 63 6f 6d 6d 75 6e ┆st-slave" will not commun┆
0xcc80…cca0 69 63 61 74 65 20 77 69 74 68 20 74 68 65 20 22 74 65 73 74 2d 6d 61 73 74 65 72 22 2e 0d 0a 0d ┆icate with the "test-master". ┆
0xcca0…ccc0 0a 62 29 20 84 57 68 65 6e 20 62 6f 74 68 20 74 68 65 20 70 61 72 61 6d 65 74 65 72 73 20 22 73 ┆ b) When both the parameters "s┆
0xccc0…cce0 75 70 70 72 65 73 73 20 73 74 61 74 75 73 20 63 68 65 63 6b 22 20 61 6e 64 20 22 73 75 70 70 72 ┆uppress status check" and "suppr┆
0xcce0…cd00 65 73 73 20 0a 19 83 80 80 64 61 74 61 20 63 68 65 63 6b 22 20 69 73 20 73 65 74 20 74 6f 20 22 ┆ess data check" is set to "┆
0xcd00…cd20 59 22 2c 20 69 74 20 77 69 6c 6c 20 6f 6e 6c 79 20 63 6f 6d 6d 75 6e 69 63 61 74 65 20 69 6e 20 ┆Y", it will only communicate in ┆
0xcd20…cd36 63 61 73 65 20 6f 66 20 0a 19 83 80 80 65 72 72 6f 72 73 2e 0d 0a ┆case of errors. ┆
0xcd36…cd39 FormFeed {
0xcd36…cd39 0c 81 b4 ┆ ┆
0xcd36…cd39 }
0xcd39…cd40 0a b0 a1 41 2e 20 4c ┆ A. L┆
0xcd40…cd60 41 59 4f 55 54 20 4f 46 20 54 48 45 20 4d 41 53 54 45 52 20 54 4f 20 53 4c 41 56 45 20 43 4f 4d ┆AYOUT OF THE MASTER TO SLAVE COM┆
0xcd60…cd73 4d 55 4e 49 43 41 54 49 4f 4e 20 42 55 46 46 45 52 0d 0a ┆MUNICATION BUFFER ┆
0xcd73…cdac Params {
0xcd73…cdac 04 00 2d 4e 0a 00 06 00 00 00 00 02 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0xcd73…cdac 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0xcd73…cdac }
0xcdac…cde5 Params {
0xcdac…cde5 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0xcdac…cde5 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0xcdac…cde5 }
0xcde5…ce00 0a 0d 0a 0d 0a a1 05 0d 0a 21 78 78 78 78 3a 46 46 46 46 20 20 20 20 21 20 69 64 ┆ !xxxx:FFFF ! id┆
0xce00…ce20 (103,) 20 66 69 65 6c 64 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a a1 21 20 20 20 20 20 ┆ field ! ! ! ! ┆
0xce20…ce40 46 46 46 45 20 20 20 20 21 20 73 74 61 74 65 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 ┆FFFE ! state ! ┆
0xce40…ce60 21 05 21 0d 0a 21 20 20 20 20 20 46 46 46 44 20 20 20 20 21 20 20 20 20 20 20 20 20 20 27 43 27 ┆! ! ! FFFD ! 'C'┆
0xce60…ce80 20 20 21 20 20 20 20 20 20 20 20 21 20 05 21 0d 0a 21 20 20 20 20 20 46 46 46 43 20 20 20 20 21 ┆ ! ! ! ! FFFC !┆
0xce80…cea0 20 20 20 20 20 20 20 20 20 27 4f 27 20 20 21 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 ┆ 'O' ! ! ┆
0xcea0…cec0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 46 46 46 42 20 20 ┆ ! ! FFFB ┆
0xcec0…cee0 20 20 21 20 6e 61 6d 65 20 20 20 20 27 4d 27 20 20 21 20 20 20 20 20 20 20 20 21 20 20 20 20 20 ┆ ! name 'M' ! ! ┆
0xcee0…cf00 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 46 46 46 ┆ ! ! FFF┆
0xcf00…cf20 41 20 20 20 20 21 20 20 20 20 20 20 20 20 20 27 36 27 20 20 21 20 20 20 20 20 20 20 20 21 20 05 ┆A ! '6' ! ! ┆
0xcf20…cf40 21 0d 0a 21 20 20 20 20 20 46 46 46 39 20 20 20 20 21 20 20 20 20 20 20 20 20 20 27 30 27 20 20 ┆! ! FFF9 ! '0' ┆
0xcf40…cf60 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a a1 21 20 20 20 20 20 46 46 46 38 20 20 20 20 21 20 20 ┆! ! ! ! FFF8 ! ┆
0xcf60…cf80 20 20 20 20 20 20 20 27 31 27 20 20 21 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 ┆ '1' ! ! ┆
0xcf80…cfa0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 46 46 46 37 20 20 20 20 ┆ ! ! FFF7 ┆
0xcfa0…cfc0 21 20 72 61 6d 73 69 7a 65 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a 21 20 20 ┆! ramsize ! ! ! ! ┆
0xcfc0…cfe0 20 20 20 46 46 46 36 20 20 20 20 21 20 66 6c 61 67 5f 6f 66 66 73 65 74 20 20 21 20 20 20 20 20 ┆ FFF6 ! flag_offset ! ┆
0xcfe0…d000 20 20 20 21 05 21 0d 0a a1 21 20 20 20 20 20 46 46 46 35 20 20 20 20 21 20 64 61 74 61 20 70 61 ┆ ! ! ! FFF5 ! data pa┆
0xd000…d020 (104,) 74 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a 21 20 20 20 20 20 46 46 46 34 20 20 ┆t ! ! ! ! FFF4 ┆
0xd020…d040 20 20 21 20 73 77 69 74 63 68 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 20 05 21 0d 0a ┆ ! switch ! ! ! ┆
0xd040…d060 a1 21 20 20 20 20 20 46 46 46 33 20 20 20 20 21 20 74 65 73 74 20 6e 6f 20 20 20 20 20 20 21 20 ┆ ! FFF3 ! test no ! ┆
0xd060…d080 20 20 20 20 20 20 20 21 05 21 0d 0a a1 21 20 20 20 20 20 46 46 46 32 20 20 20 20 21 20 70 61 72 ┆ ! ! ! FFF2 ! par┆
0xd080…d0a0 61 6d 20 66 6c 61 67 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a 21 20 20 20 20 20 46 46 ┆am flag ! ! ! ! FF┆
0xd0a0…d0c0 46 31 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 20 ┆F1 ! ! ! ┆
0xd0c0…d0e0 05 21 0d 0a 21 20 20 20 20 20 46 46 46 30 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ! FFF0 ! ┆
0xd0e0…d100 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a 21 20 20 20 20 20 2a 2a 2a 2a 20 20 20 20 21 20 73 ┆ ! ! ! ! **** ! s┆
0xd100…d120 6c 61 76 65 20 65 72 72 6f 72 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a 21 20 20 20 20 20 ┆lave error ! ! ! ! ┆
0xd120…d140 2a 2a 2a 2a 20 20 20 20 21 20 74 65 78 74 20 73 74 72 69 6e 67 20 20 21 20 20 20 20 20 20 20 20 ┆**** ! text string ! ┆
0xd140…d160 21 05 21 0d 0a 21 20 20 20 20 20 2a 2a 2a 2a 20 20 20 20 21 20 6d 61 78 20 38 30 20 63 68 61 72 ┆! ! ! **** ! max 80 char┆
0xd160…d180 73 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a 21 20 20 20 20 20 46 46 41 33 20 20 20 20 21 20 ┆s ! ! ! ! FFA3 ! ┆
0xd180…d1a0 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a a1 21 20 20 20 ┆ ! ! ! ! ┆
0xd1a0…d1c0 20 20 46 46 41 32 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 ┆ FFA2 ! ! ┆
0xd1c0…d1e0 20 20 21 05 21 0d 0a 21 20 20 20 20 20 46 46 41 31 20 20 20 20 21 20 74 65 78 74 20 6c 65 6e 67 ┆ ! ! ! FFA1 ! text leng┆
0xd1e0…d200 74 68 20 20 21 20 20 20 20 20 20 20 20 21 20 05 21 0d 0a a1 21 20 20 20 20 20 46 46 41 30 20 20 ┆th ! ! ! ! FFA0 ┆
0xd200…d220 (105,) 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 20 20 20 20 20 ┆ ! ! ! ┆
0xd220…d240 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 46 46 39 ┆ ! ! FF9┆
0xd240…d260 46 20 20 20 20 21 20 61 75 78 33 5f 64 61 74 61 20 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 ┆F ! aux3_data ! ! !┆
0xd260…d280 0d 0a a1 21 20 20 20 20 20 46 46 39 45 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! FF9E ! ┆
0xd280…d2a0 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a 21 20 20 20 20 20 46 46 39 44 20 20 20 20 21 20 61 75 ┆! ! ! ! FF9D ! au┆
0xd2a0…d2c0 78 32 5f 64 61 74 61 20 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a a1 21 20 20 20 20 20 ┆x2_data ! ! ! ! ┆
0xd2c0…d2e0 46 46 39 43 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 ┆FF9C ! ! ┆
0xd2e0…d300 21 05 21 0d 0a 21 20 20 20 20 20 46 46 39 42 20 20 20 20 21 20 61 75 78 31 5f 64 61 74 61 20 20 ┆! ! ! FF9B ! aux1_data ┆
0xd300…d320 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a a1 21 20 20 20 20 20 46 46 39 41 20 20 20 20 21 ┆ ! ! ! ! FF9A !┆
0xd320…d340 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a 21 20 20 20 ┆ ! ! ! ! ┆
0xd340…d360 20 20 46 46 39 39 20 20 20 20 21 20 72 65 63 5f 64 61 74 61 20 20 20 20 20 21 20 20 20 20 20 20 ┆ FF99 ! rec_data ! ┆
0xd360…d380 20 20 21 05 21 0d 0a a1 21 20 20 20 20 20 46 46 39 38 20 20 20 20 21 20 20 20 20 20 20 20 20 20 ┆ ! ! ! FF98 ! ┆
0xd380…d3a0 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a 21 20 20 20 20 20 46 46 39 37 20 20 20 ┆ ! ! ! ! FF97 ┆
0xd3a0…d3c0 20 21 20 65 78 70 5f 64 61 74 61 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a a1 21 ┆ ! exp_data ! ! ! !┆
0xd3c0…d3e0 20 20 20 20 20 46 46 39 36 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 ┆ FF96 ! ! ┆
0xd3e0…d400 20 20 20 20 20 21 05 21 0d 0a 21 20 20 20 20 20 46 46 39 35 20 20 20 20 21 20 61 64 72 5f 64 61 ┆ ! ! ! FF95 ! adr_da┆
0xd400…d420 (106,) 74 61 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a a1 21 20 20 20 20 20 46 46 39 34 ┆ta ! ! ! ! FF94┆
0xd420…d440 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d ┆ ! ! ! ! ┆
0xd440…d460 0a 21 20 20 20 20 20 46 46 39 33 20 20 20 20 21 20 65 72 72 5f 6e 6f 20 20 20 20 20 20 20 21 20 ┆ ! FF93 ! err_no ! ┆
0xd460…d480 20 20 20 20 20 20 20 21 05 21 0d 0a a1 21 20 20 20 20 20 46 46 39 32 20 20 20 20 21 20 65 72 72 ┆ ! ! ! FF92 ! err┆
0xd480…d4a0 6f 72 20 66 6c 61 67 20 20 20 21 20 20 20 20 20 20 20 20 21 05 21 0d 0a 1a 1a 6f 6e 64 69 6e 67 ┆or flag ! ! ! onding┆
0xd4a0…d4c0 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 2e 0d 0a 0d 0a b0 46 6c 6f 70 70 79 20 74 65 73 74 ┆ error number i. Floppy test┆
0xd4c0…d4e0 20 3a 20 64 72 69 76 65 20 6e 6f 74 20 72 65 61 67 75 72 61 74 0a b0 6f 74 20 66 6f 75 6e 64 0d ┆ : drive not reagurat ot found ┆
0xd4e0…d500 0a b0 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 ┆ Corresponding error number i┆