⟦8eb405be5⟧

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T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_

1. DESCRIPTION ........................................... 1
1.1 General Description .............................. 1
1.2 Functional Description ........................... 1
1.3 Power Supply ..................................... 2

2. BLOCK DIAGRAM ......................................... 4

3. LOGIC DIAGRAMS ........................................ 6
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F_ 1_._ _ _ _ _ _ _ _ _D_E_S_C_R_I_P_T_I_O_N_ 1.

1_._1_ _ _ _ _ _ _ _G_e_n_e_r_a_l_ _D_e_s_c_r_i_p_t_i_o_n_ 1.1

LIS701 is a V24-switch able to connect two of eight DTE>s with
two DCE>s, as requested by the DTE>s.

A DTE performs a connection request by means of the signals Data
Terminal Ready and Request To Send.

RTS is used to select the DCE, and DTR indicates connection
request.

If the selected DCE is not busy, the signals are connected
through, and the connection persists as long as DTR is true.

To each DCE output, is assigned a scanner, which, when the DCE is
not busy, scans the DTE-inputs for a possible connection request.

1_._2_ _ _ _ _ _ _ _F_u_n_c_t_i_o_n_a_l_ _D_e_s_c_r_i_p_t_i_o_n_ 1.2

The signal inputs from the DTE ports are connected through line
receivers to tristate gates connecting them to the A-bus or B-bus
(see the block diagram). The tristate enable signals ASEL(1) to
ASEL(8) and BSEL(1) to BSEL(8) are the decoded values of
A(0:2) and B(0:2). (The number 000 is converted into sel(8),
creating a sequence 1 to 8 rather than 0 to 7). The pointers
A(0:2) and B(0:2) are the outputs of two binary counters, which
when ABUSY and BBUSY are false, are scanning the DTE inputs for a
possible DTR.

If the A-scanner meets a DTR together with a RTS, ABUSY is set,
blocking the clockpulses to the A-scanner, turning on the
A-display indicating the value on the A-scanner, gating the
signals through between the DTE and the DCE and finally sending
DTR to the DCE.

1_._3_ _ _ _ _ _ _ _P_o_w_e_r_ _S_u_p_p_l_y_ 1.3

The power supply supplies +_12 V for the V24 transmitters, and +5
V for the logic. The +_12 V are supplied via monolitic serial
regulators. Due to the greater power dissipation resulting if a
linear regulator was used for the 5 V, a switch mode regulator is
used for this voltage.

The function of this regulator is best understood by rewriting
the diagram as done in figs. 1 and 2.

The box in fig. 1 contains a comparator and a 5 V reference. The
voltage on the output of this switches between +25 V and 0 V with
an average value of 5 V. The voltage developed across C is this
average superposed a small ripple voltage, equal to the
hysteresis defined by R1 and R2: Uripple.pp. = (r2/(R1+R2))*25 V.

The operation cyclus is thus: point 1 outputs 25 V until the
voltage on C has increased to 5 V + Uripple, then the voltage on
point 1 switches to 0 V, and the voltage on C decreases to 5 V,
at which voltage, point 1 again switches to +25 V, etc.

Fig. 2 shows what the box in fig. 1 really contains. The IC
LM78L05 contains the 5 V reference plus the comparator except the
"output stage". This consists of the transistor T and the
"freewheeling" diode D. Current flows always out of point 1
either through T from 25 V or through D from 0 V.

F_\f

F_ Signal Destination Description

RXD(1) J1 Received Data to J1
V24-levels

DSR(1) J1 Data Set Ready to J1
V24-levels

CTS(1) J1 Clear To Send to J1
V24-levels

CD(1) J1 Carrier Detect to J1
V24-levels

TXDA(1) p. 5 Transmitted Data from J1
tristate-multiplexed to A bus

DTRA(1) p. 5 Data Terminal Ready from J1
tristate-multiplexed to A bus

RTSA(1) p. 5 Request To Send from J1
tristate-multiplexed to A bus

TXD(1) p. 6 Transmitted Data from J1
tristate-multiplexed to B bus

DTR B(1) p. 6 Data Terminal Ready from J1
tristate-multiplexed to B bus

RTS B(1) p. 6 Request To send from J1
tristate-multiplexed to B bus

RXD(2) J2 Received Data to J2
V24-levels

DSR(2) J2 Data Set Ready to J2
V24-levels

CTS(2) J2 Clear To Send to J2
V24-levels

CD(2) J2 Carrier Detect to J2
V24-levels

TXDA(2) p. 5 Transmitted Data from J2
tristate-multiplexed to A bus

DTRA(2) p. 5 Data Terminal Ready from J2
tristate-multiplexed to A bus

RTSA(2) p. 5 Request To Send from J2
tristate-multiplexed to A bus

TXD(2) p. 6 Transmitted Data from J2
tristate-multiplexed to B bus

DTR B(2) p. 6 Data Terminal Ready from J2
tristate-multiplexed to B bus

RTS B(2) p. 6 Request To send from J2
tristate-multiplexed to B bus\f

F_\f

F_ Signal Destination Description

RXD(3) J3 Received Data to J3
V24-levels

DSR(3) J3 Data Set Ready to J3
V24-levels

CTS(3) J3 Clear To Send to J3
V24-levels

CD(3) J3 Carrier Detect to J3
V24-levels

TXDA(3) p. 5 Transmitted Data from J3
tristate-multiplexed to A bus

DTRA(3) p. 5 Data Terminal Ready from J3
tristate-multiplexed to A bus

RTSA(3) p. 5 Request To Send from J3
tristate-multiplexed to A bus

TXD(3) p. 6 Transmitted Data from J3
tristate-multiplexed to B bus

DTR B(3) p. 6 Data Terminal Ready from J3
tristate-multiplexed to B bus

RTS B(3) p. 6 Request To send from J3
tristate-multiplexed to B bus

RXD(4) J4 Received Data to J4
V24-levels

DSR(4) J4 Data Set Ready to J4
V24-levels

CTS(4) J4 Clear To Send to J4
V24-levels

CD(4) J4 Carrier Detect to J4
V24-levels

TXDA(4) p. 5 Transmitted Data from J4
tristate-multiplexed to A bus

DTRA(4) p. 5 Data Terminal Ready from J4
tristate-multiplexed to A bus

RTSA(4) p. 5 Request To Send from J4
tristate-multiplexed to A bus

TXD(4) p. 6 Transmitted Data from J4
tristate-multiplexed to B bus

DTR B(4) p. 6 Data Terminal Ready from J4
tristate-multiplexed to B bus

RTS B(4) p. 6 Request To send from J4
tristate-multiplexed to B bus\f

F_\f

F_ Signal Destination Description

RXD(5) J5 Received Data to J5
V24-levels

DSR(5) J5 Data Set Ready to J5
V24-levels

CTS(5) J5 Clear To Send to J5
V24-levels

CD(5) J5 Carrier Detect to J5
V24-levels

TXDA(5) p. 5 Transmitted Data from J5
tristate-multiplexed to A bus

DTRA(5) p. 5 Data Terminal Ready from J5
tristate-multiplexed to A bus

RTSA(5) p. 5 Request To Send from J5
tristate-multiplexed to A bus

TXD(5) p. 6 Transmitted Data from J5
tristate-multiplexed to B bus

DTR B(5) p. 6 Data Terminal Ready from J5
tristate-multiplexed to B bus

RTS B(5) p. 6 Request To send from J5
tristate-multiplexed to B bus

RXD(6) J6 Received Data to J6
V24-levels

DSR(6) J6 Data Set Ready to J6
V24-levels

CTS(6) J6 Clear To Send to J6
V24-levels

CD(6) J6 Carrier Detect to J6
V24-levels

TXDA(6) p. 5 Transmitted Data from J6
tristate-multiplexed to A bus

DTRA(6) p. 5 Data Terminal Ready from J6
tristate-multiplexed to A bus

RTSA(6) p. 5 Request To Send from J6
tristate-multiplexed to A bus

TXD(6) p. 6 Transmitted Data from J6
tristate-multiplexed to B bus

DTR B(6) p. 6 Data Terminal Ready from J6
tristate-multiplexed to B bus

RTS B(6) p. 6 Request To send from J6
tristate-multiplexed to B bus\f

F_\f

F_ Signal Destination Description

RXD(7) J7 Received Data to J7
V24-levels

DSR(7) J7 Data Set Ready to J7
V24-levels

CTS(7) J7 Clear To Send to J7
V24-levels

CD(7) J7 Carrier Detect to J7
V24-levels

TXDA(7) p. 5 Transmitted Data from J7
tristate-multiplexed to A bus

DTRA(7) p. 5 Data Terminal Ready from J7
tristate-multiplexed to A bus

RTSA(7) p. 5 Request To Send from J7
tristate-multiplexed to A bus

TXD(7) p. 6 Transmitted Data from J7
tristate-multiplexed to B bus

DTR B(7) p. 6 Data Terminal Ready from J7
tristate-multiplexed to B bus

RTS B(7) p. 6 Request To send from J7
tristate-multiplexed to B bus

RXD(8) J8 Received Data to J8
V24-levels

DSR(8) J8 Data Set Ready to J8
V24-levels

CTS(8) J8 Clear To Send to J8
V24-levels

CD(8) J8 Carrier Detect to J8
V24-levels

TXDA(8) p. 5 Transmitted Data from J8
tristate-multiplexed to A bus

DTRA(8) p. 5 Data Terminal Ready from J8
tristate-multiplexed to A bus

RTSA(8) p. 5 Request To Send from J8
tristate-multiplexed to A bus

TXD(8) p. 6 Transmitted Data from J8
tristate-multiplexed to B bus

DTR B(8) p. 6 Data Terminal Ready from J8
tristate-multiplexed to B bus

RTS B(8) p. 6 Request To send from J8
tristate-multiplexed to B bus\f

F_\f

F_ Signal Destination Description

RXDA p. 1. 2. 3. 4 Received Data to J9

DSRA p. 1. 2. 3. 4 Data Set Ready to J9

CTSA p. 1. 2. 3. 4 Clear To Send to J9

CDA p. 1. 2. 3. 4 Carrier Detected from J9

RTSA(7) p. 5, 7 Request To Send from A bus
V24-levels

TXD J9 Transmitted Data to J9
V24-levels
RDTR A,
RDTR A p. 7 Data Terminal Ready from A bus

DTR J9 Data Terminal Ready to J9
V24-levels
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F_\f

F_ Signal Destination Description

RXDB p. 1. 2. 3. 4 Received Data from J10

DSRB p. 1. 2. 3. 4 Data Set Ready from J10

CTSB p. 1. 2. 3. 4 Clear To Send from J10

CDB p. 1. 2. 3. 4 Carrier Detected from J10

RTSB p. 7 Request To Send from B bus
RTSB p. 5

RTS J10 Request To Send to J10
V24-levels

TXD J10 Transmitted Data to J10

RDTR B,
DTR B p. 7 Data Terminal Ready from B bus

DTR J10 Data Terminal Ready to J10
V24-levels
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F_\f

F_ Signal Destination Description

ABUSY p. 5, 7 port A busy, indicates that
ABUSY p. 1, 2, 3, 4, 7 A(0:2) points at an input port
which is currently connected
to port A.

A(0:2) p. 5, 7 A-Scanner output
BBUSY p. 6, 7 port B busy, indicates that
BBUSY p. 1, 2, 3, 4, 7 B(0:2) points at an input port
which is currently connected
to port B.

BUSYX p. 7 low when both scanners point
at same input port, and one is
busy. Used to prevent one
input from connecting to both
outputs, at the same time.

ASEL(1),
ASEL(2) p. 1
ASEL(3),
ASEL(4) p. 2 tristate-enable signals for
ASEL(5),
ASEL(6) p. 3 the A bus.
ASEL(7),
ASEL(8) p. 4

ASEL8 p. 5 most significant bit of
A(-1:2)

BSEL(1),
BSEL(2) p. 1
BSEL(3),
BSEL(4) p. 2 tristate-enable signals for
BSEL(5),
BSEL(6) p. 3 the B bus.
BSEL(7),
BSEL(8) p. 4

BSEL8 p. 6 most significant bit of
B(-1:2)
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F_\f

F_ Signal Destination Description

12 V/400 mA, Power supply for V24 trans-
-12 V/400 mA mitters

+5 V/850 mA Power supply for all
logic circuits, and
LED-displays.

T1, T2 Jumper is installed, when
signal ground is required
connected to protective
ground.

Powrst p. 7 Logic reset signal, goes low
when 5 V regulator starts
switching (when 5 V is up).

CP p. 7 Clockpulse for driving the
scanners, derived from the 5 V
switches. Frequency is about
30 KHz.
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F_\f

T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_

1. DESCRIPTION ........................................... 1

2. MIC702 MICROCOMPUTER AND CHARACTER GENERATOR .......... 6
2.1 General Description .............................. 6
2.2 Block Diagram .................................... 6
2.3 Functional Description ........................... 6
2.3.1 CPU Description ........................... 6
2.3.2 Address Decoder ........................... 10
2.3.3 Parallel I/O Controller ................... 10
2.3.4 Serial Input/Output Controller ............ 18
2.3.5 Counter Timer Controller .................. 20
2.3.6 Interrupt System .......................... 22
2.3.7 ROM Memory ................................ 28
2.3.8 RAM Memory ................................ 28
2.3.9 DMA Controller ............................ 28
2.3.10 Select Switches ........................... 36
2.3.11 Video Display Controller .................. 36
2.3.12 Floppy Disk Controller .................... 44
2.4 Character Generator .............................. 88

3. KBN702 CABINET WITH CABLES ECT. ....................... 92

4. POW739 POWER SUPPLY ................................... 104
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F_ 1_._ _ _ _ _ _ _ _ _D_E_S_C_R_I_P_T_I_O_N_ 1.

The RC702 Microcomputer is a selfcontained computer system, which
together with keyboard, videomonitor, and zero, one, or two
flexible disc drives make a complete computer system.

The keyboard used may be an RC721 or an RC722. The video monitor
used may be an RC752. The flexible disc drive may be an RC761 or
an RC762. All theese units are described in their own manuals.
Fig. 1.1 shows an example of how to connect these units.

The RC702 itself is built up by the following parts:

1. MIC702 Microcomputer board
2. ROAxxx Character generator
3. KBN702 Cabinet with cables, transformer, and rectifier
unit
4. CBL921 Internal video cable
5. CBL903 Internal power cable
6. CBL928 Internal sync. cable
7. CBL440 External power cable
8. POW739 Power supply

Part 1 and 2 are described in chapter 2 of this manual. Part 3 to
7 are described in chapter 3 of this manual, and part 8 is
described in chapter 4 of this manual.

F_ 2_._ _ _ _ _ _ _ _ _M_I_C_7_0_2_ _M_I_C_R_O_C_O_M_P_U_T_E_R_ _A_N_D_ _C_H_A_R_A_C_T_E_R_ _G_E_N_E_R_A_T_O_R_ 2.

2_._1_ _ _ _ _ _ _ _G_e_n_e_r_a_l_ _D_e_s_c_r_i_p_t_i_o_n_ 2.1

The MIC 702 is built on a single circuit board. Power is supplied
via a 4 pin connector, and MIC702 needs the following supply:

+5 V typical 2.5 Amp.
+12 V typical 0.1 Amp.
-12 V typical 0.1 Amp.

The board layout is shown in fig. 2.1 which also shows the input/
output connections.

2_._2_ _ _ _ _ _ _ _B_l_o_c_k_ _D_i_a_g_r_a_m_ 2.2

Fig. 2.2 shows a block diagram of MIC702. In the diagram is shown
where each block is found in the circuit diagrams.

2_._3_ _ _ _ _ _ _ _F_u_n_c_t_i_o_n_a_l_ _D_e_s_c_r_i_p_t_i_o_n_ 2.3

The functional description follows the block diagram. This paper
does not contain a full description of all the functions of the
VLSI circuits used in MIC702. This kind of informations may be
supplied by the manufactures of the VLSI circuits.

2_._3_._1_ _ _ _ _ _C_P_U_ _D_e_s_c_r_i_p_t_i_o_n_ 2.3.1

A block diagram of the architecture of the Z-80A CPU is shown in
fig. 2.3.1. The diagram shows all the major elements in the CPU
and it should be referred to throughout the following de-
scription.

Z-80A CPU contains 208 bits of R/W memory that are accessible to
the programmers. Fig. 2.3.2 illustrates how this memory is con-
figurated into eighteen 8-bit registers and four 16-bit
registers.\f

All Z-80A registers are implemented using static RAM. The regis-
ters include two sets of six general purpose registers that may
be used individually as 8-bit registers or in pairs as 16-bit re-
gisters. There are also two sets of accumulators and flag regis-
ters.

CPU timing can be broken down into a few very simple timing dia-
grams. The diagrams show basic operations with one wait state
(the wait state is added to synchronize the CPU to the RAM mem-
ory). Figs. 2.3.3 to 2.3.5 show the CPU timing.

The Z80A CPU can execute 158 different instruction types includ-
ing all 78 of the 8.080A CPU. A description of this may be ob-
tained from Zilog Z80A CPU Technical Manual.

2_._3_._2_ _ _ _ _ _A_d_d_r_e_s_s_ _D_e_c_o_d_e_r_ 2.3.2

The addressing of devices is made very simple with the circuit
shown in diagram page MIC03. Each device uses 4 addresses except
the DMA controller which uses 16 addresses. This is shown in fig.
2.3.6.

Addressing of dynamic RAM and ROM is made using the PROM in Pos.
55. Most significant bit in the PROM is controlled by the flip-
flop in Pos. 42. The flip-flop is reset by the RESET signal and
set by the program using the following instruction:

OUT (18 Hex), A

The resulting addressing is shown in fig. 2.3.7.

This circuit makes it possible for the program to disconnect the
program stored in PROM 0 and in PROM 1.

2_._3_._3_ _ _ _ _ _P_a_r_a_l_l_e_l_ _I_/_O_ _C_o_n_t_r_o_l_l_e_r_ 2.3.3

The Z-80A parallel I/O (PIO) interface controller is a program-\f

mable, two port device which provides interface between the CPU
and the two connectors for keyboard and for parallel I/O. The
diagram is shown on page MIC07. The block diagram is shown in
fig. 2.3.8. The internal structure of the Z80A-PIO consists of a
bus interface, internal control logic, port A I/O logic, port B
I/O logic, and interrupt control logic.

Each of the two port I/O logic is composed of 6 registers. The
registers include: an 8-bit input register, an 8-bit output re-
gister, a 2-bit moderegister, an 8-bit mask register, an 8-bit
input/output select register, and a 2-bit mask control register.

Before using the PIO it has to be programmed to the wanted Inter-
rupt Vector and operating mode. This is described in manuals from
Zilog.

The timing diagram in fig. 2.3.9 shows input from keyboard. The
interrupt system is described in subsection 2.3.7.

2_._3_._4_ _ _ _ _ _S_e_r_i_a_l_ _I_n_p_u_t_/_O_u_t_p_u_t_ _C_o_n_t_r_o_l_l_e_r_ 2.3.4

The Z80-SIO/2 (Serial Input/Output) is a dual-channel multi-func-
tion peripheral component designed to satisfy a wide varity of
serial data communications requirements in microcomputer systems.
Its basic function is a serial-to-parallel, parallel-to-serial
converter/controller, but - within that role - it is configurable
by system software so its "personality" can be optimized for a
given serial data communications application.

The Z80-SIO/2 is in RC702 capable of handling asynchronous
formats.

The Z80-SIO/2 can generate and check CRC codes in any synchronous
mode and can be programmed to check data integrity in various
modes. The device also has facilities for modem controls in both
channels. Block diagram for the Z80-SIO/2 is shown in fig.
2.3.10.
The internal structure includes Z80A CPU interface, internal con-\f

trol and interrupt logic, and two full duplex channels. Each
channel contains read and write registers, and discreet control
and status logic that provides interface to modems.

The logic for both channels provides formats, synchronization,
and validation for data transferred to and from the channel
interface. The modem control inputs, Clear to Send (CTS) and Data
Carrier Detect (DCD) are monitored by the discreet control logic
under program control. All the modem control signals are general
purpose in nature.

The programming for the SIO/2 is very complex and is described in
manuals from Zilog.

2_._3_._5_ _ _ _ _ _C_o_u_n_t_e_r_ _T_i_m_e_r_ _C_o_n_t_r_o_l_l_e_r_ 2.3.5

The Z80A Counter Timer Controller (CTC) is a programmable four
channel device that provides counting and timing functions for
the system. The diagram is shown in page MIC15 and the block dia-
gram is shown in fig. 2.3.11.

The internal structure of the Z80-CTC consists of a Z80 CPU bus
interface, internal control logic, four counter channels, and in-
terrupt control logic. Each channel has an interrupt vector for
automatic interrupt vectoring, and interrupt priority is determi-
ned by channel number with channel 0 having the highest priority.

The channel logic is composed of 2 registers, 2 counters, and
control logic as shown in fig. 2.3.12. The registers include an
8-bit constant register and an 8-bit channel control register.
The counters include an 8-bit readable down counter and an 8-bit
prescaler. The prescaler may be programmed to divide the system
clock by either 16 or 256.

Channel 0 and 1 are used to generate the clock to channel A and B
in the Z80A-SIO/2. The clock delivered to the SIO is again
divided in the SIO to make the baudrate for the terminal and
printer connections. Input to these two channels is a clock of\f

0.614 MHz. How the clock is divided in the SIO is shown in fig.
2.3.13.

Channel 2 and 3 are initiated in counter mode with interrupt
enabled and with a time constant of 1. This means that for every
clock input an interrupt is sent to the CPU. Channel 2 is
connected to the display controller and channel 3 is connected to
the floppy controller, and in this way their interrupt is
connected to the CPU.

2_._3_._6_ _ _ _ _ _I_n_t_e_r_r_u_p_t_ _S_y_s_t_e_m_ 2.3.6

The CPU has two interrupt inputs, a software maskable interrupt
and a non-maskable interrupt. The non-maskable interrupt (NMI)
cannot be disabled by the program and is not used in MIC702. The
CPU can be programmed to respond to maskable interrupts in one of
three modes. In MIC702 mode 2 is selected. In this mode a single
8-bit byte from the controller (the interrupt vector) is used to
make an indirect call instruction.

The interrupt signal is sampled by the CPU with the rising edge
of the last clock at the end of any instruction. When an
interrupt is accepted a special M1 cycle (INTA) is generated.
During this M1 cycle IORQ becomes active (instead of MREQ)
indicating the INTA cycle. The Z80 peripherals have an interrupt
enable input (IEI) and an interrupt enable output (IEO) and are
connected in daisy chain. The peripheral with IEI high and IEO
low, will during INTA place the preprogrammed 8-bit interrupt
vector on the data bus.

IEO is held low until a return from interrupt (RETI) instruction
is executed by the CPU while IEI is high. The 2-byte RETI
instruction is decoded internally by the peripheral for this
purpose.

Fig. 2.3.14 shows the daisy chain interrupt system in MIC702.

2_._3_._7_ _ _ _ _ _R_O_M_ _M_e_m_o_r_y_ 2.3.7

The ROM, Read Only Memory, contains the autoload program. After a
reset signal is generated, the CPU starts to execute the program
stored in POS. 66. In subsection 2.3.3 is shown how this addres-
sing is made. In a test situation both ROM POS. 66 and 65 may
contain a ROM. The ROMs are normally 2 K bytes PROM.

2_._3_._8_ _ _ _ _ _R_A_M_ _M_e_m_o_r_y_ 2.3.8

The RAM, Random Access Memory, is shown in 3 blocks in the block
diagram: the TIMING GEN block, the 64 K BYTES RAM block, and the
REG. block. This subsection describes these 3 blocks. The circuit
diagram is on page MIC05. The timing generator is made using the
IC I8202. This circuit makes all the signals which the RAM cir-
cuits need. Fig. 2.3.15 shows the block diagram for the I8202 and
the timing diagram for the whole RAM circuit is shown in fig.
2.3.16.

2_._3_._9_ _ _ _ _ _D_M_A_ _C_o_n_t_r_o_l_l_e_r_ 2.3.9

The DMA controller to MIC702 is based on the Am9517A-4 from
Advance Micro Devices or an 8237-2 from Intel. The IC is designed
to be used in conjunction with an external 8-bit address register
made by an 74LS373. The circuit diagram is shown in MIC06. The
Am9517A-4 contains 4 channels which have full 64 K address and
word count capability.

The four channels are in MIC702 used in the following way:

channel 0 : External debugger
channel 1 : Floppy disk controller
channel 2 : Visual display controller
chAnnel 3 : Visual display controller.

The block diagram for Am9517A-4 is shown in fig. 2.3.17.
\f

Fig. 2.3.18 shows the timing diagram for a normal operation of
Am9517A-4.

More specific description of the units. may be obtained from one
of the two manufacturers.

2_._3_._1_0_ _ _ _ _S_e_l_e_c_t_ _S_w_i_t_c_h_e_s_ 2.3.10

8 switches are situated on the board. Their position may be
sensed by the program. The switches are mainly used when the ROM
is replaced with a testprogram ROM. One switch (BUS 7) is used to
switch between Mini and Maxi floppy. The circuit may be seen in
diagram MIC15.

2_._3_._1_1_ _ _ _ _V_i_d_e_o_ _D_i_s_p_l_a_y_ _C_o_n_t_r_o_l_l_e_r_ 2.3.11

The video display controller is based on the 8275 programmable
CRT controller from Intel. The device interfaces the CRT raster
scan display with the system. The controller refreshes the
display by buffering the information from the memory and it keeps
track of the display position of the screen. Fig. 2.3.19 shows a
block diagram for the 8275 controller. The program initiates the
controller to make the wanted picture. The initiations needed may
be seen in the description from Intel.

The initiation made in MIC702 is listed in fig. 2.3.20.

The video display controller needs a number of registers, etc. to
support it. This circuits are shown in diagram pages MIC11 to
MIC14. Fig. 2.3.21 shows a block diagram with this circuit.

The output from the video display controller system is made with
comp. sync and with normal TTL signal output. In RC702 the comp.
sync. is used and fig. 2.3.22 shows the timing of this signal.

2_._3_._1_2_ _ _ _ _F_l_o_p_p_y_ _D_i_s_k_ _C_o_n_t_r_o_l_l_e_r_ 2.3.12

The floppy disk controller to MIC702 is based on the FDC chip
uPD765 from NEC or 8272 from Intel. The chip contains the
circuitry and control functions for interfacing the processor to
4 floppy disk drives. It supports both IBM3740 single density
format (FM) and IBM system 34 double density format including
double sided recording.

Fig. 2.3.23 shows a block diagram for the controller chip.

The uPD765 contains two registers which may be accessed by the
program. The 8-bit main status register contains the status
information of the FDC and may be accessed at any time. The 8-bit
data register (actually consists of several registers in stack
with only one register present to the bus at a time), which
stores data, commands, parameters, and floppy disk drive
information. Fig. 2.3.24 shows the information stored in the
status register.

Fig. 2.3.25 shows the information delivered to and from the data
register during a read or write instruction to the controller.
The programming of uPD765 is very complex and is described by the
manufacturer. The controller interfaced to both Maxi- and Mini
disk drives. The circuits on diagrams MIC09 and MIC10 show this.

Fig. 2.3.26 shows the data media floppy diskette. The diskette
contains a number of tracks which again are divided into a number
of sectors as shown in fig. 2.3.26. The controller is able to
format, read, or write the diskette. Information about the actual
formats used is available in the software manuals. Fig. 2.3.28
shows the two recording methods used.

Signal Destination Description
MIC No.

ADD(0:15) 3, 4, 5, 6, 7, 9, The address bus is the TRI-
11, 15, 16 state bus supplying address
information to all the
controllers.

BUS(0:7) 3, 5, 6, 7, 9 The data bus is the TRI-state
bus supplying data informa-
tion between the CPU and the
controllers.

WR 2 WRITE output from the CPU.
RD 2 READ - - - -
IORQ 2 INPUT OUTPUT REQUEST, when
active the WR or RD pulse is
addressing a controller and
not the memory.

M1 2 MACHINE CYCLE ONE, indicates
the op code fetch cycle of
the CPU.

MREQ 2 MEMORY REQUEST, indicates a
read or write memory cycle.

RFSH 2 REFRESH, indicates a refresh
cycle by the CPU, the signal
is not used in MIC702.

HALT HALT indicates that the CPU
is executing a halt instruc-
tion. An error situation.

BUS ACK 2 BUS ACKNOWLEDGE, the CPU has
received a BUS REQ and lets
the DMA use the BUS.

BUS EN 1 BUS ENABLE for the CPU.
\f

Signal Destination Description
MIC No.

WR BUF 1 * WRITE output pulse from the CPU
RD BUF 1, 7, 15, 16 * READ - - - - -
IORQ BUF 1, 7, 15, 16 * IORQ - - - - -
M1 BUF 7, 15, 16 * M1 - - - - -
M REQ BUF 4 * M REQ - - - - -
RFSH BUF * RFSH - - - - -

IOWR 3, 6, 7, 9 ** INPUT/OUTPUT WRITE, write
pulse to controllers which
are not of the Zilog type.

IORD 6, 9, 11, 15 ** INPUT/OUTPUT READ, read
pulse to controllers which
are not of the Zilog type.

MEM WR 4, 5 ** MEMORY WRITE pulse.

MEM RD 3, 4, 5 ** MEMORY READ pulse.

CLK 1, 4, 6, 7, 4 MHz symmetric clock to the
15, 16 system.

HOLD ACK 1, 6 BUS ACK signal through a
buffer.

BUS REQ 1 The DMA controller or the
tester demand control over the
BUS.

WAIT BUF 1 This signal inserts at least one
wait state in each CPU cycle.

NMI BUF 1 NON MASKABLE INTERRUPT, only
used by a tester.

INT BUF 1 INTERRUPT REQUEST to CPU.

HALT BUF HALT signal through a buffer.
DEBUG REQ 6 DMA REQUEST from a tester.
EXT ADDR STB 6 DMA REQUEST signal from a tester.
EXT AEN - - - - - -
ADDR EN 1, 2, 3, 4, 6 ADDRESS ENABLE when active the
CPU controls the BUS system.

INT PIN 15 INT PIN may be used by a unit
connected to J8 and is interrupt
priority in.

* signal is only active, when
ADDR EN is active.

** Signal may also be active when
ADDR EN is active. The DMA also
uses these signals, which are of
the TRI-state type.
\f

Signal Destination Description
MIC No.

EN DYN OUT 5 * This signal enables the
output register from the
RAM.
EN PROM 1 4 * This signal enables the
output from PROM 1 which is
only used when running a
testprogram.

EN PROM 0 4 * This signal enables the
output from PROM 0 which
contains the program used
under initiation.

EN DISP 11 * ENABLE DISPLAY controller
EN FLOP 9 * ENABLE FLOPPY controller
EN SIO 16 * ENABLE SERIAL IN/OUT
controller
EN CTC 15 * ENABLE COUNTER/TIMER
controller
EN PIO 7 * ENABLE PARALLEL IN/OUT
controller
EN SWITCH 3, 15 * ENABLE SWITCHES
DIS PROM * DISABLE PROM, the signal is
used to disable the PROM
and enable the whole RAM
EN SOUND 7 * ENABLE SOUND gives the
acoustic signal
EN DMA 6 * ENABLE DMA controller

MOTOR EN 10 MOTOR ENABLE is used to
switch on and off the motor
used in the Mini floppy disk
drive.

RESET 1, 3, 6, 9, 11 RESET is the power up reset
15, 16 or a RESET initiated from the
switch on the front of the
computer.

* Subsection 2.3.3. describes
the actual addresses used in
MIC702.
\f

Signal Destination Description
MIC No.

BUS(0:7) The data bus is the TRI-state
bus supplying data informa-
tion between the CPU and the
controllers.

WAIT 2 WAIT supplies at least one
wait state to the CPU-fetch
cycle. More wait states are
inseted when the RAM control-
ler is making a refresh
cycle.

WAIT DMA 6 WAIT DMA supplies at least
one wait state in the
DMA-cycle. More wait states
are supplied when the memory
controller is making a
refresh cycle.
\f

Signal Destination Description
MIC No.

BUS(0:7) The data bus is the TRI-state
bus supplying data informa-
tion between the CPU and the
controllers.

SACK 4 Output signal from the RAM
controller showing that the
cycle is finished. (SACK
means System Acknowledge).
\f

Signal Destination Description
MIC No

ADD(0:7) Address lines containing the
8 most significant bits. Bit
(0:4) is both input to the
DMA controller (under
programming) and output from
the DMA controller (under
DMA-cycle).

DACK 0 2 Data acknowledge answer to
debug request.

FDACK 9 Floppy data acknowledge,
answer to FD req. delay.

DACK 2 11 Data acknowledge answer to
DREQ2.
DACK 3 Data acknowledge answer to
DREQ3.

DISP ACK 11 Display acknowledge. The
display controller uses two
channels in the DMA.

TERMINAL COUNT 2, 9, 11 The signal is used to
terminate the operation.

HOLD 2 Request to stop the CPU.

DMA ADDR EN 2 Request to gain control over
the data and address bus.

MEM RD Memory read output from the
DMA.

MEM WR Memory write output from the
DMA.

ADDR STROBE 6 Address strobe is a pulse to
load the address register.

BUS(0:7) Data bus used to supply
information between the CPU
and the controllers. Here
also used to send address
information from the DMA
controller to the address
register.

HOLD ACK Hold acknowledge is the
replay from the CPU that the
bus is idle.

FD REQ DEL DMA request signal from
floppy disk controller.
\f

Signal Destination Description
MIC No.

KEY(0:7) 8-bit parallel input used to
receive information from the
keyboard.

KEY STROBE Input strobe from the
keyboard.

IN/OUT(0:7) 8-bit parallel input/output
used to receive or transmit
information to and from an
external unit.

STROBE Input strobe from external
unit.

INT 2 Interrupt request.

INT P OUT 2 Interrupt priority out.
\f

Signal Destination Description
MIC No.

8 MHz 8, 9 Symmetric clock signal of 8 MHz
4 MHz 2, 8 - - - - 4 MHz
2 MHz 8 - - - - 2 MHz
1 MHz 8 - - - - 1 MHz
0.5 MHz 8 - - - - 0.5 MHz
0.25 MHz 8 - - - - 0.25 MHz

CLOCK 1 10 Clock to read logic for the
CLOCK 2 8 floppy controller. Frequency
is selected by the controller
and by the MINI SELECT
switch.

8 MHz/4 MHz 9 Clock to the floppy
controller 8 MHz for Maxi
floppy and 4 MHz for Mini
floppy drive.

WRITE CLOCK 9 Clock input to floppy
controller. The frequency is
selected by the controller
and by the MINI SELECT
switch.

MEM CLOCK 5, 15 Clock to the memory
controller. The frequency is
19.66 MHz.
\f

Signal Destination Description
MIC No.

WR DATA 10 WRITE DATA to the floppy disk
drive. Valid when WRITE GATE
is on.

WRITE GATE 10 Control signal to floppy disk
drive. Informs that now the
WR DATA is valid.

MFM MODE 8 MFM mode is dual density,
FM mode is single density.

VCO 10 Signal to control the voltage
controlled oscillator.

SEEK MODE 10 Sets the selectors in seek
mode.

FR/STP 10 Control signal; Fault Reset/
Step
LC/DIR 10 Control signal; Low Current/
Direction
HEAD LOAD 10 Control signal; Head Load
SIDE SELECT 10 Control signal; Side Select
US0, US1 Unit select decoded to:
DRIVE SEL 0 10 Drive Select 0
DRIVE SEL 1 10 Drive Select 1
DRIVE SEL 2 10 Drive Select 2
DRIVE SEL 3 10 Drive Select 3.

FD REQ 6 DMA reguest from floppy
controller.

F INTP 15 Floppy controller interrupt
request.

RDY 9 Ready from floppy controller.
Note that Mini floppy is
always ready.

INDEX 9 Index mark from floppy disk
drive.
\f

Signal Destination Description
MIC No.

READ DATA 9 Read data from the floppy,
synchronized with the VCO to
separate phase bits and data
bits.

LD COUNT 10 Load counter is used to
synchronize the window
counter.

D WINDOW 9, 10 Data Window is used by the
controller to separate data
bits from phase bits.

STEP 10 Output pulse to make the
floppy head move from one
cylinder to the next.

DIRECTION SEL 10 Direction select is used
together with the STEP pulse.
A low signal and the head
moves towards the counter of
the disc.

WP/TS 9 Write Protect/Two Sided
signal from the floppy disk
drive.

FLT/TRO 9 Fault/Track 0 signal from
floppy disk drive.

LOW CURRENT 10 Output signal to Maxi floppy
disc drive. Used to decrease
the write current when close
to the center of the disk.

INDEX 9 Index mark signal from the
floppy.
TRACK 0 10 Track 0 signal from the
floppy.
WRITE PROT 10 The diskette used is
writeprotected.
RD DATA 10 Read data supplied from the
floppy disk drive including
data and phase bits.

READY 9 Ready signal from the Maxi
floppy drive.
TWO SIDED 10 The Maxi floppy is a two
sided version.
\f

Signal Destination Description
MIC No.

DSP DRQ 11 DMA request from the display
controller.

BUFF CC(0:6) 12 Output from the display
controller containing the
address of the character to
be written on the display.

BUFF LC(0:3) 12 Output from the display
controller containing the
line number written on the
display.

LTEN DEL 11 Light enable from the
display.

VSP DEL 11 Video suppression. This
output signal is used to
blank the video to the
display.

GPA 0 11 Control signal used to select
semigraphic PROM.

DISP INTR 11, 15 Display interrupt request.

HRTC BUF B 13 Horizontal retrace signal.
VRTC BUF B 13 Vertical retrace signal.
LTEN BUF B 13, 14 LTEN DEL delayed one CHAR
CLOCK
VSP BUF B 13 VSP DEL delayed one CHAR
CLOCK
RVV BUF B 13 REVERSE VIDEO. This output is
used to reverse the video
signal to the display.

CHAR GEN SEL 12 This signal selects the
standard character
generator.

GRAF GEN SEL 12 This signal selects the
semigraphic character
generator.

DRQ3 and DRQ2 6 The display controller uses
two channels out of the DMA>s
four channels. This is done
to make the roll function of
the display. DRQ2 and DRQ3
are the two data request
signals.
\f

Signal Destination Description
MIC No.

SERIAL VIDEO 13 The video output from the
shift register.

LOAD 12 Signal to load the output
from the character ROM or the
semigraphic ROM into the
shift register.

CH CLOCK 11 Character clock. The period
time of this clock is 7 times
the DOT CLOCK time.

7 x 86 nsec. = 0.601 usec.
\f

Signal Destination Description
MIC No.

VIDEO OUT 13 Video out signal. *)

HRTC OUT 13 Horizontal output pulse. *)

VRTC OUT Vertical output pulse. *)

*) These three signals are
ready to be used if a
video monitor without
decoding for comp. video
is used. RC702 uses comp.
video signals.

COMP VIDEO Compressed video is the
signal containing both video
horizontal sync. and vertical
sync.

+5 V filtered 7 +5 V supply after an RC
filter.
\f

Signal Destination Description
MIC No.

DOT CLOCK 12 The dot clock is an 11.64 MHz
clock which is synchronized
with the main frequency.

SYNC IN The input is a 50 Hz signal
from the REC701 rectifier
unit.

T1 Testpoint 1. The signal here
is a 50 Hz signal and the
coil H1 is adjusted until the
dutycycle of this signal is
50%.

-5 V The -5 V is used to the
dynamic RAM.
\f

Signal Destination Description
MIC No.

BUS(0:7) 1 The data bus is the TRI-state
bus supplying data
information between the CPU
and all of the controllers.

MINI SELECT 8, 9 Control signal selects Mini
floppy disk drives. The
signal is supplied to the
clock generator and divides
the clock signals to the
floppy controller by two.

9.63 MHz 2 Clock of 9.63 MHz is not used
on the board but supplied to
the output plug J8.

0.614 MHZ 15 Clock of 0.614 MHz is used as
input to the counter timer
controller to be counted down
to make the clock signal to
the two Serial In/Out
Channels.

CLOCK A 16 Clock signal to the two
CLOCK B 16 Serial In/Out Channels just
mentioned.

CHAIN 1 16 Interrupt priority chain

INT Interrupt from the counter
timer controller.
\f

Signal Destination Description
MIC No.

WAIT 4 This open collector output
from the SIO is connected to
the WAIT signal generated on
page 04 and slows the CPU
down to wait for the SIO.

INT 2 Interrupt request from the
SIO/2.
CHAIN 2 Interrupt priority chain out
from the SIO/2.

V.24 input outputs Pin 2 TRANS DATA
- 3 REC DATA
- 4 REQ TO SEND
- 5 CLEAR TO SEND
- 7 Ground
- 8 DATA CARRIER DETECT
- 20 DATA TERM READY

J1 to channel A (Terminal)
J2 to channel B (Printer)
\f

F_ 2_._4_ _ _ _ _ _ _ _C_h_a_r_a_c_t_e_r_ _G_e_n_e_r_a_t_o_r_ 2.4

The character generator is made of the ROM with the technical
name ROA296 and the layout is shown in fig. 2.5. The different
national alphabets are chosen via the software.

Fig. 2.6 shows the ROM with the name ROA327 which makes the
semigraphic alphabeth.

F_ 3_._ _ _ _ _ _ _ _ _K_B_N_7_0_2_ _C_A_B_I_N_E_T_ _W_I_T_H_ _C_A_B_L_E_S_ _E_C_T_. 3.

Fig. 3.1 shows the cabinet KBN702 with the power supply POW739
mounted. The cabinet itself contains transformer, blower, mains
connection, rectifier unit RC702, and the internal cable.

Fig. 3.2 shows the cabinet with MIC702 mounted.

Fig. 3.3 shows diagram for rectifier unit and transformer,
blower, and main connection.

Fig. 3.4 shows the internal cable in the KBN702.

Fig. 3.5 shows the cables connection KBN702 to MIC702 and POW739.

Fig. 3.6 shows the power cable CBL440.

F_ 4_._ _ _ _ _ _ _ _ _P_O_W_7_3_9_ _P_O_W_E_R_ _S_U_P_P_L_Y_ 4.

The power supply to RC702 is built on a single printed circuit
board. Fig. 4.1 shows a block diagram for the POW739.

Input to the powersupply is +26 V DC or -26 V DC delivered from
REC702 rectifier unit. This unit is described in chapter 3.

Fig. 4.2 shows the layout of the printed circuit board.

Fig. 4.3 and fig. 4.4 show the circuit diagram for the unit.

Fig. 4.5 and fig. 4.6 show the timing diagram for the unit.

T_A_B_L_E_ _O_F_ _C_O_N_T_E_N_T_S_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _P_A_G_E_

1. INTRODUCTION ........................................... 1

2. CALL ................................................... 2

3. FUNCTION ............................................... 3

4. STORAGE REQUIREMENTS ................................... 4

5. ERROR MESSAGES ......................................... 5

6. EXAMPLES ............................................... 6
6.1 base user ......................................... 6
6.2 base abs .......................................... 6
6.3 base 1 ............................................ 6
6.4 base what ......................................... 6
6.5 base what std 0 3 what ............................ 7
\f

1_._ _ _ _ _ _ _ _ _I_N_T_R_O_D_U_C_T_I_O_N_ 1.

The program changes the catalog base of the job process according
to the parameters in the call.

The catalog, standard, user and max bases of the process may be
listed on current output before as well as after the change of
catalog base.

The catalog base may be changed to any interval which is con-
tained in (or equal to) the max base and which also contains the
std base, equals it or is contained in the std base.

F_ 2_._ _ _ _ _ _ _ _ _C_A_L_L_ 2.

M_m_m_ " 1 1 1
base (what) (<specifier>) (<modifier>) (what)
P_p_p_ 0 0 0 0
<specifier>::= std user max abs
M_m_m_ 1
<modifier>::= <modif1> (<modif2>)
P_p_p_ 0
<modif1>::=
<modif2>::= <integer> <integer>.<integer>

However, an empty modifier to the specifier 'abs', i.e. the call:

base abs

will not be accepted.
\f

F_ 3_._ _ _ _ _ _ _ _ _F_U_N_C_T_I_O_N_ 3.

If the parameter 'what' is met before a possible specifier/mo-
difier, the current values of the catalog base, standard base,
user base and max base of the job process are listed on current
output.

The catalog base of the job process is changed to the interval
specified. The interval is found as follows:

1) The specifier is determined:
no specifier: the lower limit of the current catalog base
std : the lower limit of the current standard base
user : the lower limit of the current user base
max : the lower limit of the current max base
abs : the integer zero

2) The new interval is derived from the specifier and a possible
modifier:
no modifier: lower limit, upper limit of the specified base
<modif1> : specifier + <modif1>, specifier + <modif1>
<modif1>.<modif2>: specifier + <modif1>, specifier + <modif2>

The parameter <modif1>.<modif2> is interpreted as <modif1>
shift 12 + <modif2>

By specifying <modif1> greater than 2047, a negative modifier
may be specified.

This may also be done by specifying an integer greater than
8 388 607, e.q. the modifier -1000 is specified as 16 777 216
- 1000 = 16 776 216.

Notice that an empty specifier/modifier defines the current cata-
log base, i.e. no change.

If the parameter 'what' is met after a possible specifier/mo-
difier, the values of the bases after the changes of catalog base
are listed on current output.
\f

F_ 4_._ _ _ _ _ _ _ _ _S_T_O_R_A_G_E_ _R_E_Q_U_I_R_E_M_E_N_T_S_ 4.

512 halfwords plus space for FP.
\f

F_ 5_._ _ _ _ _ _ _ _ _E_R_R_O_R_ _M_E_S_S_A_G_E_S_ 5.

*** base interval
The interval specified is not a legal catalog base for the
job process. The catalog base remains unchanged.

*** base param
Parameter error in the call of the program. The catalog base
remains unchanged.
\f

F_ 6_._ _ _ _ _ _ _ _ _E_X_A_M_P_L_E_S_ 6.

6_._1_ _ _ _ _ _ _ _b_a_s_e_ _u_s_e_r_ 6.1

The call
base user
will change the catalog base to equal the user base.

6_._2_ _ _ _ _ _ _ _b_a_s_e_ _a_b_s_ 6.2

The call
base abs 1532 1584
will change the catalog base to the interval 1532, 1584 provided
it is a legal catalog base for the process.

6_._3_ _ _ _ _ _ _ _b_a_s_e_ _1_ 6.3

The call
base 1
will change the catalog base to the interval lower catalog base +
1, lower catalog base + 1 provided it is a legal catalog base.

6_._4_ _ _ _ _ _ _ _b_a_s_e_ _w_h_a_t_ 6.4

The call
base what
will write
cat base : 420 429
std base (login) : 420 420
user base : 420 429
max base (project) : 400 499
provided the current bases have these values.

6_._5_ _ _ _ _ _ _ _b_a_s_e_ _w_h_a_t_ _s_t_d_ _0_ _3_ _w_h_a_t_ 6.5

The call
base what std 0 3 what
will write
cat base : 420 429
std base (login) : 420 420
user base : 420 429
max base (project) : 400 499

cat base : 420 423
std base (login) : 420 420
user base : 420 429
max base (project) : 400 499
provided the bases of the process initially have the above
values.

F_
\f

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