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    Length: 4112 (0x1010)
    Types: TextFile
    Notes: UNIX file
    Names: »sunreg.h«

└─⟦a6ab2eb36⟧ Bits:30004042/kconfig3.imd SW95705I 386/ix Multi-user Release 1.2
└─⟦a6ab2eb36⟧ UNIX Filesystem
    └─⟦this⟧ »kc/new/usr/include/sys/sunreg.h« 

TextFile

/*
 * defines for the SUNRIVER driver
 */

/*
 * Copyrighted as an unpublished work.
 * (c) Copyright 1987 INTERACTIVE Systems Corporation
 * All rights reserved.
 *
 * RESTRICTED RIGHTS
 *
 * These programs are supplied under a license.  They may be used,
 * disclosed, and/or copied only as permitted under such license
 * agreement.  Any copy must contain the above copyright notice and
 * this restricted rights notice.  Use, copying, and/or disclosure
 * of the programs is strictly prohibited unless otherwise provided
 * in the license agreement.
 */

#ident  "@(#)sunreg.h	1.2 - 88/04/04"

/* need this for final release driver */
#define NEWSUN  1

/* number of final devices supported, 2 boards, 4 chips, 8 remote terminals */
#define NSUNBRDS 2
#define NSUNCHIPS  NSUNBRDS * 2
#define NSUNTERMS  NSUNBRDS * 4
#define SUNDIV  2

/* enable interrupts on terminal or not */
#define NOENABLE  0xff
#define ENABLE    0x00

/* size of the board */
#define SUNSIZE 0x60000     /* 192K */

/* board status bits */
#define ABSENT 0x01
#define PRESENT  0x02
#define BSTATMASK 0x03    /* use for anding out ABSENT/PRESENT */

/* terminal status info */
#define DEAD      0x10
#define ALIVE     0x20
#define TSTATMASK 0xCF    /* use for anding out DEAD/ALIVE */
#define SLEEPING  0x40

/* the offset from the base address is different in the two releases */
#define BASEADDR         0xF00000
#define BASEOFFSET       0x00
#define SUN_CNTRLBASE    0xFF00
#define SUN_SCRBASE      0x10000 
#define SUN_SWMEMBASE    SUN_SCRBASE

/* here are the registers on each board */
#define CHANNELSELECT  SUN_CNTRLBASE + 0      /* top 6 bits = board, 
						    bottom 2 = channel */
#define MODEREGISTER   SUN_CNTRLBASE + 1      /* mode register see below */
#define INTCHANNEL     SUN_CNTRLBASE + 2      /* interrupt channel id    */
#define INTDEVID       SUN_CNTRLBASE + 3      /* device id register */
#define INTSTATUS      SUN_CNTRLBASE + 4      /* interrupt control/status*/
#define IRQLEV         SUN_CNTRLBASE + 5      /* not used  */
#define INTLATCH       SUN_CNTRLBASE + 6      /* interrupt latch register*/

/* the mode register can operate in 4 ways */
#define DIRECT_IO     0x01       /* EGA registers in io space         */
#define PAGED_IO      0x00       /* EGA registers in memory space     */
#define SW_DIRECT_IO  0x05       /* Switched memory with direct io    */
#define SW_PAGED_IO   0x04       /* switched memory with paged io     */

/* interrupt channel id register has two types - Note: ACTIVE LOW */
#define INT_STATION   0x01
#define INT_TIMEOUT   0x02
#define INT_SHIFT_VAL 2

/* the interrupt device id register contents will be used as an index into  
   our array of interrupt vectors */
#define POWERUP    0x00      /*  power up reset interrupt */
#define KEYBINT    0x01      /*  interrupt from keyboard */
#define EGAINT     0x02      /*  this should almost never occur */
#define COM2INT    0x03      /*  interrupt from COM1 serial port */
#define COM1INT    0x04      /*  interrupt from COM2 serial port */
#define PARINT     0x05      /*  interrupt from parallel port */

/* the interrupt status register */
#define ENABLEINT   0x01     /* enables interrupts for the chip */
#define INTSTATMASK 0x04     /* indicates this chip requested the interrupt */
                             /* Note: ACTIVE LOW */ 

/* switched memory registers */
#define SW_RESET     SUN_SWMEMBASE + 0
#define SW_REARM     SUN_SWMEMBASE + 4
#define SW_HACK      SUN_SWMEMBASE + 1
#define SW_EGACNTRL  SUN_SWMEMBASE + 7

/* temp definitions */
#define PARR_TEMP_REG   0x3bc    /* address of parallel register */

/* main macro's that convert direct io operations to memory operations */
#define SUNOUT( address, value )   ((char *) brdaddr) [(address)] = (unsigned char) (value)
#define SUNIN( address )      (unsigned char)((char *) brdaddr)[(address)]

#define CPQ_OFFSET	0x80000000	/* offset used on Compaq machines to */
					/* avoid the cache		     */
#define VGA_DISAB       0x46e8          /* register to disable the VGA adapter
					   on Compaq VGA's when a SunRiver is
					   bankswitched in  */