|
DataMuseum.dkPresents historical artifacts from the history of: Regnecentalen RC-900 |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about Regnecentalen RC-900 Excavated with: AutoArchaeologist - Free & Open Source Software. |
top - metrics - downloadIndex: T U c
Length: 3914 (0xf4a)
Types: TextFile
Notes: UNIX file
Names: »cram.h«
└─⟦22cab2c1b⟧ Bits:30004042/kcaddon.imd SW95705I 386/ix Multi-user Release 1.2
└─⟦22cab2c1b⟧ UNIX Filesystem
└─⟦this⟧ »KC/new/usr/include/sys/cram.h«
/*
* Defines for accessing the PC AT CMOS ram.
*/
/*
* Copyrighted as an unpublished work.
* (c) Copyright 1986 INTERACTIVE Systems Corporation
* All rights reserved.
*
* RESTRICTED RIGHTS
*
* These programs are supplied under a license. They may be used,
* disclosed, and/or copied only as permitted under such license
* agreement. Any copy must contain the above copyright notice and
* this restricted rights notice. Use, copying, and/or disclosure
* of the programs is strictly prohibited unless otherwise provided
* in the license agreement.
*/
/* 87.09.04 rc extensions to nvm included */
#ident "@(#)cram.h 1.3 - 87/01/06"
#define CMOS_ADDR 0x70 /* I/O port address for CMOS ram address */
#define CMOS_DATA 0x71 /* I/O port address for CMOS ram data */
#define DSB 0x0e /* Diagnostic status byte ram address */
#define SSB 0x0f /* Shutdown status byte ram address */
#define DDTB 0x10 /* Diskette drive type byte ram address */
#define FDTB 0x12 /* Fixed disk type byte ram address */
#define EB 0x14 /* Equipment byte ram address */
#define BMLOW 0x15 /* Base mem size low byte ram address */
#define BMHIGH 0x16 /* Base mem size high byte ram address */
#define EMLOW 0x17 /* Expansion mem size low byte ram address */
#define EMHIGH 0x18 /* Expansion mem size high byte ram address */
#define DCEB 0x19 /* Drive C Extended byte ram address */
#define DDEB 0x1a /* Drive D Extended byte ram address */
#define CKSUMLOW 0x2e /* Checksum low byte ram address */
#define CKSUMHIGH 0x2f /* Checksum high byte ram address */
#define EMLOW2 0x30 /* Expansion mem size low byte ram address */
#define EMHIGH2 0x31 /* Expansion mem size high byte ram address */
#define DCB 0x32 /* Date century byte ram address */
#define IF 0x33 /* Information flag ram address */
/*
* RC NWM assignments
*/
#define DRV_C_CYLLOW 0x40 /* Drive C no of cylinders, low byte */
#define DRV_C_CYLHIGH 0x41 /* , high byte */
#define DRV_C_LZLOW 0x42 /* Drive C landing zone, low byte */
#define DRV_C_LZHIGH 0x43 /* D0-D2: Drive C landing zone, high byte */
/* D3-D7: Drive C no of heads */
#define DRV_C_PCLOW 0x44 /* Drive C pre compensation, low byte */
#define DRV_C_PCHIGH 0x45 /* D0-D1: Drive C pre compensation, high byte */
/* D2-D7: Drive C sectors per track */
#define DRV_D_CYLLOW 0x46 /* Drive D no of cylinders, low byte */
#define DRV_D_CYLHIGH 0x47 /* , high byte */
#define DRV_D_LZLOW 0x48 /* Drive D landing zone, low byte */
#define DRV_D_LZHIGH 0x49 /* D0-D2: Drive D landing zone, high byte */
/* D3-D7: Drive D no of heads */
#define DRV_D_PCLOW 0x4a /* Drive D pre compensation, low byte */
#define DRV_D_PCHIGH 0x4b /* D0-D1: Drive D pre compensation, high byte */
/* D2-D7: Drive D sectors per track */
#define CARDMASK 0x4c /* Intelligent controllers installed: */
/* D0: LAN451 or 452 no 1 installed */
/* D1: LAN451 or 452 no 2 installed */
/* D2: COM451 no 1 installed */
/* D3: COM451 no 2 installed */
/* D4: MUX451 no 1 installed */
/* D5: MUX451 no 2 installed */
/* D6,D7: reserved for future use */
/* 0x4d reserved for future use */
#define CARDWINDOWS 0x4e /* number of 64K segments reserved for */
/* communication with and between */
/* intelligent cards */
#define DEBUGFLAGS 0x4f
#define EGACONF 0x50 /* EGA configuration: */
/* D0: CGA auto emulation on */
/* D1: 8 * 16 bit character font on */
/* D2-D7: reserved */
#define RCINIT 0x7e /* = 5a if 0x40-0x7e is initialized */
#define RCMAGIC 0x5a
#define CHECKSUM 0x7f /* checksum of bytes 0x40 .. 0x7e */
/* bits in DEBUGFLAGS */
#define ENTERDEBUGGER 0x1
#define CTRLALTSYSREQ 0x2
#define NVMTESTBIT 0x4
/*
* ioctls for accessing CMOS ram.
*/
#define CMOSIOC ('C' << 8)
#define CMOSREAD (CMOSIOC | 0x01)
#define CMOSWRITE (CMOSIOC | 0x02)
extern unsigned char CMOSread();