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    Length: 5323 (0x14cb)
    Types: TextFile
    Notes: UNIX file
    Names: »scc.h«

└─⟦a6ab2eb36⟧ Bits:30004042/kconfig3.imd SW95705I 386/ix Multi-user Release 1.2
└─⟦a6ab2eb36⟧ UNIX Filesystem
    └─⟦this⟧ »kc/new/usr/include/sys/scc.h« 

TextFile

/*
 * ICC Driver bit and register definitions for SCC chip
 */

/*
 * Copyrighted as an unpublished work.
 * (c) Copyright 1986,1988 INTERACTIVE Systems Corporation
 * All rights reserved.
 *
 * RESTRICTED RIGHTS
 *
 * These programs are supplied under a license.  They may be used,
 * disclosed, and/or copied only as permitted under such license
 * agreement.  Any copy must contain the above copyright notice and
 * this restricted rights notice.  Use, copying, and/or disclosure
 * of the programs is strictly prohibited unless otherwise provided
 * in the license agreement.
 */

#ident "@(#)scc.h	1.2 - 88/02/02"
#ident "@(#) (c) Copyright INTERACTIVE Systems Corporation 1986,1988"

/* write registers */
#define IMODE	1
#define	IVEC	2
#define	RMODE	3
#define	BMODE	4
#define	TMODE	5
#define	SYNC1	6
#define	SYNC2	7
#define	TDATA	8
#define	IENABL	9
#define	SCNTRL	10
#define	CLKMODE	11
#define	CLKLO	12	/* may also be read */
#define	CLKHI	13	/* may also be read */
#define	MISC	14
#define	WR15	15	/* may also be read */
/* read registers */
#define	RERROR	1
#define	VECTOR	2	/* modified in channel B only */
#define	INTR	3	/* channel A only */
#define	RDATA	8

/* bit definitions */
/* WR0 */
#define	EXRESET	0x10		/* external/status latch reset */
#define	SABORT	0x18		/* send abort (SDLC) */	
#define	RXRESET	0x20		/* Rx interrupt enable */
#define	TXRESET	0x28		/* Tx interrupt reset */
#define	ERRESET	0x30		/* receive error reset */
#define	IRESET	0x38		/* int reset */
/* IMODE */
#define	WENABL	0x80		/* wait enable */
#define	WAITDMA	0x40		/* 0=wait, 1=request */
#define	WAITDIR	0x20		/* 0=xmit, 1=rcv */
#define RISPEC	0x18		/* Rx int on special condition only */
#define	RIALL	0x10		/* Rx int on all chars */
#define	RIFIRST	0x08		/* Rx int on error or first char only */
#define	PARINT	0x04		/* enable parity special condition */
#define	TIENABL	0x02		/* Tx int enable */
#define EIENABL	0x01		/* External status int enable */
/* RMODE */
#define	RX8BITS	0xC0		/* receive character width */
#define	RX7BITS	0x40
#define	RX6BITS	0x80
#define	RX5BITS	0x00
#define	AUTOEN	0x20		/* auto enable (hardware handshaking */
				/* CTS enables xmit, CD enables rcv */
#define	RXENABL	0x01		/* enable receiver */
/* BMODE */
#define	DIV1	0x00		/* clock divisor */
#define	DIV16	0x40
#define	DIV32	0x80
#define	DIV64	0xC0
#define	STOP1	0x04		/* stop bits */
#define	STOP1P5	0x08
#define	STOP2	0x0C
#define	EVENP	0x02		/* 0=odd, 1=even parity */
#define	PENABL	0x01		/* enable parity */
/* TMODE */
#define	DTR	0x80		/* dtr control bit */
#define	TX8BITS	0x60		/* xmit character width */
#define	TX7BITS	0x20
#define	TX6BITS	0x40
#define	TX5BITS	0x00
#define	SNDBRK	0x10		/* send break */
#define	TXENABL	0x08		/* enable xmitter */
#define	RTS	0x02		/* rts control bit */
/* IENABL */
#define	HRESET	0xC0		/* hardware reset */
#define	RESETA	0x80		/* reset channel A */
#define	RESETB	0x40		/* reset channel B */
#define	MIE	0x08		/* master interrupt enable */
#define	DLC	0x04		/* disable lower chain */
#define	NV	0x02		/* no vector on interrupt */
#define	VIS	0x01		/* vector includes status */
/* SCNTRL */
#define LOOP	0x02		/* loop mode */
/* CLKMODE */
#define	XTAL	0x80		/* 1=crystal clock, 0=ttl clock */
				/* receive clock source */
#define	RCDP	0x60		/* DPLL output */
#define	RCBR	0x40		/* baud rate counter */
#define	RCTC	0x20		/* external TRxC pin */
#define	RCRC	0x00		/* external RTxC pin */
				/* xmit clock source */
#define	TCDP	0x18		/* DPLL output */
#define	TCBR	0x10		/* baud rate counter */
#define	TCTC	0x08		/* external TRxC pin */
#define	TCRC	0x00		/* external RTxC pin */

#define	TOUT	0x04		/* 1=external TRxC pin is an output */
				/* TRxC output source */
#define	TRDP	0x03		/* DPLL output */
#define	TRBR	0x02		/* baud rate counter */
#define	TRTC	0x01		/* transmit clock */
#define	TRRC	0x00		/* crystal output */
/* MISC */
#define	LLOOP	0x10		/* local loopback */
#define	HDUPLEX	0x08		/* local echo */
#define	REQ	0x04		/* use DTR pin as request */
#define	PCLK	0x02		/* use PCLK input */
#define	CLKENABL	0x01	/* enable baud rate generator */
/* EXCNTRL */
#define	BRKIE	0x80		/* enable int on break */
#define	CTSIE	0x20		/* enable int on change of CTS */
#define	DCDIE	0x08		/* enable int on change of CD  */
/* read register bits */
/* RR0 */
#define	RBRK	0x80		/* break seen */
#define	CTS	0x20		/* CTS status */
#define	DCD	0x08		/* CD status */
#define	TRDY	0x04		/* xmit buffer empty */
#define	RRDY	0x01		/* rcvd char available */
/* RERROR */
#define	FERR	0x40		/* framing error */
#define	OVERR	0x20		/* rcv overrun error */
#define	PERR	0x10		/* parity error */
#define	TXDONE	0x01		/* xmit done, all chars sent */
/* VECTOR */
#define	VCHA	0x08		/* interrupt in channel A */
#define	VTYP	0x06		/* interrupt type mask */
#define	VTX	0x00		/* xmit interrupt */
#define	VEX	0x02		/* external status */
#define	VRCV	0x04		/* normal receive */
#define	VSPC	0x06		/* special receive */
/* INTR	*/
#define	RXA	0x20		/* channel A rcv interrupt */
#define	TXA	0x10		/* channel A xmit interrupt */
#define	ESA	0x08		/* channel A external status interrupt */
#define	AINTR	(RXA|TXA|ESA)
#define	RXB	0x04		/* channel B rcv interrupt */
#define	TXB	0x02		/* channel B xmit interrupt */
#define	ESB	0x01		/* channel B external status interrupt */
#define	BINTR	(RXB|TXB|ESB)