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└─⟦5a9f1bdbd⟧ Bits:30004698 RC900 Environment Rel. 2.0 (5.25 inch)
└─⟦5a9f1bdbd⟧ UNIX Filesystem
    └─⟦34bca131b⟧ »RCENV.ISC/new/usr/include/sys/bbu.h.Z« 
└─⟦de58d8f44⟧ Bits:30004699 RC900 Environment Rel. 2.0 (3.5 inch)
└─⟦de58d8f44⟧ UNIX Filesystem
    └─⟦34bca131b⟧ »RCENV.ISC/new/usr/include/sys/bbu.h.Z« 
        └─⟦this⟧ 

TextFile

#ident	"@(#)bbu.h	1.1 - 91/01/03"
/*
   87.08.14  JCO, moved to RC900
 */

/********************************************************************/
/*																	*/
/*	Definitions of ports and data for Power Fail Warning (PFW)		*/
/*																	*/
/********************************************************************/

#define SRS_PORT	0x22		/* System Register Select			*/

#define SCR_SELECT	0x04		/* SCR_PORT Select					*/
#define SCR_PORT	0x23		/* System Configuration Register	*/

#define PFWE_DATA	0x08		/* Power Fail Warning Enable		*/
#define PFW_DATA	0x02		/* Power Fail Warning				*/

#define PDR_DATA	0x26		/* Power Down Register (DATA)		*/
#define PDR_CNTRL	0x27		/* Power Down Register (CNTRL)		*/

#define PDR_PPOK	0x01		/* Primary Power OK					*/
#define PDR_PKOFF	0x02		/* PowerKey OFF						*/
#define PDR_PKULCK	0x04		/* PowerKey UnLoCKed				*/
#define PDR_TOK		0x08		/* Temperature OK					*/

#define PD_ENABLE	0x00		/* Enable Power Down Processing		*/
#define PD_PWOFF	0x01		/* Power Down (or Reset)			*/


/********************************************************************/
/*																	*/
/*	Definitions of ports and data for X-Bus READY Timeout (XBRT)	*/
/*																	*/
/********************************************************************/

#define XBRTE_DATA	0x04		/* X-Bus READY Timeout NMI Enable	*/
#define XBRT_DATA	0x01		/* X-Bus READY Timeout				*/


/********************************************************************/
/*																	*/
/*	Definitions of ports and data for Memory Parity Check (MPC)		*/
/*																	*/
/********************************************************************/

#define MPC_PORT	0x61		/* Port B register					*/

#define EMPC_DATA	0x04		/* Enable Memory Parity Check		*/
#define MPC_DATA	0x80		/* Memory Parity Check				*/

#define	PCR_PORT1	0x28		/* Parity Check Register Port1		*/ 
#define	PCR_PORT2	0x29		/* Parity Check Register Port2		*/ 

#define	PER_BANK	0x3FF		/* Parity Error Bank (64K bank)		*/


/********************************************************************/
/*																	*/
/*	Definitions of ports and data for I/O Channel Check (IOCC)		*/
/*																	*/
/********************************************************************/

#define IOCC_PORT	0x61		/* Port B register					*/

#define EIOCC_DATA	0x08		/* Enable I/O Channel Check			*/
#define IOCC_DATA	0x40		/* I/O Channel Check				*/


/********************************************************************/
/*																	*/
/*	Definitions of bbu_state and bbu_source bits					*/
/*																	*/
/********************************************************************/

#define BBU_ACTV	0x0001
#define BBU_WAIT	0x0002
#define BBU_RUN		0x0004
#define BBU_PWINT	0x0008
#define BBU_BAT		0x0010
#define BBU_IGNKEY	0x0020
#define BBU_DBG		0x0040

#define BBU_IOCTL	0x8000
#define BBU_INIT	BBU_IOCTL + 0
#define BBU_GETTM	BBU_IOCTL + 1
#define BBU_KEYOFF	BBU_IOCTL + 2
#define BBU_KEYON	BBU_IOCTL + 3
#define BBU_DEBUG	BBU_IOCTL + 4