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    Length: 3233 (0xca1)
    Types: TextFile
    Notes: UNIX file
    Names: »dma.h«

└─⟦a6ab2eb36⟧ Bits:30004042/kconfig3.imd SW95705I 386/ix Multi-user Release 1.2
└─⟦a6ab2eb36⟧ UNIX Filesystem
    └─⟦this⟧ »kc/new/usr/include/sys/dma.h« 

TextFile

/*
 * Defines for PC AT DMA controllers.
 * The PC AT has two intel 8237A-5 dma controllers with page registers
 * for each channel, allowing access to the entire 16M address space.
 */

/*
 * Copyrighted as an unpublished work.
 * (c) Copyright 1986 INTERACTIVE Systems Corporation
 * All rights reserved.
 *
 * RESTRICTED RIGHTS
 *
 * These programs are supplied under a license.  They may be used,
 * disclosed, and/or copied only as permitted under such license
 * agreement.  Any copy must contain the above copyright notice and
 * this restricted rights notice.  Use, copying, and/or disclosure
 * of the programs is strictly prohibited unless otherwise provided
 * in the license agreement.
 */

#ident "@(#)dma.h	1.2 - 86/12/16"

#define	DMACH0PG	0x87	/* port address for dma chan. 0 page reg. */
#define	DMACH1PG	0x83	/* port address for dma chan. 1 page reg. */
#define	DMACH2PG	0x81	/* port address for dma chan. 2 page reg. */
#define	DMACH3PG	0x82	/* port address for dma chan. 3 page reg. */
#define	DMACH5PG	0x8b	/* port address for dma chan. 5 page reg. */
#define	DMACH6PG	0x89	/* port address for dma chan. 6 page reg. */
#define	DMACH7PG	0x8a	/* port address for dma chan. 7 page reg. */

/*
 * I/O port addresses for controller 1 programming.
 */
#define	DMA1BCA0	0x00	/* chan. 0 base and current address */
#define	DMA1BCWC0	0x01	/* chan. 0 base and current word count */
#define	DMA1BCA1	0x02	/* chan. 1 base and current address */
#define	DMA1BCWC1	0x03	/* chan. 1 base and current word count */
#define	DMA1BCA2	0x04	/* chan. 2 base and current address */
#define	DMA1BCWC2	0x05	/* chan. 2 base and current word count */
#define	DMA1BCA3	0x06	/* chan. 3 base and current address */
#define	DMA1BCWC3	0x07	/* chan. 3 base and current word count */
#define DMA1RSWWCR	0x08	/* read status reg/write command reg */
#define	DMA1WRR		0x09	/* write request register */
#define	DMA1WSMR	0x0a	/* write single mask register bit */
#define	DMA1WMR		0x0b	/* write mode register */
#define	DMA1CBPFF	0x0c	/* clear byte pointer flip flop */
#define	DMA1RTRWMC	0x0d	/* read temp reg/write master clear */
#define	DMA1CMR		0x0e	/* clear mask register */
#define	DMA1WAMRB	0x0f	/* write all mask register bits */

/*
 * I/O port addresses for controller 2 programming.
 */
#define	DMA2BCA0	0xc0	/* chan. 0 base and current address */
#define	DMA2BCWC0	0xc2	/* chan. 0 base and current word count */
#define	DMA2BCA1	0xc4	/* chan. 1 base and current address */
#define	DMA2BCWC1	0xc6	/* chan. 1 base and current word count */
#define	DMA2BCA2	0xc8	/* chan. 2 base and current address */
#define	DMA2BCWC2	0xca	/* chan. 2 base and current word count */
#define	DMA2BCA3	0xcc	/* chan. 3 base and current address */
#define	DMA2BCWC3	0xce	/* chan. 3 base and current word count */
#define DMA2RSWWCR	0xd0	/* read status reg/write command reg */
#define	DMA2WRR		0xd2	/* write request register */
#define	DMA2WSMR	0xd4	/* write single mask register bit */
#define	DMA2WMR		0xd6	/* write mode register */
#define	DMA2CBPFF	0xd8	/* clear byte pointer flip flop */
#define	DMA2RTRWMC	0xda	/* read temp reg/write master clear */
#define	DMA2CMR		0xdc	/* clear mask register */
#define	DMA2WAMRB	0xde	/* write all mask register bits */