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/*
 * Definitions for the Adaptec AHA-1540 AT-bus Intelligent SCSI Host Adapter.
 * This file is for use with a low-end driver under the Generic Disk Driver.
 */

/*
 * Copyrighted as an unpublished work.
 * (c) Copyright 1988 INTERACTIVE Systems Corporation
 * All rights reserved.
 *
 * RESTRICTED RIGHTS
 *
 * These programs are supplied under a license.  They may be used,
 * disclosed, and/or copied only as permitted under such license
 * agreement.  Any copy must contain the above copyright notice and
 * this restricted rights notice.  Use, copying, and/or disclosure
 * of the programs is strictly prohibited unless otherwise provided
 * in the license agreement.
 */

#ident "@(#)aha1540.h	1.5 - 88/10/19"

/*
 * Adapter I/O ports.  These are offsets from dcb_ioaddr1.
 */

#define AHACTL          0       /* Host Adapter Control Port (WRITE) */
#define AHASTAT         0       /* Status Port (READ) */
#define AHADATACMD      1       /* Command (WRITE) and Data (READ/WRITE) Port */
#define AHAINTFLGS      2       /* Interrupt Flags Port (READ) */

/*
 * Bit definitions for AHACTL port:
 */

#define CTL_HRST        0x80    /* Hard Reset of Host Adapter */
#define CTL_SRST        0x40    /* Soft Reset (clears commands, no diagnostics) */
#define CTL_IRST        0x20    /* Interrupt Reset (clears AHAINTFLGS) */
#define CTL_SCRST       0x10    /* Reset SCSI Bus */

/*
 * Bit definitions for AHASTAT port:
 */

#define STAT_STST       0x80    /* Self-test in progress */
#define STAT_DIAGF      0x40    /* Internal Diagnostic Failure */
#define STAT_INIT       0x20    /* Mailbox Init required */
#define STAT_IDLE       0x10    /* Adapter is Idle */
#define STAT_CDF        0x08    /* AHADATACMD (outgoing) is full */
#define STAT_DF         0x04    /* AHADATACMD (incoming) is full */
#define STAT_INVDCMD    0x01    /* Invalid host adapter command */
#define STAT_MASK       0xfd    /* mask for valid status bits */

/*
 * Bit definitions for AHAINTFLGS port:
 */

#define INT_ANY         0x80    /* Any interrupt (set when bits 0-3 valid) */
#define INT_SCRD        0x08    /* SCSI reset detected */
#define INT_HACC        0x04    /* Host Adapter command complete */
#define INT_MBOE        0x02    /* MailBox (outgoing) Empty */
#define INT_MBIF        0x01    /* MailBox (incoming) Full */

/*
 * AHA-1540 Host Adapter Command Opcodes:
 * NOTE: for all multi-byte values sent in AHADATACMD, MSB is sent FIRST
 */

#define CMD_NOP         0x00    /* No operation, sets INT_HACC */

#define CMD_MBXINIT     0x01    /* Initialize Mailboxes */
				/* ARGS: count, 1-255 valid */
				/*       mbox addr (3 bytes) */

#define CMD_DOSCSI      0x02    /* Start SCSI (Scan outgoing mailboxes) */

#define CMD_ATBIOS      0x03    /* Start AT BIOS command */
				/* ARGS: 10 bytes, see 1540 manual, sect 6.1.3 */

#define CMD_ADINQ       0x04    /* Adapter Inquiry */
				/* RETURNS: 4 bytes of firmware info */

#define CMD_MBOE_CTL    0x05    /* Enable/Disable INT_MBOE interrupt */
				/* ARG: 0 - Disable, 1 - Enable */

#define CMD_SELTO_CTL   0x06    /* Set SCSI Selection Time Out */
				/* ARGS: 0 - TO off, 1 - TO on */
				/*       Reserved (0) */
				/*       Time-out value (in ms, 2 bytes) */

#define CMD_BONTIME     0x07    /* Set Bus-ON Time */
				/* ARG: time in microsec, 2-15 valid */

#define CMD_BOFFTIME    0x08    /* Set Bus-OFF Time */
				/* ARG: time in microsec, 0-250 valid */

#define CMD_XFERSPEED   0x09    /* Set AT bus burst rate (MB/sec) */
				/* ARG: 0 - 5MB, 1 - 6.7 MB, */
				/* 2 - 8MB, 3 - 10MB */
				/* 4 - 5.7MB (1542 ONLY!) */

#define CMD_INSTDEV     0x0a    /* Return Installed Devices */
				/* RETURNS: 8 bytes, one per target ID, starting */
				/*          with 0.  Bits set (bitpos=LUN) in */
				/*          each indicate Unit Ready */
				/* NOTE: Can only be executed ONCE after power */
				/*       up or any RESET */

#define CMD_CONFIG      0x0b    /* Return Configuration Data */
				/* RETURNS: 3 bytes, which are: */
				/*  byte 0: DMA Channel, bit encoded as */
#define CFG_DMA_CH5     0x20    /*              Channel 5 */
#define CFG_DMA_CH6     0x40    /*              Channel 6 */
#define CFG_CMD_CH7     0x80    /*              Channel 7 */
#define CFG_DMA_MASK    0xe0    /*              (mask for above) */
				/*  byte 1: Interrupt Channel, bit encoded as */
#define CFG_INT_CH9     0x01    /*              Channel 9 */
#define CFG_INT_CH10    0x02    /*              Channel 10 */
#define CFG_INT_CH11    0x04    /*              Channel 11 */
#define CFG_INT_CH12    0x08    /*              Channel 12 */
#define CFG_INT_CH14    0x20    /*              Channel 14 */
#define CFG_INT_CH15    0x40    /*              Channel 15 */
#define CFG_INT_MASK    0x6f    /*              (mask for above) */
				/*  byte 2: Host Adapter SCSI ID, in binary */
#define CFG_ID_MASK     0x03    /*              (mask for above) */

#define CMD_WTFIFO      0x1c    /* Write Adapter FIFO Buffer */
				/* ARG: addr (3 bytes) of 56 bytes to write */

#define CMD_RDFIFO      0x1d    /* Read Adapter FIFO Buffer */
				/* ARG: addr (3 bytes) of buf for 56 bytes data */

#define CMD_ECHO        0x1f    /* Echo Data */
				/* ARG: one byte of test data */
				/* RETURNS: the same byte (hopefully) */


/* Our values for Bus On/Off times so as not to cause floppy overrun */

#define BONTIME_ARG     5
#define BOFFTIME_ARG    9


/*
 * The Mail Box Structure.  NOTE: THE AHA-1540 REQUIRES ADDRESSES IN REVERSE
 *                          BYTE ORDER FROM THE 80386.  USE 'to_aha_paddr'
 *                          TO CONVERT PHYSICAL ADDRESSES TO 1540 FORM,
 *                          'from_aha_paddr' TO CONVERT BACK!
 */

#define AHA_NUM_MBOX    8       /* The number of outgoing and incoming */
				/* mailboxes (AHA_NUM_BOX of each...) */
#define AHA_RES_MBOX    2       /* The number of outgoing mailboxes to reserve */
				/* for simultaneous retry operations */
extern ushort aha_num_mbox;     /* set in space.c */
extern ushort aha_res_mbox;

struct  mbox_entry
	{
	unchar  mbx_cmdstat;            /* Command/Status byte (below) */
	unchar  mbx_ccb_addr[3];        /* AHA-1540-style CCB address */
	};

/*
 * Command codes for mbx_cmdstat:
 */

#define MBX_FREE        0       /* Available mailbox slot */

#define MBX_CMD_START   1       /* Start SCSI command described by CCB */
#define MBX_CMD_ABORT   2       /* Abort SCSI command described by CCB */

#define MBX_STAT_DONE   1       /* CCB completed without error */
#define MBX_STAT_ABORT  2       /* CCB was aborted by host */
#define MBX_STAT_CCBNF  3       /* CCB for ABORT request not found */
#define MBX_STAT_ERROR  4       /* CCB completed with error */

/*
 * The Adaptec Host Adapter Command Control Block (CCB)
 */

#define MAX_CDB_LEN     12      /* Max size of a SCSI Command Descriptor Block */
#define MAX_DMA_SEGS    16      /* Max # of Scatter/Gather DMA segments */

/* a Scatter/Gather DMA Segment Descriptor */
struct aha_dma_seg
	{
	unchar  dma_len[3];     /* segment length */
	unchar  dma_ptr[3];     /* segment address */
	};

struct aha_ccb
	{
	unchar  ccb_op;         /* CCB Operation Code */
	unchar  ccb_targ;       /* Target/LUN byte (defined below) */
	unchar  ccb_cdblen;     /* Length of SCSI Command Descriptor Block */
	unchar  ccb_reserved1;
	unchar  ccb_dlen[3];    /* Data Length (msb, mid, lsb) */
	unchar  ccb_dptr[3];    /* Data (buffer) pointer (msb, mid, lsb) */
	unchar  ccb_link[3];    /* Link Pointer (msb, mid, lsb) */
	unchar  ccb_linkid;     /* Command Link ID */
	unchar  ccb_hastat;     /* Host Adapter status */
	unchar  ccb_tarstat;    /* Target Status */
	unchar  ccb_reserved2[2];
/*
 * The following allows space for MAX_CDB_LEN bytes of SCSI CDB, followed
 * by 14 bytes of sense data acquired by the AHA-1540 in the event of an
 * error.  The beginning of the sense data will be:
 *             &aha_ccb.ccb_cdb[aha_ccb.ccb_cdblen]
 */
	unchar  ccb_cdb[MAX_CDB_LEN+14];
	struct  aha_dma_seg ccb_dma[MAX_DMA_SEGS];      /* scatter/gather segs */
	unchar  ccb_scratch[64];        /* spare buffer space, if needed */
	};

/*
 * The following structure defines the ccb_targ field.  It is not included
 * in the structure above due to 'C' alignment problems...
 * In actual practice, we use this only once, when the ccb is initialized,
 * to set tf_lun and tf_tid.  tf_in and tf_out are set by the CTD_
 * values, below.
 */

union targ_field
	{
	struct
		{
		uint    tf_lun  : 3;    /* LUN on target device */
		uint    tf_in   : 1;    /* 'incoming' xfer, length is checked */
		uint    tf_out  : 1;    /* 'outgoing' xfer, length is checked */
		uint    tf_tid  : 3;    /* Target ID */
		} tff;
	unchar  tfc;
	};

/* Direction bits for ccb_targ: */
#define CTD_MASK        0x18    /* The 2 direction bits */
#define CTD_IN          0x8     /* The tf_in bit */
#define CTD_OUT         0x10    /* The tf_out bit */


/*
 * ccb_op values:
 */
#define COP_COMMAND     0       /* Normal SCSI Command */
#define COP_SCATGATH    2       /* SCSI Command with Scatter/Gather */
#define COP_RESET       0x81    /* Bus Device Reset (Aborts all outstanding */
				/* commands against the target) */

/*
 * ccb_hastat values:
 */
#define HS_OK           0x00    /* No host adapter detected error */
#define HS_LINKOK       0x0a    /* Linked command completed OK */
#define HS_LINKOK_INT   0x0b    /* Linked command OK, interrupt generated */
#define HS_SELTO        0x11    /* Selection Time Out */
#define HS_DATARUN      0x12    /* Data over/under-run */
#define HS_BADFREE      0x13    /* Unexpected Bus Free */
#define HS_BUSPHASE     0x14    /* Target bus phase sequence failure */
#define HS_BADMBO       0x15    /* mbx_cmdstat wasn't 0 or 2 on MBO */
#define HS_BADCCB       0x16    /* ccb_op wasn't 0 or 0x81 on MBO's CCB */
#define HS_BADLINK      0x17    /* linked CCB doesn't have same status byte */

/*
 * ccb_tarstat values:
 */
#define TS_CHECK        0x02    /* Check Status (first 14 bytes of sense data */
				/* are after the CDB -- use 'Request Sense' cmd */
				/* if more is required... */
#define TS_LUNBUSY      0x08    /* Requested Target LUN is BUSY */
#define TS_RESCONF      0x18    /* Reservation Conflict (??) */


/*
 * overlay definitions for dcb_lowlev fields:
 * NOTE: these need to be coerced to/from the proper data types...
 */
#define dcb_aha_mboutp  dcb_lowlev[0]   /* pointer at outgoing mailboxes */
#define dcb_aha_mbinp   dcb_lowlev[1]   /* pointer at incoming mailboxes */
#define dcb_aha_mbocount dcb_lowlev[2]  /* number of available MBOs */
#define dcb_aha_mep     dcb_lowlev[3]   /* active mailbox entry pointer */
#define dcb_aha_ccbp    dcb_lowlev[4]   /* ccb for active mailbox */
#define dcb_aha_config  dcb_lowlev[5]   /* AHA configuration flag (below) */

/* values for dcb_aha_config */
#define AHA_CFG_64HD    1               /* this version uses 64-head BIOS */

/*
 * overlay definitions for dpb_lowlev fields:
 * NOTE: dpb_aha_ccbp needs to be coerced...
 */
#define dpb_aha_ccbp    dpb_lowlev[0]   /* pointer at adaptec CCB */
#define dpb_aha_targid  dpb_lowlev[1]   /* target ID of disk drive */
#define dpb_aha_lun     dpb_lowlev[2]   /* lun (on target) of disk drive */
#define dpb_aha_xfer    dpb_lowlev[3]   /* number of sectors transferred */


/*
 * structures to aid in the translation between native (i386) number
 * format and Adaptec/SCSI representation...
 */

struct aha_int
	{       /* a SCSI 4-byte value */
	unchar  ai_msb;
	unchar  ai_midh;
	unchar  ai_midl;
	unchar  ai_lsb;
	};

struct aha_paddr
	{       /* Adaptec Physical Address or SCSI 3-byte value */
	unchar  ap_msb;
	unchar  ap_mid;
	unchar  ap_lsb;
	};

struct native_int
	{       /* i386 4-byte value */
	unchar  ni_lsb;
	unchar  ni_midl;
	unchar  ni_midh;
	unchar  ni_msb;
	};

struct native_paddr
	{       /* i386 3-byte value */
	unchar  np_lsb;
	unchar  np_mid;
	unchar  np_msb;
	};

/*
 * function def's for space.c files
*/

extern int aha_bdinit();
extern int aha_drvinit();
extern int aha_cmd();
extern int aha_mastint();
extern struct gdev_parm_block *aha_diskint();
extern int aha_tpbdinit();
extern int aha_tpdinit();
extern struct gdev_parm_block *aha_tapeint();
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