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    Length: 3294 (0xcde)
    Types: TextFile
    Notes: @(#)cpu_board.h 13.1 (RC International) 91/02/02 */
    Names: »cpu_board.h«

└─⟦50656ff4a⟧ Bits:30010538 TX 3.1 Coldstart
    └─⟦bbf173f5c⟧ »0004« 
        └─⟦this⟧ »./usr/include/rc/cpu_board.h« 

TextFile

/*	@(#)cpu_board.h	13.1 (RC International) 91/02/02	*/

/*
 * Definitions for CPU901/CPU903, and the environment in the PU
 */

/*
 * Locations used below the exception vector (Physical addresses)
 */
#define	DBGMON_BREAK	0x78		/* Dbgmon breakpoint entry */
#define	DBGMON_CLIENT	0x7C		/* Dbgmon client entry */

/*
 * Cache configurations
 */
#define	DCACHE_SIZE	0x10000		/* Size of data cache (64 Kbytes) */
#define	ICACHE_SIZE	0x10000		/* Size of instruction cache (64 Kbytes ) */

/*
 * Definitions of address offsets in the slot specific memory space
 */
#define	SLOT_STATUS	0x0		/* Status Register */
#define	SLOT_CONTROL	0x100		/* Control register */
#define	SLOT_FIFO	0x400		/* Interrupt queue */
#define SLOT_MODULE	0x500		/* Module identification */
#define	SLOT_MESSAGE	0x700		/* Message register */

#define	SLOT_ERAM	0x00080000	/* offset of the local memory (even) */
#define	SLOT_ORAM	0x000a0000	/* offset of the local memory (odd) */
#define	SLOT_LTIMER	0x000C0104	/* Offset within the slotbase mem */
					/* of the timer reload register */
#define	SLOT_UART	0x000C0300	/* UART (write)	*/

/*
 * Definitions for the 8254 on CPU903
 * Addresses are relative to start of slot
 */
#define	SLOT_8254_0	0x000C0107	/* Register for counter 0 */
#define	SLOT_8254_1	0x000C010f	/* Register for counter 1 */
#define	SLOT_8254_2	0x000C0117	/* Register for counter 2 */
#define	SLOT_8254_CTL	0x000C011f	/* Control register */

/*
 * Definitions of private memory space for CPU901 in KSEG0 (Read-Only)
 */
#define	CPU_LRAM	0x9FC00000	/* Start of private ram */

/* Special locations in the private ram */
#define	CPU_SLOTNUM	0x9FC00010	/* Slotnumber set by SSP */
#define	CPU_CONFDATA	0x9FC00014	/* Address of confdata (set by SSP) */
#define	CPU_EXCADDR	0x9FC00018	/* Address of exception routine (read)*/
#define	CPU_CPUNO	0x9FC0001C	/* =0 for RPU, =1..3 for UPU */
#define	CPU_CPUTYPE	0x9FC00020	/* =0 for CPU901, =1 for CPU903 */
#define	CPU901_TYPE	0
#define	CPU903_TYPE	1

/*
 * Definitions of private memory space for CPU901 in KSEG1 (Read-Only)
 */
#define	CPU_FIFO	0xBFFC0006	/* Own interrupt queue */
#define	CPU_TIMER	0xBFFC0204	/* Timer counter */
#define	CPU_UART	0xBFFC0300	/* UART (read)	*/
#define CPU_CTIMERC	0xBFFC0504	/* Clear timer counter (read) */
#define	CPU_MESSAGE	0xBFFC0600	/* Message Register */
#define	CPU_CTIMER	0xBFFC0704	/* Clear timer (read) */
#define	CPU_CBUSY	0xBFFC0804	/* Clear slave busy (read) */
#define	CPU_CACCESS	0xBFFC0904	/* Clear access error (read) */
#define	CPU_CTIMER0	0xBFFC0504	/* Clear timer 0 (read) CPU903 */
#define	RPU_TIMERCOUNT	100000		/* Timer period is 10msec (clock is 100nsec) */

#define	UPU_TIMERCOUNT	166666		/* Timer period is 16.6 msec (clock is 100nsec) */

/*
 * Defines for slot specific memory
 */
#define SLOTBASE	0xff000000	/* address of slot 0 */
#define SLOTMASK	0x00f00000	/* mask for slotnumber */
#define SLOTINC		0x00100000	/* # bytes in each slot */
#define SLOTSHIFT	20		/* LOG2(SLOTINC) */

#ifdef UPU

#ifdef LANGUAGE_C
extern u_int   *rpu_slot_base;
extern u_int   *upu_slot_base;
#else
IMPORT(rpu_slot_base,4)
IMPORT(upu_slot_base,4)
#endif

#define RPU_FIFO     (rpu_slot_base[SLOT_FIFO/4])
#define UPU_LTIMER   (upu_slot_base[SLOT_LTIMER/4])
#define	UPU_UART     (upu_slot_base[SLOT_UART/4])


#endif