OctetView
0x00000…00100 (0, 0, 0) Sector 01374130313337 ┆ 7A0137A ┆
0x00100…00200 (0, 0, 1) Sector 00000000000000 ┆ ┆
0x00200…00300 (0, 0, 2) Sector ff00feffffc0ff ┆ ~ @ p ~ ┆
0x00300…00306 (0, 0, 3) WangDocument {d00=0x17, d01=0x08, d02=0x41, ptr=(70,0, 0), d05=0x00}
0x00306…0030c WangDocument {d00=0x17, d01=0x67, d02=0x41, ptr=(69,0, 8), d05=0x00}
0x0030c…00312 WangDocument {d00=0x18, d01=0x00, d02=0x41, ptr=(22,0, 8), d05=0x00}
0x00312…00318 WangDocument {d00=0x18, d01=0x01, d02=0x41, ptr=(69,0, 0), d05=0x00}
0x00318…0031e WangDocument {d00=0x18, d01=0x17, d02=0x41, ptr=(70,0, 8), d05=0x00}
0x0031e…00324 WangDocument {d00=0x18, d01=0x18, d02=0x41, ptr=(68,0, 0), d05=0x00}
0x00324…00340 18 89 41 45 08 48 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ AE H ┆
0x00340…00360 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
[…0x4…]
0x003e0…00400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 24 ┆ $┆
0x00400…00500 (0, 0, 4) Sector 00000000000000 ┆ ┆
0x00500…00600 (0, 0, 5) Sector 86312020202020 ┆ 1 B 4 7 Q? > 7 | Z d N ~< v <+&4'>( 1c5 & & ┆
0x00600…00700 (0, 0, 6) Sector 421c402600415b ┆B @& A[' % X% %1 PO P ; A : C g x g V WD O 7 :D( D+B | 1708A g H < {C < { ; 1 C 0w Ng b bD K : 9 8,B t xY bH yx D+ 4 7 8 5Z(Z) ┆
0x00700…00800 (0, 0, 7) Sector 00000000000000 ┆ ┆
[…0x8…]
0x01000…01100 (1, 0, 0) WangDocumentBody
[…0x6…]
0x01700…01800 (1, 0, 7) Sector 00000000000000 ┆ ┆
0x01800…01900 (1, 0, 8) WangDocumentBody
[…0x11…]
0x02a00…02b00 (2, 0, 10) Sector 0000e100180041 ┆ a Aty profile. This profile determines the allowed functions and the highest permissible classification level to be accessed. The system will always check against these profiles before any exchange of data are performed. se of recovery and is only of ┆
0x02b00…02c00 (2, 0, 11) Sector 020cff00181741 ┆ A 1 8. OPTIONS 8.1 TEMPEST CLEARED VDU In order to cater to the demand that some of the operator workstations of the MPF will be placed in a non EMI shielded room, CHRISTIAN ROVSI┆
0x02c00…02d00 (2, 0, 12) Sector 020dff00181741 ┆ ANG A/S hereby present a quote for a tempest cleared VDU. The VDU proposed for this use is the DELTA DATA 7260 TC which is tempest cleared according to the NATO COMSEC requirement. For a description of the VDU, see section 4.3.5.1. This DELTA DA┆
0x02d00…02e00 (2, 0, 13) Sector 020eff00181741 ┆ ATA VDU is the same VDU as proposed for the MCSF workstation. For secure wiring between the MPF equipment and the tempest VDU an optical link is proposed. The secure terminal configuration with a tempest cleared VDU, opto transceivers and optical┆
0x02e00…02f00 (2, 0, 14) Sector 020f4100181741 ┆ A A fiber has been developed for use in the CAMPS project. &! w"2< hMI sM & E 0= u M% :^=~ Bl1{M40sI:^=~ J 1!"<6;!#<6 !&<6 ! "$<! <6 {M;(s! 9"c=! "(= Z=q#p!"<6 !&<6 ! "$<!#<6 ! <6 {M)(sC I! <6 ! "(= <q#p!"<6 !#<6 ! "$<!&<6$`i6 {M)(sM &M7 ┆
0x02f00…03000 (2, 0, 15) Sector 00004a00181741 ┆ J A 1 "(=~~ BW2I! <6 M /M?.I*:="8=IM2&MP'Mc2! m"2< [MI !?=6 : #wI>K!8=>R 2!8=6 #4 E*8=k L<M% :8=F 28=I!#<:"<>R<2> I E*#<& "< DM L<M% :#<F 2#<> I:g= Ro2M/2 Rl2> IC13!?=4~~ B|2> I:A=!┆
0x03000…03100 (3, 0, 0) WangDocumentBody
[…0xf…]
0x04000…04100 (4, 0, 0) Sector 0401ff00170841 ┆ Aguration Management. 3.5 AVAILABILITY Availability is treated in the Technical Proposal, section on Availability. 3.6 TESTING AND ACCEPTANCE Following system integration and unit testing of each software module, a Factory Qualification Tes┆
0x04100…04200 (4, 0, 1) Sector 04029f00170841 ┆ At (FQT) is performed. Thereafter, each MPF system will be subjected to a Factory Post Production Test (FPPT) before shipment to site for installation. - Site 301 A more detailed description of the documentation is contained in the techn┆
0x04200…04300 (4, 0, 2) Sector 0403ff00170841 ┆ A 1 At the site, system integration is carried out, and a Preliminary Site Acceptance Test (PSAT) is performed. Following this, a Sub-Net-Test (SNT) - Category iii verifies that the M┆
0x04300…04400 (4, 0, 3) Sector 0404ff00170841 ┆ APF interfaces properly to the TARE Communication Processor Sub-System and to the Telegraph Message Sub-System. Additionally, at the second site, a SNT - category iv verifies that the two MPF's communicate properly with each other, both already havi┆
0x04400…04500 (4, 0, 4) Sector 0405ff00170841 ┆ Ang been tested to SNT iii. Finally, an Official System Acceptance Tesat (OSAT) is performed, and succesful completion of the OSAT constitutes final acceptance of the MPF by NODECA. The following is a list of formal tests: FQT Pre-Test in Copen┆
0x04500…04600 (4, 0, 5) Sector 0406c700170841 ┆ G Ahagen FQT and FPPT in Copenhagen for site 101 equipment PSAT site 101 SNT (iii) site 101 FPPT in Copenhagen for site 301 equipment PSAT 301 SNT (iii) site 301 SNT (iv) OSAT nfiguration identification o Configuration Control o S┆
0x04600…04700 (4, 0, 6) Sector 00006100170841 ┆ a A 1 3.7 TECHNICAL TRANSFER r evaluation & qualification, and performs a support function for receiving inspection and purchasing. 2. Reliability This is a supervision function av┆
0x04700…04800 (4, 0, 7) Sector 00000000000000 ┆ ┆
0x04800…04900 (4, 0, 8) WangDocumentBody
[…0x3…]
0x04c00…04d00 (4, 0, 12) Sector 040dff00170841 ┆ A 1 The Configuration Status Accounting function records and maintains the informaton and documentation required by configuration control management. It includes listings of approved e┆
0x04d00…04e00 (4, 0, 13) Sector 040eff00170841 ┆ Angineering documentation, status reports of proposed changes, and implementation status of approved changes. The Physical Configuration Audit (PCA) is the formal examination of the as-built version of a configuration item against its technical doc┆
0x04e00…04f00 (4, 0, 14) Sector 040fff00170841 ┆ Aumentation in order to establish the Configuration Item's product baseline. The Functional Configuration Audit (FCA) is the verification of the completion, or extent of completon, of all tests required by development specifications. The Configurat┆
0x04f00…05000 (4, 0, 15) Sector 0400ff00170841 ┆ Aion Management function gets involved in updating of the PIP and other plans of the project by the fact that DATA MANAGEMENT is handled by configuration control. The changes are normally initiated through the project office but controlled by Confi┆
0x05000…05100 (5, 0, 0) WangDocumentBody
[…0x117…]
0x16800…16900 (22, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(22,0, 9), len=0xff, h3=41180041}, f00=»1800A «, f01=»Crossfox Tilbud «, f02=»kk «, f03=»ALF «, f04=»Indfletning af Tilb «, f05=04-03-82 17:05, f06=» «, f07=»02 «, f08=» 111 «, f09=05-05-82 10:33, f10=» «, f11=»03 «, f12=» 15 «, f13=06-05-82 08:33, f14=10-05-82 13:24, f15=»0137A «, f16=» 14 «, f17=» «, f18=»48 «, f19=» 268 «, f20=» 828 «, f21=» «, f22=» «, f99=200003000110066610110180aaca15050000000000000137035200df}
0x16900…16a00 (22, 0, 9) WangDocumentBody
[…0xd…]
0x17700…17800 (23, 0, 7) Sector 1608ff00180041 ┆ An of the CROSSFOX Broadcast will be implemented in the MPF in accordance with the relevant paragraphs in ACP127 Supplement 1 as listed in the IFB. Below, these operational procedures will briefly be described. For detailed information please refer┆
0x17800…17900 (23, 0, 8) WangDocumentBody
[…0x28…]
0x1a100…1a200 (26, 0, 1) Sector 00008200180141 ┆ Ad security requirements will have to be made and demonstrated by the contractor before the final acceptance of the software.ns of the Failure Reporting System. tured by Christian Rovsing A/S are subject to the provisions of the company's Quality ┆
[…0x1…]
0x1a300…1a400 (26, 0, 3) Sector 00008300180141 ┆ Ad security requirements shall have to be made and demonstrated by the contractor before the final acceptance of the software.em. ed for subassemblies of low complexity as well as analog ones. 2) "In-circuit Tester", ZEHNTEL Troubleshooter 800. ┆
0x1a400…1a500 (26, 0, 4) Sector 1a05ff00180141 ┆ Aystem test into two subtests. The first subtest will consist of a complete functional test. Test procedures will be specified by the contractor and shall be agreed by the purchaser. Initially all functions shall be exercised one by one, subseque┆
0x1a500…1a600 (26, 0, 5) Sector 1a06e600180141 ┆ f Ant Zunctional testing shall be performed by execution of functions in parallel. Any deviation from the specified functional requirements shall be corrected and all functions affected by the corrections shall be retested. bility Verification The┆
0x1a600…1a700 (26, 0, 6) Sector 1a07ff00180141 ┆ A 1 After completion of the functional subtest the final operational subtest can be initiated. The test scenarios and procedures for the operational test shall be prepared by the purc┆
0x1a700…1a800 (26, 0, 7) Sector 1908ff00180141 ┆ Ahaser together with the contractor. The operational test shall be successfully performed by exercising the complete CROSS FOX network over 3 periods each lasting at least 10 days. Any software modifications required to comply with operational an┆
0x1a800…1a900 (26, 0, 8) WangDocumentBody
[…0x297…]
0x44000…44100 (68, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(68,0, 1), len=0xff, h3=41181841}, f00=»1818A «, f01=»Crossfox tilbud «, f02=»kk «, f03=»alf «, f04=»fletning «, f05=05-03-81 11:07, f06=» «, f07=»09 «, f08=» 355 «, f09=06-05-82 16:34, f10=» «, f11=»03 «, f12=» 23 «, f13=06-05-82 16:38, f14=10-05-82 13:25, f15=»0137A «, f16=»104 «, f17=» 4 «, f18=»21 «, f19=» 1432 «, f20=» 6665 «, f21=» «, f22=» «, f99=503020000110066610110280aaca1505000000000000003703cf01df}
0x44100…44200 (68, 0, 1) WangDocumentBody
[…0xe…]
0x45000…45100 (69, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(69,0, 1), len=0xff, h3=41180141}, f00=»1801A «, f01=»Crossfox tilbud «, f02=»kk «, f03=»ALF «, f04=»Indfletning Tilbud «, f05=04-03-82 17:20, f06=» «, f07=»02 «, f08=» 122 «, f09=06-05-82 14:25, f10=» «, f11=»00 «, f12=» 2 «, f13=06-05-82 14:28, f14=10-05-82 13:25, f15=»0137A «, f16=» 53 «, f17=» 3 «, f18=»34 «, f19=» 692 «, f20=» 4876 «, f21=» «, f22=» «, f99=023070000110066610110280aaca1505000000000000013703e100df}
0x45100…45200 (69, 0, 1) WangDocumentBody
[…0x6…]
0x45800…45900 (69, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(69,0, 9), len=0xff, h3=41176741}, f00=»1767A «, f01=»Crosfox Tilbud «, f02=»ktd «, f03=»OE «, f04=»table 6.7-A1 to A9 «, f05=01-03-82 08:21, f06=» «, f07=»21 «, f08=» 396 «, f09=21-04-82 10:58, f10=» «, f11=»00 «, f12=» 9 «, f13=22-03-82 13:47, f14=26-04-82 13:47, f15=»0137A «, f16=» 57 «, f17=» «, f18=»49 «, f19=» 48 «, f20=» 2162 «, f21=» «, f22=» «, f99=020010000110066610110180aaca15050000000000000037034700df}
0x45900…45a00 (69, 0, 9) WangDocumentBody
[…0x6…]
0x46000…46100 (70, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(70,0, 1), len=0xff, h3=41170841}, f00=»1708A «, f01=»CROSSFOX «, f02=»kk «, f03=»ALF «, f04=»Contractual Part «, f05=18-02-82 08:49, f06=» 5 «, f07=»08 «, f08=» 16753 «, f09=24-02-83 18:48, f10=» «, f11=»00 «, f12=» 4 «, f13=24-02-83 18:48, f14=24-02-83 19:01, f15=»0137A «, f16=» 66 «, f17=» 7 «, f18=»52 «, f19=» 736 «, f20=» 23733 «, f21=» «, f22=» «, f99=100093300910062710110490aaca1505000000000000013703f400df}
0x46100…46200 (70, 0, 1) WangDocumentBody
[…0x6…]
0x46800…46900 (70, 0, 8) WangDocumentHead {hdr=WangSectHead {next=(70,0, 9), len=0xff, h3=41181741}, f00=»1817A «, f01=»Crossfox «, f02=»kk «, f03=»ALF «, f04=»Fletning «, f05=05-03-81 10:12, f06=» «, f07=»02 «, f08=» 165 «, f09=05-05-82 11:05, f10=» «, f11=»03 «, f12=» 12 «, f13=29-04-82 12:44, f14=10-05-82 13:25, f15=»0137A «, f16=» 2 «, f17=» «, f18=»32 «, f19=» 16 «, f20=» 481 «, f21=» «, f22=» «, f99=103095000110066610110180aaca15050000000000000037030800df}
0x46900…46a00 (70, 0, 9) WangDocumentBody
[…0x6…]
0x47000…47100 (71, 0, 0) Sector 4701ff00181841 ┆G Ad. A peripheral processor can only access its own compartment, and not that of another peripheral processor or parts of main memory allocated for general processing. The combination of a peripheral processor and compartmentalized memory is defined┆
0x47100…47200 (71, 0, 1) Sector 4702ff00181841 ┆G A as a peripheral module. This design ensures integrity and security of Input/Output and provides each peripheral module with its own path to mainmemory, thus removing restrictions and avoiding speed degradation commonly associately with multiplexed┆
0x47200…47300 (71, 0, 2) Sector 47031f00181841 ┆G A I/O access to memory. essentially consists of fast transfer buses joined to each other by adapters which allow units on one bus to access those on another. Dualization at the internal level and multiple redundancy at the system level provide a ┆
0x47300…47400 (71, 0, 3) Sector 4704ff00181841 ┆G A 1 4.3.4 Watchdog Processor System The Watchdog Processor System is a Maintenance and Configuration Processor (MCP). It is based on a standard programmable Line Termination Unit (L┆
0x47400…47500 (71, 0, 4) Sector 4705ff00181841 ┆G ATU) which has been programmed to monitor and control the overall operation of the CR80 computer system. The MCP is interfaced to both PUs and CUs and is also interfaced to the Watchdog Panel, which is used to choose the different modes of Watchdog┆
0x47500…47600 (71, 0, 5) Sector 4706ff00181841 ┆G A operation. During normal opration the watchdog will continuously monitor the well-functioning of all modules in the PUs and CUs. In the event that a failure occurs, the watchdog will initiate switchover procedures and recovery procedures if appr┆
0x47600…47700 (71, 0, 6) Sector 4707ff00181841 ┆G Aopriate. The watchdog by itself is not dualized. Hence any failure in the Watchdog will require manual operation. The watchdog can be set in a manual mode to allow this. System controller facilities are provided by a VDU, a printer and floppy d┆
0x47700…47800 (71, 0, 7) Sector 4608ff00181841 ┆F Aisc attached to the Watchdog. The system operator can use this equipment for system control. 4.3.5 Peripherals The different peripherals used in the MPF configuration are described in the following sub-sections. 4.3.5.1 Visual Display Unit┆
0x47800…47900 (71, 0, 8) Sector 4709ff00181841 ┆G Aadapters. The software which controls the disk operation will ensure that the contents of the two disks are identical, i.e. the disks are mirrored. In the event that one disk fails, the other disk will continue operation while the faulty disk is b┆
0x47900…47a00 (71, 0, 9) Sector 470aff00181841 ┆G Aeing repaired. After restoration of the erroneous disk, software can copy all the contents of the correct disk to the newly installed (repaired) disk. This can be done during normal operation. The offline disk and the floppy disks are not dualize┆
0x47a00…47b00 (71, 0, 10) Sector 470bff00181841 ┆G Ad. 4.3.3 CR80 Processor System As has been seen previously, a CR80 Processor System is implemented in 2 types of crates (card cages), the Processor Unit (PU) containing all address sourcing devices (CPU's and DMA's) and the memory. The second┆
0x47b00…47c00 (71, 0, 11) Sector 470c0800181841 ┆G A and all components are listed in fig. 4.3.1-2. More details are found in the datasheets in fig. 4.3.1-3. processor system with up to 5 CPU's and 16 megawords of memory with an operating range of 0.6 to 2.0 million instructions/second and a Data C┆
0x47c00…47d00 (71, 0, 12) Sector 470dff00181841 ┆G A 1 type of crate is the channel Unit which can contain additional memory if required. The Channel Units (CU), furthermore, contain all peripheral processors interfacing peripherals (┆
0x47d00…47e00 (71, 0, 13) Sector 470eff00181841 ┆G Ae.g. disc, tape, terminals, communication lines etc.). All modules in each type of crate are attached to buses to allow communication between all modules. The P-bus in the PU is reserved for used by the Central Processing Units (CPU's), while the┆
0x47e00…47f00 (71, 0, 14) Sector 470fff00181841 ┆G A C-bus, which is also located in the PU crate, is utilized by Direct Memory Access (DMA) devices, e.g. the MAP module. In the Channel Unit (CU), peripherals (disc, terminals, communication lines etc.) are attached by peripheral processors that per┆
0x47f00…48000 (71, 0, 15) Sector 4700ff00181841 ┆G Aform distributedly I/O processing associated with the specific types of attached devices and communicate directly data and status/control messages to the main memory. The parts of main memory accessible by peripheral processors is compartmentalize┆
0x48000…48100 (72, 0, 0) Sector 4801ff00181841 ┆H ACR8087M/010 SFA 22 11 CR8066M/010AB LTU 23 11 CR8082M/010 LIA-N 24 1 CR890/104 WATCHDOG 25 1 DELTA DATA 7260TC TEMPEST VDU 26 1 TRACOR 8000 TEMPEST PRINTER 27 5 DELTA DATA 7301 VDU 28 3 CR8330/200 PRINTER 29 1 CR8300/080 80MB SMD DISC DRIVE ┆
0x48100…48200 (72, 0, 1) Sector 4802ff00181841 ┆H A 30 2 CR8300/150 150 MB SMD DISC DRIVE 31 2 CR8300/001 ACUSTIC CABINET 32 1 CR8319/80 80 MB DISC PACK 33 2 CR8319/150 150 MB DISC PACK 34 3 sets CABLES FOR DISC 35 1 CR8308/232 DUAL FLOPPY DISC 36 1 CR1081S/020 S-CRATE 37 3 CR81053/010 S-FAN┆
0x48200…48300 (72, 0, 2) Sector 48030700181841 ┆H A odularity. The hardware essentially consists of fast transfer buses joined to each other by adapters which allow units on one bus to access those on another. Dualization at the internal level and multiple redundancy at the system level provide a ┆
0x48300…48400 (72, 0, 3) Sector 4804f200181841 ┆H r A 1 38 1 CR8022S/000 S-POWER SUPPLY 39 2 OPTO MULTIPLEXOR 40 3 CR1086S/000 BACK PANEL ADAPTOR 41 1 CHANNEL L/L ADAPTOR 42 4 CR2560/008 MCU's BOX Fig. 4.3.1-2 real-time and┆
0x48400…48500 (72, 0, 4) Sector 4805ff00181841 ┆H A 1 4.3.2 Dualization Concept Two identical Processor Units are part of the hardware configuration. One is the active PU, while the other is the standby, ready to take over from th┆
0x48500…48600 (72, 0, 5) Sector 4806ff00181841 ┆H Ae the active. Each Processor Unit is equipped with Power Supply, 2 CPUs with CACHE memory, 3 128 kW memory board, and a MAP module. The MAP module performs address translation between the logical addresses used by the CPUs and the physical addres┆
0x48600…48700 (72, 0, 6) Sector 4807ff00181841 ┆H Ases in the memory boards. The MAP module is connected to the MIA module, i.e. the memory interface adapter which connects a Processor Unit with Channel Units. The dualization principle in the Channels Units is different from the principle applied┆
0x48700…48800 (72, 0, 7) Sector 4708ff00181841 ┆G A in the Processor Units as each CU is dualized within itself. All modules in a CU are attached to both of the two buses, which are powered from separate power suppliers. The two 150 MB disk drives are attached to two separate disk controllers and ┆
0x48800…48900 (72, 0, 8) Sector 4809ff00181841 ┆H A 1 4.3.1 Hardware Configuration The MPF system will be based on the CR80 FATOM series, more specifically the CR860/002 configuration. This computer configuration is a fault toleran┆
0x48900…48a00 (72, 0, 9) Sector 480aff00181841 ┆H At, virtual memory computer constituted of 2 racks, each containing a dual bused Processor Unit crate and a dual bused Channel Unit Crate. The CR860/002 computer is a standard computer manufactured and tested according to standard procedures set up┆
0x48a00…48b00 (72, 0, 10) Sector 480bff00181841 ┆H A by our Production Division. Further details can be found in the CR80 Handbook. The custom-tailored MPF system will be established from the CR860/002 by adding an extra rack for adaptors and disc. The MPF configuration is depicted in fig. 4.3.1-┆
0x48b00…48c00 (72, 0, 11) Sector 480c7200181841 ┆H r A1 and all components are listed in fig. 4.3.1-2. More details are found in the datasheets in fig. 4.3.1-3. processor system with up to 5 CPU's and 16 megawords of memory with an operating range of 0.6 to 2.0 million instructions/second and a Data C┆
0x48c00…48d00 (72, 0, 12) Sector 480d7b00181841 ┆H { A 1 Fig. 4.3.1-1 odules - CR80 FATOM, a fault-tolerant system including as many as 16 multiprocessors interconnected through a 512 megabit transpor┆
0x48d00…48e00 (72, 0, 13) Sector 480eff00181841 ┆H A 1 Item Number Description 1 3 CR8101-/036/00 Rack 2 2 CR8125M/225PC/00 PU-CRATE 3 2 CR8125M/425AB/00 CU-CRATE 4 4 CR8105M/020-/00 FAN UNIT 5 3 CR8106-/220-/00 MAINS FILTER ┆
0x48e00…48f00 (72, 0, 14) Sector 480fff00181841 ┆H A 6 8 CR8050M/010-/00 POWER SUPPLY 7 3 CR8107-/010-/00 POWER DIST.PANEL 8 2 CR8020M/000PC/00 MAP 9 2 CR8071M/010-/00 MIA 10 4 CR8030M/040PC/00 CPU CACHE 11 6 CR8016M/128PC/00 RAM 128K 12 2 CR8081M/010A-/00 CIA-A 13 2 CR8081M/010-B/00 CIA-B 14┆
0x48f00…49000 (72, 0, 15) Sector 4800ff00181841 ┆H A 2 CR8211M/738-/00 DATA CHANNEL TERM. 15 4 CR8211M/015-/00 CABLE DATA CHANNEL 16 20 CR8201M/015-/00 CABLE RACK POWER 17 12 CR8055M/020-/00 MBT 18 3 CR8044M/040AB DISC CONTROLLER 19 3 CR8084M/010 DCA 20 1 CR8047M/040AB FLOPPY DISC CONTR. 21 1 ┆
0x49000…49100 (73, 0, 0) Sector 4901ff00181841 ┆I A 1 - a 80:1 range in processing power, utilizing one CPU or up to 16 interconnected multiprocessors with a maximum of 5 CPU's each. - a 400:1 range in connectivity, through Peripher┆
0x49100…49200 (73, 0, 1) Sector 4902ff00181841 ┆I Aal controllers accommodating a variety of terminations with as many as 960 peripherals or up to 4096 communication lines. Flexible variation in the size and structure of the CR80 systems is permitted by the unusual degree of hardware and software ┆
0x49200…49300 (73, 0, 2) Sector 4903ff00181841 ┆I Amodularity. The hardware essentially consists of fast transfer buses joined to each other by adapters which allow units on one bus to access those on another. Dualization at the internal level and multiple redundancy at the system level provide a ┆
0x49300…49400 (73, 0, 3) Sector 4904ff00181841 ┆I ACR80 hardware architecture which is fully exploited by the DAMOS software operating system and programs to provide survival after operational failure of individual components. Reliability, which is increasingly becoming of concern in real-time and┆
0x49400…49500 (73, 0, 4) Sector 4905ff00181841 ┆I A distributed network applications, is achieved in the CR80 computer systems by applying unique architectural concepts. The CR80 hardware/software architecture treats all multiprocessors as equal elements, none absolutely dedicated to a specific rol┆
0x49500…49600 (73, 0, 5) Sector 4906ff00181841 ┆I Ae. Fault tolerance and backup are achieved through an n+1 redundance scheme without preassignment of system functions to specific processors. This is in marked contrast to the more common, rigid dualized configurations often encountered in dedic┆
0x49600…49700 (73, 0, 6) Sector 4907ff00181841 ┆I Aated applications with on-line master/slave arrangements or with off-line back and switchover facilities. The many functional and operational features inherent in the CR80 computer system configurations go beyond, therefore, mere physical size var┆
0x49700…49800 (73, 0, 7) Sector 48082800181841 ┆H ( Aiations and expansion options. challenge the power of large mainframes, but with far superior operational characteristics and hitherto unrealizable advantages. The CR80 building block modules allow a system configuration flexibility previously ┆
0x49800…49900 (73, 0, 8) Sector 4909ff00181841 ┆I Aunachievable; this has led to the definition of the CR80 Computer Family. System boundaries are arbitrary and somewhat hard to define since they are actually non-existent. The CR80 product line, as such, probably offers the most versatile compute┆
0x49900…49a00 (73, 0, 9) Sector 490ace00181841 ┆I N Ar configurations in the industry. Nevertheless, for purposes of categorization the CR80 systems are based on 4 standard computer modules, the unmapped MINI and TWIN and the Mapped MAXIM and FATOM:. AH1 R^4 ]M, C 4:>=2A=Ms!:g=~ Jr4Mj2:g=~ B}4C75! ┆
0x49a00…49b00 (73, 0, 10) Sector 490bff00181841 ┆I A 1 - CR80 MINI, a multiprocessor system with up to 4 CPU's and 256 K words of memory with an operating range of 0.6 to 1.3 million instructions/second - CR80 TWIN, a fully dualized ┆
0x49b00…49c00 (73, 0, 11) Sector 490cff00181841 ┆I Aversion of the MINI with twin multiprocessors and a dual bused peripheral subsystem. - CR80 MAXIM, a multiprocessor system with up to 5 CPU's and 16 megawords of memory with an operating range of 0.6 to 2.0 million instructions/second and a Data C┆
0x49c00…49d00 (73, 0, 12) Sector 490dff00181841 ┆I Ahannel with a megabyte/second, transfer rate interfacing up to 15 channel units for control of up to 960 peripheral modules - CR80 FATOM, a fault-tolerant system including as many as 16 multiprocessors interconnected through a 512 megabit transpor┆
0x49d00…49e00 (73, 0, 13) Sector 490eff00181841 ┆I At; and multiprocessor has the same capacity message as a CR80 MAXIM with 256 megawords of memory and an operating range up to 30 million instructions/second Unmapped systems are supported by the AMOS software operating system and mapped `systems ┆
0x49e00…49f00 (73, 0, 14) Sector 490fff00181841 ┆I Aare supported by the DAMOS software operating system. These standard configurations encompass a broad range of physical characteristics to meet the requirements of the smaller stand-alone user and those of the largest multi-installation network ap┆
0x49f00…4a000 (73, 0, 15) Sector 4900c700181841 ┆I G Aplications. The four models offer: - a 50:1 range in instruction execution rate, varying from 0.6 mips to 30 mips. - a 1000:1 range in memory capacity, from 512 K bytes to 512 megabytes. ┆
0x4a000…4a100 (74, 0, 0) WangDocumentHead {hdr=WangSectHead {next=(74,0, 1), len=0xff, h3=41181841}, f00=»1818A «, f01=»Crossfox tilbud «, f02=»kk «, f03=»alf «, f04=»fletning «, f05=05-03-81 11:07, f06=» «, f07=»09 «, f08=» 355 «, f09=05-03-81 12:41, f10=» «, f11=» «, f12=» «, f13=05-03-81 11:17, f14=11-03-82 10:14, f15=»0137A «, f16=»110 «, f17=» «, f18=»09 «, f19=»02256 «, f20=» 355 «, f21=» «, f22=») «, f99=020010000110066610110480aaca1505000000000000003703d801df}
0x4a100…4a200 (74, 0, 1) Sector 4a026e00181841 ┆J n A J J I I H H H H H G G F F F E E E D D D D D D C C C C B B B A A A A A A @ @ @ @ ? ? ? ? > > > = = = = < < < < ; ; : : : : : 9 9 9 8 8 8 8 7 7 7 7 6 6 6 5 5 5 5 5 4 4 4 3 3 3 3 2 2 1 1 0 0 0 0 0 0 / / / / / . . . . - - - - ┆
0x4a200…4a300 (74, 0, 2) Sector 4a03aa00181841 ┆J * A 1 VOLUME IV 1982-03-05 TECHNICAL PROPOSAL 2&*/=MM, > I!e=6 !Z="(=e*$<kas#r 9x2"<! <6 M8)I:^=~ B#.!#<6 ! <6 M&&:!<~ J#.:!<2.=M2┆
0x4a300…4a400 (74, 0, 3) Sector 4a04ff00181841 ┆J A 1 4.3 MPF HARDWARE SPECIFICATION The MPF hardware will be based on the CR80 familily of computers. Several years of rapid computer technology evolution have led to the developmen┆
0x4a400…4a500 (74, 0, 4) Sector 4a05ff00181841 ┆J At of the CR80 computer product line at Christian Rovsing A/S. The computer family is a collection of units architecturally structured in an innovative way into powerful multiprocessor systems. Through a high degree of parallelism and redundancy, t┆
0x4a500…4a600 (74, 0, 5) Sector 4a06ff00181841 ┆J Ahe configurations introduced herein offer nearly unlimited operating power and outstanding system reliability. From the outset, system architects at Christian Rovsing recognized that micro -electronics was the driving force behind modern computer ┆
0x4a600…4a700 (74, 0, 6) Sector 4a07ff00181841 ┆J Atechnology. The CR80 product line is based on the functional modularity made feasible by low-cost LSI with advanced distributed architecture and multiprocessing concepts. Though they appear to be minicomputers, the CR80 systems in the larger confi┆
0x4a700…4a800 (74, 0, 7) Sector 4908ff00181841 ┆I Agurations are competitive with and challenge the power of large mainframes, but with far superior operational characteristics and hitherto unrealizable advantages. The CR80 building block modules allow a system configuration flexibility previously ┆
0x4a800…4a900 (74, 0, 8) Sector 00000000000000 ┆ ┆
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