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Length: 11264 (0x2c00)
Types: Ada Source
Notes: 03_class, FILE, R1k_Segment, e3_tag, package body Port_Serie, seg_05a049
└─⟦8527c1e9b⟧ Bits:30000544 8mm tape, Rational 1000, Arrival backup of disks in PAM's R1000
└─ ⟦cfc2e13cd⟧ »Space Info Vol 2«
└─⟦this⟧
with File_Attente;
with Simple_Io;
package body Port_Serie is
procedure Initialiser (N_Port : General_Defs.Port;
Vitesse : General_Defs.Baud_Rate;
Parite : General_Defs.Parite;
Nb_Bit : General_Defs.Nbre_Bits_Par_Caractere;
Nb_Bit_Stop : General_Defs.Stop_Bits) is
begin
Serie.Pos_Vitesse (Port_Serie => N_Port, Vitesse => Vitesse);
Serie.Pos_Parite (Port_Serie => N_Port, Val_Parite => Parite);
Serie.Pos_Stop_Bits (Port_Serie => N_Port,
Val_Stop_Bits => Nb_Bit_Stop);
Serie.Pos_Nbre_Bits_Caractere (Port_Serie => N_Port,
Val_Nbre_Bits_Par_Caractere => Nb_Bit);
end Initialiser;
procedure Emission_Reception (Config : Sorte_E_R) is
begin
case Config is
when Ea =>
Serie.Emission_Reception
(Port_Serie => General_Defs.Port_A, Mode => Serie.E_R);
Serie.Emission_Reception
(Port_Serie => General_Defs.Port_B, Mode => Serie.R);
when Eb =>
Serie.Emission_Reception
(Port_Serie => General_Defs.Port_A, Mode => Serie.R);
Serie.Emission_Reception
(Port_Serie => General_Defs.Port_B, Mode => Serie.E_R);
when R_Seule =>
Serie.Emission_Reception
(Port_Serie => General_Defs.Port_A, Mode => Serie.R);
Serie.Emission_Reception
(Port_Serie => General_Defs.Port_B, Mode => Serie.R);
when Rien =>
Serie.Emission_Reception
(Port_Serie => General_Defs.Port_A, Mode => Serie.Aucun);
Serie.Emission_Reception
(Port_Serie => General_Defs.Port_B, Mode => Serie.Aucun);
end case;
end Emission_Reception;
procedure Validation_It (Sorte : Sorte_It) is
begin
case Sorte is
when R_Ab =>
Serie.Pos_Interruption (Mode => Serie.R);
when Ea_R =>
Serie.Pos_Interruption (Mode => Serie.Ea_R);
when Eb_R =>
Serie.Pos_Interruption (Mode => Serie.Eb_R);
when Pas_It =>
Serie.Pos_Interruption (Mode => Serie.Aucun);
end case;
end Validation_It;
procedure Envoi_Donnee_Par_It (Type_Port : General_Defs.Port) is
begin
case Type_Port is
when General_Defs.Port_A =>
Emission_Reception (Ea);
Serie.Pos_Interruption (Serie.Ea_R);
when General_Defs.Port_B =>
Emission_Reception (Eb);
Serie.Pos_Interruption (Serie.Eb_R);
end case;
end Envoi_Donnee_Par_It;
task body Transmettre is
Car : General_Defs.Byte;
Sorte_It : Serie.Evenement_Interruption;
package Buffer_Reception is
new File_Attente (Element => General_Defs.Byte,
Longueur_Max => General_Defs.Taille_Trame);
Buffer_Reception_A : Buffer_Reception.Objet;
Buffer_Reception_B : Buffer_Reception.Objet;
begin
Serie.Pos_Interruption (Serie.Aucun);
Buffer_Reception.Raz (File_Attente => Buffer_Reception_A);
Buffer_Reception.Raz (File_Attente => Buffer_Reception_B);
loop
accept Lit_Ecrit_Caractere do
Sorte_It := Serie.Donner_Evenement_Interruption;
case Sorte_It is
when Serie.Reception_A =>
begin
Simple_Io.Put_Line ("IT RECEP A");
Car := Serie.Lire_Donnee (General_Defs.Port_A);
Buffer_Reception.Enfiler
(File_Attente => Buffer_Reception_A,
Elem => Car);
exception
when Buffer_Reception.File_Pleine =>
null; -- A implementer
when others =>
null; -- A implementer
end;
when Serie.Reception_B =>
begin
Simple_Io.Put_Line ("IT RECEP B");
Car := Serie.Lire_Donnee (General_Defs.Port_B);
Buffer_Reception.Enfiler
(File_Attente => Buffer_Reception_B,
Elem => Car);
exception
when Buffer_Reception.File_Pleine =>
null; -- A implementer
when others =>
null; -- A implementer
end;
when Serie.Emission_A =>
begin
Ecriture (Car, General_Defs.Port_A);
Serie.Ecrire_Donnee (General_Defs.Port_A, Car);
exception
when others =>
null; -- A implementer
end;
when Serie.Emission_B =>
begin
Ecriture (Car, General_Defs.Port_B);
Serie.Ecrire_Donnee (General_Defs.Port_B, Car);
exception
when others =>
null; -- A implementer
end;
when Serie.Inconnu =>
raise Erreur_Interruption;
end case;
end Lit_Ecrit_Caractere;
while (Buffer_Reception.Est_Vide
(File_Attente => Buffer_Reception_A) = False) loop
declare
Car : General_Defs.Byte;
begin
Car := Buffer_Reception.Element_Tete
(File_Attente => Buffer_Reception_A);
Buffer_Reception.Defiler
(File_Attente => Buffer_Reception_A);
Lecture (Car, General_Defs.Port_A);
end;
end loop;
while (Buffer_Reception.Est_Vide
(File_Attente => Buffer_Reception_B) = False) loop
declare
Car : General_Defs.Byte;
begin
Car := Buffer_Reception.Element_Tete
(File_Attente => Buffer_Reception_B);
Buffer_Reception.Defiler
(File_Attente => Buffer_Reception_B);
Lecture (Car, General_Defs.Port_B);
end;
end loop;
end loop;
exception
when others =>
Simple_Io.Put_Line ("Erreur sur Tache Gestion IT ");
end Transmettre;
end Port_Serie;
nblk1=a
nid=5
hdr6=10
[0x00] rec0=18 rec1=00 rec2=01 rec3=01a
[0x01] rec0=13 rec1=00 rec2=03 rec3=01e
[0x02] rec0=1d rec1=00 rec2=04 rec3=032
[0x03] rec0=14 rec1=00 rec2=09 rec3=036
[0x04] rec0=13 rec1=00 rec2=06 rec3=012
[0x05] rec0=14 rec1=00 rec2=02 rec3=01c
[0x06] rec0=18 rec1=00 rec2=08 rec3=058
[0x07] rec0=0c rec1=00 rec2=07 rec3=000
[0x08] rec0=16 rec1=00 rec2=08 rec3=00c
[0x09] rec0=06 rec1=00 rec2=07 rec3=001
tail 0x21769a3e48924822ace32 0x42a00088462060003
Free Block Chain:
0x5: 0000 00 0a 03 ee 80 34 20 20 20 20 20 20 20 20 20 20 ┆ 4 ┆
0xa: 0000 00 00 00 17 80 14 20 20 20 20 20 20 28 50 6f 72 ┆ (Por┆