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Length: 6144 (0x1800)
Types: Ada Source
Notes: 03_class, FILE, R1k_Segment, e3_tag, package Krn_Cpu_Defs, seg_04cdf2
└─⟦8527c1e9b⟧ Bits:30000544 8mm tape, Rational 1000, Arrival backup of disks in PAM's R1000
└─⟦cfc2e13cd⟧ »Space Info Vol 2«
└─⟦this⟧
-- Copyright 1991 Verdix Corporation
with System;
use System;
with Unchecked_Conversion;
package Krn_Cpu_Defs is
pragma Suppress (All_Checks);
pragma Suppress (Exception_Tables);
pragma Not_Elaborated;
-------------------------------------------------------------------------
-- Kernel type definitions that are M68K cross target specific
-------------------------------------------------------------------------
-- Allocation and stack alignment
Alignment : constant := 4;
-- Size of exception stack frame for a trap instruction
Trap_Frame_Size : constant := 8;
-- This is to get around the problem with 'SIZE not working when
-- the elaboration code doesn't get executed.
Storage_Units_Per_Word : constant := 4;
-- Note: for RTS performance reasons a6, a7 and pc aren't being
-- updated. They're only there for the debugger.
type Cpu_State_T is
record
A6 : Address; -- fp\x09\x09-- 0
A7 : Address; -- sp\x09\x09-- 4
Pc : Address; -- 8
Sr : Short_Integer; -- c
Sr_Pad : Short_Integer;
-- When entered_from_intr = TRUE, restore_ssp points to
-- preempted_state_t record pushed on the task's supervisor stack.
-- The task's SSP is equal to the restore_ssp after this
-- record has been popped from the stack. The restore_usp field
-- contains the task's USP. None of the above registers
-- are valid.
--
-- When entered_from_intr = 0, the above registers reflect
-- the task's state upon entering the RTS.
Entered_From_Intr : Boolean; -- 10
Entered_From_Intr_Pad1 : Tiny_Integer; -- 11
Entered_From_Intr_Pad2 : Short_Integer; -- 12
Restore_Ssp : Address; -- 14
Restore_Usp : Address; -- 18
Stack_Limit : Address; -- 1c
end record;
for Cpu_State_T'Size use 16#20# * 8;
type A_Cpu_State_T is access Cpu_State_T;
-- Length of fields in krn_tcb_t record preceding cpu_state.
Cpu_State_Offset : constant := 0;
-- CPU state record field offsets from beginning of task control
-- block, not beginning of cpu_state
A6_Offset : constant := Cpu_State_Offset + 16#00#;
A7_Offset : constant := Cpu_State_Offset + 16#04#;
Pc_Offset : constant := Cpu_State_Offset + 16#08#;
Sr_Offset : constant := Cpu_State_Offset + 16#0C#;
Fp_Offset : constant := A6_Offset;
Sp_Offset : constant := A7_Offset;
Entered_From_Intr_Offset : constant := Cpu_State_Offset + 16#10#;
Restore_Ssp_Offset : constant := Cpu_State_Offset + 16#14#;
Restore_Usp_Offset : constant := Cpu_State_Offset + 16#18#;
Stack_Limit_Offset : constant := Cpu_State_Offset + 16#1C#;
--
-- The following state is pushed on the current task's supervisor stack
-- when the RTS is entered from an interrupt. For this case,
-- ts.ct.proc_state.entered_from_intr = TRUE and
-- ts.ct.proc_state.restore_ssp points to this record on the stack.
--
type Preempted_Reg_T is array (0 .. 14) of Integer; -- d0..d7, a0..a6
type Preempted_State_T is
record
Preempted_Reg : Preempted_Reg_T;
Sr : Short_Integer;
Pc : Integer;
end record;
pragma Pack (Preempted_State_T);
for Preempted_State_T'Size use 8 * 32 + 7 * 32 + 16 + 32;
type A_Preempted_State_T is access Preempted_State_T;
--
-- The following state is pushed on the current task's supervisor stack
-- before doing a task switch. For this case,
-- ts.ct.proc_state.entered_from_intr = FALSE and
-- ts.ct.proc_state.restore_ssp points to this record on the stack.
--
type Switch_Reg_T is array (0 .. 8) of Integer; -- d4..d7, a2..a6
type Task_Switch_State_T is
record
Switch_Reg : Switch_Reg_T;
Pc : Integer;
end record;
pragma Pack (Task_Switch_State_T);
for Task_Switch_State_T'Size use 4 * 32 + 5 * 32 + 32;
type A_Task_Switch_State_T is access Task_Switch_State_T;
end Krn_Cpu_Defs;
nblk1=5
nid=0
hdr6=a
[0x00] rec0=1f rec1=00 rec2=01 rec3=02e
[0x01] rec0=14 rec1=00 rec2=02 rec3=050
[0x02] rec0=18 rec1=00 rec2=03 rec3=096
[0x03] rec0=18 rec1=00 rec2=04 rec3=00c
[0x04] rec0=0a rec1=00 rec2=05 rec3=000
tail 0x217542090874f7bcbd2f7 0x42a00088462060003