|
DataMuseum.dkPresents historical artifacts from the history of: Rational R1000/400 |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about Rational R1000/400 Excavated with: AutoArchaeologist - Free & Open Source Software. |
top - download
Length: 13312 (0x3400)
Types: Ada Source
Notes: 03_class, FILE, R1k_Segment, e3_tag, package body C_Driver_Serie, seg_057e0a
└─⟦8527c1e9b⟧ Bits:30000544 8mm tape, Rational 1000, Arrival backup of disks in PAM's R1000
└─ ⟦cfc2e13cd⟧ »Space Info Vol 2«
└─⟦this⟧
with Simple_Io;
package body C_Driver_Serie is
task body Tache_Driver_Serie is
Fin_Chaine_A : Boolean := False;
Fin_Chaine_B : Boolean := False;
Taille_Trame_Envoi : Integer;
Increment_Envoi : Integer := 1;
Longueur : Integer;
Ecriture_Trame_Ok : Boolean := True;
Trame_En_Cours : Boolean := False;
I : Integer;
Tempo : General_Defs.Byte;
Fin_Chaine : General_Defs.Byte := (16#0D#);
Car_Essai : General_Defs.Byte := (16#71#);
Car_Essai1 : General_Defs.Byte := (16#72#);
begin
--Interface_Serie.Emission_Reception (Interface_Serie.R_Seule);
--Interface_Serie.Validation_It (Interface_Serie.R_Ab);
Buffer_Reception.Raz (Buffer_Reception_A);
Buffer_Reception.Raz (Buffer_Reception_B);
loop
select
-------------------------------------------------------------------------------
-- Lancement lecture prioritaire
-------------------------------------------------------------------------------
accept Lecture_Circuit
(Car : in G_Defs.Byte; Port : G_Defs.Port) do
if (G_Defs."=" (Port, G_Defs.Port_A)) then
Buffer_Reception.Enfiler
(File_Attente => Buffer_Reception_A, Elem => Car);
if General_Defs.Egaux (Fin_Chaine, Car) then
Fin_Chaine_A := True;
end if;
else
Buffer_Reception.Enfiler
(File_Attente => Buffer_Reception_B, Elem => Car);
if General_Defs.Egaux (Fin_Chaine, Car) then
Fin_Chaine_B := True;
end if;
end if;
end Lecture_Circuit;
else
-------------------------------------------------------------------------------
-- Lancement lecture/ecriture
-------------------------------------------------------------------------------
select
-------------------------------------------------------------------------------
-- Lecture
-------------------------------------------------------------------------------
accept Lecture_Circuit
(Car : in G_Defs.Byte; Port : G_Defs.Port) do
if (G_Defs."=" (Port, G_Defs.Port_A)) then
Buffer_Reception.Enfiler
(File_Attente => Buffer_Reception_A,
Elem => Car);
if General_Defs.Egaux (Fin_Chaine, Car) then
Fin_Chaine_A := True;
end if;
else
Buffer_Reception.Enfiler
(File_Attente => Buffer_Reception_B,
Elem => Car);
if General_Defs.Egaux (Fin_Chaine, Car) then
Fin_Chaine_B := True;
end if;
end if;
end Lecture_Circuit;
or
when Fin_Chaine_A =>
accept Lecture_Trame (Trame : in out G_Defs.Byte_String;
Taille : out Integer;
Port : out G_Defs.Port) do
I := 1;
Buffer_Reception.Element_Tete
(Buffer_Reception_A, Trame (I));
Buffer_Reception.Defiler (Buffer_Reception_A);
while General_Defs.Egaux (Fin_Chaine, Trame (I)) =
False loop
I := I + 1;
Buffer_Reception.Element_Tete
(Buffer_Reception_A, Trame (I));
Buffer_Reception.Defiler (Buffer_Reception_A);
end loop;
Taille := I;
Fin_Chaine_A := False;
end Lecture_Trame;
or
when Fin_Chaine_B =>
accept Lecture_Trame (Trame : in out G_Defs.Byte_String;
Taille : out Integer;
Port : out G_Defs.Port) do
I := 1;
Buffer_Reception.Element_Tete
(Buffer_Reception_B, Trame (I));
Buffer_Reception.Defiler (Buffer_Reception_B);
while General_Defs.Egaux (Fin_Chaine, Trame (I)) =
False loop
I := I + 1;
Buffer_Reception.Element_Tete
(Buffer_Reception_B, Trame (I));
Buffer_Reception.Defiler (Buffer_Reception_B);
end loop;
Taille := I;
Fin_Chaine_B := False;
end Lecture_Trame;
or
-------------------------------------------------------------------------------
-- Ecriture
-------------------------------------------------------------------------------
accept Ecriture_Trame (Trame : in G_Defs.Byte_String;
Port : G_Defs.Port) do
Longueur := Trame'Length;
Interface_Serie.Envoi_Donnee_Par_It (Type_Port => Port);
Increment_Envoi := 1;
while (Increment_Envoi <= Longueur) loop
accept Ecriture_Circuit (Car : out G_Defs.Byte;
N_Port : G_Defs.Port) do
Car := Trame (Increment_Envoi);
end Ecriture_Circuit;
delay 0.01;
Increment_Envoi := Increment_Envoi + 1;
if (Increment_Envoi <= Longueur) then
Interface_Serie.Envoi_Donnee_Par_It
(Type_Port => Port);
end if;
end loop;
end Ecriture_Trame;
or
delay 100.0;
end select;
end select;
end loop;
end Tache_Driver_Serie;
end C_Driver_Serie;
nblk1=c
nid=7
hdr6=10
[0x00] rec0=1c rec1=00 rec2=01 rec3=02e
[0x01] rec0=13 rec1=00 rec2=04 rec3=034
[0x02] rec0=11 rec1=00 rec2=09 rec3=028
[0x03] rec0=12 rec1=00 rec2=02 rec3=008
[0x04] rec0=11 rec1=00 rec2=0a rec3=08e
[0x05] rec0=14 rec1=00 rec2=08 rec3=008
[0x06] rec0=13 rec1=00 rec2=03 rec3=012
[0x07] rec0=06 rec1=00 rec2=0b rec3=000
[0x08] rec0=10 rec1=00 rec2=0b rec3=086
[0x09] rec0=0f rec1=00 rec2=03 rec3=000
[0x0a] rec0=08 rec1=00 rec2=0a rec3=000
[0x0b] rec0=e3 rec1=80 rec2=00 rec3=000
tail 0x217652a6287d474737b4b 0x42a00088462060003
Free Block Chain:
0x7: 0000 00 05 02 7e 80 1f 20 20 20 20 20 20 20 20 20 20 ┆ ~ ┆
0x5: 0000 00 0c 00 52 80 21 20 20 20 20 20 20 20 20 20 20 ┆ R ! ┆
0xc: 0000 00 06 00 05 80 02 2a 2a 02 00 34 f4 aa cd 83 42 ┆ ** 4 B┆
0x6: 0000 00 00 03 fc 80 08 2a 2a 2a 2a 2a 2a 2a 2a 08 00 ┆ ******** ┆