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Length: 13312 (0x3400)
Types: Ada Source
Notes: 03_class, FILE, R1k_Segment, e3_tag, package body Driver_Serie, seg_05a2d9
└─⟦8527c1e9b⟧ Bits:30000544 8mm tape, Rational 1000, Arrival backup of disks in PAM's R1000
└─⟦cfc2e13cd⟧ »Space Info Vol 2«
└─⟦this⟧
with Simple_Io;
package body Driver_Serie is
task body Tache_Driver_Serie is
Trame_A_Ok : Buffer_Port_A.Etat_Trame := Buffer_Port_A.Autre;
Trame_B_Ok : Buffer_Port_B.Etat_Trame := Buffer_Port_B.Autre;
Trame_Envoi : Buffer_Port_A.Chaine_Trame;
Taille_Trame_Envoi : Integer;
Increment_Envoi : Integer := 1;
Ecriture_Trame_Ok : Boolean := True;
Trame_En_Cours : Boolean := False;
begin
Interface_Serie.Emission_Reception (Interface_Serie.R_Seule);
Interface_Serie.Validation_It (Interface_Serie.R_Ab);
loop
select
--*****************************************************************************
-- Lancement lecture prioritaire
--*****************************************************************************
accept Lecture_Circuit
(Car : in G_Defs.Byte; Port : G_Defs.Port) do
if (G_Defs."=" (Port, G_Defs.Port_A)) then
Trame_A_Ok :=
Buffer_Port_A.Construire_Trame_Reception (Car);
if (Buffer_Port_A."=" (Trame_A_Ok,
Buffer_Port_A.Debut)) then
Trame_En_Cours := True;
elsif (Buffer_Port_A."="
(Trame_A_Ok, Buffer_Port_A.Fin)) then
Trame_En_Cours := False;
end if;
else
Trame_B_Ok :=
Buffer_Port_B.Construire_Trame_Reception (Car);
if (Buffer_Port_B."=" (Trame_B_Ok,
Buffer_Port_B.Debut)) then
Trame_En_Cours := True;
elsif (Buffer_Port_B."="
(Trame_B_Ok, Buffer_Port_B.Fin)) then
Trame_En_Cours := False;
end if;
end if;
end Lecture_Circuit;
else
--***************************************************************************
-- Lancement lecture / ecriture
--*****************************************************************************
select
--===============
-- Lecture
--===============
accept Lecture_Circuit
(Car : in G_Defs.Byte; Port : G_Defs.Port) do
if (G_Defs."=" (Port, G_Defs.Port_A)) then
Trame_A_Ok := Buffer_Port_A.
Construire_Trame_Reception (Car);
if (Buffer_Port_A."=" (Trame_A_Ok,
Buffer_Port_A.Debut)) then
Trame_En_Cours := True;
elsif (Buffer_Port_A."="
(Trame_A_Ok, Buffer_Port_A.Fin)) then
Trame_En_Cours := False;
end if;
else
Trame_B_Ok := Buffer_Port_B.
Construire_Trame_Reception (Car);
if (Buffer_Port_B."=" (Trame_B_Ok,
Buffer_Port_B.Debut)) then
Trame_En_Cours := True;
elsif (Buffer_Port_B."="
(Trame_B_Ok, Buffer_Port_B.Fin)) then
Trame_En_Cours := False;
end if;
end if;
end Lecture_Circuit;
or
when (Buffer_Port_A."=" (Trame_A_Ok, Buffer_Port_A.Fin)) =>
accept Lecture_Trame (Trame : out G_Defs.Byte_String;
Taille : out Integer;
Port : out G_Defs.Port) do
Buffer_Port_A.Extraire_Trame_Reception
(Trame, Taille);
Trame_A_Ok := Buffer_Port_A.Autre;
end Lecture_Trame;
or
when (Buffer_Port_B."=" (Trame_B_Ok, Buffer_Port_B.Fin)) =>
accept Lecture_Trame (Trame : out G_Defs.Byte_String;
Taille : out Integer;
Port : out G_Defs.Port) do
Buffer_Port_B.Extraire_Trame_Reception
(Trame, Taille);
Trame_B_Ok := Buffer_Port_B.Autre;
end Lecture_Trame;
or
--==================
-- Ecriture
--==================
accept Ecriture_Trame (Trame : in G_Defs.Byte_String;
Port : G_Defs.Port) do
Buffer_Port_A.Construire_Trame_Emission
(Trame, Trame_Envoi, Taille_Trame_Envoi);
Interface_Serie.Envoi_Donnee_Par_It (Type_Port => Port);
Increment_Envoi := 1;
while (Increment_Envoi <= Taille_Trame_Envoi) loop
accept Ecriture_Circuit (Car : out G_Defs.Byte;
N_Port : G_Defs.Port) do
Interface_Serie.Validation_It
(Sorte => Interface_Serie.R_Ab);
Car := Trame_Envoi (Increment_Envoi);
Increment_Envoi := Increment_Envoi + 1;
if (Increment_Envoi <= Taille_Trame_Envoi) then
Interface_Serie.Envoi_Donnee_Par_It
(Type_Port => N_Port);
end if;
end Ecriture_Circuit;
end loop;
end Ecriture_Trame;
or
-- when trame_en_cours = true
delay 100.0;
end select;
end select;
end loop;
end Tache_Driver_Serie;
end Driver_Serie;
nblk1=c
nid=9
hdr6=e
[0x00] rec0=1a rec1=00 rec2=01 rec3=028
[0x01] rec0=11 rec1=00 rec2=05 rec3=080
[0x02] rec0=14 rec1=00 rec2=0a rec3=086
[0x03] rec0=15 rec1=00 rec2=03 rec3=010
[0x04] rec0=10 rec1=00 rec2=07 rec3=046
[0x05] rec0=12 rec1=00 rec2=0b rec3=01e
[0x06] rec0=14 rec1=00 rec2=02 rec3=000
[0x07] rec0=11 rec1=00 rec2=02 rec3=03a
[0x08] rec0=13 rec1=00 rec2=09 rec3=000
[0x09] rec0=0c rec1=00 rec2=08 rec3=000
[0x0a] rec0=08 rec1=00 rec2=0a rec3=000
[0x0b] rec0=e3 rec1=80 rec2=00 rec3=000
tail 0x21769c02489249170bc30 0x42a00088462060003
Free Block Chain:
0x9: 0000 00 04 02 53 80 11 54 72 61 6d 65 5f 45 6e 76 6f ┆ S Trame_Envo┆
0x4: 0000 00 08 00 09 80 06 5f 53 65 72 69 65 06 20 20 20 ┆ _Serie ┆
0x8: 0000 00 0c 00 06 80 03 74 20 47 03 20 47 06 07 08 09 ┆ t G G ┆
0xc: 0000 00 06 00 05 80 02 2a 2a 02 00 34 f4 aa cd 83 42 ┆ ** 4 B┆
0x6: 0000 00 00 03 fc 80 08 2a 2a 2a 2a 2a 2a 2a 2a 08 00 ┆ ******** ┆