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DataMuseum.dkPresents historical artifacts from the history of: Rational R1000/400 DFS Tapes |
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Length: 2547 (0x9f3)
Types: EM, TextFile
Names: »READ_IOC_WCS.EM«
└─⟦24d56d853⟧ Bits:30000744 8mm tape, Rational 1000, DFS, D_12_6_5 SEQ293
└─ ⟦this⟧ »READ_IOC_WCS.EM«
└─⟦9031b0687⟧ Bits:30000407 8mm tape, Rational 1000, DFS, D_12_7_3
└─ ⟦this⟧ »READ_IOC_WCS.EM«
set iocuir [xeq ioc read_wcs [eq,%1%,][read micro pc =,][else]%1%[end],0]; set iocuir [arg 1 [var iocuir]]; [#case,[#extract,[var iocuir],33,5]] [when 00]set rand noop; [when 01]set rand load transfer address; [when 02]set rand spare encoding 16#02#; [when 03]set rand spare encoding 16#03#; [when 04]set rand write request queue tail; [when 05]set rand read response queue head; [when 06]set rand load slice timer; [when 07]set rand load delay timer; [when 08]set rand read and clear rtc; [when 09]set rand read timers/checkbits/errorid; [when 0A]set rand clear slice event; [when 0B]set rand clear delay event; [when 0C]set rand enable slice timer; [when 0D]set rand disable slice timer; [when 0E]set rand enable delay timer; [when 0F]set rand disable delay timer; [when 10]set rand load checkbit register; [when 11]set rand disable ecc events; [when 12]set rand exit function pop below tcb event enable; [when 13]set rand set cpu running; [when 14]set rand clear cpu running; [when 15]set rand clear transfer parity error; [when 16]set rand stage data register; [when 17]set rand force type bus receivers; [when 18]set rand drive diagnostic checkbits; [when 19]set rand ecc bench testing random; [when 1A]set rand spare encoding 16#26#; [when 1B]set rand spare encoding 16#27#; [when 1C]set rand read ioc memory and increment address; [when 1D]set rand read ioc memory; [when 1E]set rand write ioc memory and increment address; [when 1F]set rand write ioc memory; [endcase] write random,,,,,,,,,,,,,=,[var rand]; kill rand; [#case,[#extract,[var iocuir],38,2]] [when 0]set bus fiu; [when 1]set bus val; [when 2]set bus typ; [when 3]set bus seq; [endcase] write address bus source,=,[var bus]; [#case,[#extract,[var iocuir],3A,2]] [when 0]set bus fiu; [when 1]set bus val; [when 2]set bus typ; [when 3]set bus seq; [endcase] write fiu bus source,,,,,=,[var bus]; [#case,[#extract,[var iocuir],3C,4]] [when 0]set bus typ/val; [when 1]set bus typ/fiu; [when 2]set bus fiu/val; [when 3]set bus fiu/fiu; [when 4]set bus ioc/ioc; [when 5]set bus seq/seq; [when 6]set bus reserved encoding 16#6#; [when 7]set bus reserved encoding 16#7#; [when 8]set bus typ/mem; [when 9]set bus typ/mem; [when A]set bus fiu/mem; [when B]set bus fiu/mem; [when C]set bus rdr; [when D]set bus rdr; [when E]set bus rdr; [when F]set bus rdr; [endcase] write typ/val bus source,=,[var bus]; kill bus; [#eq,0,[#extract,[var iocuir],32,1]] write load wdr,,,,,,,,,,,=,load; [else] write load wdr,,,,,,,,,,,=,hold; [end]