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Length: 4096 (0x1000)
Types: EM, TextFile
Names: »FIU_MM_CSA_TESTS.EM«
└─⟦b4205821b⟧ Bits:30000743 8mm tape, Rational 1000, DFS, D_12_7_3 SEQ288
└─ ⟦this⟧ »FIU_MM_CSA_TESTS.EM«
└─⟦b434774df⟧ Bits:30000528 8mm tape, Rational 1000, DFS, D_12_6_5
└─ ⟦this⟧ »FIU_MM_CSA_TESTS.EM«
└─⟦bc1274df5⟧ Bits:30000750 8mm tape, Rational 1000, DFS backup from PAM's R1000
└─ ⟦this⟧ »FIU_MM_CSA_TESTS.EM«
[write]
[write,Testing,FIU,Board,Tile,7,,-,,Fiu_mm_csa_tests]
[write,,,,,,,,,,,,,,,,,,,,,,,,,,,,&,Fiu_mm_csa2_tests]
[write,,,,,,,,,,,,,,,,,,,,,,,,,,,,&,Fiu_mm_csa3_tests]
[write]
[set experiment_result [xeq fiu test_restore_state_bits]]
[eq,[arg 1,[var experiment_result]],false]
[FAIL_MESSAGE restore_state_bits_test]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE test_restore_state_bits][write]
[else]
[PASS_MESSAGE restore_state_bits_test]
[end]
[set experiment_result [xeq fiu test_dummy_next]]
[eq,[arg 1,[var experiment_result]],false]
[FAIL_MESSAGE dummy_next_test]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE test_dummy_next][write]
[else]
[PASS_MESSAGE dummy_next_test]
[end]
[set experiment_result [xeq fiu test_restore_rdr]]
[eq,[arg 1,[var experiment_result]],false]
[FAIL_MESSAGE restore_rdr_test]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE test_restore_rdr][write]
[else]
[PASS_MESSAGE restore_rdr_test]
[end]
[eq,[var bench_mode],false]
[xeq seq write_uir 000098390800]
[xeq seq observe_runtime_state]
[end]
[set experiment_result [xeq fiu test_px_wire]]
[eq,[arg 1,[var experiment_result]],false]
[FAIL_MESSAGE px_wire_test]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE test_px_wire][write]
[else]
[PASS_MESSAGE px_wire_test]
[end]
[set experiment_result [xeq fiu test_mem_exception]]
[eq,[arg 1,[var experiment_result]],false]
[FAIL_MESSAGE mem_exception_test]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE test_mem_exception][write]
[else]
[PASS_MESSAGE mem_exception_test]
[end]
[eq,[var bench_mode],false]
[xeq seq write_uir 000098390000]
[end]
[xeq fiu load_pareg 0ff 0]
[xeq fiu load_cond_mem_ucode]
[xeq fiu clear_exceptions]
[xeq fiu step_fiu 0 3 0]
[set experiment_result [xeq fiu read_mdr 0]]
[ne,[and,00f0000000000000,[arg 1,[var experiment_result]]],20000000000000]
[FAIL_MESSAGE conditional_memory_start_test_1]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE load_pareg 0ff 0]
[NAME_MESSAGE load_cond_mem_ucode]
[NAME_MESSAGE clear_exceptions]
[NAME_MESSAGE step_fiu 0 3 0]
[NAME_MESSAGE read_mdr 0]
[write mdr should be : XX2XXXXXXXXXXXXX][write]
[else]
[PASS_MESSAGE conditional_memory_start_test_1]
[end]
[xeq fiu clear_exceptions]
[xeq fiu step_fiu 3 3 0]
[set experiment_result [xeq fiu read_mdr 0]]
[ne,[and,00f0000000000000,[arg 1,[var experiment_result]]],0]
[FAIL_MESSAGE conditional_memory_start_test_2]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE load_pareg 0ff 0]
[NAME_MESSAGE load_cond_mem_ucode]
[NAME_MESSAGE clear_exceptions]
[NAME_MESSAGE step_fiu 3 3 0]
[NAME_MESSAGE read_mdr 0]
[write mdr should be : XX0XXXXXXXXXXXXX][write]
[else]
[PASS_MESSAGE conditional_memory_start_test_2]
[end]
[xeq fiu clear_exceptions]
[xeq fiu step_fiu 6 3 0]
[set experiment_result [xeq fiu read_mdr 0]]
[ne,[and,00f0000000000000,[arg 1,[var experiment_result]]],40000000000000]
[FAIL_MESSAGE conditional_memory_start_test_3]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE load_pareg 0ff 0]
[NAME_MESSAGE load_cond_mem_ucode]
[NAME_MESSAGE clear_exceptions]
[NAME_MESSAGE step_fiu 6 3 0]
[NAME_MESSAGE read_mdr 0]
[write mdr should be : XX4XXXXXXXXXXXXX][write]
[else]
[PASS_MESSAGE conditional_memory_start_test_3]
[end]«nul»