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Length: 8188 (0x1ffc)
Types: ERRMESS, TextFile
Names: »P2MM.ERRMESS«
└─⟦24d56d853⟧ Bits:30000744 8mm tape, Rational 1000, DFS, D_12_6_5 SEQ293
└─ ⟦this⟧ »P2MM.ERRMESS«
└─⟦9031b0687⟧ Bits:30000407 8mm tape, Rational 1000, DFS, D_12_7_3
└─ ⟦this⟧ »P2MM.ERRMESS«
0 Phase II Memory Monitor tests PASSED. 1 Loading the MAR state bits with a RESTORE_MAR does not work. The diagnostic register on the FIU board was used to drive the MAR CONTROL wires. This could be a problem with the T.DIAG_MODE signal or one of the MAR_CNTL signals, if not the the problem is on the FIU board. 2 MEMORY ABORT test failed. The FIU was not asserting EL_ABORT~ and the SEQ was not asserting E_ABOT~ or L_ABORT~, but one memory board incorrectly received a LATE_ABORT. 3 MEMORY ABORT test failed. The FIU was not asserting EL_ABORT~ and the SEQ was not asserting E_ABORT~ or L_ABORT~, but more than one memory board incorrectly received a LATE_ABORT. No memories received an EARLY_ABORT. 4 MEMORY ABORT test failed. The FIU was not asserting EL_ABORT~ and the SEQ was not asserting E_ABORT~ or L_ABORT~ , but one memory board incorrectly received an EARLY_ABORT. 5 MEMORY ABORT test failed. The FIU was not asserting EL_ABORT~ and the SEQ was not asserting E_ABORT~ or L_ABORT~, but more than one memory board incorrectly received an EARLY_ABORT. No memories received a LATE_ABORT. 6 MEMORY ABORT test failed. The FIU was not asserting EL_ABORT~ and the SEQ was not asserting E_ABORT~ or L_ABORT~, but more than one memory board incorrectly received an EARLY_ABORT. More than one memory received a LATE_ABORT. 7 MEMORY ABORT test failed. When the FIU was asserting EL_ABORT~, one memory board did not receive a LATE_ABORT. 8 MEMORY ABORT test failed. When the FIU asserted EL_ABORT~, all memory boards received an EARLY_ABORT, but one or more did not receive LATE_ABORT asserted. 9 MEMORY ABORT test failed. When the FIU was asserting EL_ABORT~, one memory board did not receive an EARLY_ABORT. 10 MEMORY ABORT test failed. When the FIU asserted EL_ABORT~, multiple memory boards did not receive an EARLY_ABORT, but when the SEQUENCER asserted E_ABORT~, all memories received it correctly. 11 MEMORY ABORT test failed. When the FIU asserted EL_ABORT~, multiple memory boards did not receive an EARLY_ABORT, and when the SEQUENCER asserted E_ABORT~ one or more memories received it incorrectly. 12 MEMORY ABORT test failed. When the SEQUENCER asserted L_ABORT~ one memory board did not receive a LATE_ABORT, the FIU driving a LATE_ABORT (via EL_ABORT~) has already been tested and passed. 13 MEMORY ABORT test failed. When the SEQUENCER asserted L_ABORT~ multiple memory boards did not receive a LATE_ABORT. The FIU driving a LATE_ABORT (via EL_ABORT~) has already been tested and passed. 14 MEMORY ABORT test failed. When the SEQUENCER asserted E_ABORT~ one memory board did not receive an EARLY_ABORT, the FIU driving an EARLY_ABORT (via EL_ABORT~) has already been tested and passed. 15 MEMORY ABORT test failed. When the SEQUENCER asserted E_ABORT~ multiple memory boards did not receive an EARLY_ABORT. The FIU driving an EARLY_ABORT (via EL_ABORT~) has already been tested and passed. 16 The PHYSICAL_LAST flag test failed. 17 The WRITE_LAST flag test failed. 18 The CONTROL_ADDRESS_OUT_OF_RANGE flag test failed. 19 The PAGE_CROSSING flag test failed. 20 The INCOMPLETE_MEMORY_CYCLE flag test failed. 21 The MAR_MODIFIED flag test failed. 22 The CONDITIONAL MEMORY START wire test failed. The FIU was not able to correctly read these siganls diagnostically, but the SEQUENCER responded correctly by early aborting memory at the appropriate time. This should have no affect on normal system operation, but indicates that there may be a problem reading the FRAME ADDRESS REGISTER. 23 The CONDITIONAL MEMORY START wire test failed. The FIU was able to drive and receive these signals correctly but one memory board incorrectly received the E_ABORT~ signal from the SEQUENCER. The ABORT test has passed. 24 The CONDITIONAL MEMORY START wire test failed. The FIU was not able to drive and receive these signals correctly and only one memory board incorrectly received the E_ABORT~ signal from the SEQUENCER. The ABORT test has passed. 25 The CONDITIONAL MEMORY START wire test failed. The FIU was able to drive and receive these signals correctly but multiple memory boards incorrectly received the E_ABORT~ signal from the SEQUENCER. 26 The CONDITIONAL MEMORY START wire test failed. The FIU was not able to drive and receive these signals correctly and multiple memory boards incorrectly received the E_ABORT~ signal from the SEQUENCER. 27 The RESTORE_RDR test failed on both the FIU and SYSBUS boards. 28 The RESTORE_RDR test failed on the SYSBUS board and passed on the FIU board, This could be an FIU to SYSBUS backplane interconnect problem or a failure on the SYSBUS board. 29 The RESTORE_RDR test failed on the FIU board and passed on the SYSBUS board. This means that there is a problem only in diagnostically reading the RESTORE_RDR signal on the FIU which should have no effect on normal system operation. This could point to a problem in reading the FRAME_ADDRESS_REGISTER on the FIU board. 30 The DUMMY_ENABLE_NEXT test failed on both the FIU and SYSBUS boards. 31 The DUMMY_ENABLE_NEXT test failed on the SYSBUS board.This could be an FIU to SYSBUS backplane interconnect problem or a failure on the SYSBUS board. 32 The DUMMY_ENABLE_NEXT test failed on the FIU board and passed on the SYSBUS board. This means that there is a problem only in diagnostically reading the DUMMY_ENABLE_NEXT signal on the FIU which should have no effect on normal system operation. 33 The READ_TVR_NEXT test failed. When the FIU asserted RTV_NEXT~ one memory board received it incorrectly. 34 The READ_TVR_NEXT test failed. When the FIU was not asserting RTV_NEXT~ one memory board received it incorrectly. 35 The READ_TVR_NEXT test failed. When the FIU asserted RTV_NEXT~ multiple memory boards received it incorrectly. 36 The READ_TVR_NEXT test failed. When the FIU was not asserting RTV_NEXT~ multiple memory boards received it incorrectly. 37 The FIU board drove the MEM_CNTL signals and one MEMORY board did not receive them correctly. 38 The FIU board drove the MEM_CNTL signals and more than one MEMORY board received them incorrectly. 39 The FIU board drove the CONTINUE~ wire and one memory board received it incorrectly. 40 The FIU board drove the CONTINUE~ wire and more than one MEMORY board received it incorrectly. 41 The BOARD_HIT test failed because the FIU was computing the wrong value for the most significant SET_NUMBER bits. 42 The BOARD_HIT test failed because of a failure with BOARD_HIT0; 43 The BOARD_HIT test failed because of a failure with BOARD_HIT1; 44 The BOARD_HIT test failed because of a failure with BOARD_HIT2; 45 The BOARD_HIT test failed because of a failure with BOARD_HIT3; 46 The BOARD_HIT test failed with more than one MEMORY board because the most significant SET_NUMBER bits were bad. 47 The BOARD_HIT test failed because of a failure with more than one BOARD_HIT wire. 48 The BOARD_HIT test failed because the most significant SET_NUMBER wires were incorrect when no boards were supposed to be hitting, and the CACHE_HIT test fails on all boards. 49 The BOARD_HIT test failed because the most significant SET_NUMBER wires were incorrect when no boards were supposed to be hitting, and some (not all) of the memories failed the CACHE_MISS test. 50 The CACHE_MISS flag test failed. A logical reference caused a CACHE_MISS even though there was a CSA_HIT. 51 The CACHE_MISS flag test failed. A logical reference did not cause a CACHE_MISS when the PAGE_STATE of the hitting board was LOADING. 52 The CACHE_MISS flag test failed. A physical reference cause a CACHE_MISS. 53 The CACHE_MISS flag test failed. The test passed using all memories except MEM0, so the problem is either one with MEM0 or a bad connection on the FIU or MEM0 to the BOARD_HIT0 signal. 54 The CACHE_MISS flag test failed with a memory board other than MEM0. 55 The INIT_MRU test failed. 56 The least significant SET_NUMBER bit test failed. 57 The BOARD_HIT test failed because BOARD_HIT~0 and BOARD_HIT~1 could not be asserted correctly. 58 The BOARD_HIT test failed because BOARD_HIT~2 and BOARD_HIT~3 could not be asserted correctly.