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    Length: 7168 (0x1c00)
    Types: ERRMESS, TextFile
    Names: »P2ABUS.ERRMESS«

└─⟦b4205821b⟧ Bits:30000743 8mm tape, Rational 1000, DFS, D_12_7_3 SEQ288
    └─ ⟦this⟧ »P2ABUS.ERRMESS« 
└─⟦b434774df⟧ Bits:30000528 8mm tape, Rational 1000, DFS, D_12_6_5
    └─ ⟦this⟧ »P2ABUS.ERRMESS« 
└─⟦bc1274df5⟧ Bits:30000750 8mm tape, Rational 1000, DFS backup from PAM's R1000
    └─ ⟦this⟧ »P2ABUS.ERRMESS« 

TextFile

0	ADDRESS BUS OK
1	ABORT -> an unexpected MACHINE CHECK occured
2	ABORT -> microcode did not halt but no MACHINE CHECK occured
3	ABORT -> microcode halted at the wrong micro address
4	Both RESTORE_MAR & LOAD_MAR failed to load the FIU MAR.
	Both the TYP & VAL boards were the ABUS source for both tests,
	so it's probably not an ABUS.OE fault. A possible cause is
	both MAR_CNTL0 & MAR_CNTL1 stuck at zero, maybe shorted together.
5	The FIU MAR was not loaded by RESTORE_MAR, but it was loaded by
	LOAD_MAR (i.e. MAR_SPACE := xxx). A possible cause is MAR_CNTL1
	stuck at zero.
6	The FIU MAR was not loaded by LOAD_MAR (i.e. MAR_SPACE := xxx),
	but it was loaded by RESTORE_MAR. A possible cause is MAR_CNTL0
	stuck at zero.
7	RESTORE_MAR failed to load the memory state bits on the FIU. A
	possible cause is MAR_CNTL2 stuck at one.
8	INCREMENT_MAR loaded the memory state bits on the FIU board, which
	it shouldn't do. A possible cause is MAR_CNTL2 stuck at zero.
9	RESTORE_MAR loaded the refresh counters on the FIU board, which
	it shouldn't do. A possible cause is MAR_CNTL3 stuck at one.
10	RESTORE_MAR_REFRESH failed to load the refresh counters on the
	FIU board. A possible cause is MAR_CNTL3 stuck at zero.
11	WIERD FAILURE: The FIU MAR failed to load with the SEQ board
	driving the ABUS during a LOAD_MAR and with the TYP driving during
	a RESTORE_MAR. Yet the MAR did load with either TYP driving during
	a LOAD_MAR or the VAL driving during a RESTORE_MAR. Probably caused
	by multiple faults with SEQ_A.OE~, TYP_A.OE~ and MAR_CNTL<0..3>.
12	The SEQ board can't drive any bits of the ABUS properly, yet
	other boards can. The probable cause is SEQ_A.OE~ stuck at one.
13	The TYP board can't drive any bits of the ABUS properly, yet
	other boards can. The probable cause is TYP_A.OE~ stuck at one.
14	The VAL board can't drive any bits of the ABUS properly, yet
	other boards can. The probable cause is VAL_A.OE~ stuck at one.
15	The FIU board can't drive any bits of the ABUS properly, yet
	other boards can. The probable cause is FIU_A.OE~ stuck at one.
16	LOAD_MAR (i.e. MAR_SPACE := xxx) fails to load any of the MEM MARs.
	It loads the FIU MAR correctly. RESTORE_MAR does load the MEM MARs.
	The probable cause is MAR_CNTL0 not being ORed with MAR_CNTL1 on
	the TYP board.
17	RESTORE_MAR failed to load any of the MEM MARs. LOAD_MAR may have
	failed to load it too. Possible causes are LOAD_MAR~ stuck at one
	and MAR_CNTL1 not being ORed with MAR_CNTL0 on the TYP board.
18	The MAR on MEM0 failed to load at all, yet the MARs on at least
	one other memory did load.
19	The MAR on MEM1 failed to load at all, yet the MARs on at least
	one other memory did load.
20	The MAR on MEM2 failed to load at all, yet the MARs on at least
	one other memory did load.
21	The MAR on MEM3 failed to load at all, yet the MARs on at least
	one other memory did load.
22	The Sequencer can't drive the following ABUS NAME bits correctly
	when its ADDRESS MUX selects the NAME_BUS. It can drive them
	correctly when the CODE.ADR bus is selected.
	%1%
23	The Sequencer can't drive the following ABUS OFFS bits correctly
	when its ADDRESS MUX selects the RESOLVE_OFFS bus. It can drive
	them correctly when the OFFSET_BUS or CODE.ADR bus is selected.
	%1%
24	The FIU MAR was spuriously loaded when it shouldn't have been.
	Possible causes include MAR_CNTL0 or MAR_CNTL1 stuck at one.
25	The following ABUS bits are stuck at zero or one, regardless of
	which board drives the bus. Therefore they are shorted to something
	or an ABUS driver on some board has an output stuck at zero.
	%1%
26	The TYP board can't drive these ABUS bits correctly:
	%1%
	(If any SPACE bits are bad, they failed using both LOAD_MAR and
	RESTORE_MAR.)
27	The VAL board can't drive these ABUS bits correctly:
	%1%
28	The Sequencer can't drive the following ABUS bits correctly,
	regardless of which internal source its ADDRESS MUX selects.
	%1%
29	The Sequencer's MACRO_PC can't drive the following ABUS bits
	correctly. The ADDRESS MUX selected the CODE.ADR bus in this
	test. The ABUS was driven correctly when the MUX selected the
	NAME and RESOLVE_OFFS busses.
	%1%
30	The Sequencer's CONTROL_TOP can't drive the following ABUS bits
	correctly. The ADDRESS MUX selected the NAME & OFFSET busses in
	this test. The ABUS was driven correctly when the MUX selected
	the CODE.ADR bus.
	%1%
31	The Sequencer's RESOLVE RAM can't drive the following ABUS bits
	correctly when doing a DISPATCH on a LL_DELTA instruction.
	The ADDRESS MUX selected the NAME & RESOLVE_OFFS busses in this
	test. Other tests using the  NAME & RESOLVE_OFFS busses passed.
	%1%
32	The Sequencer's RESOLVE ADDER can't drive the following ABUS bits
	correctly when doing DISPATCH on a TOS_TYPE_LINK instruction.
	The ADDRESS MUX selected the NAME & RESOLVE_OFFS busses in this
	test. Other tests using the  NAME & RESOLVE_OFFS busses passed.
	%1%
33	The FIU board can't drive these ABUS bits correctly:
	%1%
	(it can receive these bits when they're driven from another board,
	 but not when it drives them itself)
34	The FIU board can't receive these ABUS bits correctly:
	%1%
	(even when it drives the address itself, so it's not an open finger)
35	The FIU board has an open backplane connection on these ABUS bits:
	%1%
36	MEM0 can't receive these ABUS bits correctly:
	%1%
37	MEM1 can't receive these ABUS bits correctly:
	%1%
38	MEM2 can't receive these ABUS bits correctly:
	%1%
39	MEM3 can't receive these ABUS bits correctly:
	%1%
40	An unexpected ABUS PARITY error was detected by MEM0 but not the FIU.
41	An unexpected ABUS PARITY error was detected by MEM1 but not the FIU.
42	An unexpected ABUS PARITY error was detected by MEM2 but not the FIU.
43	An unexpected ABUS PARITY error was detected by MEM3 but not the FIU.
44	An ABUS PARITY bit is probably stuck at zero or one. ABUS PARITY
	errors were detected by multiple boards with different ABUS sources.
45	An unexpected ABUS PARITY error was detected by the FIU and memories
	when TYP, VAL or SEQ drove ABUS.
	Further isolation is not implemented yet.
46	Unexpected ABUS PARITY error detected by FIU. None of the memories
	got the error so it's an FIU problem receiving or checking parity.
47	The FIU board drove incorrect ABUS PARITY to all memories and itself.
	It checks parity correctly when other boards drive the ABUS so the
	problem is a bad ABUS PARITY DRIVER.«nul»