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⟦ad106dafc⟧ EM, TextFile

    Length: 11264 (0x2c00)
    Types: EM, TextFile
    Names: »FIU_MM_CSAA_TESTS.EM«

Derivation

└─⟦b4205821b⟧ Bits:30000743 8mm tape, Rational 1000, DFS, D_12_7_3 SEQ288
    └─ ⟦this⟧ »FIU_MM_CSAA_TESTS.EM« 
└─⟦b434774df⟧ Bits:30000528 8mm tape, Rational 1000, DFS, D_12_6_5
    └─ ⟦this⟧ »FIU_MM_CSAA_TESTS.EM« 
└─⟦bc1274df5⟧ Bits:30000750 8mm tape, Rational 1000, DFS backup from PAM's R1000
    └─ ⟦this⟧ »FIU_MM_CSAA_TESTS.EM«

TextFile

[write]
[write,Testing,FIU,Board,Tile,7,,-,,Fiu_mm_csa_tests]
[write,,,,,,,,,,,,,,,,,,,,,,,,,,,,&,Fiu_mm_csa2_tests]
[write]
[set experiment_result [xeq fiu test_restore_state_bits]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE restore_state_bits_test]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_restore_state_bits][write]
     [else]
     [PASS_MESSAGE restore_state_bits_test]
[end]
[set experiment_result [xeq fiu test_dummy_next]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE dummy_next_test]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_dummy_next][write]
     [else]
     [PASS_MESSAGE dummy_next_test]
[end]
[set experiment_result [xeq fiu test_restore_rdr]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE restore_rdr_test]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_restore_rdr][write]
     [else]
     [PASS_MESSAGE restore_rdr_test]
[end]
[eq,[var bench_mode],false]
 [xeq seq write_uir 000098390800]
 [xeq seq observe_runtime_state]
[end]
[set experiment_result [xeq fiu test_px_wire]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE px_wire_test]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_px_wire][write]
     [else]
     [PASS_MESSAGE px_wire_test]
[end]
[set experiment_result [xeq fiu test_mem_exception]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE mem_exception_test]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_mem_exception][write]
     [else]
     [PASS_MESSAGE mem_exception_test]
[end]
[eq,[var bench_mode],false]
 [xeq seq write_uir 000098390000]
[end]
[xeq fiu load_pareg 0ff 0]
[xeq fiu load_cond_mem_ucode]
[xeq fiu clear_exceptions]
[xeq fiu step_fiu 0 3 0]
[set experiment_result [xeq fiu read_mdr 0]]
[ne,[and,00f0000000000000,[arg 1,[var experiment_result]]],20000000000000]
     [FAIL_MESSAGE conditional_memory_start_test_1]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE load_pareg 0ff 0]
     [NAME_MESSAGE load_cond_mem_ucode]
     [NAME_MESSAGE clear_exceptions]
     [NAME_MESSAGE step_fiu 0 3 0]
     [NAME_MESSAGE read_mdr 0]
     [write mdr should be : XX2XXXXXXXXXXXXX][write]
     [else]
     [PASS_MESSAGE conditional_memory_start_test_1]
[end]
[xeq fiu clear_exceptions]
[xeq fiu step_fiu 3 3 0]
[set experiment_result [xeq fiu read_mdr 0]]
[ne,[and,00f0000000000000,[arg 1,[var experiment_result]]],0]
     [FAIL_MESSAGE conditional_memory_start_test_2]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE load_pareg 0ff 0]
     [NAME_MESSAGE load_cond_mem_ucode]
     [NAME_MESSAGE clear_exceptions]
     [NAME_MESSAGE step_fiu 3 3 0]
     [NAME_MESSAGE read_mdr 0]
     [write mdr should be : XX0XXXXXXXXXXXXX][write]
     [else]
     [PASS_MESSAGE conditional_memory_start_test_2]
[end]
[xeq fiu clear_exceptions]
[xeq fiu step_fiu 6 3 0]
[set experiment_result [xeq fiu read_mdr 0]]
[ne,[and,00f0000000000000,[arg 1,[var experiment_result]]],40000000000000]
     [FAIL_MESSAGE conditional_memory_start_test_3]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE load_pareg 0ff 0]
     [NAME_MESSAGE load_cond_mem_ucode]
     [NAME_MESSAGE clear_exceptions]
     [NAME_MESSAGE step_fiu 6 3 0]
     [NAME_MESSAGE read_mdr 0]
     [write mdr should be : XX4XXXXXXXXXXXXX][write]
     [else]
     [PASS_MESSAGE conditional_memory_start_test_3]
[end]
[xeq fiu clear_exceptions]
[xeq fiu step_fiu 9 3 0]
[set experiment_result [xeq fiu read_mdr 0]]
[ne,[and,00f0000000000000,[arg 1,[var experiment_result]]],0]
     [FAIL_MESSAGE conditional_memory_start_test_4]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE load_pareg 0ff 0]
     [NAME_MESSAGE load_cond_mem_ucode]
     [NAME_MESSAGE clear_exceptions]
     [NAME_MESSAGE step_fiu 9 3 0]
     [NAME_MESSAGE read_mdr 0]
     [write mdr should be : XX0XXXXXXXXXXXXX][write]
     [else]
     [PASS_MESSAGE conditional_memory_start_test_4]
[end]
[xeq fiu clear_exceptions]
[xeq fiu step_fiu 0c 3 0]
[set experiment_result [xeq fiu read_mdr 0]]
[ne,[and,00f0000000000000,[arg 1,[var experiment_result]]],40000000000000]
     [FAIL_MESSAGE conditional_memory_start_test_5]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE load_pareg 0ff 0]
     [NAME_MESSAGE load_cond_mem_ucode]
     [NAME_MESSAGE clear_exceptions]
     [NAME_MESSAGE step_fiu C 3 0]
     [NAME_MESSAGE read_mdr 0]
     [write mdr should be : XX4XXXXXXXXXXXXX][write]
     [else]
     [PASS_MESSAGE conditional_memory_start_test_5]
[end]
[xeq fiu load_simple_mem_test]
[xeq fiu load_mar_state_bits 7]
[xeq fiu load_dreg 6,6,0]
[xeq fiu load_mar 4,0,1F,0]
[xeq fiu step_fiu 2,4,0]
[set experiment_result [xeq fiu read_inc_mcyc]]
[eq,[arg 1,[var experiment_result]],true]
     [FAIL_MESSAGE incomplete_memory_cycle_test_1]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE load_simple_mem_test]
     [NAME_MESSAGE load_mar_state_bits 7]
     [NAME_MESSAGE load_dreg 6,6,0]
     [NAME_MESSAGE load_mar 4,0,1F,0]
     [NAME_MESSAGE step_fiu 2 4 0]
     [NAME_MESSAGE read_inc_mcyc]
     [write result should be: false][write]
     [else]
     [PASS_MESSAGE incomplete_memory_cycle_test_1]
[end]
[xeq fiu load_mar_state_bits 7]
[xeq fiu load_dreg 6,6,0]
[xeq fiu load_mar 4,0,1F,0]
[xeq fiu step_fiu 3,3,0]
[set experiment_result [xeq fiu read_inc_mcyc]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE incomplete_memory_cycle_test_2]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [write ****** CHECK THAT ECO WIRE FROM F45-10 TO N47-13 IS CORRECT ******]
     [write [ASCII,7]]
     [NAME_MESSAGE load_simple_mem_test]
     [NAME_MESSAGE load_mar_state_bits 7]
     [NAME_MESSAGE load_dreg 6,6,0]
     [NAME_MESSAGE load_mar 4,0,1F,0]
     [NAME_MESSAGE step_fiu 3 3 0]
     [NAME_MESSAGE read_inc_mcyc]
     [write result should be: true][write]
     [else]
     [PASS_MESSAGE incomplete_memory_cycle_test_2]
[end]
[xeq fiu load_mar_state_bits 7]
[xeq fiu load_dreg 6,6,0]
[xeq fiu load_mar 4,0,1E,0]
[xeq fiu step_fiu 3,3,0]
[set experiment_result [xeq fiu read_inc_mcyc]]
[eq,[arg 1,[var experiment_result]],true]
     [FAIL_MESSAGE incomplete_memory_cycle_test_3]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE load_simple_mem_test]
     [NAME_MESSAGE load_mar_state_bits 7]
     [NAME_MESSAGE load_dreg 6,6,0]
     [NAME_MESSAGE load_mar 4,0,1E,0]
     [NAME_MESSAGE step_fiu 3 3 0]
     [NAME_MESSAGE read_inc_mcyc]
     [write result should be: false][write]
     [else]
     [PASS_MESSAGE incomplete_memory_cycle_test_3]
[end]
[xeq fiu load_mar_state_bits 7]
[xeq fiu load_dreg 6,6,0]
[xeq fiu load_mar 4,0,0,0]
[xeq fiu step_fiu 3,3,0]
[set experiment_result [xeq fiu read_inc_mcyc]]
[eq,[arg 1,[var experiment_result]],true]
     [FAIL_MESSAGE incomplete_memory_cycle_test_4]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE load_simple_mem_test]
     [NAME_MESSAGE load_mar_state_bits 7]
     [NAME_MESSAGE load_dreg 6,6,0]
     [NAME_MESSAGE load_mar 4,0,0,0]
     [NAME_MESSAGE step_fiu 3 3 0]
     [NAME_MESSAGE read_inc_mcyc]
     [write result should be: false][write]
     [else]
     [PASS_MESSAGE incomplete_memory_cycle_test_4]
[end]
[xeq fiu load_hram_0];
[xeq fiu load_hram_1];
[set experiment_result [xeq fiu test_hrams]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE hash_RAM_test]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE load_hram_0]
     [NAME_MESSAGE load_hram_1]
     [NAME_MESSAGE test_hrams][write]
     [else]
     [PASS_MESSAGE hash_RAM_test]
[end]
[set experiment_result [xeq fiu test_hash_xors]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE hash_function_xor_circuit_test]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_hash_xors][write]
     [else]
     [PASS_MESSAGE hash_function_xor_circuit_test]
[end]
[set experiment_result [xeq fiu test_name_match_1]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE name_match_test_1]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_name_match_1][write]
     [else]
     [PASS_MESSAGE name_match_test_1]
[end]
[set experiment_result [xeq fiu test_name_match_2]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE name_match_test_2]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_name_match_2][write]
     [else]
     [PASS_MESSAGE name_match_test_2]
[end]
[set experiment_result [xeq fiu test_name_match_3]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE name_match_test_3]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_name_match_3][write]
     [else]
     [PASS_MESSAGE name_match_test_3]
[end]
[set experiment_result [xeq fiu test_in_range]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE in_range_test]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_in_range][write]
     [else]
     [PASS_MESSAGE in_range_test]
[end]
[set experiment_result [xeq fiu test_csa_oor]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE csa_out_of_range_test]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_csa_oor][write]
     [else]
     [PASS_MESSAGE csa_out_of_range_test]
[end]
[set experiment_result [xeq fiu test_hit_offs]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE hit_offset_test]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_hit_offs][write]
     [else]
     [PASS_MESSAGE hit_offset_test]
[end]
[set experiment_result [xeq fiu test_csa_hit]]
[eq,[arg 1,[var experiment_result]],false]
     [FAIL_MESSAGE csa_hit_test]
     [set num_fails [add,[var num_fails],1]]
     [write [ASCII,7]]
     [NAME_MESSAGE test_csa_hit][write]
     [else]
     [PASS_MESSAGE csa_hit_test]
[end]«nul»