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Types: RcTekst
Names: »99110096.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110096.WP«
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆↲
↲
╞ Edition:╞ May 1985↲
╞ Author: Peter Lundbo↲
╞ RCSL No.:╞ 991 10096↲
↲
↲
↲
↲
↲
↲
↲
↲
INTERNAL DOCUMENT↲
↲
↲
↲
↲
↲
↲
↲
Title:↲
↲
┆06┆┆84┆RC3931 ETC 611 hardware selftest↲
user's manual↲
════════════════════════════════════════════════════════════════════════
↓
KEYWORDS:↲
╞ ╞ ┆84┆RC 39, XENIX, Remote/Local Communication, TELETEX, ↓
┆19┆┆89┆┄┄Ethernet, LAN, Hardware Selftest, ETC 611.↲
↲
↲
↲
↲
↲
↲
↲
ABSTRACT:↲
╞ ╞ ┆84┆This manual documents the ETC611 SBC selftest ↓
┆19┆┆89┆┄┄program which contain several programs for ↓
┆19┆┆89┆┄┄verifying hardware components of the Intelligent ↓
┆19┆┆89┆┄┄Ethernet Controller. The ETC611 is an INTEL ↓
┆19┆┆89┆┄┄Multibus compatible slave controller, based upon a ↓
┆19┆┆89┆┄┄16 bit iAPX 186 microprocessor.↲
════════════════════════════════════════════════════════════════════════
↓
╞ ╞ ╞ ╞ ╞ ╞ i↲
┆a1┆CONTENT PAGE ↲
↲
1. INTRODUCTION ..................................... 1↲
↲
2. THE DUAL CHANNEL COMMUNICATION APPROACH .......... 2↲
↲
3. THE BAUD RATE DETERMINATION MODE ................. 3↲
↲
4. DEFAULT INTERRUPT HANDLING ....................... 4↲
4.1 Instruction Exception ........................ 4↲
4.2 Illegal Interrupt ............................ 4↲
↲
5. ┆b0┆┆f0┆SELFTEST SWITCH SETTINGS ......................... 7↲
↲
6. INITIALIZATION .................................. 8↲
6.1 Wait States ................................. 8↲
6.2 iAPX186 Interrupt Controller ................ 8↲
6.3 Programmable Interrupt Controller 8259 ......╞ 9↲
6.4 iAPX186 Timer 1 ............................. 9↲
6.5 MPSC 8274 Ch. B (Console Interface) ......... 10↲
↲
7. TEST 0 = MEMORY TEST ............ ............... 11↲
7.1 PROM Checksum Test .......................... 11↲
7.2 RAM Memory Test ............................. 12↲
7.2.1 Memory Test Pattern ................... 12↲
7.2.2 Memory Test Flow ...................... 13↲
7.2.3 Loop On Error ......................... 13↲
↲
8. TEST 1 = Chip Select Test ....................... 14↲
↲
┆8c┆┆82┆┆f4┆↓
9. TEST 2 = iAPX 186 Timer Test .................... 15↲
↲
10. TEST 3 = iAPX 186 DMA Test ...................... 16↲
↲
11. TEST 4 = RAM Refresh Test ....................... 17↲
↲
12. TEST 5 = Ethernet Test 2 ........................ 18↲
↲
↲
┆a1┆APPENDICES↲
↲
A. REFERENCES ....................................... 20↲
↲
B. Complete Error List .............................. 21↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆╞ ╞ ╞ ┆0b┆┆a1┆↲
┆a1┆┆a1┆┆b0┆1. Introduction.↲
↲
The ETC 611 is an Intelligent Communication Controller, which ↓
offers Local Area Network service (LAN), TELETEX network service ↓
and (together with COM 601) IBM host service to the RC 39 ↓
product.↲
↲
This manual assume that the reader is familiar with the RC 39 ↓
selftest concept as described in the manual called "The RC 39 ↓
Selftest Concept". The ETC 611 selftest includes 6 different ↓
tests which may be run in several modes. Five of these tests are ↓
┆b0┆default┆f0┆ tests which allways execute after a power on. The last ↓
┆19┆┄┆81┆┄test is a┆b0┆┆f0┆n ┆b0┆extended┆b0┆┆f0┆ test which is run only when requested ↓
┆19┆┄┆84┆┄explicit by an operator. This version of the ETC 611 includes no ↓
┆19┆┄┆84┆┄┆b0┆seperately┆f0┆ run ┆f0┆tests.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆┆b0┆2. The Dual Channel Communication Approach.↲
↲
The ETC 611 SBC selftest supports the Dual Channel Communication ↓
facility as described in the "RC 39 Selftest Concept". If the ↓
strap ST7-23 is inserted the communication goes via the on-board ↓
8274 USART line 0, otherwise if the strap is omitted the ↓
communication goes transparently through the Multibus interface ↓
to a console connected to the "test-master" usually a CPU 691 or ↓
a CPU 610 board.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆3. The Baud Rate ┆a1┆Determination Mode.↲
↲
If the starp ST7-23 is inserted and a terminal is connected to the ↓
V.24 line 0 interface (DSR activ) then the selftest enters the ↓
automatic Baud Rate Determination mode. The USART is initialized ↓
to 9600 Baud and stars (*****) are written to line 0. These stars ↓
may be seen as stars, other mixed characters or not seen at all ↓
depending on the Baud Rate of the attached console. The selftest ↓
waits for the operator to enter one or two upper case U. One ↓
upper case U is enough if the Baud Rate is 9600, 4800 or 2400 ↓
Baud. Baud Rates of 1200, 600 or 300 requires two upper case U.↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆┆b0┆4┆b0┆┆a1┆┆f0┆┆f0┆┆b0┆. Default Interrupt Handling.↲
↲
When the ETC 611 SBC Selftest has finished the memory test, a set ↓
of default interrupt vectors are placed in the interrupt vector ↓
table. These vectors are primarily used to handle unexpected ↓
interrupts. There are two kinds of unexpected interrupts. The ↓
first is handled by the interrupt procedure for internal iAPX186 ↓
instruction interrupts and the second is handled by the interrupt ↓
procedure for illegal device interrupts.↲
↲
↲
┆b0┆┆a1┆4.1 Instruction Exception.↲
↲
If an Instruction Exception interrupt occurs, it is likely to ↓
believe that this was caused by a malfunction of the iAPX186, ↓
because this interrupt is related to some CPU instructions.↲
↲
if this error should occur it ↲
┆b0┆╞ ╞ ">> instruction exception"↲
↲
The corresponding error number is 8.↲
↲
↲
┆b0┆┆a1┆┆f0┆┆b0┆4.2 Illegal Interrupt.↲
↲
At the end of every test loop the reception of interrupts are ↓
enabled. Only two of the interrupt request lines will be used in ↓
the Selftest. This is the MPSC 8274 receive interrupt which is ↓
connected to the 80186 interrupt request INT1 and the parity ↓
interrupt which is connected to the 8259 interrupt request IR3.↲
↲
All other interrupt requests will be decoded as illegal ↓
interrupts and will produce the following errortext:↲
↲
┆8c┆┆83┆┆98┆↓
┆b0┆╞ ╞ "illegal interrupt"↲
↲
followed by the information about, which level was issuing the ↓
interrupt.↲
↲
The corresponding error number is 5.↲
↲
In the PIC interrupt test and the Multibus interrupt test an ↓
"illegal interrupt" error is produced if it is impossible to ↓
clear the interrupt following the test. This may happen if a ↓
jumper in the interrupt strap area S6 is missing.↲
┆8c┆┆81┆┆84┆↓
┆0e┆↓
↲
┆a1┆Interrupt name Vector type Related instructions┆05┆↲
Divide Error 0 DIV, IDIV↲
Single step 1 ALL↲
NMI 2 ALL↲
Breakpoint 3 INT↲
INT0 Detected 4 INT0↲
overflow↲
Array Bounds 5 BOUND↲
Unused Opcode 6 Undefined Opcodes↲
┆a1┆ESC Opcode 7 ESC Opcodes┆05┆↲
┆a1┆Interrupt name Vector type Related interrupt level┆05┆↲
Timer 0 Interrupt 8 8↲
Reserved 9 -↲
DMA 0 Interrupt 10 10↲
DMA 1 Interrupt 11 11↲
INT0 Interrupt 12* 12↲
INT1 Interrupt 13** 13↲
INT2 Interrupt 14* 14↲
INT3 Interrupt 15** 15↲
Timer 1 Interrupt 18 8↲
┆a1┆Timer 2 Interrupt 19 8┆05┆↲
8259 IR0 20 20↲
8259 IR1 21 21↲
8259 IR2 22 22↲
Par-int 23 23↲
8259 IR4 24 24↲
8259 IR5 25 25↲
8259 IR6 26 26↲
8259 IR7 27 27↲
↲
Figure 5: Interrupt Level Table.↲
↲
* INT0 and INT2 are used as INT0 and INTA0 for the 8259.↲
** INT1 and INT3 are used as INT1 and INTA2 for the 8274 MPSC.↲
┆0f┆↓
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆b0┆┆a1┆5┆a1┆. Selftest Switch Settings.↲
↲
The ETC611 is equipped with a Selftest configuration switch ↓
(S23), which is connected to the 8255, PA port.↲
↲
PA, bit 0-1 : ┆84┆These bits are used by the memory test to determine ↓
┆19┆┆8e┆┄┄the onboard memory size.↲
↲
PA, bit 2 : ┆84┆this bit is used to control the "test-output".↲
↲
PA, bit 3 : ┆84┆not used↲
↲
PA, bit 4 : ┆84┆this bit, if "1" makes the testprogram to assume an ↓
┆19┆┆8e┆┄┄8 MHz CPU installed. This information is used to ↓
┆19┆┆8e┆┄┄control the on-chip timer used as baudrate ↓
┆19┆┆8e┆┄┄generator.↲
↲
╞ ╞ ╞ ╞ 00 : 512 Kbytes RAM↲
. . . . .╞ ╞ ╞ 01 : 1 Mbytes RAM and 0 COM 601↲
1┆b0┆.┆f0┆ . . . .╞ ╞ ╞ 10 : 1 Mbytes RAM and 1 COM 601↲
! ! ! ┆a1┆! ! 11 : 1 Mbytes RAM and 2 COM 601↲
! ! !↲
! ! !╞ ╞ ╞ 0 : on board "test-output"↲
! ! !┆a2┆┆a1┆┆e2┆ ╞ ╞ ╞ 1 : "test-output" via MB ↲
! !↲
! !╞ ╞ ╞ 0 : not used↲
! !┆a1┆╞ ╞ ╞ 1 : ↲
!↲
!╞ ╞ ╞ 0 : 6 MHz iAPX186 ↲
!┆a1┆ ╞ ╞ ╞ 1 : 8 MHz iAPX186 ↲
↲
┆a1┆┆e1┆┆e1┆┆e1┆↲
┆a1┆Figure 8 : The S23 jumper area.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6. Initialization.↲
↲
After power up/reset the ETC611 SBC Selftest will perform some ↓
initializations of the onboard controllers.↲
↲
The initializations are common for the Selftest and the ↓
bootloader.↲
↲
↲
┆b0┆┆a1┆┆f0┆┆b0┆6.1 Wait States.↲
↲
The PROM and RAM memory will have 0 wait states.↲
↲
Pheripherals on PCS 0-3 will have 1 wait state↲
Pheripherals on PCS 4-6 will have 2 wait states.↲
↲
↲
┆b0┆┆a1┆┆f0┆┆b0┆6.2 iAPX186 Interrupt Controller.↲
↲
The interrupt vector for the iAPX186 controllers is tied to ↓
specific memory locations, equal to the location 20H for the ↓
first vector in the table. See section 2.5.↲
↲
╞ ┆1f┆┆a1┆INT0/INT2:↲
Port : FF38H↲
Value : 37H↲
↲
These two pins of the iAPX186 is used for cascading to the extern ↓
interrupt controller 8259.↲
↲
╞ ┆a1┆INT1/INT3:↲
Port : FF3AH↲
Value : 37H↲
↲
┆8c┆┆83┆┆98┆↓
These two pins of the iAPX80186 is used for cascading to the MPSC ↓
8274.↲
↲
╞ ┆a1┆Mask Register:↲
Port : FF28H↲
Value : FDH↲
↲
Which will mask the following:↲
↲
╞ I3 : 1╞ ; INT3↲
╞ I2 : 1╞ ; INT2↲
╞ I1 : 1╞ ; INT1↲
╞ I0 : 0╞ ; INT0↲
╞ D1 : 1╞ ; DMA1↲
╞ D0 : 1╞ ; DMA0↲
╞ TRM : 1╞ ; Timers↲
↲
↲
┆b0┆┆a1┆┆f0┆┆b0┆6.3 Programable Interrupt Controller 8259.↲
↲
The ETC601 SBC Selftest is configurated with USART parity ↓
interrupt connected to IR3.↲
↲
╞ ┆a1┆8259 setup:↲
ICW 1 : 1BH ; level triggered input, single mode↲
ICW 2 : 20H ; the interrupt vector table starts in 80H↲
ICW 4 : 1DH ┆84┆; non buffer mode, normal EOI and not fully ↓
┆19┆┆95┆┄┄; nested.↲
MASK : F7H ; enable parity interrupt on IR3.↲
↲
↲
┆b0┆┆a1┆┆f0┆┆b0┆6.4 iAPX186 Timer 1.↲
↲
Timer 1 is initialized as a baudrate generator in alternating ↓
mode with even duty cycle. If no console is connected the ↓
baudrate is set to 9600 baud, otherwise the Baud Rate ↓
Determination procedure is entered see chapter 6.↲
↲
↲
┆8c┆┆83┆┆d4┆↓
┆b0┆┆a1┆┆f0┆┆b0┆6.5 MPSC 8274 Ch. B (Console Interface).↲
↲
Baudrate factor : X16↲
Character length : 8 bits↲
Parity : none↲
Stop bits : 2↲
Mode : asynchronous.↲
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆7. ┆b0┆Test 0 = ┆f0┆MEMORY TEST.↲
↲
The memory test of the ETC 611 SBC selftest consists of two ↓
parts, a PROM checksum test and a RAM memory test. The PROM ↓
checksum test is only run once after power up or external reset, ↓
whereas the RAM memory test may be run several times, if ↓
requested by the operator.↲
↲
↲
┆a1┆┆b0┆7.1 PROM Checksum Test.↲
↲
The contents of both the odd and the even PROM are summarized ↓
bytewise and the result must be a zero. For that reason the ↓
PROM's contain a compensation byte which is used to bring the sum ↓
to zero.↲
┆a1┆↲
┆b0┆┆f0┆1. ┆b0┆checksum test: sum error exp.:<0000> rec.:<xyzw>↲
↲
Checksum error usually means that the content of the PROM has ↓
been damaged and that the PROM must be changed.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆7.2 RAM Memory Test.↲
↲
The RAM memory test of the ETC 611 SBC selftest verifies the on-↓
board memory. The size of RAM is determined from reading the on ↓
board straps on the 8255 parallel port A. Valid memory sizes are ↓
1 M Bytes or 512 Kbytes. If 1 M bytes are present some of the RAM ↓
cannot be used by the ETC 611 itself. The upper 64 Kbytes are ↓
reserved to onboard PROM space and is useless. If one COM 601 is ↓
present the upper 128 Kbytes are occupied, and if two COM 601 are ↓
present then the upper 256 Kbytes are shadowed. NOTE that the ↓
shadowed RAM is available to other Multibus Masters ?↲
↲
The memory test is a register based test and uses no memory space ↓
at all, neither for variables nor stack. The test verifies every ↓
single byte of the on-board memory.↲
↲
This fact lets only one register for test variables survive the ↓
memory test. That variable contains all the test switches and the ↓
test number. ↲
↲
↲
┆a1┆┆b0┆7.2.1 Memory Test Pattern.↲
↲
The memory test executes 4 passes trough the entire memory, two ↓
times writing and two times reading.↲
↲
The test pattern is the convenient modulus 3 pattern consisting ↓
of three times 0000 followed by three times FFFF (hexadecimal).↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆7.2.2 Memory Test Flow.↲
↲
The test starts in the highest RAM addresses and inserts the ↓
pattern towards lower addresses.↲
↲
When all memory words have been written and verified, they are ↓
tested again with the inversed pattern, this means, that all bits ↓
are tested for "zero" and "one" insertion. If an error occur then ↓
an attempt to send the following message, to the "test-output", ↓
is made :↲
↲
┆a1┆┆b0┆┆f0┆2. ┆b0┆RAM test: RAM error segm.:<ssss> addr.:<aaaa> exp.:<eeee>↲
╞ ╞ ╞ ╞ ┆b0┆ rec.:<rrrr>↲
↲
The secondary text is interpreted like this :↲
↲
<ssss> is the segment address↲
<aaaa> is the address offset↲
<eeee> is the expected pattern, should allways be 0000 or FFFF.↲
<rrrr> is the received pattern.↲
↲
The above mentioned information may be used to find a defective ↓
RAM memory chip from the knowledge of the RAM-layout.↲
↲
↲
┆a1┆┆b0┆7.2.3 Loop On Error.↲
↲
When a fault occur during the ram test an error message is ↓
written to the console, and the RAM test starts from the start ↓
again. This will be the case until no error is discovered. If ↓
there is a RAM error and if an L is typed from the keyboard, then ↓
the RAM test will not start from the beginning again, but proceed ↓
trough the RAM test and write all RAM errors to the console, and ↓
finally enter the "test-administrator" to execute other tests.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆8. ┆b0┆Test 1 = ┆f0┆Chip Select Test.↲
↲
To ease complex debugging, a simple chip select loop, combined ↓
with a RAM write/read, is supplied. ↲
↲
This test generates chip selects to all peripheral devices by ↓
executing input instructions to all relevant I/O-devices. These ↓
are :↲
↲
Port ┆84┆0, 2, 128, 130, 256, 258, 260, 262, 384, 386, 388, 390, 392, ↓
┆19┆┆85┆┄┄394, 396, 398, 512, 514, 516, 518, 640, 642, 644, 646, 648, ↓
┆19┆┆85┆┄┄650, 652, 654.↲
↲
When all the chip selects are made, a pattern AA55 hex. is ↓
written to a RAM cell and immediately read back.↲
↲
This test is unable to generate any error messages. It is meant ↓
only as a special fast scope loop test.↲
════════════════════════════════════════════════════════════════════════
↓
┆a2┆┆e2┆┆a1┆┆b0┆9. ┆b0┆TEST 2┆f0┆ = iAPX 186 Timer Test.↲
↲
This test verifies the ability of the iAPX 186 internal timer 0 ↓
to generate interrupts. The internal timer 0 is initialized as a ↓
real time clock which generates interrupt every 20 millisecond. ↓
If no timer interrupt is generated then an error message is ↓
generated like this.↲
↲
┆a1┆┆a1┆┆a1┆┆e1┆┆b0┆┆f0┆1. ┆b0┆iAPX186 timer test : missing timer 0 interrupt↲
↲
This error should indicate a malfunction of the iAPX 186 ↓
processor chip.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆10. ┆b0┆TEST 3┆f0┆ = iAPX 186 DMA Test.↲
↲
This test verifies the ability of the two iAPX 186 internal DMA ↓
channels to make a data transport and to generate interrupts. The ↓
two iAPX 186 DMA channels are initialized to perform a DMA memory ↓
to memory transport simultaneously. DMA channel 0 copies 8 Kbytes ↓
from a source to a destination buffer in the forward direction, ↓
and DMA channel 1 copies from the same source to another ↓
destination buffer in the reverse direction. All DMA transfers ↓
are syncronized to the internal timer 2 which generates a 250 KHz ↓
clock. The two channels are initialized to the same priority. ↓
This ensures together with the selected internal timer 2 ↓
syncronization that both DMA channels runs simultaneously and ↓
that the CPU may also get memory access. When the DMA transport ↓
is complete both destination buffers are compared to the source ↓
buffer.↲
↲
The test produces the following error messages:↲
↲
┆b0┆┆f0┆1. ┆b0┆DMA test: data error segm.: <ssss> addr.:<aaaa> rec.:<rrrr>↲
╞ ╞ ╞ ╞ ╞ ┆b0┆exp.:<eeee>↲
↲
┆b0┆┆f0┆2. ┆b0┆DMA test: transfer timeout↲
↲
The first error indictes that both DMA transports has terminated ↓
but the destination buffer is not equal to the source as ↓
expected. The latter indicates that one of the two or both DMA ↓
interrupts is missing.↲
↲
Both errors should indicate a malfunction of the iAPX 186 ↓
processor chip.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆f0┆┆a1┆┆b0┆1┆a1┆1. ┆b0┆Test 4┆f0┆ = RAM Refresh Test.↲
↲
The RAM refresh test of the ETC611 SBC Selftest assist in the ↓
verification of the memory control logic functionality. The main ↓
purpose is to discover the decay of data caused by a malfunction ↓
of the RAM refresh circuitry.↲
↲
The test pattern written is a counting pattern and the size of ↓
the test buffer is 4 K, 16 bit words.↲
↲
When the pattern has been written the test program enters a ↓
waiting loop for approximate 5 sec., in which the CPU will not ↓
access the RAM memory. After the delay, the buffer will be ↓
checked to discover any decay.↲
↲
If decay is found, a message is written like this:↲
↲
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
┆b0┆RAM refresh test: error, addr.: <aaaa>, exp.: <eeee>, rec.: <rrrr>↲
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
↲
Where↲
╞ <aaaa> ┆84┆is the offset address relative to the start of the ↓
┆19┆┆8b┆┄┄test buffer.↲
<eeee> is the pattern written in this word.↲
╞ <rrrr> is the pattern read from this word.↲
↲
The corresponding error number is 9.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆a1┆12. Test 5 ┆f0┆= Ethernet Test 2.↲
↲
The ethernet test 2 applies to the verification of the 82586 co-↓
processor and its interface circuitry. The test makes an external ↓
data loopback test on the ethernet chip.↲
↲
First a software reset of the ethernet chip is made. This reset ↓
causes the ethernet controller to issue an interrupt when the ↓
reset is complete. If no interrupt is received an error message ↓
is generated like this:↲
↲
┆b0┆Ethernet test 2 : missing reset interrupt↲
↲
Corresponding error number is 61.↲
↲
Second a configure command is executed to the ethernet controller ↓
in order to select the external loopback mode. Again the sleftest ↓
awaits a configure complete interrupt, and if none is received an ↓
error message is generated like this:↲
↲
┆b0┆Ethernet test 2 : configuration command not accepted↲
↲
Corresponding error number is 58.↲
↲
Third a transmit frame command is executed. The ethernet address ↓
is the broadcast address an the message length is 14 bytes. If↓
the transmit frame command is not accepted by the ethernet ↓
controller an error message is generated like this:↲
↲
┆b0┆Ethernet test 2 : transmit command not accepted↲
↲
corresponding error number is 59.↲
↲
Fourth, when the transmit frame command is completed the data ↓
sent is copared with the data received and if not the same an ↓
error message is generated otherwise the ethernet interface is ↓
said to be OK.↲
↲
┆8c┆┆83┆┆c8┆↓
┆b0┆Ethernet test 2 : data error add.:<aaaa>, exp.:<eeee>,↲
┆b0┆╞ ╞ ╞ ╞ rec.:<rrrr>↲
┆81┆↲
Corresponding error number is 60.↲
↲
where↲
add.:<aaaa> is offset address in the receive buffer↲
exp.:<eeee> is the expected value from the transmit buffer↲
rec.:<rrrr> is the received value in the receive buffer↲
↲
Another error message is written if the ethernet controller ↓
generates an interrupt without having reset the command just ↓
executed.↲
↲
┆b0┆Ethernet test 2 : interrupt but command word not cleared↲
↲
Corresponding error number is 48.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆A. REFERENCES┆b0┆↲
↲
(1) RCSL. 991 10092↲
RC 39 Selftest Concept, ↲
User's manual ╞ ↲
↲
(2) RCSL. 991 10095↲
ITC 602 hardware selftest, ↲
User's manual ╞ ↲
↲
(3) RCSL. 991 10097↲
F641 COM 601 hardware selftest, ↲
User's manual ↲
↲
(4) RCSL. 991 10094↲
RC3902 hardware selftest, ↲
User's manual╞ ↲
↲
(5) RCSL. 991 10134↲
RC39 monitor 8086 version, ↲
Reference manual╞ ↲
↲
(6) RCSL. 991 10093↲
RC39 monitor 80286 version, ↲
Reference manual ↲
↲
↓
↓
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0c000600000000020150310000000000000000000000000000000000000000000000000008101820283038404a4b555f69737dff04╱
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆a1┆┆b0┆B. ┆a1┆Complete Error List.↲
↲
!-----------------------------------------------------------------------------!↲
! Err. No !╞ ╞ ╞ ╞ Error Text ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
! 0 ! OK╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 1 ! Checksum Test: sum error ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 2╞ ! RAM Test: RAM error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 3 ! iAPX186 DMA Test: data error╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 4 ! iAPX186 DMA Test: timeout╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 9 ! RAM refresh Test: error╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 10 ! iAPX186 Timer Test: missing timer 0 interrupt╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 48 ! Ethernet test 2: interrupt but command word not cleared╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 60 ! Ethernet test 2: data error ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 61 ! Ethernet test 2: missing reset interrupt╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------;↲
! 62 ! Ethernet test 2: configuration command not accepted╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 63 ! Ethernet test 2: configuration command not accepted╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 64 ! Ethernet test 2: transmit command not accepted !↲
!-----------------------------------------------------------------------------!↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆1a┆┆1a┆ror List.↲
↲
!----------------------------------------------------------------