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Types: RcTekst
Names: »99110096.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110096.WP«
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆↲
↲
╞ Edition:╞ May 1985↲
╞ Author: Peter Lundbo↲
╞ RCSL No.:╞ 991 10096↲
↲
↲
↲
↲
↲
↲
↲
↲
INTERNAL DOCUMENT↲
↲
↲
↲
↲
↲
↲
↲
Title:↲
↲
┆06┆┆84┆RC3931 ETC 611 hardware selftest↲
user's manual↲
════════════════════════════════════════════════════════════════════════
↓
KEYWORDS:↲
╞ ╞ ┆84┆RC 39, XENIX, Remote/Local Communication, TELETEX, ↓
┆19┆┆89┆┄┄Ethernet, LAN, Hardware Selftest, ETC 611.↲
↲
↲
↲
↲
↲
↲
↲
ABSTRACT:↲
╞ ╞ ┆84┆This manual documents the ETC611 SBC selftest ↓
┆19┆┆89┆┄┄program which contain several programs for ↓
┆19┆┆89┆┄┄verifying hardware components of the Intelligent ↓
┆19┆┆89┆┄┄Ethernet Controller. The ETC611 is an INTEL ↓
┆19┆┆89┆┄┄Multibus compatible slave controller, based upon a ↓
┆19┆┆89┆┄┄16 bit iAPX 186 microprocessor.↲
════════════════════════════════════════════════════════════════════════
↓
╞ ╞ ╞ ╞ ╞ ╞ i↲
┆a1┆CONTENT PAGE ↲
↲
1. INTRODUCTION ..................................... 1↲
↲
2. THE DUAL CHANNEL COMMUNICATION APPROACH .......... 2↲
↲
3. THE BAUD RATE DETERMINATION MODE ................. 3↲
↲
4. DEFAULT INTERRUPT HANDLING ....................... 4↲
4.1 Instruction Exception ........................ 4↲
4.2 Illegal Interrupt ............................ 4↲
↲
5. ┆b0┆┆f0┆SELFTEST SWITCH SETTINGS ......................... 7↲
↲
6. INITIALIZATION .................................. 8↲
6.1 Wait States ................................. 8↲
6.2 iAPX186 Interrupt Controller ................ 8↲
6.3 Programmable Interrupt Controller 8259 ......╞ 9↲
6.4 iAPX186 Timer 1 ............................. 9↲
6.5 MPSC 8274 Ch. B (Console Interface) ......... 10↲
↲
7. TEST 0 = MEMORY TEST ............ ............... 11↲
7.1 PROM Checksum Test .......................... 11↲
7.2 RAM Memory Test ............................. 12↲
7.2.1 Memory Test Pattern ................... 12↲
7.2.2 Memory Test Flow ...................... 13↲
7.2.3 Loop On Error ......................... 13↲
↲
8. TEST 1 = Chip Select Test ....................... 14↲
↲
┆8c┆┆82┆┆f4┆↓
9. TEST 2 = iAPX 186 Timer Test .................... 15↲
↲
10. TEST 3 = iAPX 186 DMA Test ...................... 16↲
↲
11. TEST 4 = RAM Refresh Test ....................... 17↲
↲
12. TEST 5 = Ethernet Test 2 ........................ 18↲
↲
↲
┆a1┆APPENDICES↲
↲
A. REFERENCES ....................................... 20↲
↲
B. Complete Error List .............................. 21↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆╞ ╞ ╞ ┆0b┆┆a1┆↲
┆a1┆┆a1┆┆b0┆1. Introduction.↲
↲
The ETC 611 is an Intelligent Communication Controller, which ↓
offers Local Area Network service (LAN), TELETEX network service ↓
and (together with COM 601) IBM host service to the RC 39 ↓
product.↲
↲
This manual assume that the reader is familiar with the RC 39 ↓
selftest concept as described in the manual called "The RC 39 ↓
Selftest Concept". The ETC 611 selftest includes 6 different ↓
tests which may be run in several modes. Five of these tests are ↓
┆b0┆default┆f0┆ tests which allways execute after a power on. The last ↓
┆19┆┄┆81┆┄test is a┆b0┆┆f0┆n ┆b0┆extended┆b0┆┆f0┆ test which is run only when requested ↓
┆19┆┄┆84┆┄explicit by an operator. This version of the ETC 611 includes no ↓
┆19┆┄┆84┆┄┆b0┆seperately┆f0┆ run ┆f0┆tests.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆┆b0┆2. The Dual Channel Communication Approach.↲
↲
The ETC 611 SBC selftest supports the Dual Channel Communication ↓
facility as described in the "RC 39 Selftest Concept". If the ↓
strap ST7-23 is inserted the communication goes via the on-board ↓
8274 USART line 0, otherwise if the strap is omitted the ↓
communication goes transparently through the Multibus interface ↓
to a console connected to the "test-master" usually a CPU 691 or ↓
a CPU 610 board.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆3. The Baud Rate ┆a1┆Determination Mode.↲
↲
If the starp ST7-23 is inserted and a terminal is connected to the ↓
V.24 line 0 interface (DSR activ) then the selftest enters the ↓
automatic Baud Rate Determination mode. The USART is initialized ↓
to 9600 Baud and stars (*****) are written to line 0. These stars ↓
may be seen as stars, other mixed characters or not seen at all ↓
depending on the Baud Rate of the attached console. The selftest ↓
waits for the operator to enter one or two upper case U. One ↓
upper case U is enough if the Baud Rate is 9600, 4800 or 2400 ↓
Baud. Baud Rates of 1200, 600 or 300 requires two upper case U.↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆┆b0┆4┆b0┆┆a1┆┆f0┆┆f0┆┆b0┆. Default Interrupt Handling.↲
↲
When the ETC 611 SBC Selftest has finished the memory test, a set ↓
of default interrupt vectors are placed in the interrupt vector ↓
table. These vectors are primarily used to handle unexpected ↓
interrupts. There are two kinds of unexpected interrupts. The ↓
first is handled by the interrupt procedure for internal iAPX186 ↓
instruction interrupts and the second is handled by the interrupt ↓
procedure for illegal device interrupts.↲
↲
↲
┆b0┆┆a1┆4.1 Instruction Exception.↲
↲
If an Instruction Exception interrupt occurs, it is likely to ↓
believe that this was caused by a malfunction of the iAPX186, ↓
because this interrupt is related to some CPU instructions.↲
↲
if this error should occur it ↲
┆b0┆╞ ╞ ">> instruction exception"↲
↲
The corresponding error number is 8.↲
↲
↲
┆b0┆┆a1┆┆f0┆┆b0┆4.2 Illegal Interrupt.↲
↲
At the end of every test loop the reception of interrupts are ↓
enabled. Only two of the interrupt request lines will be used in ↓
the Selftest. This is the MPSC 8274 receive interrupt which is ↓
connected to the 80186 interrupt request INT1 and the parity ↓
interrupt which is connected to the 8259 interrupt request IR3.↲
↲
All other interrupt requests will be decoded as illegal ↓
interrupts and will produce the following errortext:↲
↲
┆8c┆┆83┆┆98┆↓
┆b0┆╞ ╞ "illegal interrupt"↲
↲
followed by the information about, which level was issuing the ↓
interrupt.↲
↲
The corresponding error number is 5.↲
↲
In the PIC interrupt test and the Multibus interrupt test an ↓
"illegal interrupt" error is produced if it is impossible to ↓
clear the interrupt following the test. This may happen if a ↓
jumper in the interrupt strap area S6 is missing.↲
┆8c┆┆81┆┆84┆↓
┆0e┆↓
↲
┆a1┆Interrupt name Vector type Related instructions┆05┆↲
Divide Error 0 DIV, IDIV↲
Single step 1 ALL↲
NMI 2 ALL↲
Breakpoint 3 INT↲
INT0 Detected 4 INT0↲
overflow↲
Array Bounds 5 BOUND↲
Unused Opcode 6 Undefined Opcodes↲
┆a1┆ESC Opcode 7 ESC Opcodes┆05┆↲
┆a1┆Interrupt name Vector type Related interrupt level┆05┆↲
Timer 0 Interrupt 8 8↲
Reserved 9 -↲
DMA 0 Interrupt 10 10↲
DMA 1 Interrupt 11 11↲
INT0 Interrupt 12* 12↲
INT1 Interrupt 13** 13↲
INT2 Interrupt 14* 14↲
INT3 Interrupt 15** 15↲
Timer 1 Interrupt 18 8↲
┆a1┆Timer 2 Interrupt 19 8┆05┆↲
8259 IR0 20 20↲
8259 IR1 21 21↲
8259 IR2 22 22↲
Par-int 23 23↲
8259 IR4 24 24↲
8259 IR5 25 25↲
8259 IR6 26 26↲
8259 IR7 27 27↲
↲
Figure 5: Interrupt Level Table.↲
↲
* INT0 and INT2 are used as INT0 and INTA0 for the 8259.↲
** INT1 and INT3 are used as INT1 and INTA2 for the 8274 MPSC.↲
┆0f┆↓
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆b0┆┆a1┆5┆a1┆. Selftest Switch Settings.↲
↲
The ETC611 is equipped with a Selftest configuration switch ↓
(S23), which is connected to the 8255, PA port.↲
↲
PA, bit 0-1 : ┆84┆These bits are used by the memory test to determine ↓
┆19┆┆8e┆┄┄the onboard memory size.↲
↲
PA, bit 2 : ┆84┆this bit is used to control the "test-output".↲
↲
PA, bit 3 : ┆84┆not used↲
↲
PA, bit 4 : ┆84┆this bit, if "1" makes the testprogram to assume an ↓
┆19┆┆8e┆┄┄8 MHz CPU installed. This information is used to ↓
┆19┆┆8e┆┄┄control the on-chip timer used as baudrate ↓
┆19┆┆8e┆┄┄generator.↲
↲
╞ ╞ ╞ ╞ 00 : 512 Kbytes RAM↲
. . . . .╞ ╞ ╞ 01 : 1 Mbytes RAM and 0 COM 601↲
1┆b0┆.┆f0┆ . . . .╞ ╞ ╞ 10 : 1 Mbytes RAM and 1 COM 601↲
! ! ! ┆a1┆! ! 11 : 1 Mbytes RAM and 2 COM 601↲
! ! !↲
! ! !╞ ╞ ╞ 0 : on board "test-output"↲
! ! !┆a2┆┆a1┆┆e2┆ ╞ ╞ ╞ 1 : "test-output" via MB ↲
! !↲
! !╞ ╞ ╞ 0 : not used↲
! !┆a1┆╞ ╞ ╞ 1 : ↲
!↲
!╞ ╞ ╞ 0 : 6 MHz iAPX186 ↲
!┆a1┆ ╞ ╞ ╞ 1 : 8 MHz iAPX186 ↲
↲
┆a1┆┆e1┆┆e1┆┆e1┆↲
┆a1┆Figure 8 : The S23 jumper area.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6. Initialization.↲
↲
After power up/reset the ETC611 SBC Selftest will perform some ↓
initializations of the onboard controllers.↲
↲
The initializations are common for the Selftest and the ↓
bootloader.↲
↲
↲
┆b0┆┆a1┆┆f0┆┆b0┆6.1 Wait States.↲
↲
The PROM and RAM memory will have 0 wait states.↲
↲
Pheripherals on PCS 0-3 will have 1 wait state↲
Pheripherals on PCS 4-6 will have 2 wait states.↲
↲
↲
┆b0┆┆a1┆┆f0┆┆b0┆6.2 iAPX186 Interrupt Controller.↲
↲
The interrupt vector for the iAPX186 controllers is tied to ↓
specific memory locations, equal to the location 20H for the ↓
first vector in the table. See section 2.5.↲
↲
╞ ┆1f┆┆a1┆INT0/INT2:↲
Port : FF38H↲
Value : 37H↲
↲
These two pins of the iAPX186 is used for cascading to the extern ↓
interrupt controller 8259.↲
↲
╞ ┆a1┆INT1/INT3:↲
Port : FF3AH↲
Value : 37H↲
↲
┆8c┆┆83┆┆98┆↓
These two pins of the iAPX80186 is used for cascading to the MPSC ↓
8274.↲
↲
╞ ┆a1┆Mask Register:↲
Port : FF28H↲
Value : FDH↲
↲
Which will mask the following:↲
↲
╞ I3 : 1╞ ; INT3↲
╞ I2 : 1╞ ; INT2↲
╞ I1 : 1╞ ; INT1↲
╞ I0 : 0╞ ; INT0↲
╞ D1 : 1╞ ; DMA1↲
╞ D0 : 1╞ ; DMA0↲
╞ TRM : 1╞ ; Timers↲
↲
↲
┆b0┆┆a1┆┆f0┆┆b0┆6.3 Programable Interrupt Controller 8259.↲
↲
The ETC601 SBC Selftest is configurated with USART parity ↓
interrupt connected to IR3.↲
↲
╞ ┆a1┆8259 setup:↲
ICW 1 : 1BH ; level triggered input, single mode↲
ICW 2 : 20H ; the interrupt vector table starts in 80H↲
ICW 4 : 1DH ┆84┆; non buffer mode, normal EOI and not fully ↓
┆19┆┆95┆┄┄; nested.↲
MASK : F7H ; enable parity interrupt on IR3.↲
↲
↲
┆b0┆┆a1┆┆f0┆┆b0┆6.4 iAPX186 Timer 1.↲
↲
Timer 1 is initialized as a baudrate generator in alternating ↓
mode with even duty cycle. If no console is connected the ↓
baudrate is set to 9600 baud, otherwise the Baud Rate ↓
Determination procedure is entered see chapter 6.↲
↲
↲
┆8c┆┆83┆┆d4┆↓
┆b0┆┆a1┆┆f0┆┆b0┆6.5 MPSC 8274 Ch. B (Console Interface).↲
↲
Baudrate factor : X16↲
Character length : 8 bits↲
Parity : none↲
Stop bits : 2↲
Mode : asynchronous.↲
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆7. ┆b0┆Test 0 = ┆f0┆MEMORY TEST.↲
↲
The memory test of the ETC 611 SBC selftest consists of two ↓
parts, a PROM checksum test and a RAM memory test. The PROM ↓
checksum test is only run once after power up or external reset, ↓
whereas the RAM memory test may be run several times, if ↓
requested by the operator.↲
↲
↲
┆a1┆┆b0┆7.1 PROM Checksum Test.↲
↲
The contents of both the odd and the even PROM are summarized ↓
bytewise and the result must be a zero. For that reason the ↓
PROM's contain a compensation byte which is used to bring the sum ↓
to zero.↲
┆a1┆↲
┆b0┆┆f0┆1. ┆b0┆checksum test: sum error exp.:<0000> rec.:<xyzw>↲
↲
Checksum error usually means that the content of the PROM has ↓
been damaged and that the PROM must be changed.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆7.2 RAM Memory Test.↲
↲
The RAM memory test of the ETC 611 SBC selftest verifies the on-↓
board memory. The size of RAM is determined from reading the on ↓
board straps on the 8255 parallel port A. Valid memory sizes are ↓
1 M Bytes or 512 Kbytes. If 1 M bytes are present some of the RAM ↓
cannot be used by the ETC 611 itself. The upper 64 Kbytes are ↓
reserved to onboard PROM space and is useless. If one COM 601 is ↓
present the upper 128 Kbytes are occupied, and if two COM 601 are ↓
present then the upper 256 Kbytes are shadowed. NOTE that the ↓
shadowed RAM is available to other Multibus Masters ?↲
↲
The memory test is a register based test and uses no memory space ↓
at all, neither for variables nor stack. The test verifies every ↓
single byte of the on-board memory.↲
↲
This fact lets only one register for test variables survive the ↓
memory test. That variable contains all the test switches and the ↓
test number. ↲
↲
↲
┆a1┆┆b0┆7.2.1 Memory Test Pattern.↲
↲
The memory test executes 4 passes trough the entire memory, two ↓
times writing and two times reading.↲
↲
The test pattern is the convenient modulus 3 pattern consisting ↓
of three times 0000 followed by three times FFFF (hexadecimal).↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆7.2.2 Memory Test Flow.↲
↲
The test starts in the highest RAM addresses and inserts the ↓
pattern towards lower addresses.↲
↲
When all memory words have been written and verified, they are ↓
tested again with the inversed pattern, this means, that all bits ↓
are tested for "zero" and "one" insertion. If an error occur then ↓
an attempt to send the following message, to the "test-output", ↓
is made :↲
↲
┆a1┆┆b0┆┆f0┆2. ┆b0┆RAM test: RAM error segm.:<ssss> addr.:<aaaa> exp.:<eeee>↲
╞ ╞ ╞ ╞ ┆b0┆ rec.:<rrrr>↲
↲
The secondary text is interpreted like this :↲
↲
<ssss> is the segment address↲
<aaaa> is the address offset↲
<eeee> is the expected pattern, should allways be 0000 or FFFF.↲
<rrrr> is the received pattern.↲
↲
The above mentioned information may be used to find a defective ↓
RAM memory chip from the knowledge of the RAM-layout.↲
↲
↲
┆a1┆┆b0┆7.2.3 Loop On Error.↲
↲
When a fault occur during the ram test an error message is ↓
written to the console, and the RAM test starts from the start ↓
again. This will be the case until no error is discovered. If ↓
there is a RAM error and if an L is typed from the keyboard, then ↓
the RAM test will not start from the beginning again, but proceed ↓
trough the RAM test and write all RAM errors to the console, and ↓
finally enter the "test-administrator" to execute other tests.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆8. ┆b0┆Test 1 = ┆f0┆Chip Select Test.↲
↲
To ease complex debugging, a simple chip select loop, combined ↓
with a RAM write/read, is supplied. ↲
↲
This test generates chip selects to all peripheral devices by ↓
executing input instructions to all relevant I/O-devices. These ↓
are :↲
↲
Port ┆84┆0, 2, 128, 130, 256, 258, 260, 262, 384, 386, 388, 390, 392, ↓
┆19┆┆85┆┄┄394, 396, 398, 512, 514, 516, 518, 640, 642, 644, 646, 648, ↓
┆19┆┆85┆┄┄650, 652, 654.↲
↲
When all the chip selects are made, a pattern AA55 hex. is ↓
written to a RAM cell and immediately read back.↲
↲
This test is unable to generate any error messages. It is meant ↓
only as a special fast scope loop test.↲
════════════════════════════════════════════════════════════════════════
↓
┆a2┆┆e2┆┆a1┆┆b0┆9. ┆b0┆TEST 2┆f0┆ = iAPX 186 Timer Test.↲
↲
This test verifies the ability of the iAPX 186 internal timer 0 ↓
to generate interrupts. The internal timer 0 is initialized as a ↓
real time clock which generates interrupt every 20 millisecond. ↓
If no timer interrupt is generated then an error message is ↓
generated like this.↲
↲
┆a1┆┆a1┆┆a1┆┆e1┆┆b0┆┆f0┆1. ┆b0┆iAPX186 timer test : missing timer 0 interrupt↲
↲
This error should indicate a malfunction of the iAPX 186 ↓
processor chip.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆10. ┆b0┆TEST 3┆f0┆ = iAPX 186 DMA Test.↲
↲
This test verifies the ability of the two iAPX 186 internal DMA ↓
channels to make a data transport and to generate interrupts. The ↓
two iAPX 186 DMA channels are initialized to perform a DMA memory ↓
to memory transport simultaneously. DMA channel 0 copies 8 Kbytes ↓
from a source to a destination buffer in the forward direction, ↓
and DMA channel 1 copies from the same source to another ↓
destination buffer in the reverse direction. All DMA transfers ↓
are syncronized to the internal timer 2 which generates a 250 KHz ↓
clock. The two channels are initialized to the same priority. ↓
This ensures together with the selected internal timer 2 ↓
syncronization that both DMA channels runs simultaneously and ↓
that the CPU may also get memory access. When the DMA transport ↓
is complete both destination buffers are compared to the source ↓
buffer.↲
↲
The test produces the following error messages:↲
↲
┆b0┆┆f0┆1. ┆b0┆DMA test: data error segm.: <ssss> addr.:<aaaa> rec.:<rrrr>↲
╞ ╞ ╞ ╞ ╞ ┆b0┆exp.:<eeee>↲
↲
┆b0┆┆f0┆2. ┆b0┆DMA test: transfer timeout↲
↲
The first error indictes that both DMA transports has terminated ↓
but the destination buffer is not equal to the source as ↓
expected. The latter indicates that one of the two or both DMA ↓
interrupts is missing.↲
↲
Both errors should indicate a malfunction of the iAPX 186 ↓
processor chip.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆f0┆┆a1┆┆b0┆1┆a1┆1. ┆b0┆Test 4┆f0┆ = RAM Refresh Test.↲
↲
The RAM refresh test of the ETC611 SBC Selftest assist in the ↓
verification of the memory control logic functionality. The main ↓
purpose is to discover the decay of data caused by a malfunction ↓
of the RAM refresh circuitry.↲
↲
The test pattern written is a counting pattern and the size of ↓
the test buffer is 4 K, 16 bit words.↲
↲
When the pattern has been written the test program enters a ↓
waiting loop for approximate 5 sec., in which the CPU will not ↓
access the RAM memory. After the delay, the buffer will be ↓
checked to discover any decay.↲
↲
If decay is found, a message is written like this:↲
↲
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
┆b0┆RAM refresh test: error, addr.: <aaaa>, exp.: <eeee>, rec.: <rrrr>↲
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000301453100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
↲
Where↲
╞ <aaaa> ┆84┆is the offset address relative to the start of the ↓
┆19┆┆8b┆┄┄test buffer.↲
<eeee> is the pattern written in this word.↲
╞ <rrrr> is the pattern read from this word.↲
↲
The corresponding error number is 9.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆a1┆12. Test 5 ┆f0┆= Ethernet Test 2.↲
↲
The ethernet test 2 applies to the verification of the 82586 co-↓
processor and its interface circuitry. The test makes an external ↓
data loopback test on the ethernet chip.↲
↲
First a software reset of the ethernet chip is made. This reset ↓
causes the ethernet controller to issue an interrupt when the ↓
reset is complete. If no interrupt is received an error message ↓
is generated like this:↲
↲
┆b0┆Ethernet test 2 : missing reset interrupt↲
↲
Corresponding error number is 61.↲
↲
Second a configure command is executed to the ethernet controller ↓
in order to select the external loopback mode. Again the sleftest ↓
awaits a configure complete interrupt, and if none is received an ↓
error message is generated like this:↲
↲
┆b0┆Ethernet test 2 : configuration command not accepted↲
↲
Corresponding error number is 58.↲
↲
Third a transmit frame command is executed. The ethernet address ↓
is the broadcast address an the message length is 14 bytes. If↓
the transmit frame command is not accepted by the ethernet ↓
controller an error message is generated like this:↲
↲
┆b0┆Ethernet test 2 : transmit command not accepted↲
↲
corresponding error number is 59.↲
↲
Fourth, when the transmit frame command is completed the data ↓
sent is copared with the data received and if not the same an ↓
error message is generated otherwise the ethernet interface is ↓
said to be OK.↲
↲
┆8c┆┆83┆┆c8┆↓
┆b0┆Ethernet test 2 : data error add.:<aaaa>, exp.:<eeee>,↲
┆b0┆╞ ╞ ╞ ╞ rec.:<rrrr>↲
┆81┆↲
Corresponding error number is 60.↲
↲
where↲
add.:<aaaa> is offset address in the receive buffer↲
exp.:<eeee> is the expected value from the transmit buffer↲
rec.:<rrrr> is the received value in the receive buffer↲
↲
Another error message is written if the ethernet controller ↓
generates an interrupt without having reset the command just ↓
executed.↲
↲
┆b0┆Ethernet test 2 : interrupt but command word not cleared↲
↲
Corresponding error number is 48.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆A. REFERENCES┆b0┆↲
↲
(1) RCSL. 991 10092↲
RC 39 Selftest Concept, ↲
User's manual ╞ ↲
↲
(2) RCSL. 991 10095↲
ITC 602 hardware selftest, ↲
User's manual ╞ ↲
↲
(3) RCSL. 991 10097↲
F641 COM 601 hardware selftest, ↲
User's manual ↲
↲
(4) RCSL. 991 10094↲
RC3902 hardware selftest, ↲
User's manual╞ ↲
↲
(5) RCSL. 991 10134↲
RC39 monitor 8086 version, ↲
Reference manual╞ ↲
↲
(6) RCSL. 991 10093↲
RC39 monitor 80286 version, ↲
Reference manual ↲
↲
↓
↓
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0c000600000000020150310000000000000000000000000000000000000000000000000008101820283038404a4b555f69737dff04╱
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆a1┆┆b0┆B. ┆a1┆Complete Error List.↲
↲
!-----------------------------------------------------------------------------!↲
! Err. No !╞ ╞ ╞ ╞ Error Text ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
! 0 ! OK╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 1 ! Checksum Test: sum error ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 2╞ ! RAM Test: RAM error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 3 ! iAPX186 DMA Test: data error╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 4 ! iAPX186 DMA Test: timeout╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 9 ! RAM refresh Test: error╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 10 ! iAPX186 Timer Test: missing timer 0 interrupt╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 48 ! Ethernet test 2: interrupt but command word not cleared╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 60 ! Ethernet test 2: data error ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 61 ! Ethernet test 2: missing reset interrupt╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------;↲
! 62 ! Ethernet test 2: configuration command not accepted╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 63 ! Ethernet test 2: configuration command not accepted╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
!-----------------------------------------------------------------------------!↲
! 64 ! Ethernet test 2: transmit command not accepted !↲
!-----------------------------------------------------------------------------!↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆1a┆┆1a┆ror List.↲
↲
!----------------------------------------------------------------
0x0000…0020 (0,) 00 00 00 00 00 00 00 00 42 05 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 4e 00 00 00 ┆ B N ┆
0x0020…0040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
0x0040…0047 00 00 00 00 00 00 00 ┆ ┆
0x0047…0080 Params {
0x0047…0080 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x0047…0080 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
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0x0080…0083 }
0x0083…00a0 0a a1 a1 0d 0a 0d 0a 09 45 64 69 74 69 6f 6e 3a 09 4d 61 79 20 31 39 38 35 0d 0a 09 41 ┆ Edition: May 1985 A┆
0x00a0…00c0 75 74 68 6f 72 3a 20 20 20 50 65 74 65 72 20 4c 75 6e 64 62 6f 0d 0a 09 52 43 53 4c 20 4e 6f 2e ┆uthor: Peter Lundbo RCSL No.┆
0x00c0…00e0 3a 09 39 39 31 20 31 30 30 39 36 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 20 20 20 ┆: 991 10096 ┆
0x00e0…0100 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 49 4e 54 45 52 4e 41 4c 20 44 ┆ INTERNAL D┆
0x0100…0120 4f 43 55 4d 45 4e 54 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 54 69 74 6c 65 3a 0d 0a 0d ┆OCUMENT Title: ┆
0x0120…0140 0a 06 84 52 43 33 39 33 31 20 45 54 43 20 36 31 31 20 68 61 72 64 77 61 72 65 20 73 65 6c 66 74 ┆ RC3931 ETC 611 hardware selft┆
0x0140…0160 65 73 74 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆est ┆
0x0160…0170 20 75 73 65 72 27 73 20 6d 61 6e 75 61 6c 0d 0a ┆ user's manual ┆
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0x0170…0173 0c 82 ac ┆ ┆
0x0170…0173 }
0x0173…0180 0a 4b 45 59 57 4f 52 44 53 3a 0d 0a 09 ┆ KEYWORDS: ┆
0x0180…01a0 09 84 52 43 20 33 39 2c 20 58 45 4e 49 58 2c 20 52 65 6d 6f 74 65 2f 4c 6f 63 61 6c 20 43 6f 6d ┆ RC 39, XENIX, Remote/Local Com┆
0x01a0…01c0 6d 75 6e 69 63 61 74 69 6f 6e 2c 20 54 45 4c 45 54 45 58 2c 20 0a 19 89 80 80 45 74 68 65 72 6e ┆munication, TELETEX, Ethern┆
0x01c0…01e0 65 74 2c 20 4c 41 4e 2c 20 48 61 72 64 77 61 72 65 20 53 65 6c 66 74 65 73 74 2c 20 45 54 43 20 ┆et, LAN, Hardware Selftest, ETC ┆
0x01e0…0200 36 31 31 2e 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 41 42 53 54 52 41 43 54 3a 0d 0a 09 ┆611. ABSTRACT: ┆
0x0200…0220 (1,) 09 84 54 68 69 73 20 6d 61 6e 75 61 6c 20 64 6f 63 75 6d 65 6e 74 73 20 74 68 65 20 45 54 43 36 ┆ This manual documents the ETC6┆
0x0220…0240 31 31 20 53 42 43 20 73 65 6c 66 74 65 73 74 20 0a 19 89 80 80 70 72 6f 67 72 61 6d 20 77 68 69 ┆11 SBC selftest program whi┆
0x0240…0260 63 68 20 63 6f 6e 74 61 69 6e 20 73 65 76 65 72 61 6c 20 70 72 6f 67 72 61 6d 73 20 66 6f 72 20 ┆ch contain several programs for ┆
0x0260…0280 0a 19 89 80 80 76 65 72 69 66 79 69 6e 67 20 68 61 72 64 77 61 72 65 20 63 6f 6d 70 6f 6e 65 6e ┆ verifying hardware componen┆
0x0280…02a0 74 73 20 6f 66 20 74 68 65 20 49 6e 74 65 6c 6c 69 67 65 6e 74 20 0a 19 89 80 80 45 74 68 65 72 ┆ts of the Intelligent Ether┆
0x02a0…02c0 6e 65 74 20 43 6f 6e 74 72 6f 6c 6c 65 72 2e 20 54 68 65 20 45 54 43 36 31 31 20 69 73 20 61 6e ┆net Controller. The ETC611 is an┆
0x02c0…02e0 20 49 4e 54 45 4c 20 0a 19 89 80 80 4d 75 6c 74 69 62 75 73 20 63 6f 6d 70 61 74 69 62 6c 65 20 ┆ INTEL Multibus compatible ┆
0x02e0…0300 73 6c 61 76 65 20 63 6f 6e 74 72 6f 6c 6c 65 72 2c 20 62 61 73 65 64 20 75 70 6f 6e 20 61 20 0a ┆slave controller, based upon a ┆
0x0300…0320 19 89 80 80 31 36 20 62 69 74 20 69 41 50 58 20 31 38 36 20 6d 69 63 72 6f 70 72 6f 63 65 73 73 ┆ 16 bit iAPX 186 microprocess┆
0x0320…0325 6f 72 2e 0d 0a ┆or. ┆
0x0325…0328 FormFeed {
0x0325…0328 0c 81 cc ┆ ┆
0x0325…0328 }
0x0328…0340 0a 09 09 09 09 09 09 69 0d 0a a1 43 4f 4e 54 45 4e 54 20 20 20 20 20 20 ┆ i CONTENT ┆
0x0340…0360 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x0360…0380 20 20 20 20 20 20 20 20 50 41 47 45 20 20 0d 0a 0d 0a 31 2e 20 49 4e 54 52 4f 44 55 43 54 49 4f ┆ PAGE 1. INTRODUCTIO┆
0x0380…03a0 4e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆N ..............................┆
0x03a0…03c0 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 0d 0a 0d 0a 32 2e 20 54 48 45 20 44 55 41 4c 20 43 48 41 4e 4e ┆....... 1 2. THE DUAL CHANN┆
0x03c0…03e0 45 4c 20 43 4f 4d 4d 55 4e 49 43 41 54 49 4f 4e 20 41 50 50 52 4f 41 43 48 20 2e 2e 2e 2e 2e 2e ┆EL COMMUNICATION APPROACH ......┆
0x03e0…0400 2e 2e 2e 2e 20 20 20 32 0d 0a 0d 0a 33 2e 20 54 48 45 20 42 41 55 44 20 52 41 54 45 20 44 45 54 ┆.... 2 3. THE BAUD RATE DET┆
0x0400…0420 (2,) 45 52 4d 49 4e 41 54 49 4f 4e 20 4d 4f 44 45 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ERMINATION MODE ................┆
0x0420…0440 2e 20 20 20 33 0d 0a 0d 0a 34 2e 20 44 45 46 41 55 4c 54 20 49 4e 54 45 52 52 55 50 54 20 48 41 ┆. 3 4. DEFAULT INTERRUPT HA┆
0x0440…0460 4e 44 4c 49 4e 47 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 ┆NDLING ....................... ┆
0x0460…0480 20 34 0d 0a 20 20 20 34 2e 31 20 49 6e 73 74 72 75 63 74 69 6f 6e 20 45 78 63 65 70 74 69 6f 6e ┆ 4 4.1 Instruction Exception┆
0x0480…04a0 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 34 0d 0a 20 ┆ ........................ 4 ┆
0x04a0…04c0 20 20 34 2e 32 20 49 6c 6c 65 67 61 6c 20 49 6e 74 65 72 72 75 70 74 20 2e 2e 2e 2e 2e 2e 2e 2e ┆ 4.2 Illegal Interrupt ........┆
0x04c0…04e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 34 0d 0a 0d 0a 35 2e 20 b0 ┆.................... 4 5. ┆
0x04e0…0500 f0 53 45 4c 46 54 45 53 54 20 53 57 49 54 43 48 20 53 45 54 54 49 4e 47 53 20 2e 2e 2e 2e 2e 2e ┆ SELFTEST SWITCH SETTINGS ......┆
0x0500…0520 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 37 0d 0a 0d 0a 36 2e 20 49 4e ┆................... 7 6. IN┆
0x0520…0540 49 54 49 41 4c 49 5a 41 54 49 4f 4e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ITIALIZATION ...................┆
0x0540…0560 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 38 0d 0a 20 20 20 36 2e 31 20 57 61 69 ┆............... 8 6.1 Wai┆
0x0560…0580 74 20 53 74 61 74 65 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆t States .......................┆
0x0580…05a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 38 0d 0a 20 20 20 36 2e 32 20 69 41 50 58 31 38 36 20 ┆.......... 8 6.2 iAPX186 ┆
0x05a0…05c0 49 6e 74 65 72 72 75 70 74 20 43 6f 6e 74 72 6f 6c 6c 65 72 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆Interrupt Controller ...........┆
0x05c0…05e0 2e 2e 2e 2e 2e 20 20 20 20 38 0d 0a 20 20 20 36 2e 33 20 50 72 6f 67 72 61 6d 6d 61 62 6c 65 20 ┆..... 8 6.3 Programmable ┆
0x05e0…0600 49 6e 74 65 72 72 75 70 74 20 43 6f 6e 74 72 6f 6c 6c 65 72 20 38 32 35 39 20 2e 2e 2e 2e 2e 2e ┆Interrupt Controller 8259 ......┆
0x0600…0620 (3,) 09 20 20 39 0d 0a 20 20 20 36 2e 34 20 69 41 50 58 31 38 36 20 54 69 6d 65 72 20 31 20 2e 2e 2e ┆ 9 6.4 iAPX186 Timer 1 ...┆
0x0620…0640 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 39 0d ┆.......................... 9 ┆
0x0640…0660 0a 20 20 20 36 2e 35 20 4d 50 53 43 20 38 32 37 34 20 43 68 2e 20 42 20 28 43 6f 6e 73 6f 6c 65 ┆ 6.5 MPSC 8274 Ch. B (Console┆
0x0660…0680 20 49 6e 74 65 72 66 61 63 65 29 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 30 0d 0a 20 0d 0a 37 ┆ Interface) ......... 10 7┆
0x0680…06a0 2e 20 54 45 53 54 20 30 20 3d 20 4d 45 4d 4f 52 59 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆. TEST 0 = MEMORY TEST .........┆
0x06a0…06c0 2e 2e 2e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 31 0d 0a 20 20 20 37 2e 31 ┆... ............... 11 7.1┆
0x06c0…06e0 20 50 52 4f 4d 20 43 68 65 63 6b 73 75 6d 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ PROM Checksum Test ............┆
0x06e0…0700 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 31 0d 0a 20 20 20 37 2e 32 20 52 41 4d 20 ┆.............. 11 7.2 RAM ┆
0x0700…0720 4d 65 6d 6f 72 79 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆Memory Test ....................┆
0x0720…0740 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 32 0d 0a 20 20 20 20 20 20 20 37 2e 32 2e 31 20 4d 65 6d ┆......... 12 7.2.1 Mem┆
0x0740…0760 6f 72 79 20 54 65 73 74 20 50 61 74 74 65 72 6e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ory Test Pattern ...............┆
0x0760…0780 2e 2e 2e 2e 20 20 20 31 32 0d 0a 20 20 20 20 20 20 20 37 2e 32 2e 32 20 4d 65 6d 6f 72 79 20 54 ┆.... 12 7.2.2 Memory T┆
0x0780…07a0 65 73 74 20 46 6c 6f 77 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 ┆est Flow ...................... ┆
0x07a0…07c0 20 20 31 33 0d 0a 20 20 20 20 20 20 20 37 2e 32 2e 33 20 4c 6f 6f 70 20 4f 6e 20 45 72 72 6f 72 ┆ 13 7.2.3 Loop On Error┆
0x07c0…07e0 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 33 0d ┆ ......................... 13 ┆
0x07e0…0800 0a 0d 0a 38 2e 20 54 45 53 54 20 31 20 3d 20 43 68 69 70 20 53 65 6c 65 63 74 20 54 65 73 74 20 ┆ 8. TEST 1 = Chip Select Test ┆
0x0800…0820 (4,) 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 34 0d 0a 0d 0a ┆....................... 14 ┆
0x0820…0840 8c 82 f4 0a 39 2e 20 54 45 53 54 20 32 20 3d 20 69 41 50 58 20 31 38 36 20 54 69 6d 65 72 20 54 ┆ 9. TEST 2 = iAPX 186 Timer T┆
0x0840…0860 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 35 0d 0a 0d ┆est .................... 15 ┆
0x0860…0880 0a 31 30 2e 20 54 45 53 54 20 33 20 3d 20 69 41 50 58 20 31 38 36 20 44 4d 41 20 54 65 73 74 20 ┆ 10. TEST 3 = iAPX 186 DMA Test ┆
0x0880…08a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 36 0d 0a 0d 0a 31 31 ┆...................... 16 11┆
0x08a0…08c0 2e 20 54 45 53 54 20 34 20 3d 20 52 41 4d 20 52 65 66 72 65 73 68 20 54 65 73 74 20 2e 2e 2e 2e ┆. TEST 4 = RAM Refresh Test ....┆
0x08c0…08e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 37 0d 0a 0d 0a 31 32 2e 20 54 ┆................... 17 12. T┆
0x08e0…0900 45 53 54 20 35 20 3d 20 45 74 68 65 72 6e 65 74 20 54 65 73 74 20 32 20 2e 2e 2e 2e 2e 2e 2e 2e ┆EST 5 = Ethernet Test 2 ........┆
0x0900…0920 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 38 0d 0a 0d 0a 0d 0a a1 41 50 50 45 4e ┆................ 18 APPEN┆
0x0920…0940 44 49 43 45 53 0d 0a 0d 0a 41 2e 20 52 45 46 45 52 45 4e 43 45 53 20 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆DICES A. REFERENCES .........┆
0x0940…0960 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 ┆.............................. ┆
0x0960…0980 32 30 0d 0a 0d 0a 42 2e 20 43 6f 6d 70 6c 65 74 65 20 45 72 72 6f 72 20 4c 69 73 74 20 2e 2e 2e ┆20 B. Complete Error List ...┆
0x0980…09a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 31 0d ┆........................... 21 ┆
0x09a0…09a3 0a 0d 0a ┆ ┆
0x09a3…09a6 FormFeed {
0x09a3…09a6 0c 81 b4 ┆ ┆
0x09a3…09a6 }
0x09a6…09c0 0a 14 b3 09 09 09 20 20 20 20 20 0b a1 0d 0a a1 a1 b0 31 2e 20 49 6e 74 72 6f ┆ 1. Intro┆
0x09c0…09e0 64 75 63 74 69 6f 6e 2e 0d 0a 0d 0a 54 68 65 20 45 54 43 20 36 31 31 20 69 73 20 61 6e 20 49 6e ┆duction. The ETC 611 is an In┆
0x09e0…0a00 74 65 6c 6c 69 67 65 6e 74 20 43 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 43 6f 6e 74 72 6f 6c 6c ┆telligent Communication Controll┆
0x0a00…0a20 (5,) 65 72 2c 20 77 68 69 63 68 20 0a 6f 66 66 65 72 73 20 4c 6f 63 61 6c 20 41 72 65 61 20 4e 65 74 ┆er, which offers Local Area Net┆
0x0a20…0a40 77 6f 72 6b 20 73 65 72 76 69 63 65 20 28 4c 41 4e 29 2c 20 54 45 4c 45 54 45 58 20 6e 65 74 77 ┆work service (LAN), TELETEX netw┆
0x0a40…0a60 6f 72 6b 20 73 65 72 76 69 63 65 20 0a 61 6e 64 20 28 74 6f 67 65 74 68 65 72 20 77 69 74 68 20 ┆ork service and (together with ┆
0x0a60…0a80 43 4f 4d 20 36 30 31 29 20 49 42 4d 20 68 6f 73 74 20 73 65 72 76 69 63 65 20 74 6f 20 74 68 65 ┆COM 601) IBM host service to the┆
0x0a80…0aa0 20 52 43 20 33 39 20 0a 70 72 6f 64 75 63 74 2e 0d 0a 0d 0a 54 68 69 73 20 6d 61 6e 75 61 6c 20 ┆ RC 39 product. This manual ┆
0x0aa0…0ac0 61 73 73 75 6d 65 20 74 68 61 74 20 74 68 65 20 72 65 61 64 65 72 20 69 73 20 66 61 6d 69 6c 69 ┆assume that the reader is famili┆
0x0ac0…0ae0 61 72 20 77 69 74 68 20 74 68 65 20 52 43 20 33 39 20 0a 73 65 6c 66 74 65 73 74 20 63 6f 6e 63 ┆ar with the RC 39 selftest conc┆
0x0ae0…0b00 65 70 74 20 61 73 20 64 65 73 63 72 69 62 65 64 20 69 6e 20 74 68 65 20 6d 61 6e 75 61 6c 20 63 ┆ept as described in the manual c┆
0x0b00…0b20 61 6c 6c 65 64 20 22 54 68 65 20 52 43 20 33 39 20 0a 53 65 6c 66 74 65 73 74 20 43 6f 6e 63 65 ┆alled "The RC 39 Selftest Conce┆
0x0b20…0b40 70 74 22 2e 20 54 68 65 20 45 54 43 20 36 31 31 20 73 65 6c 66 74 65 73 74 20 69 6e 63 6c 75 64 ┆pt". The ETC 611 selftest includ┆
0x0b40…0b60 65 73 20 36 20 64 69 66 66 65 72 65 6e 74 20 0a 74 65 73 74 73 20 77 68 69 63 68 20 6d 61 79 20 ┆es 6 different tests which may ┆
0x0b60…0b80 62 65 20 72 75 6e 20 69 6e 20 73 65 76 65 72 61 6c 20 6d 6f 64 65 73 2e 20 46 69 76 65 20 6f 66 ┆be run in several modes. Five of┆
0x0b80…0ba0 20 74 68 65 73 65 20 74 65 73 74 73 20 61 72 65 20 0a b0 64 65 66 61 75 6c 74 f0 20 74 65 73 74 ┆ these tests are default test┆
0x0ba0…0bc0 73 20 77 68 69 63 68 20 61 6c 6c 77 61 79 73 20 65 78 65 63 75 74 65 20 61 66 74 65 72 20 61 20 ┆s which allways execute after a ┆
0x0bc0…0be0 70 6f 77 65 72 20 6f 6e 2e 20 54 68 65 20 6c 61 73 74 20 0a 19 80 81 80 74 65 73 74 20 69 73 20 ┆power on. The last test is ┆
0x0be0…0c00 61 b0 f0 6e 20 b0 65 78 74 65 6e 64 65 64 b0 f0 20 74 65 73 74 20 77 68 69 63 68 20 69 73 20 72 ┆a n extended test which is r┆
0x0c00…0c20 (6,) 75 6e 20 6f 6e 6c 79 20 77 68 65 6e 20 72 65 71 75 65 73 74 65 64 20 0a 19 80 84 80 65 78 70 6c ┆un only when requested expl┆
0x0c20…0c40 69 63 69 74 20 62 79 20 61 6e 20 6f 70 65 72 61 74 6f 72 2e 20 54 68 69 73 20 76 65 72 73 69 6f ┆icit by an operator. This versio┆
0x0c40…0c60 6e 20 6f 66 20 74 68 65 20 45 54 43 20 36 31 31 20 69 6e 63 6c 75 64 65 73 20 6e 6f 20 0a 19 80 ┆n of the ETC 611 includes no ┆
0x0c60…0c7c 84 80 b0 73 65 70 65 72 61 74 65 6c 79 f0 20 72 75 6e 20 f0 74 65 73 74 73 2e 0d 0a ┆ seperately run tests. ┆
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0x0c7f…0c80 0a ┆ ┆
0x0c80…0ca0 a1 a1 b0 32 2e 20 54 68 65 20 44 75 61 6c 20 43 68 61 6e 6e 65 6c 20 43 6f 6d 6d 75 6e 69 63 61 ┆ 2. The Dual Channel Communica┆
0x0ca0…0cc0 74 69 6f 6e 20 41 70 70 72 6f 61 63 68 2e 0d 0a 0d 0a 54 68 65 20 45 54 43 20 36 31 31 20 53 42 ┆tion Approach. The ETC 611 SB┆
0x0cc0…0ce0 43 20 73 65 6c 66 74 65 73 74 20 73 75 70 70 6f 72 74 73 20 74 68 65 20 44 75 61 6c 20 43 68 61 ┆C selftest supports the Dual Cha┆
0x0ce0…0d00 6e 6e 65 6c 20 43 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 0a 66 61 63 69 6c 69 74 79 20 61 73 20 ┆nnel Communication facility as ┆
0x0d00…0d20 64 65 73 63 72 69 62 65 64 20 69 6e 20 74 68 65 20 22 52 43 20 33 39 20 53 65 6c 66 74 65 73 74 ┆described in the "RC 39 Selftest┆
0x0d20…0d40 20 43 6f 6e 63 65 70 74 22 2e 20 49 66 20 74 68 65 20 0a 73 74 72 61 70 20 53 54 37 2d 32 33 20 ┆ Concept". If the strap ST7-23 ┆
0x0d40…0d60 69 73 20 69 6e 73 65 72 74 65 64 20 74 68 65 20 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 67 6f ┆is inserted the communication go┆
0x0d60…0d80 65 73 20 76 69 61 20 74 68 65 20 6f 6e 2d 62 6f 61 72 64 20 0a 38 32 37 34 20 55 53 41 52 54 20 ┆es via the on-board 8274 USART ┆
0x0d80…0da0 6c 69 6e 65 20 30 2c 20 6f 74 68 65 72 77 69 73 65 20 69 66 20 74 68 65 20 73 74 72 61 70 20 69 ┆line 0, otherwise if the strap i┆
0x0da0…0dc0 73 20 6f 6d 69 74 74 65 64 20 74 68 65 20 0a 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 67 6f 65 ┆s omitted the communication goe┆
0x0dc0…0de0 73 20 74 72 61 6e 73 70 61 72 65 6e 74 6c 79 20 74 68 72 6f 75 67 68 20 74 68 65 20 4d 75 6c 74 ┆s transparently through the Mult┆
0x0de0…0e00 69 62 75 73 20 69 6e 74 65 72 66 61 63 65 20 0a 74 6f 20 61 20 63 6f 6e 73 6f 6c 65 20 63 6f 6e ┆ibus interface to a console con┆
0x0e00…0e20 (7,) 6e 65 63 74 65 64 20 74 6f 20 74 68 65 20 22 74 65 73 74 2d 6d 61 73 74 65 72 22 20 75 73 75 61 ┆nected to the "test-master" usua┆
0x0e20…0e40 6c 6c 79 20 61 20 43 50 55 20 36 39 31 20 6f 72 20 0a 61 20 43 50 55 20 36 31 30 20 62 6f 61 72 ┆lly a CPU 691 or a CPU 610 boar┆
0x0e40…0e44 64 2e 0d 0a ┆d. ┆
0x0e44…0e47 FormFeed {
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0x0e47…0e60 0a a1 b0 33 2e 20 54 68 65 20 42 61 75 64 20 52 61 74 65 20 a1 44 65 74 65 ┆ 3. The Baud Rate Dete┆
0x0e60…0e80 72 6d 69 6e 61 74 69 6f 6e 20 4d 6f 64 65 2e 0d 0a 0d 0a 49 66 20 74 68 65 20 73 74 61 72 70 20 ┆rmination Mode. If the starp ┆
0x0e80…0ea0 53 54 37 2d 32 33 20 69 73 20 69 6e 73 65 72 74 65 64 20 61 6e 64 20 61 20 74 65 72 6d 69 6e 61 ┆ST7-23 is inserted and a termina┆
0x0ea0…0ec0 6c 20 69 73 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 74 68 65 20 0a 56 2e 32 34 20 6c 69 6e 65 ┆l is connected to the V.24 line┆
0x0ec0…0ee0 20 30 20 69 6e 74 65 72 66 61 63 65 20 28 44 53 52 20 61 63 74 69 76 29 20 74 68 65 6e 20 74 68 ┆ 0 interface (DSR activ) then th┆
0x0ee0…0f00 65 20 73 65 6c 66 74 65 73 74 20 65 6e 74 65 72 73 20 74 68 65 20 0a 61 75 74 6f 6d 61 74 69 63 ┆e selftest enters the automatic┆
0x0f00…0f20 20 42 61 75 64 20 52 61 74 65 20 44 65 74 65 72 6d 69 6e 61 74 69 6f 6e 20 6d 6f 64 65 2e 20 54 ┆ Baud Rate Determination mode. T┆
0x0f20…0f40 68 65 20 55 53 41 52 54 20 69 73 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 0a 74 6f 20 39 36 30 30 ┆he USART is initialized to 9600┆
0x0f40…0f60 20 42 61 75 64 20 61 6e 64 20 73 74 61 72 73 20 28 2a 2a 2a 2a 2a 29 20 61 72 65 20 77 72 69 74 ┆ Baud and stars (*****) are writ┆
0x0f60…0f80 74 65 6e 20 74 6f 20 6c 69 6e 65 20 30 2e 20 54 68 65 73 65 20 73 74 61 72 73 20 0a 6d 61 79 20 ┆ten to line 0. These stars may ┆
0x0f80…0fa0 62 65 20 73 65 65 6e 20 61 73 20 73 74 61 72 73 2c 20 6f 74 68 65 72 20 6d 69 78 65 64 20 63 68 ┆be seen as stars, other mixed ch┆
0x0fa0…0fc0 61 72 61 63 74 65 72 73 20 6f 72 20 6e 6f 74 20 73 65 65 6e 20 61 74 20 61 6c 6c 20 0a 64 65 70 ┆aracters or not seen at all dep┆
0x0fc0…0fe0 65 6e 64 69 6e 67 20 6f 6e 20 74 68 65 20 42 61 75 64 20 52 61 74 65 20 6f 66 20 74 68 65 20 61 ┆ending on the Baud Rate of the a┆
0x0fe0…1000 74 74 61 63 68 65 64 20 63 6f 6e 73 6f 6c 65 2e 20 54 68 65 20 73 65 6c 66 74 65 73 74 20 0a 77 ┆ttached console. The selftest w┆
0x1000…1020 (8,) 61 69 74 73 20 66 6f 72 20 74 68 65 20 6f 70 65 72 61 74 6f 72 20 74 6f 20 65 6e 74 65 72 20 6f ┆aits for the operator to enter o┆
0x1020…1040 6e 65 20 6f 72 20 74 77 6f 20 75 70 70 65 72 20 63 61 73 65 20 55 2e 20 4f 6e 65 20 0a 75 70 70 ┆ne or two upper case U. One upp┆
0x1040…1060 65 72 20 63 61 73 65 20 55 20 69 73 20 65 6e 6f 75 67 68 20 69 66 20 74 68 65 20 42 61 75 64 20 ┆er case U is enough if the Baud ┆
0x1060…1080 52 61 74 65 20 69 73 20 39 36 30 30 2c 20 34 38 30 30 20 6f 72 20 32 34 30 30 20 0a 42 61 75 64 ┆Rate is 9600, 4800 or 2400 Baud┆
0x1080…10a0 2e 20 42 61 75 64 20 52 61 74 65 73 20 6f 66 20 31 32 30 30 2c 20 36 30 30 20 6f 72 20 33 30 30 ┆. Baud Rates of 1200, 600 or 300┆
0x10a0…10bc 20 72 65 71 75 69 72 65 73 20 74 77 6f 20 75 70 70 65 72 20 63 61 73 65 20 55 2e 0a ┆ requires two upper case U. ┆
0x10bc…10bf FormFeed {
0x10bc…10bf 0c 81 84 ┆ ┆
0x10bc…10bf }
0x10bf…10c0 0a ┆ ┆
0x10c0…10e0 a1 b0 b0 34 b0 a1 f0 f0 b0 2e 20 44 65 66 61 75 6c 74 20 49 6e 74 65 72 72 75 70 74 20 48 61 6e ┆ 4 . Default Interrupt Han┆
0x10e0…1100 64 6c 69 6e 67 2e 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 45 54 43 20 36 31 31 20 53 42 43 20 53 ┆dling. When the ETC 611 SBC S┆
0x1100…1120 65 6c 66 74 65 73 74 20 68 61 73 20 66 69 6e 69 73 68 65 64 20 74 68 65 20 6d 65 6d 6f 72 79 20 ┆elftest has finished the memory ┆
0x1120…1140 74 65 73 74 2c 20 61 20 73 65 74 20 0a 6f 66 20 64 65 66 61 75 6c 74 20 69 6e 74 65 72 72 75 70 ┆test, a set of default interrup┆
0x1140…1160 74 20 76 65 63 74 6f 72 73 20 61 72 65 20 70 6c 61 63 65 64 20 69 6e 20 74 68 65 20 69 6e 74 65 ┆t vectors are placed in the inte┆
0x1160…1180 72 72 75 70 74 20 76 65 63 74 6f 72 20 0a 74 61 62 6c 65 2e 20 54 68 65 73 65 20 76 65 63 74 6f ┆rrupt vector table. These vecto┆
0x1180…11a0 72 73 20 61 72 65 20 70 72 69 6d 61 72 69 6c 79 20 75 73 65 64 20 74 6f 20 68 61 6e 64 6c 65 20 ┆rs are primarily used to handle ┆
0x11a0…11c0 75 6e 65 78 70 65 63 74 65 64 20 0a 69 6e 74 65 72 72 75 70 74 73 2e 20 54 68 65 72 65 20 61 72 ┆unexpected interrupts. There ar┆
0x11c0…11e0 65 20 74 77 6f 20 6b 69 6e 64 73 20 6f 66 20 75 6e 65 78 70 65 63 74 65 64 20 69 6e 74 65 72 72 ┆e two kinds of unexpected interr┆
0x11e0…1200 75 70 74 73 2e 20 54 68 65 20 0a 66 69 72 73 74 20 69 73 20 68 61 6e 64 6c 65 64 20 62 79 20 74 ┆upts. The first is handled by t┆
0x1200…1220 (9,) 68 65 20 69 6e 74 65 72 72 75 70 74 20 70 72 6f 63 65 64 75 72 65 20 66 6f 72 20 69 6e 74 65 72 ┆he interrupt procedure for inter┆
0x1220…1240 6e 61 6c 20 69 41 50 58 31 38 36 20 0a 69 6e 73 74 72 75 63 74 69 6f 6e 20 69 6e 74 65 72 72 75 ┆nal iAPX186 instruction interru┆
0x1240…1260 70 74 73 20 61 6e 64 20 74 68 65 20 73 65 63 6f 6e 64 20 69 73 20 68 61 6e 64 6c 65 64 20 62 79 ┆pts and the second is handled by┆
0x1260…1280 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 0a 70 72 6f 63 65 64 75 72 65 20 66 6f 72 20 69 6c ┆ the interrupt procedure for il┆
0x1280…12a0 6c 65 67 61 6c 20 64 65 76 69 63 65 20 69 6e 74 65 72 72 75 70 74 73 2e 0d 0a 0d 0a 0d 0a b0 a1 ┆legal device interrupts. ┆
0x12a0…12c0 34 2e 31 20 49 6e 73 74 72 75 63 74 69 6f 6e 20 45 78 63 65 70 74 69 6f 6e 2e 0d 0a 0d 0a 49 66 ┆4.1 Instruction Exception. If┆
0x12c0…12e0 20 61 6e 20 49 6e 73 74 72 75 63 74 69 6f 6e 20 45 78 63 65 70 74 69 6f 6e 20 69 6e 74 65 72 72 ┆ an Instruction Exception interr┆
0x12e0…1300 75 70 74 20 6f 63 63 75 72 73 2c 20 69 74 20 69 73 20 6c 69 6b 65 6c 79 20 74 6f 20 0a 62 65 6c ┆upt occurs, it is likely to bel┆
0x1300…1320 69 65 76 65 20 74 68 61 74 20 74 68 69 73 20 77 61 73 20 63 61 75 73 65 64 20 62 79 20 61 20 6d ┆ieve that this was caused by a m┆
0x1320…1340 61 6c 66 75 6e 63 74 69 6f 6e 20 6f 66 20 74 68 65 20 69 41 50 58 31 38 36 2c 20 0a 62 65 63 61 ┆alfunction of the iAPX186, beca┆
0x1340…1360 75 73 65 20 74 68 69 73 20 69 6e 74 65 72 72 75 70 74 20 69 73 20 72 65 6c 61 74 65 64 20 74 6f ┆use this interrupt is related to┆
0x1360…1380 20 73 6f 6d 65 20 43 50 55 20 69 6e 73 74 72 75 63 74 69 6f 6e 73 2e 0d 0a 0d 0a 69 66 20 74 68 ┆ some CPU instructions. if th┆
0x1380…13a0 69 73 20 65 72 72 6f 72 20 73 68 6f 75 6c 64 20 6f 63 63 75 72 20 69 74 20 0d 0a b0 09 09 22 3e ┆is error should occur it ">┆
0x13a0…13c0 3e 20 69 6e 73 74 72 75 63 74 69 6f 6e 20 65 78 63 65 70 74 69 6f 6e 22 0d 0a 0d 0a 54 68 65 20 ┆> instruction exception" The ┆
0x13c0…13e0 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 38 2e ┆corresponding error number is 8.┆
0x13e0…1400 0d 0a 0d 0a 0d 0a b0 a1 f0 b0 34 2e 32 20 49 6c 6c 65 67 61 6c 20 49 6e 74 65 72 72 75 70 74 2e ┆ 4.2 Illegal Interrupt.┆
0x1400…1420 (10,) 0d 0a 0d 0a 41 74 20 74 68 65 20 65 6e 64 20 6f 66 20 65 76 65 72 79 20 74 65 73 74 20 6c 6f 6f ┆ At the end of every test loo┆
0x1420…1440 70 20 74 68 65 20 72 65 63 65 70 74 69 6f 6e 20 6f 66 20 69 6e 74 65 72 72 75 70 74 73 20 61 72 ┆p the reception of interrupts ar┆
0x1440…1460 65 20 0a 65 6e 61 62 6c 65 64 2e 20 4f 6e 6c 79 20 74 77 6f 20 6f 66 20 74 68 65 20 69 6e 74 65 ┆e enabled. Only two of the inte┆
0x1460…1480 72 72 75 70 74 20 72 65 71 75 65 73 74 20 6c 69 6e 65 73 20 77 69 6c 6c 20 62 65 20 75 73 65 64 ┆rrupt request lines will be used┆
0x1480…14a0 20 69 6e 20 0a 74 68 65 20 53 65 6c 66 74 65 73 74 2e 20 54 68 69 73 20 69 73 20 74 68 65 20 4d ┆ in the Selftest. This is the M┆
0x14a0…14c0 50 53 43 20 38 32 37 34 20 72 65 63 65 69 76 65 20 69 6e 74 65 72 72 75 70 74 20 77 68 69 63 68 ┆PSC 8274 receive interrupt which┆
0x14c0…14e0 20 69 73 20 0a 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 74 68 65 20 38 30 31 38 36 20 69 6e 74 65 ┆ is connected to the 80186 inte┆
0x14e0…1500 72 72 75 70 74 20 72 65 71 75 65 73 74 20 49 4e 54 31 20 61 6e 64 20 74 68 65 20 70 61 72 69 74 ┆rrupt request INT1 and the parit┆
0x1500…1520 79 20 0a 69 6e 74 65 72 72 75 70 74 20 77 68 69 63 68 20 69 73 20 63 6f 6e 6e 65 63 74 65 64 20 ┆y interrupt which is connected ┆
0x1520…1540 74 6f 20 74 68 65 20 38 32 35 39 20 69 6e 74 65 72 72 75 70 74 20 72 65 71 75 65 73 74 20 49 52 ┆to the 8259 interrupt request IR┆
0x1540…1560 33 2e 0d 0a 0d 0a 41 6c 6c 20 6f 74 68 65 72 20 69 6e 74 65 72 72 75 70 74 20 72 65 71 75 65 73 ┆3. All other interrupt reques┆
0x1560…1580 74 73 20 77 69 6c 6c 20 62 65 20 64 65 63 6f 64 65 64 20 61 73 20 69 6c 6c 65 67 61 6c 20 0a 69 ┆ts will be decoded as illegal i┆
0x1580…15a0 6e 74 65 72 72 75 70 74 73 20 61 6e 64 20 77 69 6c 6c 20 70 72 6f 64 75 63 65 20 74 68 65 20 66 ┆nterrupts and will produce the f┆
0x15a0…15c0 6f 6c 6c 6f 77 69 6e 67 20 65 72 72 6f 72 74 65 78 74 3a 0d 0a 0d 0a 8c 83 98 0a b0 09 09 22 69 ┆ollowing errortext: "i┆
0x15c0…15e0 6c 6c 65 67 61 6c 20 69 6e 74 65 72 72 75 70 74 22 0d 0a 0d 0a 66 6f 6c 6c 6f 77 65 64 20 62 79 ┆llegal interrupt" followed by┆
0x15e0…1600 20 74 68 65 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 20 61 62 6f 75 74 2c 20 77 68 69 63 68 20 6c 65 ┆ the information about, which le┆
0x1600…1620 (11,) 76 65 6c 20 77 61 73 20 69 73 73 75 69 6e 67 20 74 68 65 20 0a 69 6e 74 65 72 72 75 70 74 2e 0d ┆vel was issuing the interrupt. ┆
0x1620…1640 0a 0d 0a 54 68 65 20 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 ┆ The corresponding error numbe┆
0x1640…1660 72 20 69 73 20 35 2e 0d 0a 0d 0a 49 6e 20 74 68 65 20 50 49 43 20 69 6e 74 65 72 72 75 70 74 20 ┆r is 5. In the PIC interrupt ┆
0x1660…1680 74 65 73 74 20 61 6e 64 20 74 68 65 20 4d 75 6c 74 69 62 75 73 20 69 6e 74 65 72 72 75 70 74 20 ┆test and the Multibus interrupt ┆
0x1680…16a0 74 65 73 74 20 61 6e 20 0a 22 69 6c 6c 65 67 61 6c 20 69 6e 74 65 72 72 75 70 74 22 20 65 72 72 ┆test an "illegal interrupt" err┆
0x16a0…16c0 6f 72 20 69 73 20 70 72 6f 64 75 63 65 64 20 69 66 20 69 74 20 69 73 20 69 6d 70 6f 73 73 69 62 ┆or is produced if it is impossib┆
0x16c0…16e0 6c 65 20 74 6f 20 0a 63 6c 65 61 72 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 66 6f 6c 6c 6f ┆le to clear the interrupt follo┆
0x16e0…1700 77 69 6e 67 20 74 68 65 20 74 65 73 74 2e 20 54 68 69 73 20 6d 61 79 20 68 61 70 70 65 6e 20 69 ┆wing the test. This may happen i┆
0x1700…1720 66 20 61 20 0a 6a 75 6d 70 65 72 20 69 6e 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 73 74 72 ┆f a jumper in the interrupt str┆
0x1720…1740 61 70 20 61 72 65 61 20 53 36 20 69 73 20 6d 69 73 73 69 6e 67 2e 0d 0a 8c 81 84 0a 0e 0a 0d 0a ┆ap area S6 is missing. ┆
0x1740…1760 a1 49 6e 74 65 72 72 75 70 74 20 6e 61 6d 65 20 20 20 20 56 65 63 74 6f 72 20 74 79 70 65 20 20 ┆ Interrupt name Vector type ┆
0x1760…1780 20 52 65 6c 61 74 65 64 20 69 6e 73 74 72 75 63 74 69 6f 6e 73 05 0d 0a 44 69 76 69 64 65 20 45 ┆ Related instructions Divide E┆
0x1780…17a0 72 72 6f 72 20 20 20 20 20 20 20 20 20 20 30 20 20 20 20 20 20 20 20 20 44 49 56 2c 20 49 44 49 ┆rror 0 DIV, IDI┆
0x17a0…17c0 56 0d 0a 53 69 6e 67 6c 65 20 73 74 65 70 20 20 20 20 20 20 20 20 20 20 20 31 20 20 20 20 20 20 ┆V Single step 1 ┆
0x17c0…17e0 20 20 20 41 4c 4c 0d 0a 4e 4d 49 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 20 ┆ ALL NMI 2 ┆
0x17e0…1800 20 20 20 20 20 20 20 20 41 4c 4c 0d 0a 42 72 65 61 6b 70 6f 69 6e 74 20 20 20 20 20 20 20 20 20 ┆ ALL Breakpoint ┆
0x1800…1820 (12,) 20 20 20 33 20 20 20 20 20 20 20 20 20 49 4e 54 0d 0a 49 4e 54 30 20 44 65 74 65 63 74 65 64 20 ┆ 3 INT INT0 Detected ┆
0x1820…1840 20 20 20 20 20 20 20 20 34 20 20 20 20 20 20 20 20 20 49 4e 54 30 0d 0a 6f 76 65 72 66 6c 6f 77 ┆ 4 INT0 overflow┆
0x1840…1860 0d 0a 41 72 72 61 79 20 42 6f 75 6e 64 73 20 20 20 20 20 20 20 20 20 20 35 20 20 20 20 20 20 20 ┆ Array Bounds 5 ┆
0x1860…1880 20 20 42 4f 55 4e 44 0d 0a 55 6e 75 73 65 64 20 4f 70 63 6f 64 65 20 20 20 20 20 20 20 20 20 36 ┆ BOUND Unused Opcode 6┆
0x1880…18a0 20 20 20 20 20 20 20 20 20 55 6e 64 65 66 69 6e 65 64 20 4f 70 63 6f 64 65 73 0d 0a a1 45 53 43 ┆ Undefined Opcodes ESC┆
0x18a0…18c0 20 4f 70 63 6f 64 65 20 20 20 20 20 20 20 20 20 20 20 20 37 20 20 20 20 20 20 20 20 20 45 53 43 ┆ Opcode 7 ESC┆
0x18c0…18e0 20 4f 70 63 6f 64 65 73 05 0d 0a a1 49 6e 74 65 72 72 75 70 74 20 6e 61 6d 65 20 20 20 20 56 65 ┆ Opcodes Interrupt name Ve┆
0x18e0…1900 63 74 6f 72 20 74 79 70 65 20 20 20 52 65 6c 61 74 65 64 20 69 6e 74 65 72 72 75 70 74 20 6c 65 ┆ctor type Related interrupt le┆
0x1900…1920 76 65 6c 05 0d 0a 54 69 6d 65 72 20 30 20 49 6e 74 65 72 72 75 70 74 20 20 20 20 20 38 20 20 20 ┆vel Timer 0 Interrupt 8 ┆
0x1920…1940 20 20 20 20 20 20 20 20 20 20 20 20 38 0d 0a 52 65 73 65 72 76 65 64 20 20 20 20 20 20 20 20 20 ┆ 8 Reserved ┆
0x1940…1960 20 20 20 20 20 39 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2d 0d 0a 44 4d 41 20 30 20 49 6e ┆ 9 - DMA 0 In┆
0x1960…1980 74 65 72 72 75 70 74 20 20 20 20 20 20 31 30 20 20 20 20 20 20 20 20 20 20 20 20 20 20 31 30 0d ┆terrupt 10 10 ┆
0x1980…19a0 0a 44 4d 41 20 31 20 49 6e 74 65 72 72 75 70 74 20 20 20 20 20 20 31 31 20 20 20 20 20 20 20 20 ┆ DMA 1 Interrupt 11 ┆
0x19a0…19c0 20 20 20 20 20 20 31 31 0d 0a 49 4e 54 30 20 49 6e 74 65 72 72 75 70 74 20 20 20 20 20 20 20 31 ┆ 11 INT0 Interrupt 1┆
0x19c0…19e0 32 2a 20 20 20 20 20 20 20 20 20 20 20 20 20 31 32 0d 0a 49 4e 54 31 20 49 6e 74 65 72 72 75 70 ┆2* 12 INT1 Interrup┆
0x19e0…1a00 74 20 20 20 20 20 20 20 31 33 2a 2a 20 20 20 20 20 20 20 20 20 20 20 20 31 33 0d 0a 49 4e 54 32 ┆t 13** 13 INT2┆
0x1a00…1a20 (13,) 20 49 6e 74 65 72 72 75 70 74 20 20 20 20 20 20 20 31 34 2a 20 20 20 20 20 20 20 20 20 20 20 20 ┆ Interrupt 14* ┆
0x1a20…1a40 20 31 34 0d 0a 49 4e 54 33 20 49 6e 74 65 72 72 75 70 74 20 20 20 20 20 20 20 31 35 2a 2a 20 20 ┆ 14 INT3 Interrupt 15** ┆
0x1a40…1a60 20 20 20 20 20 20 20 20 20 20 31 35 0d 0a 54 69 6d 65 72 20 31 20 49 6e 74 65 72 72 75 70 74 20 ┆ 15 Timer 1 Interrupt ┆
0x1a60…1a80 20 20 20 31 38 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 38 0d 0a a1 54 69 6d 65 72 20 32 20 ┆ 18 8 Timer 2 ┆
0x1a80…1aa0 49 6e 74 65 72 72 75 70 74 20 20 20 20 31 39 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 38 05 ┆Interrupt 19 8 ┆
0x1aa0…1ac0 0d 0a 38 32 35 39 20 49 52 30 20 20 20 20 20 20 20 20 20 20 20 20 20 32 30 20 20 20 20 20 20 20 ┆ 8259 IR0 20 ┆
0x1ac0…1ae0 20 20 20 20 20 20 20 32 30 0d 0a 38 32 35 39 20 49 52 31 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ 20 8259 IR1 ┆
0x1ae0…1b00 32 31 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 31 0d 0a 38 32 35 39 20 49 52 32 20 20 20 20 ┆21 21 8259 IR2 ┆
0x1b00…1b20 20 20 20 20 20 20 20 20 20 32 32 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 32 0d 0a 50 61 72 ┆ 22 22 Par┆
0x1b20…1b40 2d 69 6e 74 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 33 20 20 20 20 20 20 20 20 20 20 20 20 ┆-int 23 ┆
0x1b40…1b60 20 20 32 33 0d 0a 38 32 35 39 20 49 52 34 20 20 20 20 20 20 20 20 20 20 20 20 20 32 34 20 20 20 ┆ 23 8259 IR4 24 ┆
0x1b60…1b80 20 20 20 20 20 20 20 20 20 20 20 32 34 0d 0a 38 32 35 39 20 49 52 35 20 20 20 20 20 20 20 20 20 ┆ 24 8259 IR5 ┆
0x1b80…1ba0 20 20 20 20 32 35 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 35 0d 0a 38 32 35 39 20 49 52 36 ┆ 25 25 8259 IR6┆
0x1ba0…1bc0 20 20 20 20 20 20 20 20 20 20 20 20 20 32 36 20 20 20 20 20 20 20 20 20 20 20 20 20 20 32 36 0d ┆ 26 26 ┆
0x1bc0…1be0 0a 38 32 35 39 20 49 52 37 20 20 20 20 20 20 20 20 20 20 20 20 20 32 37 20 20 20 20 20 20 20 20 ┆ 8259 IR7 27 ┆
0x1be0…1c00 20 20 20 20 20 20 32 37 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 46 69 67 75 72 65 ┆ 27 Figure┆
0x1c00…1c20 (14,) 20 35 3a 20 49 6e 74 65 72 72 75 70 74 20 4c 65 76 65 6c 20 54 61 62 6c 65 2e 0d 0a 0d 0a 2a 20 ┆ 5: Interrupt Level Table. * ┆
0x1c20…1c40 49 4e 54 30 20 61 6e 64 20 49 4e 54 32 20 61 72 65 20 75 73 65 64 20 61 73 20 49 4e 54 30 20 61 ┆INT0 and INT2 are used as INT0 a┆
0x1c40…1c60 6e 64 20 49 4e 54 41 30 20 66 6f 72 20 74 68 65 20 38 32 35 39 2e 0d 0a 2a 2a 20 49 4e 54 31 20 ┆nd INTA0 for the 8259. ** INT1 ┆
0x1c60…1c80 61 6e 64 20 49 4e 54 33 20 61 72 65 20 75 73 65 64 20 61 73 20 49 4e 54 31 20 61 6e 64 20 49 4e ┆and INT3 are used as INT1 and IN┆
0x1c80…1c9a 54 41 32 20 66 6f 72 20 74 68 65 20 38 32 37 34 20 4d 50 53 43 2e 0d 0a 0f 0a ┆TA2 for the 8274 MPSC. ┆
0x1c9a…1c9d FormFeed {
0x1c9a…1c9d 0c 83 a4 ┆ ┆
0x1c9a…1c9d }
0x1c9d…1ca0 0a b0 a1 ┆ ┆
0x1ca0…1cc0 b0 b0 a1 35 a1 2e 20 53 65 6c 66 74 65 73 74 20 53 77 69 74 63 68 20 53 65 74 74 69 6e 67 73 2e ┆ 5 . Selftest Switch Settings.┆
0x1cc0…1ce0 0d 0a 0d 0a 54 68 65 20 45 54 43 36 31 31 20 69 73 20 65 71 75 69 70 70 65 64 20 77 69 74 68 20 ┆ The ETC611 is equipped with ┆
0x1ce0…1d00 61 20 53 65 6c 66 74 65 73 74 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 73 77 69 74 63 68 20 ┆a Selftest configuration switch ┆
0x1d00…1d20 0a 28 53 32 33 29 2c 20 77 68 69 63 68 20 69 73 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 74 68 ┆ (S23), which is connected to th┆
0x1d20…1d40 65 20 38 32 35 35 2c 20 50 41 20 70 6f 72 74 2e 0d 0a 0d 0a 50 41 2c 20 62 69 74 20 30 2d 31 20 ┆e 8255, PA port. PA, bit 0-1 ┆
0x1d40…1d60 3a 20 84 54 68 65 73 65 20 62 69 74 73 20 61 72 65 20 75 73 65 64 20 62 79 20 74 68 65 20 6d 65 ┆: These bits are used by the me┆
0x1d60…1d80 6d 6f 72 79 20 74 65 73 74 20 74 6f 20 64 65 74 65 72 6d 69 6e 65 20 0a 19 8e 80 80 74 68 65 20 ┆mory test to determine the ┆
0x1d80…1da0 6f 6e 62 6f 61 72 64 20 6d 65 6d 6f 72 79 20 73 69 7a 65 2e 0d 0a 0d 0a 50 41 2c 20 62 69 74 20 ┆onboard memory size. PA, bit ┆
0x1da0…1dc0 32 20 20 20 3a 20 84 74 68 69 73 20 62 69 74 20 69 73 20 75 73 65 64 20 74 6f 20 63 6f 6e 74 72 ┆2 : this bit is used to contr┆
0x1dc0…1de0 6f 6c 20 74 68 65 20 22 74 65 73 74 2d 6f 75 74 70 75 74 22 2e 0d 0a 0d 0a 50 41 2c 20 62 69 74 ┆ol the "test-output". PA, bit┆
0x1de0…1e00 20 33 20 20 20 3a 20 84 6e 6f 74 20 75 73 65 64 0d 0a 0d 0a 50 41 2c 20 62 69 74 20 34 20 20 20 ┆ 3 : not used PA, bit 4 ┆
0x1e00…1e20 (15,) 3a 20 84 74 68 69 73 20 62 69 74 2c 20 69 66 20 22 31 22 20 6d 61 6b 65 73 20 74 68 65 20 74 65 ┆: this bit, if "1" makes the te┆
0x1e20…1e40 73 74 70 72 6f 67 72 61 6d 20 74 6f 20 61 73 73 75 6d 65 20 61 6e 20 0a 19 8e 80 80 38 20 4d 48 ┆stprogram to assume an 8 MH┆
0x1e40…1e60 7a 20 43 50 55 20 69 6e 73 74 61 6c 6c 65 64 2e 20 54 68 69 73 20 69 6e 66 6f 72 6d 61 74 69 6f ┆z CPU installed. This informatio┆
0x1e60…1e80 6e 20 69 73 20 75 73 65 64 20 74 6f 20 0a 19 8e 80 80 63 6f 6e 74 72 6f 6c 20 74 68 65 20 6f 6e ┆n is used to control the on┆
0x1e80…1ea0 2d 63 68 69 70 20 74 69 6d 65 72 20 75 73 65 64 20 61 73 20 62 61 75 64 72 61 74 65 20 0a 19 8e ┆-chip timer used as baudrate ┆
0x1ea0…1ec0 80 80 67 65 6e 65 72 61 74 6f 72 2e 0d 0a 0d 0a 09 09 09 09 30 30 20 3a 20 35 31 32 20 4b 62 79 ┆ generator. 00 : 512 Kby┆
0x1ec0…1ee0 74 65 73 20 52 41 4d 0d 0a 20 20 20 20 2e 20 2e 20 2e 20 2e 20 2e 09 09 09 30 31 20 3a 20 31 20 ┆tes RAM . . . . . 01 : 1 ┆
0x1ee0…1f00 4d 62 79 74 65 73 20 52 41 4d 20 61 6e 64 20 30 20 43 4f 4d 20 36 30 31 0d 0a 20 20 20 31 b0 2e ┆Mbytes RAM and 0 COM 601 1 .┆
0x1f00…1f20 f0 20 2e 20 2e 20 2e 20 2e 09 09 09 31 30 20 3a 20 31 20 4d 62 79 74 65 73 20 52 41 4d 20 61 6e ┆ . . . . 10 : 1 Mbytes RAM an┆
0x1f20…1f40 64 20 31 20 43 4f 4d 20 36 30 31 0d 0a 20 20 20 20 21 20 21 20 21 20 a1 21 20 21 20 20 20 20 20 ┆d 1 COM 601 ! ! ! ! ! ┆
0x1f40…1f60 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 31 31 20 3a 20 31 20 4d 62 79 74 65 73 20 52 41 ┆ 11 : 1 Mbytes RA┆
0x1f60…1f80 4d 20 61 6e 64 20 32 20 43 4f 4d 20 36 30 31 0d 0a 20 20 20 20 21 20 21 20 21 0d 0a 20 20 20 20 ┆M and 2 COM 601 ! ! ! ┆
0x1f80…1fa0 21 20 21 20 21 09 09 09 20 30 20 3a 20 6f 6e 20 62 6f 61 72 64 20 22 74 65 73 74 2d 6f 75 74 70 ┆! ! ! 0 : on board "test-outp┆
0x1fa0…1fc0 75 74 22 0d 0a 20 20 20 20 21 20 21 20 21 a2 a1 e2 20 20 20 09 09 09 20 31 20 3a 20 22 74 65 73 ┆ut" ! ! ! 1 : "tes┆
0x1fc0…1fe0 74 2d 6f 75 74 70 75 74 22 20 76 69 61 20 4d 42 20 20 20 20 20 20 0d 0a 20 20 20 20 21 20 21 0d ┆t-output" via MB ! ! ┆
0x1fe0…2000 0a 20 20 20 20 21 20 21 09 09 09 20 30 20 3a 20 6e 6f 74 20 75 73 65 64 0d 0a 20 20 20 20 21 20 ┆ ! ! 0 : not used ! ┆
0x2000…2020 (16,) 21 a1 09 09 09 20 31 20 3a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆! 1 : ┆
0x2020…2040 20 20 20 20 0d 0a 20 20 20 20 21 0d 0a 20 20 20 20 21 09 09 09 20 30 20 3a 20 36 20 4d 48 7a 20 ┆ ! ! 0 : 6 MHz ┆
0x2040…2060 69 41 50 58 31 38 36 20 0d 0a 20 20 20 20 21 a1 20 09 09 09 20 31 20 3a 20 38 20 4d 48 7a 20 69 ┆iAPX186 ! 1 : 8 MHz i┆
0x2060…2080 41 50 58 31 38 36 20 20 20 20 20 20 20 20 20 20 20 20 20 0d 0a 0d 0a a1 e1 e1 e1 0d 0a 20 20 20 ┆APX186 ┆
0x2080…20a0 20 20 20 20 20 20 20 20 20 20 20 a1 46 69 67 75 72 65 20 38 20 3a 20 54 68 65 20 53 32 33 20 6a ┆ Figure 8 : The S23 j┆
0x20a0…20ad 75 6d 70 65 72 20 61 72 65 61 2e 0d 0a ┆umper area. ┆
0x20ad…20b0 FormFeed {
0x20ad…20b0 0c 83 8c ┆ ┆
0x20ad…20b0 }
0x20b0…20c0 0a b0 a1 36 2e 20 49 6e 69 74 69 61 6c 69 7a 61 ┆ 6. Initializa┆
0x20c0…20e0 74 69 6f 6e 2e 0d 0a 0d 0a 41 66 74 65 72 20 70 6f 77 65 72 20 75 70 2f 72 65 73 65 74 20 74 68 ┆tion. After power up/reset th┆
0x20e0…2100 65 20 45 54 43 36 31 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 77 69 6c 6c 20 70 65 72 66 6f ┆e ETC611 SBC Selftest will perfo┆
0x2100…2120 72 6d 20 73 6f 6d 65 20 0a 69 6e 69 74 69 61 6c 69 7a 61 74 69 6f 6e 73 20 6f 66 20 74 68 65 20 ┆rm some initializations of the ┆
0x2120…2140 6f 6e 62 6f 61 72 64 20 63 6f 6e 74 72 6f 6c 6c 65 72 73 2e 0d 0a 0d 0a 54 68 65 20 69 6e 69 74 ┆onboard controllers. The init┆
0x2140…2160 69 61 6c 69 7a 61 74 69 6f 6e 73 20 61 72 65 20 63 6f 6d 6d 6f 6e 20 66 6f 72 20 74 68 65 20 53 ┆ializations are common for the S┆
0x2160…2180 65 6c 66 74 65 73 74 20 61 6e 64 20 74 68 65 20 0a 62 6f 6f 74 6c 6f 61 64 65 72 2e 0d 0a 0d 0a ┆elftest and the bootloader. ┆
0x2180…21a0 0d 0a b0 a1 f0 b0 36 2e 31 20 57 61 69 74 20 53 74 61 74 65 73 2e 0d 0a 0d 0a 54 68 65 20 50 52 ┆ 6.1 Wait States. The PR┆
0x21a0…21c0 4f 4d 20 61 6e 64 20 52 41 4d 20 6d 65 6d 6f 72 79 20 77 69 6c 6c 20 68 61 76 65 20 30 20 77 61 ┆OM and RAM memory will have 0 wa┆
0x21c0…21e0 69 74 20 73 74 61 74 65 73 2e 0d 0a 0d 0a 50 68 65 72 69 70 68 65 72 61 6c 73 20 6f 6e 20 50 43 ┆it states. Pheripherals on PC┆
0x21e0…2200 53 20 30 2d 33 20 77 69 6c 6c 20 68 61 76 65 20 31 20 77 61 69 74 20 73 74 61 74 65 0d 0a 50 68 ┆S 0-3 will have 1 wait state Ph┆
0x2200…2220 (17,) 65 72 69 70 68 65 72 61 6c 73 20 6f 6e 20 50 43 53 20 34 2d 36 20 77 69 6c 6c 20 68 61 76 65 20 ┆eripherals on PCS 4-6 will have ┆
0x2220…2240 32 20 77 61 69 74 20 73 74 61 74 65 73 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 b0 36 2e 32 20 69 41 50 58 ┆2 wait states. 6.2 iAPX┆
0x2240…2260 31 38 36 20 49 6e 74 65 72 72 75 70 74 20 43 6f 6e 74 72 6f 6c 6c 65 72 2e 0d 0a 0d 0a 54 68 65 ┆186 Interrupt Controller. The┆
0x2260…2280 20 69 6e 74 65 72 72 75 70 74 20 76 65 63 74 6f 72 20 66 6f 72 20 74 68 65 20 69 41 50 58 31 38 ┆ interrupt vector for the iAPX18┆
0x2280…22a0 36 20 63 6f 6e 74 72 6f 6c 6c 65 72 73 20 69 73 20 74 69 65 64 20 74 6f 20 0a 73 70 65 63 69 66 ┆6 controllers is tied to specif┆
0x22a0…22c0 69 63 20 6d 65 6d 6f 72 79 20 6c 6f 63 61 74 69 6f 6e 73 2c 20 65 71 75 61 6c 20 74 6f 20 74 68 ┆ic memory locations, equal to th┆
0x22c0…22e0 65 20 6c 6f 63 61 74 69 6f 6e 20 32 30 48 20 66 6f 72 20 74 68 65 20 0a 66 69 72 73 74 20 76 65 ┆e location 20H for the first ve┆
0x22e0…2300 63 74 6f 72 20 69 6e 20 74 68 65 20 74 61 62 6c 65 2e 20 53 65 65 20 73 65 63 74 69 6f 6e 20 32 ┆ctor in the table. See section 2┆
0x2300…2320 2e 35 2e 0d 0a 0d 0a 09 1f a1 49 4e 54 30 2f 49 4e 54 32 3a 0d 0a 20 20 20 20 20 20 20 20 20 50 ┆.5. INT0/INT2: P┆
0x2320…2340 6f 72 74 20 20 3a 20 46 46 33 38 48 0d 0a 20 20 20 20 20 20 20 20 20 56 61 6c 75 65 20 3a 20 33 ┆ort : FF38H Value : 3┆
0x2340…2360 37 48 0d 0a 0d 0a 54 68 65 73 65 20 74 77 6f 20 70 69 6e 73 20 6f 66 20 74 68 65 20 69 41 50 58 ┆7H These two pins of the iAPX┆
0x2360…2380 31 38 36 20 69 73 20 75 73 65 64 20 66 6f 72 20 63 61 73 63 61 64 69 6e 67 20 74 6f 20 74 68 65 ┆186 is used for cascading to the┆
0x2380…23a0 20 65 78 74 65 72 6e 20 0a 69 6e 74 65 72 72 75 70 74 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 38 32 ┆ extern interrupt controller 82┆
0x23a0…23c0 35 39 2e 0d 0a 0d 0a 09 a1 49 4e 54 31 2f 49 4e 54 33 3a 0d 0a 20 20 20 20 20 20 20 20 50 6f 72 ┆59. INT1/INT3: Por┆
0x23c0…23e0 74 20 20 3a 20 46 46 33 41 48 0d 0a 20 20 20 20 20 20 20 20 56 61 6c 75 65 20 3a 20 33 37 48 0d ┆t : FF3AH Value : 37H ┆
0x23e0…2400 0a 0d 0a 8c 83 98 0a 54 68 65 73 65 20 74 77 6f 20 70 69 6e 73 20 6f 66 20 74 68 65 20 69 41 50 ┆ These two pins of the iAP┆
0x2400…2420 (18,) 58 38 30 31 38 36 20 69 73 20 75 73 65 64 20 66 6f 72 20 63 61 73 63 61 64 69 6e 67 20 74 6f 20 ┆X80186 is used for cascading to ┆
0x2420…2440 74 68 65 20 4d 50 53 43 20 0a 38 32 37 34 2e 0d 0a 0d 0a 09 a1 4d 61 73 6b 20 52 65 67 69 73 74 ┆the MPSC 8274. Mask Regist┆
0x2440…2460 65 72 3a 0d 0a 20 20 20 20 20 20 20 20 50 6f 72 74 20 20 3a 20 46 46 32 38 48 0d 0a 20 20 20 20 ┆er: Port : FF28H ┆
0x2460…2480 20 20 20 20 56 61 6c 75 65 20 3a 20 46 44 48 0d 0a 0d 0a 57 68 69 63 68 20 77 69 6c 6c 20 6d 61 ┆ Value : FDH Which will ma┆
0x2480…24a0 73 6b 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 3a 0d 0a 0d 0a 09 49 33 20 20 3a 20 31 09 3b 20 ┆sk the following: I3 : 1 ; ┆
0x24a0…24c0 49 4e 54 33 0d 0a 09 49 32 20 20 3a 20 31 09 3b 20 49 4e 54 32 0d 0a 09 49 31 20 20 3a 20 31 09 ┆INT3 I2 : 1 ; INT2 I1 : 1 ┆
0x24c0…24e0 3b 20 49 4e 54 31 0d 0a 09 49 30 20 20 3a 20 30 09 3b 20 49 4e 54 30 0d 0a 09 44 31 20 20 3a 20 ┆; INT1 I0 : 0 ; INT0 D1 : ┆
0x24e0…2500 31 09 3b 20 44 4d 41 31 0d 0a 09 44 30 20 20 3a 20 31 09 3b 20 44 4d 41 30 0d 0a 09 54 52 4d 20 ┆1 ; DMA1 D0 : 1 ; DMA0 TRM ┆
0x2500…2520 3a 20 31 09 3b 20 54 69 6d 65 72 73 0d 0a 0d 0a 0d 0a b0 a1 f0 b0 36 2e 33 20 50 72 6f 67 72 61 ┆: 1 ; Timers 6.3 Progra┆
0x2520…2540 6d 61 62 6c 65 20 49 6e 74 65 72 72 75 70 74 20 43 6f 6e 74 72 6f 6c 6c 65 72 20 38 32 35 39 2e ┆mable Interrupt Controller 8259.┆
0x2540…2560 0d 0a 0d 0a 54 68 65 20 45 54 43 36 30 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 69 73 20 63 ┆ The ETC601 SBC Selftest is c┆
0x2560…2580 6f 6e 66 69 67 75 72 61 74 65 64 20 77 69 74 68 20 55 53 41 52 54 20 70 61 72 69 74 79 20 0a 69 ┆onfigurated with USART parity i┆
0x2580…25a0 6e 74 65 72 72 75 70 74 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 49 52 33 2e 0d 0a 0d 0a 09 a1 ┆nterrupt connected to IR3. ┆
0x25a0…25c0 38 32 35 39 20 73 65 74 75 70 3a 0d 0a 20 20 20 20 20 20 20 20 49 43 57 20 31 20 3a 20 31 42 48 ┆8259 setup: ICW 1 : 1BH┆
0x25c0…25e0 20 20 3b 20 6c 65 76 65 6c 20 74 72 69 67 67 65 72 65 64 20 69 6e 70 75 74 2c 20 73 69 6e 67 6c ┆ ; level triggered input, singl┆
0x25e0…2600 65 20 6d 6f 64 65 0d 0a 20 20 20 20 20 20 20 20 49 43 57 20 32 20 3a 20 32 30 48 20 20 3b 20 74 ┆e mode ICW 2 : 20H ; t┆
0x2600…2620 (19,) 68 65 20 69 6e 74 65 72 72 75 70 74 20 76 65 63 74 6f 72 20 74 61 62 6c 65 20 73 74 61 72 74 73 ┆he interrupt vector table starts┆
0x2620…2640 20 69 6e 20 38 30 48 0d 0a 20 20 20 20 20 20 20 20 49 43 57 20 34 20 3a 20 31 44 48 20 20 84 3b ┆ in 80H ICW 4 : 1DH ;┆
0x2640…2660 20 6e 6f 6e 20 62 75 66 66 65 72 20 6d 6f 64 65 2c 20 6e 6f 72 6d 61 6c 20 45 4f 49 20 61 6e 64 ┆ non buffer mode, normal EOI and┆
0x2660…2680 20 6e 6f 74 20 66 75 6c 6c 79 20 0a 19 95 80 80 3b 20 6e 65 73 74 65 64 2e 0d 0a 20 20 20 20 20 ┆ not fully ; nested. ┆
0x2680…26a0 20 20 20 4d 41 53 4b 20 20 3a 20 46 37 48 20 20 3b 20 65 6e 61 62 6c 65 20 70 61 72 69 74 79 20 ┆ MASK : F7H ; enable parity ┆
0x26a0…26c0 69 6e 74 65 72 72 75 70 74 20 6f 6e 20 49 52 33 2e 0d 0a 0d 0a 0d 0a b0 a1 f0 b0 36 2e 34 20 69 ┆interrupt on IR3. 6.4 i┆
0x26c0…26e0 41 50 58 31 38 36 20 54 69 6d 65 72 20 31 2e 0d 0a 0d 0a 54 69 6d 65 72 20 31 20 69 73 20 69 6e ┆APX186 Timer 1. Timer 1 is in┆
0x26e0…2700 69 74 69 61 6c 69 7a 65 64 20 61 73 20 61 20 62 61 75 64 72 61 74 65 20 67 65 6e 65 72 61 74 6f ┆itialized as a baudrate generato┆
0x2700…2720 72 20 69 6e 20 61 6c 74 65 72 6e 61 74 69 6e 67 20 0a 6d 6f 64 65 20 77 69 74 68 20 65 76 65 6e ┆r in alternating mode with even┆
0x2720…2740 20 64 75 74 79 20 63 79 63 6c 65 2e 20 49 66 20 6e 6f 20 63 6f 6e 73 6f 6c 65 20 69 73 20 63 6f ┆ duty cycle. If no console is co┆
0x2740…2760 6e 6e 65 63 74 65 64 20 74 68 65 20 0a 62 61 75 64 72 61 74 65 20 69 73 20 73 65 74 20 74 6f 20 ┆nnected the baudrate is set to ┆
0x2760…2780 39 36 30 30 20 62 61 75 64 2c 20 6f 74 68 65 72 77 69 73 65 20 74 68 65 20 42 61 75 64 20 52 61 ┆9600 baud, otherwise the Baud Ra┆
0x2780…27a0 74 65 20 0a 44 65 74 65 72 6d 69 6e 61 74 69 6f 6e 20 70 72 6f 63 65 64 75 72 65 20 69 73 20 65 ┆te Determination procedure is e┆
0x27a0…27c0 6e 74 65 72 65 64 20 73 65 65 20 63 68 61 70 74 65 72 20 36 2e 0d 0a 0d 0a 0d 0a 8c 83 d4 0a b0 ┆ntered see chapter 6. ┆
0x27c0…27e0 a1 f0 b0 36 2e 35 20 4d 50 53 43 20 38 32 37 34 20 43 68 2e 20 42 20 28 43 6f 6e 73 6f 6c 65 20 ┆ 6.5 MPSC 8274 Ch. B (Console ┆
0x27e0…2800 49 6e 74 65 72 66 61 63 65 29 2e 0d 0a 0d 0a 42 61 75 64 72 61 74 65 20 66 61 63 74 6f 72 20 20 ┆Interface). Baudrate factor ┆
0x2800…2820 (20,) 3a 20 58 31 36 0d 0a 43 68 61 72 61 63 74 65 72 20 6c 65 6e 67 74 68 20 3a 20 38 20 62 69 74 73 ┆: X16 Character length : 8 bits┆
0x2820…2840 0d 0a 50 61 72 69 74 79 20 20 20 20 20 20 20 20 20 20 20 3a 20 6e 6f 6e 65 0d 0a 53 74 6f 70 20 ┆ Parity : none Stop ┆
0x2840…2860 62 69 74 73 20 20 20 20 20 20 20 20 3a 20 32 0d 0a 4d 6f 64 65 20 20 20 20 20 20 20 20 20 20 20 ┆bits : 2 Mode ┆
0x2860…2874 20 20 3a 20 61 73 79 6e 63 68 72 6f 6e 6f 75 73 2e 0d 0a 0a ┆ : asynchronous. ┆
0x2874…2877 FormFeed {
0x2874…2877 0c 80 e0 ┆ ┆
0x2874…2877 }
0x2877…2880 0a a1 b0 37 2e 20 b0 54 65 ┆ 7. Te┆
0x2880…28a0 73 74 20 30 20 3d 20 f0 4d 45 4d 4f 52 59 20 54 45 53 54 2e 0d 0a 0d 0a 54 68 65 20 6d 65 6d 6f ┆st 0 = MEMORY TEST. The memo┆
0x28a0…28c0 72 79 20 74 65 73 74 20 6f 66 20 74 68 65 20 45 54 43 20 36 31 31 20 53 42 43 20 73 65 6c 66 74 ┆ry test of the ETC 611 SBC selft┆
0x28c0…28e0 65 73 74 20 63 6f 6e 73 69 73 74 73 20 6f 66 20 74 77 6f 20 0a 70 61 72 74 73 2c 20 61 20 50 52 ┆est consists of two parts, a PR┆
0x28e0…2900 4f 4d 20 63 68 65 63 6b 73 75 6d 20 74 65 73 74 20 61 6e 64 20 61 20 52 41 4d 20 6d 65 6d 6f 72 ┆OM checksum test and a RAM memor┆
0x2900…2920 79 20 74 65 73 74 2e 20 54 68 65 20 50 52 4f 4d 20 0a 63 68 65 63 6b 73 75 6d 20 74 65 73 74 20 ┆y test. The PROM checksum test ┆
0x2920…2940 69 73 20 6f 6e 6c 79 20 72 75 6e 20 6f 6e 63 65 20 61 66 74 65 72 20 70 6f 77 65 72 20 75 70 20 ┆is only run once after power up ┆
0x2940…2960 6f 72 20 65 78 74 65 72 6e 61 6c 20 72 65 73 65 74 2c 20 0a 77 68 65 72 65 61 73 20 74 68 65 20 ┆or external reset, whereas the ┆
0x2960…2980 52 41 4d 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 6d 61 79 20 62 65 20 72 75 6e 20 73 65 76 65 72 ┆RAM memory test may be run sever┆
0x2980…29a0 61 6c 20 74 69 6d 65 73 2c 20 69 66 20 0a 72 65 71 75 65 73 74 65 64 20 62 79 20 74 68 65 20 6f ┆al times, if requested by the o┆
0x29a0…29c0 70 65 72 61 74 6f 72 2e 0d 0a 0d 0a 0d 0a a1 b0 37 2e 31 20 50 52 4f 4d 20 43 68 65 63 6b 73 75 ┆perator. 7.1 PROM Checksu┆
0x29c0…29e0 6d 20 54 65 73 74 2e 0d 0a 0d 0a 54 68 65 20 63 6f 6e 74 65 6e 74 73 20 6f 66 20 62 6f 74 68 20 ┆m Test. The contents of both ┆
0x29e0…2a00 74 68 65 20 6f 64 64 20 61 6e 64 20 74 68 65 20 65 76 65 6e 20 50 52 4f 4d 20 61 72 65 20 73 75 ┆the odd and the even PROM are su┆
0x2a00…2a20 (21,) 6d 6d 61 72 69 7a 65 64 20 0a 62 79 74 65 77 69 73 65 20 61 6e 64 20 74 68 65 20 72 65 73 75 6c ┆mmarized bytewise and the resul┆
0x2a20…2a40 74 20 6d 75 73 74 20 62 65 20 61 20 7a 65 72 6f 2e 20 46 6f 72 20 74 68 61 74 20 72 65 61 73 6f ┆t must be a zero. For that reaso┆
0x2a40…2a60 6e 20 74 68 65 20 0a 50 52 4f 4d 27 73 20 63 6f 6e 74 61 69 6e 20 61 20 63 6f 6d 70 65 6e 73 61 ┆n the PROM's contain a compensa┆
0x2a60…2a80 74 69 6f 6e 20 62 79 74 65 20 77 68 69 63 68 20 69 73 20 75 73 65 64 20 74 6f 20 62 72 69 6e 67 ┆tion byte which is used to bring┆
0x2a80…2aa0 20 74 68 65 20 73 75 6d 20 0a 74 6f 20 7a 65 72 6f 2e 0d 0a a1 0d 0a b0 f0 31 2e 20 b0 63 68 65 ┆ the sum to zero. 1. che┆
0x2aa0…2ac0 63 6b 73 75 6d 20 74 65 73 74 3a 20 73 75 6d 20 65 72 72 6f 72 20 20 65 78 70 2e 3a 3c 30 30 30 ┆cksum test: sum error exp.:<000┆
0x2ac0…2ae0 30 3e 20 20 72 65 63 2e 3a 3c 78 79 7a 77 3e 0d 0a 0d 0a 43 68 65 63 6b 73 75 6d 20 65 72 72 6f ┆0> rec.:<xyzw> Checksum erro┆
0x2ae0…2b00 72 20 75 73 75 61 6c 6c 79 20 6d 65 61 6e 73 20 74 68 61 74 20 74 68 65 20 63 6f 6e 74 65 6e 74 ┆r usually means that the content┆
0x2b00…2b20 20 6f 66 20 74 68 65 20 50 52 4f 4d 20 68 61 73 20 0a 62 65 65 6e 20 64 61 6d 61 67 65 64 20 61 ┆ of the PROM has been damaged a┆
0x2b20…2b40 6e 64 20 74 68 61 74 20 74 68 65 20 50 52 4f 4d 20 6d 75 73 74 20 62 65 20 63 68 61 6e 67 65 64 ┆nd that the PROM must be changed┆
0x2b40…2b47 2e 0d 0a 0d 0a 0d 0a ┆. ┆
0x2b47…2b4a FormFeed {
0x2b47…2b4a 0c 82 88 ┆ ┆
0x2b47…2b4a }
0x2b4a…2b60 0a a1 b0 37 2e 32 20 52 41 4d 20 4d 65 6d 6f 72 79 20 54 65 73 74 ┆ 7.2 RAM Memory Test┆
0x2b60…2b80 2e 0d 0a 0d 0a 54 68 65 20 52 41 4d 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 6f 66 20 74 68 65 20 ┆. The RAM memory test of the ┆
0x2b80…2ba0 45 54 43 20 36 31 31 20 53 42 43 20 73 65 6c 66 74 65 73 74 20 76 65 72 69 66 69 65 73 20 74 68 ┆ETC 611 SBC selftest verifies th┆
0x2ba0…2bc0 65 20 6f 6e 2d 0a 62 6f 61 72 64 20 6d 65 6d 6f 72 79 2e 20 54 68 65 20 73 69 7a 65 20 6f 66 20 ┆e on- board memory. The size of ┆
0x2bc0…2be0 52 41 4d 20 69 73 20 64 65 74 65 72 6d 69 6e 65 64 20 66 72 6f 6d 20 72 65 61 64 69 6e 67 20 74 ┆RAM is determined from reading t┆
0x2be0…2c00 68 65 20 6f 6e 20 0a 62 6f 61 72 64 20 73 74 72 61 70 73 20 6f 6e 20 74 68 65 20 38 32 35 35 20 ┆he on board straps on the 8255 ┆
0x2c00…2c20 (22,) 70 61 72 61 6c 6c 65 6c 20 70 6f 72 74 20 41 2e 20 56 61 6c 69 64 20 6d 65 6d 6f 72 79 20 73 69 ┆parallel port A. Valid memory si┆
0x2c20…2c40 7a 65 73 20 61 72 65 20 0a 31 20 4d 20 42 79 74 65 73 20 6f 72 20 35 31 32 20 4b 62 79 74 65 73 ┆zes are 1 M Bytes or 512 Kbytes┆
0x2c40…2c60 2e 20 49 66 20 31 20 4d 20 62 79 74 65 73 20 61 72 65 20 70 72 65 73 65 6e 74 20 73 6f 6d 65 20 ┆. If 1 M bytes are present some ┆
0x2c60…2c80 6f 66 20 74 68 65 20 52 41 4d 20 0a 63 61 6e 6e 6f 74 20 62 65 20 75 73 65 64 20 62 79 20 74 68 ┆of the RAM cannot be used by th┆
0x2c80…2ca0 65 20 45 54 43 20 36 31 31 20 69 74 73 65 6c 66 2e 20 54 68 65 20 75 70 70 65 72 20 36 34 20 4b ┆e ETC 611 itself. The upper 64 K┆
0x2ca0…2cc0 62 79 74 65 73 20 61 72 65 20 0a 72 65 73 65 72 76 65 64 20 74 6f 20 6f 6e 62 6f 61 72 64 20 50 ┆bytes are reserved to onboard P┆
0x2cc0…2ce0 52 4f 4d 20 73 70 61 63 65 20 61 6e 64 20 69 73 20 75 73 65 6c 65 73 73 2e 20 49 66 20 6f 6e 65 ┆ROM space and is useless. If one┆
0x2ce0…2d00 20 43 4f 4d 20 36 30 31 20 69 73 20 0a 70 72 65 73 65 6e 74 20 74 68 65 20 75 70 70 65 72 20 31 ┆ COM 601 is present the upper 1┆
0x2d00…2d20 32 38 20 4b 62 79 74 65 73 20 61 72 65 20 6f 63 63 75 70 69 65 64 2c 20 61 6e 64 20 69 66 20 74 ┆28 Kbytes are occupied, and if t┆
0x2d20…2d40 77 6f 20 43 4f 4d 20 36 30 31 20 61 72 65 20 0a 70 72 65 73 65 6e 74 20 74 68 65 6e 20 74 68 65 ┆wo COM 601 are present then the┆
0x2d40…2d60 20 75 70 70 65 72 20 32 35 36 20 4b 62 79 74 65 73 20 61 72 65 20 73 68 61 64 6f 77 65 64 2e 20 ┆ upper 256 Kbytes are shadowed. ┆
0x2d60…2d80 4e 4f 54 45 20 74 68 61 74 20 74 68 65 20 0a 73 68 61 64 6f 77 65 64 20 52 41 4d 20 69 73 20 61 ┆NOTE that the shadowed RAM is a┆
0x2d80…2da0 76 61 69 6c 61 62 6c 65 20 74 6f 20 6f 74 68 65 72 20 4d 75 6c 74 69 62 75 73 20 4d 61 73 74 65 ┆vailable to other Multibus Maste┆
0x2da0…2dc0 72 73 20 3f 0d 0a 0d 0a 54 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 69 73 20 61 20 72 65 67 ┆rs ? The memory test is a reg┆
0x2dc0…2de0 69 73 74 65 72 20 62 61 73 65 64 20 74 65 73 74 20 61 6e 64 20 75 73 65 73 20 6e 6f 20 6d 65 6d ┆ister based test and uses no mem┆
0x2de0…2e00 6f 72 79 20 73 70 61 63 65 20 0a 61 74 20 61 6c 6c 2c 20 6e 65 69 74 68 65 72 20 66 6f 72 20 76 ┆ory space at all, neither for v┆
0x2e00…2e20 (23,) 61 72 69 61 62 6c 65 73 20 6e 6f 72 20 73 74 61 63 6b 2e 20 54 68 65 20 74 65 73 74 20 76 65 72 ┆ariables nor stack. The test ver┆
0x2e20…2e40 69 66 69 65 73 20 65 76 65 72 79 20 0a 73 69 6e 67 6c 65 20 62 79 74 65 20 6f 66 20 74 68 65 20 ┆ifies every single byte of the ┆
0x2e40…2e60 6f 6e 2d 62 6f 61 72 64 20 6d 65 6d 6f 72 79 2e 0d 0a 0d 0a 54 68 69 73 20 66 61 63 74 20 6c 65 ┆on-board memory. This fact le┆
0x2e60…2e80 74 73 20 6f 6e 6c 79 20 6f 6e 65 20 72 65 67 69 73 74 65 72 20 66 6f 72 20 74 65 73 74 20 76 61 ┆ts only one register for test va┆
0x2e80…2ea0 72 69 61 62 6c 65 73 20 73 75 72 76 69 76 65 20 74 68 65 20 0a 6d 65 6d 6f 72 79 20 74 65 73 74 ┆riables survive the memory test┆
0x2ea0…2ec0 2e 20 54 68 61 74 20 76 61 72 69 61 62 6c 65 20 63 6f 6e 74 61 69 6e 73 20 61 6c 6c 20 74 68 65 ┆. That variable contains all the┆
0x2ec0…2ee0 20 74 65 73 74 20 73 77 69 74 63 68 65 73 20 61 6e 64 20 74 68 65 20 0a 74 65 73 74 20 6e 75 6d ┆ test switches and the test num┆
0x2ee0…2f00 62 65 72 2e 20 20 0d 0a 0d 0a 0d 0a a1 b0 37 2e 32 2e 31 20 4d 65 6d 6f 72 79 20 54 65 73 74 20 ┆ber. 7.2.1 Memory Test ┆
0x2f00…2f20 50 61 74 74 65 72 6e 2e 0d 0a 0d 0a 54 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 65 78 65 63 ┆Pattern. The memory test exec┆
0x2f20…2f40 75 74 65 73 20 34 20 70 61 73 73 65 73 20 74 72 6f 75 67 68 20 74 68 65 20 65 6e 74 69 72 65 20 ┆utes 4 passes trough the entire ┆
0x2f40…2f60 6d 65 6d 6f 72 79 2c 20 74 77 6f 20 0a 74 69 6d 65 73 20 77 72 69 74 69 6e 67 20 61 6e 64 20 74 ┆memory, two times writing and t┆
0x2f60…2f80 77 6f 20 74 69 6d 65 73 20 72 65 61 64 69 6e 67 2e 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 70 61 ┆wo times reading. The test pa┆
0x2f80…2fa0 74 74 65 72 6e 20 69 73 20 74 68 65 20 63 6f 6e 76 65 6e 69 65 6e 74 20 6d 6f 64 75 6c 75 73 20 ┆ttern is the convenient modulus ┆
0x2fa0…2fc0 33 20 70 61 74 74 65 72 6e 20 63 6f 6e 73 69 73 74 69 6e 67 20 0a 6f 66 20 74 68 72 65 65 20 74 ┆3 pattern consisting of three t┆
0x2fc0…2fe0 69 6d 65 73 20 30 30 30 30 20 66 6f 6c 6c 6f 77 65 64 20 62 79 20 74 68 72 65 65 20 74 69 6d 65 ┆imes 0000 followed by three time┆
0x2fe0…2ffb 73 20 46 46 46 46 20 28 68 65 78 61 64 65 63 69 6d 61 6c 29 2e 0d 0a 0d 0a 0d 0a ┆s FFFF (hexadecimal). ┆
0x2ffb…2ffe FormFeed {
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0x2ffe…3000 0a a1 ┆ ┆
0x3000…3020 (24,) b0 37 2e 32 2e 32 20 4d 65 6d 6f 72 79 20 54 65 73 74 20 46 6c 6f 77 2e 0d 0a 0d 0a 54 68 65 20 ┆ 7.2.2 Memory Test Flow. The ┆
0x3020…3040 74 65 73 74 20 73 74 61 72 74 73 20 69 6e 20 74 68 65 20 68 69 67 68 65 73 74 20 52 41 4d 20 61 ┆test starts in the highest RAM a┆
0x3040…3060 64 64 72 65 73 73 65 73 20 61 6e 64 20 69 6e 73 65 72 74 73 20 74 68 65 20 0a 70 61 74 74 65 72 ┆ddresses and inserts the patter┆
0x3060…3080 6e 20 74 6f 77 61 72 64 73 20 6c 6f 77 65 72 20 61 64 64 72 65 73 73 65 73 2e 0d 0a 0d 0a 57 68 ┆n towards lower addresses. Wh┆
0x3080…30a0 65 6e 20 61 6c 6c 20 6d 65 6d 6f 72 79 20 77 6f 72 64 73 20 68 61 76 65 20 62 65 65 6e 20 77 72 ┆en all memory words have been wr┆
0x30a0…30c0 69 74 74 65 6e 20 61 6e 64 20 76 65 72 69 66 69 65 64 2c 20 74 68 65 79 20 61 72 65 20 0a 74 65 ┆itten and verified, they are te┆
0x30c0…30e0 73 74 65 64 20 61 67 61 69 6e 20 77 69 74 68 20 74 68 65 20 69 6e 76 65 72 73 65 64 20 70 61 74 ┆sted again with the inversed pat┆
0x30e0…3100 74 65 72 6e 2c 20 74 68 69 73 20 6d 65 61 6e 73 2c 20 74 68 61 74 20 61 6c 6c 20 62 69 74 73 20 ┆tern, this means, that all bits ┆
0x3100…3120 0a 61 72 65 20 74 65 73 74 65 64 20 66 6f 72 20 22 7a 65 72 6f 22 20 61 6e 64 20 22 6f 6e 65 22 ┆ are tested for "zero" and "one"┆
0x3120…3140 20 69 6e 73 65 72 74 69 6f 6e 2e 20 49 66 20 61 6e 20 65 72 72 6f 72 20 6f 63 63 75 72 20 74 68 ┆ insertion. If an error occur th┆
0x3140…3160 65 6e 20 0a 61 6e 20 61 74 74 65 6d 70 74 20 74 6f 20 73 65 6e 64 20 74 68 65 20 66 6f 6c 6c 6f ┆en an attempt to send the follo┆
0x3160…3180 77 69 6e 67 20 6d 65 73 73 61 67 65 2c 20 74 6f 20 74 68 65 20 22 74 65 73 74 2d 6f 75 74 70 75 ┆wing message, to the "test-outpu┆
0x3180…31a0 74 22 2c 20 0a 69 73 20 6d 61 64 65 20 3a 0d 0a 0d 0a a1 b0 f0 32 2e 20 b0 52 41 4d 20 74 65 73 ┆t", is made : 2. RAM tes┆
0x31a0…31c0 74 3a 20 52 41 4d 20 65 72 72 6f 72 20 20 73 65 67 6d 2e 3a 3c 73 73 73 73 3e 20 20 61 64 64 72 ┆t: RAM error segm.:<ssss> addr┆
0x31c0…31e0 2e 3a 3c 61 61 61 61 3e 20 20 65 78 70 2e 3a 3c 65 65 65 65 3e 0d 0a 09 20 09 09 09 20 20 20 20 ┆.:<aaaa> exp.:<eeee> ┆
0x31e0…3200 20 20 20 20 20 20 20 20 20 20 20 20 20 b0 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 0d 0a 54 68 ┆ rec.:<rrrr> Th┆
0x3200…3220 (25,) 65 20 73 65 63 6f 6e 64 61 72 79 20 74 65 78 74 20 69 73 20 69 6e 74 65 72 70 72 65 74 65 64 20 ┆e secondary text is interpreted ┆
0x3220…3240 6c 69 6b 65 20 74 68 69 73 20 3a 0d 0a 0d 0a 3c 73 73 73 73 3e 20 69 73 20 74 68 65 20 73 65 67 ┆like this : <ssss> is the seg┆
0x3240…3260 6d 65 6e 74 20 61 64 64 72 65 73 73 0d 0a 3c 61 61 61 61 3e 20 69 73 20 74 68 65 20 61 64 64 72 ┆ment address <aaaa> is the addr┆
0x3260…3280 65 73 73 20 6f 66 66 73 65 74 0d 0a 3c 65 65 65 65 3e 20 69 73 20 74 68 65 20 65 78 70 65 63 74 ┆ess offset <eeee> is the expect┆
0x3280…32a0 65 64 20 70 61 74 74 65 72 6e 2c 20 73 68 6f 75 6c 64 20 61 6c 6c 77 61 79 73 20 62 65 20 30 30 ┆ed pattern, should allways be 00┆
0x32a0…32c0 30 30 20 6f 72 20 46 46 46 46 2e 0d 0a 3c 72 72 72 72 3e 20 69 73 20 74 68 65 20 72 65 63 65 69 ┆00 or FFFF. <rrrr> is the recei┆
0x32c0…32e0 76 65 64 20 70 61 74 74 65 72 6e 2e 0d 0a 0d 0a 54 68 65 20 61 62 6f 76 65 20 6d 65 6e 74 69 6f ┆ved pattern. The above mentio┆
0x32e0…3300 6e 65 64 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 20 6d 61 79 20 62 65 20 75 73 65 64 20 74 6f 20 66 ┆ned information may be used to f┆
0x3300…3320 69 6e 64 20 61 20 64 65 66 65 63 74 69 76 65 20 0a 52 41 4d 20 6d 65 6d 6f 72 79 20 63 68 69 70 ┆ind a defective RAM memory chip┆
0x3320…3340 20 66 72 6f 6d 20 74 68 65 20 6b 6e 6f 77 6c 65 64 67 65 20 6f 66 20 74 68 65 20 52 41 4d 2d 6c ┆ from the knowledge of the RAM-l┆
0x3340…3360 61 79 6f 75 74 2e 0d 0a 0d 0a 0d 0a a1 b0 37 2e 32 2e 33 20 4c 6f 6f 70 20 4f 6e 20 45 72 72 6f ┆ayout. 7.2.3 Loop On Erro┆
0x3360…3380 72 2e 0d 0a 0d 0a 57 68 65 6e 20 61 20 66 61 75 6c 74 20 6f 63 63 75 72 20 64 75 72 69 6e 67 20 ┆r. When a fault occur during ┆
0x3380…33a0 74 68 65 20 72 61 6d 20 74 65 73 74 20 61 6e 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 69 73 ┆the ram test an error message is┆
0x33a0…33c0 20 0a 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 63 6f 6e 73 6f 6c 65 2c 20 61 6e 64 20 74 68 ┆ written to the console, and th┆
0x33c0…33e0 65 20 52 41 4d 20 74 65 73 74 20 73 74 61 72 74 73 20 66 72 6f 6d 20 74 68 65 20 73 74 61 72 74 ┆e RAM test starts from the start┆
0x33e0…3400 20 0a 61 67 61 69 6e 2e 20 54 68 69 73 20 77 69 6c 6c 20 62 65 20 74 68 65 20 63 61 73 65 20 75 ┆ again. This will be the case u┆
0x3400…3420 (26,) 6e 74 69 6c 20 6e 6f 20 65 72 72 6f 72 20 69 73 20 64 69 73 63 6f 76 65 72 65 64 2e 20 49 66 20 ┆ntil no error is discovered. If ┆
0x3420…3440 0a 74 68 65 72 65 20 69 73 20 61 20 52 41 4d 20 65 72 72 6f 72 20 61 6e 64 20 69 66 20 61 6e 20 ┆ there is a RAM error and if an ┆
0x3440…3460 4c 20 69 73 20 74 79 70 65 64 20 66 72 6f 6d 20 74 68 65 20 6b 65 79 62 6f 61 72 64 2c 20 74 68 ┆L is typed from the keyboard, th┆
0x3460…3480 65 6e 20 0a 74 68 65 20 52 41 4d 20 74 65 73 74 20 77 69 6c 6c 20 6e 6f 74 20 73 74 61 72 74 20 ┆en the RAM test will not start ┆
0x3480…34a0 66 72 6f 6d 20 74 68 65 20 62 65 67 69 6e 6e 69 6e 67 20 61 67 61 69 6e 2c 20 62 75 74 20 70 72 ┆from the beginning again, but pr┆
0x34a0…34c0 6f 63 65 65 64 20 0a 74 72 6f 75 67 68 20 74 68 65 20 52 41 4d 20 74 65 73 74 20 61 6e 64 20 77 ┆oceed trough the RAM test and w┆
0x34c0…34e0 72 69 74 65 20 61 6c 6c 20 52 41 4d 20 65 72 72 6f 72 73 20 74 6f 20 74 68 65 20 63 6f 6e 73 6f ┆rite all RAM errors to the conso┆
0x34e0…3500 6c 65 2c 20 61 6e 64 20 0a 66 69 6e 61 6c 6c 79 20 65 6e 74 65 72 20 74 68 65 20 22 74 65 73 74 ┆le, and finally enter the "test┆
0x3500…3520 2d 61 64 6d 69 6e 69 73 74 72 61 74 6f 72 22 20 74 6f 20 65 78 65 63 75 74 65 20 6f 74 68 65 72 ┆-administrator" to execute other┆
0x3520…3529 20 74 65 73 74 73 2e 0d 0a ┆ tests. ┆
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0x352c…3540 0a a1 b0 38 2e 20 b0 54 65 73 74 20 31 20 3d 20 f0 43 68 69 ┆ 8. Test 1 = Chi┆
0x3540…3560 70 20 53 65 6c 65 63 74 20 54 65 73 74 2e 0d 0a 0d 0a 54 6f 20 65 61 73 65 20 63 6f 6d 70 6c 65 ┆p Select Test. To ease comple┆
0x3560…3580 78 20 64 65 62 75 67 67 69 6e 67 2c 20 61 20 73 69 6d 70 6c 65 20 63 68 69 70 20 73 65 6c 65 63 ┆x debugging, a simple chip selec┆
0x3580…35a0 74 20 6c 6f 6f 70 2c 20 63 6f 6d 62 69 6e 65 64 20 0a 77 69 74 68 20 61 20 52 41 4d 20 77 72 69 ┆t loop, combined with a RAM wri┆
0x35a0…35c0 74 65 2f 72 65 61 64 2c 20 69 73 20 73 75 70 70 6c 69 65 64 2e 20 0d 0a 0d 0a 54 68 69 73 20 74 ┆te/read, is supplied. This t┆
0x35c0…35e0 65 73 74 20 67 65 6e 65 72 61 74 65 73 20 63 68 69 70 20 73 65 6c 65 63 74 73 20 74 6f 20 61 6c ┆est generates chip selects to al┆
0x35e0…3600 6c 20 70 65 72 69 70 68 65 72 61 6c 20 64 65 76 69 63 65 73 20 62 79 20 0a 65 78 65 63 75 74 69 ┆l peripheral devices by executi┆
0x3600…3620 (27,) 6e 67 20 69 6e 70 75 74 20 69 6e 73 74 72 75 63 74 69 6f 6e 73 20 74 6f 20 61 6c 6c 20 72 65 6c ┆ng input instructions to all rel┆
0x3620…3640 65 76 61 6e 74 20 49 2f 4f 2d 64 65 76 69 63 65 73 2e 20 54 68 65 73 65 20 0a 61 72 65 20 3a 0d ┆evant I/O-devices. These are : ┆
0x3640…3660 0a 0d 0a 50 6f 72 74 20 84 30 2c 20 32 2c 20 31 32 38 2c 20 31 33 30 2c 20 32 35 36 2c 20 32 35 ┆ Port 0, 2, 128, 130, 256, 25┆
0x3660…3680 38 2c 20 32 36 30 2c 20 32 36 32 2c 20 33 38 34 2c 20 33 38 36 2c 20 33 38 38 2c 20 33 39 30 2c ┆8, 260, 262, 384, 386, 388, 390,┆
0x3680…36a0 20 33 39 32 2c 20 0a 19 85 80 80 33 39 34 2c 20 33 39 36 2c 20 33 39 38 2c 20 35 31 32 2c 20 35 ┆ 392, 394, 396, 398, 512, 5┆
0x36a0…36c0 31 34 2c 20 35 31 36 2c 20 35 31 38 2c 20 36 34 30 2c 20 36 34 32 2c 20 36 34 34 2c 20 36 34 36 ┆14, 516, 518, 640, 642, 644, 646┆
0x36c0…36e0 2c 20 36 34 38 2c 20 0a 19 85 80 80 36 35 30 2c 20 36 35 32 2c 20 36 35 34 2e 0d 0a 0d 0a 57 68 ┆, 648, 650, 652, 654. Wh┆
0x36e0…3700 65 6e 20 61 6c 6c 20 74 68 65 20 63 68 69 70 20 73 65 6c 65 63 74 73 20 61 72 65 20 6d 61 64 65 ┆en all the chip selects are made┆
0x3700…3720 2c 20 61 20 70 61 74 74 65 72 6e 20 41 41 35 35 20 68 65 78 2e 20 69 73 20 0a 77 72 69 74 74 65 ┆, a pattern AA55 hex. is writte┆
0x3720…3740 6e 20 74 6f 20 61 20 52 41 4d 20 63 65 6c 6c 20 61 6e 64 20 69 6d 6d 65 64 69 61 74 65 6c 79 20 ┆n to a RAM cell and immediately ┆
0x3740…3760 72 65 61 64 20 62 61 63 6b 2e 0d 0a 0d 0a 54 68 69 73 20 74 65 73 74 20 69 73 20 75 6e 61 62 6c ┆read back. This test is unabl┆
0x3760…3780 65 20 74 6f 20 67 65 6e 65 72 61 74 65 20 61 6e 79 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 73 ┆e to generate any error messages┆
0x3780…37a0 2e 20 49 74 20 69 73 20 6d 65 61 6e 74 20 0a 6f 6e 6c 79 20 61 73 20 61 20 73 70 65 63 69 61 6c ┆. It is meant only as a special┆
0x37a0…37b8 20 66 61 73 74 20 73 63 6f 70 65 20 6c 6f 6f 70 20 74 65 73 74 2e 0d 0a ┆ fast scope loop test. ┆
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0x37c0…37e0 39 2e 20 b0 54 45 53 54 20 32 f0 20 3d 20 69 41 50 58 20 31 38 36 20 54 69 6d 65 72 20 54 65 73 ┆9. TEST 2 = iAPX 186 Timer Tes┆
0x37e0…3800 74 2e 0d 0a 0d 0a 54 68 69 73 20 74 65 73 74 20 76 65 72 69 66 69 65 73 20 74 68 65 20 61 62 69 ┆t. This test verifies the abi┆
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0x3820…3840 6d 65 72 20 30 20 0a 74 6f 20 67 65 6e 65 72 61 74 65 20 69 6e 74 65 72 72 75 70 74 73 2e 20 54 ┆mer 0 to generate interrupts. T┆
0x3840…3860 68 65 20 69 6e 74 65 72 6e 61 6c 20 74 69 6d 65 72 20 30 20 69 73 20 69 6e 69 74 69 61 6c 69 7a ┆he internal timer 0 is initializ┆
0x3860…3880 65 64 20 61 73 20 61 20 0a 72 65 61 6c 20 74 69 6d 65 20 63 6c 6f 63 6b 20 77 68 69 63 68 20 67 ┆ed as a real time clock which g┆
0x3880…38a0 65 6e 65 72 61 74 65 73 20 69 6e 74 65 72 72 75 70 74 20 65 76 65 72 79 20 32 30 20 6d 69 6c 6c ┆enerates interrupt every 20 mill┆
0x38a0…38c0 69 73 65 63 6f 6e 64 2e 20 0a 49 66 20 6e 6f 20 74 69 6d 65 72 20 69 6e 74 65 72 72 75 70 74 20 ┆isecond. If no timer interrupt ┆
0x38c0…38e0 69 73 20 67 65 6e 65 72 61 74 65 64 20 74 68 65 6e 20 61 6e 20 65 72 72 6f 72 20 6d 65 73 73 61 ┆is generated then an error messa┆
0x38e0…3900 67 65 20 69 73 20 0a 67 65 6e 65 72 61 74 65 64 20 6c 69 6b 65 20 74 68 69 73 2e 0d 0a 0d 0a a1 ┆ge is generated like this. ┆
0x3900…3920 a1 a1 e1 b0 f0 31 2e 20 b0 69 41 50 58 31 38 36 20 74 69 6d 65 72 20 74 65 73 74 20 3a 20 6d 69 ┆ 1. iAPX186 timer test : mi┆
0x3920…3940 73 73 69 6e 67 20 74 69 6d 65 72 20 30 20 69 6e 74 65 72 72 75 70 74 0d 0a 0d 0a 54 68 69 73 20 ┆ssing timer 0 interrupt This ┆
0x3940…3960 65 72 72 6f 72 20 73 68 6f 75 6c 64 20 69 6e 64 69 63 61 74 65 20 61 20 6d 61 6c 66 75 6e 63 74 ┆error should indicate a malfunct┆
0x3960…3980 69 6f 6e 20 6f 66 20 74 68 65 20 69 41 50 58 20 31 38 36 20 0a 70 72 6f 63 65 73 73 6f 72 20 63 ┆ion of the iAPX 186 processor c┆
0x3980…3986 68 69 70 2e 0d 0a ┆hip. ┆
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0x3989…39a0 0a a1 b0 31 30 2e 20 b0 54 45 53 54 20 33 f0 20 3d 20 69 41 50 58 20 ┆ 10. TEST 3 = iAPX ┆
0x39a0…39c0 31 38 36 20 44 4d 41 20 54 65 73 74 2e 0d 0a 0d 0a 54 68 69 73 20 74 65 73 74 20 76 65 72 69 66 ┆186 DMA Test. This test verif┆
0x39c0…39e0 69 65 73 20 74 68 65 20 61 62 69 6c 69 74 79 20 6f 66 20 74 68 65 20 74 77 6f 20 69 41 50 58 20 ┆ies the ability of the two iAPX ┆
0x39e0…3a00 31 38 36 20 69 6e 74 65 72 6e 61 6c 20 44 4d 41 20 0a 63 68 61 6e 6e 65 6c 73 20 74 6f 20 6d 61 ┆186 internal DMA channels to ma┆
0x3a00…3a20 (29,) 6b 65 20 61 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 61 6e 64 20 74 6f 20 67 65 6e 65 72 ┆ke a data transport and to gener┆
0x3a20…3a40 61 74 65 20 69 6e 74 65 72 72 75 70 74 73 2e 20 54 68 65 20 0a 74 77 6f 20 69 41 50 58 20 31 38 ┆ate interrupts. The two iAPX 18┆
0x3a40…3a60 36 20 44 4d 41 20 63 68 61 6e 6e 65 6c 73 20 61 72 65 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 74 ┆6 DMA channels are initialized t┆
0x3a60…3a80 6f 20 70 65 72 66 6f 72 6d 20 61 20 44 4d 41 20 6d 65 6d 6f 72 79 20 0a 74 6f 20 6d 65 6d 6f 72 ┆o perform a DMA memory to memor┆
0x3a80…3aa0 79 20 74 72 61 6e 73 70 6f 72 74 20 73 69 6d 75 6c 74 61 6e 65 6f 75 73 6c 79 2e 20 44 4d 41 20 ┆y transport simultaneously. DMA ┆
0x3aa0…3ac0 63 68 61 6e 6e 65 6c 20 30 20 63 6f 70 69 65 73 20 38 20 4b 62 79 74 65 73 20 0a 66 72 6f 6d 20 ┆channel 0 copies 8 Kbytes from ┆
0x3ac0…3ae0 61 20 73 6f 75 72 63 65 20 74 6f 20 61 20 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 66 66 65 72 ┆a source to a destination buffer┆
0x3ae0…3b00 20 69 6e 20 74 68 65 20 66 6f 72 77 61 72 64 20 64 69 72 65 63 74 69 6f 6e 2c 20 0a 61 6e 64 20 ┆ in the forward direction, and ┆
0x3b00…3b20 44 4d 41 20 63 68 61 6e 6e 65 6c 20 31 20 63 6f 70 69 65 73 20 66 72 6f 6d 20 74 68 65 20 73 61 ┆DMA channel 1 copies from the sa┆
0x3b20…3b40 6d 65 20 73 6f 75 72 63 65 20 74 6f 20 61 6e 6f 74 68 65 72 20 0a 64 65 73 74 69 6e 61 74 69 6f ┆me source to another destinatio┆
0x3b40…3b60 6e 20 62 75 66 66 65 72 20 69 6e 20 74 68 65 20 72 65 76 65 72 73 65 20 64 69 72 65 63 74 69 6f ┆n buffer in the reverse directio┆
0x3b60…3b80 6e 2e 20 41 6c 6c 20 44 4d 41 20 74 72 61 6e 73 66 65 72 73 20 0a 61 72 65 20 73 79 6e 63 72 6f ┆n. All DMA transfers are syncro┆
0x3b80…3ba0 6e 69 7a 65 64 20 74 6f 20 74 68 65 20 69 6e 74 65 72 6e 61 6c 20 74 69 6d 65 72 20 32 20 77 68 ┆nized to the internal timer 2 wh┆
0x3ba0…3bc0 69 63 68 20 67 65 6e 65 72 61 74 65 73 20 61 20 32 35 30 20 4b 48 7a 20 0a 63 6c 6f 63 6b 2e 20 ┆ich generates a 250 KHz clock. ┆
0x3bc0…3be0 54 68 65 20 74 77 6f 20 63 68 61 6e 6e 65 6c 73 20 61 72 65 20 69 6e 69 74 69 61 6c 69 7a 65 64 ┆The two channels are initialized┆
0x3be0…3c00 20 74 6f 20 74 68 65 20 73 61 6d 65 20 70 72 69 6f 72 69 74 79 2e 20 0a 54 68 69 73 20 65 6e 73 ┆ to the same priority. This ens┆
0x3c00…3c20 (30,) 75 72 65 73 20 74 6f 67 65 74 68 65 72 20 77 69 74 68 20 74 68 65 20 73 65 6c 65 63 74 65 64 20 ┆ures together with the selected ┆
0x3c20…3c40 69 6e 74 65 72 6e 61 6c 20 74 69 6d 65 72 20 32 20 0a 73 79 6e 63 72 6f 6e 69 7a 61 74 69 6f 6e ┆internal timer 2 syncronization┆
0x3c40…3c60 20 74 68 61 74 20 62 6f 74 68 20 44 4d 41 20 63 68 61 6e 6e 65 6c 73 20 72 75 6e 73 20 73 69 6d ┆ that both DMA channels runs sim┆
0x3c60…3c80 75 6c 74 61 6e 65 6f 75 73 6c 79 20 61 6e 64 20 0a 74 68 61 74 20 74 68 65 20 43 50 55 20 6d 61 ┆ultaneously and that the CPU ma┆
0x3c80…3ca0 79 20 61 6c 73 6f 20 67 65 74 20 6d 65 6d 6f 72 79 20 61 63 63 65 73 73 2e 20 57 68 65 6e 20 74 ┆y also get memory access. When t┆
0x3ca0…3cc0 68 65 20 44 4d 41 20 74 72 61 6e 73 70 6f 72 74 20 0a 69 73 20 63 6f 6d 70 6c 65 74 65 20 62 6f ┆he DMA transport is complete bo┆
0x3cc0…3ce0 74 68 20 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 66 66 65 72 73 20 61 72 65 20 63 6f 6d 70 61 ┆th destination buffers are compa┆
0x3ce0…3d00 72 65 64 20 74 6f 20 74 68 65 20 73 6f 75 72 63 65 20 0a 62 75 66 66 65 72 2e 0d 0a 0d 0a 54 68 ┆red to the source buffer. Th┆
0x3d00…3d20 65 20 74 65 73 74 20 70 72 6f 64 75 63 65 73 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 65 72 ┆e test produces the following er┆
0x3d20…3d40 72 6f 72 20 6d 65 73 73 61 67 65 73 3a 0d 0a 0d 0a b0 f0 31 2e 20 b0 44 4d 41 20 74 65 73 74 3a ┆ror messages: 1. DMA test:┆
0x3d40…3d60 20 64 61 74 61 20 65 72 72 6f 72 20 20 73 65 67 6d 2e 3a 20 3c 73 73 73 73 3e 20 61 64 64 72 2e ┆ data error segm.: <ssss> addr.┆
0x3d60…3d80 3a 3c 61 61 61 61 3e 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 09 09 09 09 09 20 20 20 20 20 20 ┆:<aaaa> rec.:<rrrr> ┆
0x3d80…3da0 20 20 b0 65 78 70 2e 3a 3c 65 65 65 65 3e 0d 0a 0d 0a b0 f0 32 2e 20 b0 44 4d 41 20 74 65 73 74 ┆ exp.:<eeee> 2. DMA test┆
0x3da0…3dc0 3a 20 74 72 61 6e 73 66 65 72 20 74 69 6d 65 6f 75 74 0d 0a 0d 0a 54 68 65 20 66 69 72 73 74 20 ┆: transfer timeout The first ┆
0x3dc0…3de0 65 72 72 6f 72 20 69 6e 64 69 63 74 65 73 20 74 68 61 74 20 62 6f 74 68 20 44 4d 41 20 74 72 61 ┆error indictes that both DMA tra┆
0x3de0…3e00 6e 73 70 6f 72 74 73 20 68 61 73 20 74 65 72 6d 69 6e 61 74 65 64 20 0a 62 75 74 20 74 68 65 20 ┆nsports has terminated but the ┆
0x3e00…3e20 (31,) 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 66 66 65 72 20 69 73 20 6e 6f 74 20 65 71 75 61 6c 20 ┆destination buffer is not equal ┆
0x3e20…3e40 74 6f 20 74 68 65 20 73 6f 75 72 63 65 20 61 73 20 0a 65 78 70 65 63 74 65 64 2e 20 54 68 65 20 ┆to the source as expected. The ┆
0x3e40…3e60 6c 61 74 74 65 72 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 6f 6e 65 20 6f 66 20 74 68 65 ┆latter indicates that one of the┆
0x3e60…3e80 20 74 77 6f 20 6f 72 20 62 6f 74 68 20 44 4d 41 20 0a 69 6e 74 65 72 72 75 70 74 73 20 69 73 20 ┆ two or both DMA interrupts is ┆
0x3e80…3ea0 6d 69 73 73 69 6e 67 2e 0d 0a 0d 0a 42 6f 74 68 20 65 72 72 6f 72 73 20 73 68 6f 75 6c 64 20 69 ┆missing. Both errors should i┆
0x3ea0…3ec0 6e 64 69 63 61 74 65 20 61 20 6d 61 6c 66 75 6e 63 74 69 6f 6e 20 6f 66 20 74 68 65 20 69 41 50 ┆ndicate a malfunction of the iAP┆
0x3ec0…3eda 58 20 31 38 36 20 0a 70 72 6f 63 65 73 73 6f 72 20 63 68 69 70 2e 0d 0a 0d 0a ┆X 186 processor chip. ┆
0x3eda…3edd FormFeed {
0x3eda…3edd 0c 83 80 ┆ ┆
0x3eda…3edd }
0x3edd…3ee0 0a b0 f0 ┆ ┆
0x3ee0…3f00 a1 b0 31 a1 31 2e 20 b0 54 65 73 74 20 34 f0 20 3d 20 52 41 4d 20 52 65 66 72 65 73 68 20 54 65 ┆ 1 1. Test 4 = RAM Refresh Te┆
0x3f00…3f20 73 74 2e 0d 0a 0d 0a 54 68 65 20 52 41 4d 20 72 65 66 72 65 73 68 20 74 65 73 74 20 6f 66 20 74 ┆st. The RAM refresh test of t┆
0x3f20…3f40 68 65 20 45 54 43 36 31 31 20 53 42 43 20 53 65 6c 66 74 65 73 74 20 61 73 73 69 73 74 20 69 6e ┆he ETC611 SBC Selftest assist in┆
0x3f40…3f60 20 74 68 65 20 0a 76 65 72 69 66 69 63 61 74 69 6f 6e 20 6f 66 20 74 68 65 20 6d 65 6d 6f 72 79 ┆ the verification of the memory┆
0x3f60…3f80 20 63 6f 6e 74 72 6f 6c 20 6c 6f 67 69 63 20 66 75 6e 63 74 69 6f 6e 61 6c 69 74 79 2e 20 54 68 ┆ control logic functionality. Th┆
0x3f80…3fa0 65 20 6d 61 69 6e 20 0a 70 75 72 70 6f 73 65 20 69 73 20 74 6f 20 64 69 73 63 6f 76 65 72 20 74 ┆e main purpose is to discover t┆
0x3fa0…3fc0 68 65 20 64 65 63 61 79 20 6f 66 20 64 61 74 61 20 63 61 75 73 65 64 20 62 79 20 61 20 6d 61 6c ┆he decay of data caused by a mal┆
0x3fc0…3fe0 66 75 6e 63 74 69 6f 6e 20 0a 6f 66 20 74 68 65 20 52 41 4d 20 72 65 66 72 65 73 68 20 63 69 72 ┆function of the RAM refresh cir┆
0x3fe0…4000 63 75 69 74 72 79 2e 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 70 61 74 74 65 72 6e 20 77 72 69 74 ┆cuitry. The test pattern writ┆
0x4000…4020 (32,) 74 65 6e 20 69 73 20 61 20 63 6f 75 6e 74 69 6e 67 20 70 61 74 74 65 72 6e 20 61 6e 64 20 74 68 ┆ten is a counting pattern and th┆
0x4020…4040 65 20 73 69 7a 65 20 6f 66 20 0a 74 68 65 20 74 65 73 74 20 62 75 66 66 65 72 20 69 73 20 34 20 ┆e size of the test buffer is 4 ┆
0x4040…4060 4b 2c 20 31 36 20 62 69 74 20 77 6f 72 64 73 2e 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 70 61 74 ┆K, 16 bit words. When the pat┆
0x4060…4080 74 65 72 6e 20 68 61 73 20 62 65 65 6e 20 77 72 69 74 74 65 6e 20 74 68 65 20 74 65 73 74 20 70 ┆tern has been written the test p┆
0x4080…40a0 72 6f 67 72 61 6d 20 65 6e 74 65 72 73 20 61 20 0a 77 61 69 74 69 6e 67 20 6c 6f 6f 70 20 66 6f ┆rogram enters a waiting loop fo┆
0x40a0…40c0 72 20 61 70 70 72 6f 78 69 6d 61 74 65 20 35 20 73 65 63 2e 2c 20 69 6e 20 77 68 69 63 68 20 74 ┆r approximate 5 sec., in which t┆
0x40c0…40e0 68 65 20 43 50 55 20 77 69 6c 6c 20 6e 6f 74 20 0a 61 63 63 65 73 73 20 74 68 65 20 52 41 4d 20 ┆he CPU will not access the RAM ┆
0x40e0…4100 6d 65 6d 6f 72 79 2e 20 41 66 74 65 72 20 74 68 65 20 64 65 6c 61 79 2c 20 74 68 65 20 62 75 66 ┆memory. After the delay, the buf┆
0x4100…4120 66 65 72 20 77 69 6c 6c 20 62 65 20 0a 63 68 65 63 6b 65 64 20 74 6f 20 64 69 73 63 6f 76 65 72 ┆fer will be checked to discover┆
0x4120…4140 20 61 6e 79 20 64 65 63 61 79 2e 0d 0a 0d 0a 49 66 20 64 65 63 61 79 20 69 73 20 66 6f 75 6e 64 ┆ any decay. If decay is found┆
0x4140…4160 2c 20 61 20 6d 65 73 73 61 67 65 20 69 73 20 77 72 69 74 74 65 6e 20 6c 69 6b 65 20 74 68 69 73 ┆, a message is written like this┆
0x4160…4165 3a 0d 0a 0d 0a ┆: ┆
0x4165…419e Params {
0x4165…419e 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 45 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N E1 ┆
0x4165…419e 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x4165…419e }
0x419e…41d7 Params {
0x419e…41d7 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x419e…41d7 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x419e…41d7 }
0x41d7…41e0 0a b0 52 41 4d 20 72 65 66 ┆ RAM ref┆
0x41e0…4200 72 65 73 68 20 74 65 73 74 3a 20 65 72 72 6f 72 2c 20 61 64 64 72 2e 3a 20 3c 61 61 61 61 3e 2c ┆resh test: error, addr.: <aaaa>,┆
0x4200…421d (33,) 20 65 78 70 2e 3a 20 3c 65 65 65 65 3e 2c 20 72 65 63 2e 3a 20 3c 72 72 72 72 3e 0d 0a ┆ exp.: <eeee>, rec.: <rrrr> ┆
0x421d…4256 Params {
0x421d…4256 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0x421d…4256 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x421d…4256 }
0x4256…428f Params {
0x4256…428f 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 45 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N E1 ┆
0x4256…428f 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x4256…428f }
0x428f…42a0 0a 0d 0a 57 68 65 72 65 0d 0a 09 3c 61 61 61 61 3e ┆ Where <aaaa>┆
0x42a0…42c0 20 84 69 73 20 74 68 65 20 6f 66 66 73 65 74 20 61 64 64 72 65 73 73 20 72 65 6c 61 74 69 76 65 ┆ is the offset address relative┆
0x42c0…42e0 20 74 6f 20 74 68 65 20 73 74 61 72 74 20 6f 66 20 74 68 65 20 0a 19 8b 80 80 74 65 73 74 20 62 ┆ to the start of the test b┆
0x42e0…4300 75 66 66 65 72 2e 0d 0a 20 20 20 20 3c 65 65 65 65 3e 20 69 73 20 74 68 65 20 70 61 74 74 65 72 ┆uffer. <eeee> is the patter┆
0x4300…4320 6e 20 77 72 69 74 74 65 6e 20 69 6e 20 74 68 69 73 20 77 6f 72 64 2e 0d 0a 09 3c 72 72 72 72 3e ┆n written in this word. <rrrr>┆
0x4320…4340 20 69 73 20 74 68 65 20 70 61 74 74 65 72 6e 20 72 65 61 64 20 66 72 6f 6d 20 74 68 69 73 20 77 ┆ is the pattern read from this w┆
0x4340…4360 6f 72 64 2e 0d 0a 0d 0a 54 68 65 20 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 ┆ord. The corresponding error ┆
0x4360…436e 6e 75 6d 62 65 72 20 69 73 20 39 2e 0d 0a ┆number is 9. ┆
0x436e…4371 FormFeed {
0x436e…4371 0c 82 b8 ┆ ┆
0x436e…4371 }
0x4371…4380 0a b0 a1 b0 a1 31 32 2e 20 54 65 73 74 20 35 ┆ 12. Test 5┆
0x4380…43a0 20 f0 3d 20 45 74 68 65 72 6e 65 74 20 54 65 73 74 20 32 2e 0d 0a 0d 0a 54 68 65 20 65 74 68 65 ┆ = Ethernet Test 2. The ethe┆
0x43a0…43c0 72 6e 65 74 20 74 65 73 74 20 32 20 61 70 70 6c 69 65 73 20 74 6f 20 74 68 65 20 76 65 72 69 66 ┆rnet test 2 applies to the verif┆
0x43c0…43e0 69 63 61 74 69 6f 6e 20 6f 66 20 74 68 65 20 38 32 35 38 36 20 63 6f 2d 0a 70 72 6f 63 65 73 73 ┆ication of the 82586 co- process┆
0x43e0…4400 6f 72 20 61 6e 64 20 69 74 73 20 69 6e 74 65 72 66 61 63 65 20 63 69 72 63 75 69 74 72 79 2e 20 ┆or and its interface circuitry. ┆
0x4400…4420 (34,) 54 68 65 20 74 65 73 74 20 6d 61 6b 65 73 20 61 6e 20 65 78 74 65 72 6e 61 6c 20 0a 64 61 74 61 ┆The test makes an external data┆
0x4420…4440 20 6c 6f 6f 70 62 61 63 6b 20 74 65 73 74 20 6f 6e 20 74 68 65 20 65 74 68 65 72 6e 65 74 20 63 ┆ loopback test on the ethernet c┆
0x4440…4460 68 69 70 2e 0d 0a 0d 0a 46 69 72 73 74 20 61 20 73 6f 66 74 77 61 72 65 20 72 65 73 65 74 20 6f ┆hip. First a software reset o┆
0x4460…4480 66 20 74 68 65 20 65 74 68 65 72 6e 65 74 20 63 68 69 70 20 69 73 20 6d 61 64 65 2e 20 54 68 69 ┆f the ethernet chip is made. Thi┆
0x4480…44a0 73 20 72 65 73 65 74 20 0a 63 61 75 73 65 73 20 74 68 65 20 65 74 68 65 72 6e 65 74 20 63 6f 6e ┆s reset causes the ethernet con┆
0x44a0…44c0 74 72 6f 6c 6c 65 72 20 74 6f 20 69 73 73 75 65 20 61 6e 20 69 6e 74 65 72 72 75 70 74 20 77 68 ┆troller to issue an interrupt wh┆
0x44c0…44e0 65 6e 20 74 68 65 20 0a 72 65 73 65 74 20 69 73 20 63 6f 6d 70 6c 65 74 65 2e 20 49 66 20 6e 6f ┆en the reset is complete. If no┆
0x44e0…4500 20 69 6e 74 65 72 72 75 70 74 20 69 73 20 72 65 63 65 69 76 65 64 20 61 6e 20 65 72 72 6f 72 20 ┆ interrupt is received an error ┆
0x4500…4520 6d 65 73 73 61 67 65 20 0a 69 73 20 67 65 6e 65 72 61 74 65 64 20 6c 69 6b 65 20 74 68 69 73 3a ┆message is generated like this:┆
0x4520…4540 0d 0a 0d 0a b0 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 20 3a 20 6d 69 73 73 69 6e 67 20 72 ┆ Ethernet test 2 : missing r┆
0x4540…4560 65 73 65 74 20 69 6e 74 65 72 72 75 70 74 0d 0a 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 ┆eset interrupt Corresponding ┆
0x4560…4580 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 36 31 2e 0d 0a 0d 0a 53 65 63 6f 6e 64 20 61 20 ┆error number is 61. Second a ┆
0x4580…45a0 63 6f 6e 66 69 67 75 72 65 20 63 6f 6d 6d 61 6e 64 20 69 73 20 65 78 65 63 75 74 65 64 20 74 6f ┆configure command is executed to┆
0x45a0…45c0 20 74 68 65 20 65 74 68 65 72 6e 65 74 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 0a 69 6e 20 6f 72 64 ┆ the ethernet controller in ord┆
0x45c0…45e0 65 72 20 74 6f 20 73 65 6c 65 63 74 20 74 68 65 20 65 78 74 65 72 6e 61 6c 20 6c 6f 6f 70 62 61 ┆er to select the external loopba┆
0x45e0…4600 63 6b 20 6d 6f 64 65 2e 20 41 67 61 69 6e 20 74 68 65 20 73 6c 65 66 74 65 73 74 20 0a 61 77 61 ┆ck mode. Again the sleftest awa┆
0x4600…4620 (35,) 69 74 73 20 61 20 63 6f 6e 66 69 67 75 72 65 20 63 6f 6d 70 6c 65 74 65 20 69 6e 74 65 72 72 75 ┆its a configure complete interru┆
0x4620…4640 70 74 2c 20 61 6e 64 20 69 66 20 6e 6f 6e 65 20 69 73 20 72 65 63 65 69 76 65 64 20 61 6e 20 0a ┆pt, and if none is received an ┆
0x4640…4660 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 20 6c 69 6b 65 20 ┆error message is generated like ┆
0x4660…4680 74 68 69 73 3a 0d 0a 0d 0a b0 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 20 3a 20 63 6f 6e 66 ┆this: Ethernet test 2 : conf┆
0x4680…46a0 69 67 75 72 61 74 69 6f 6e 20 63 6f 6d 6d 61 6e 64 20 6e 6f 74 20 61 63 63 65 70 74 65 64 0d 0a ┆iguration command not accepted ┆
0x46a0…46c0 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 ┆ Corresponding error number is ┆
0x46c0…46e0 35 38 2e 0d 0a 0d 0a 54 68 69 72 64 20 61 20 74 72 61 6e 73 6d 69 74 20 66 72 61 6d 65 20 63 6f ┆58. Third a transmit frame co┆
0x46e0…4700 6d 6d 61 6e 64 20 69 73 20 65 78 65 63 75 74 65 64 2e 20 54 68 65 20 65 74 68 65 72 6e 65 74 20 ┆mmand is executed. The ethernet ┆
0x4700…4720 61 64 64 72 65 73 73 20 0a 69 73 20 74 68 65 20 62 72 6f 61 64 63 61 73 74 20 61 64 64 72 65 73 ┆address is the broadcast addres┆
0x4720…4740 73 20 61 6e 20 74 68 65 20 6d 65 73 73 61 67 65 20 6c 65 6e 67 74 68 20 69 73 20 31 34 20 62 79 ┆s an the message length is 14 by┆
0x4740…4760 74 65 73 2e 20 49 66 0a 74 68 65 20 74 72 61 6e 73 6d 69 74 20 66 72 61 6d 65 20 63 6f 6d 6d 61 ┆tes. If the transmit frame comma┆
0x4760…4780 6e 64 20 69 73 20 6e 6f 74 20 61 63 63 65 70 74 65 64 20 62 79 20 74 68 65 20 65 74 68 65 72 6e ┆nd is not accepted by the ethern┆
0x4780…47a0 65 74 20 0a 63 6f 6e 74 72 6f 6c 6c 65 72 20 61 6e 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 ┆et controller an error message ┆
0x47a0…47c0 69 73 20 67 65 6e 65 72 61 74 65 64 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a b0 45 74 68 65 ┆is generated like this: Ethe┆
0x47c0…47e0 72 6e 65 74 20 74 65 73 74 20 32 20 3a 20 74 72 61 6e 73 6d 69 74 20 63 6f 6d 6d 61 6e 64 20 20 ┆rnet test 2 : transmit command ┆
0x47e0…4800 6e 6f 74 20 61 63 63 65 70 74 65 64 0d 0a 0d 0a 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 ┆not accepted corresponding er┆
0x4800…4820 (36,) 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 35 39 2e 0d 0a 0d 0a 46 6f 75 72 74 68 2c 20 77 68 65 ┆ror number is 59. Fourth, whe┆
0x4820…4840 6e 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 66 72 61 6d 65 20 63 6f 6d 6d 61 6e 64 20 69 73 20 ┆n the transmit frame command is ┆
0x4840…4860 63 6f 6d 70 6c 65 74 65 64 20 74 68 65 20 64 61 74 61 20 0a 73 65 6e 74 20 69 73 20 63 6f 70 61 ┆completed the data sent is copa┆
0x4860…4880 72 65 64 20 77 69 74 68 20 74 68 65 20 64 61 74 61 20 72 65 63 65 69 76 65 64 20 61 6e 64 20 69 ┆red with the data received and i┆
0x4880…48a0 66 20 6e 6f 74 20 74 68 65 20 73 61 6d 65 20 61 6e 20 0a 65 72 72 6f 72 20 6d 65 73 73 61 67 65 ┆f not the same an error message┆
0x48a0…48c0 20 69 73 20 67 65 6e 65 72 61 74 65 64 20 6f 74 68 65 72 77 69 73 65 20 74 68 65 20 65 74 68 65 ┆ is generated otherwise the ethe┆
0x48c0…48e0 72 6e 65 74 20 69 6e 74 65 72 66 61 63 65 20 69 73 20 0a 73 61 69 64 20 74 6f 20 62 65 20 4f 4b ┆rnet interface is said to be OK┆
0x48e0…4900 2e 0d 0a 0d 0a 8c 83 c8 0a b0 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 20 3a 20 64 61 74 61 ┆. Ethernet test 2 : data┆
0x4900…4920 20 65 72 72 6f 72 20 20 61 64 64 2e 3a 3c 61 61 61 61 3e 2c 20 65 78 70 2e 3a 3c 65 65 65 65 3e ┆ error add.:<aaaa>, exp.:<eeee>┆
0x4920…4940 2c 0d 0a b0 09 09 09 09 20 20 20 20 20 20 20 20 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 81 0d ┆, rec.:<rrrr> ┆
0x4940…4960 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 20 6e 75 6d 62 65 72 20 69 73 20 36 ┆ Corresponding error number is 6┆
0x4960…4980 30 2e 0d 0a 0d 0a 77 68 65 72 65 0d 0a 20 20 20 20 20 61 64 64 2e 3a 3c 61 61 61 61 3e 20 69 73 ┆0. where add.:<aaaa> is┆
0x4980…49a0 20 6f 66 66 73 65 74 20 61 64 64 72 65 73 73 20 69 6e 20 74 68 65 20 72 65 63 65 69 76 65 20 62 ┆ offset address in the receive b┆
0x49a0…49c0 75 66 66 65 72 0d 0a 20 20 20 20 20 65 78 70 2e 3a 3c 65 65 65 65 3e 20 69 73 20 74 68 65 20 65 ┆uffer exp.:<eeee> is the e┆
0x49c0…49e0 78 70 65 63 74 65 64 20 76 61 6c 75 65 20 66 72 6f 6d 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 ┆xpected value from the transmit ┆
0x49e0…4a00 62 75 66 66 65 72 0d 0a 20 20 20 20 20 72 65 63 2e 3a 3c 72 72 72 72 3e 20 69 73 20 74 68 65 20 ┆buffer rec.:<rrrr> is the ┆
0x4a00…4a20 (37,) 72 65 63 65 69 76 65 64 20 76 61 6c 75 65 20 69 6e 20 74 68 65 20 72 65 63 65 69 76 65 20 62 75 ┆received value in the receive bu┆
0x4a20…4a40 66 66 65 72 0d 0a 0d 0a 41 6e 6f 74 68 65 72 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 69 73 ┆ffer Another error message is┆
0x4a40…4a60 20 77 72 69 74 74 65 6e 20 69 66 20 74 68 65 20 65 74 68 65 72 6e 65 74 20 63 6f 6e 74 72 6f 6c ┆ written if the ethernet control┆
0x4a60…4a80 6c 65 72 20 0a 67 65 6e 65 72 61 74 65 73 20 61 6e 20 69 6e 74 65 72 72 75 70 74 20 77 69 74 68 ┆ler generates an interrupt with┆
0x4a80…4aa0 6f 75 74 20 68 61 76 69 6e 67 20 72 65 73 65 74 20 74 68 65 20 63 6f 6d 6d 61 6e 64 20 6a 75 73 ┆out having reset the command jus┆
0x4aa0…4ac0 74 20 0a 65 78 65 63 75 74 65 64 2e 0d 0a 0d 0a b0 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 ┆t executed. Ethernet test 2┆
0x4ac0…4ae0 20 3a 20 69 6e 74 65 72 72 75 70 74 20 62 75 74 20 63 6f 6d 6d 61 6e 64 20 77 6f 72 64 20 6e 6f ┆ : interrupt but command word no┆
0x4ae0…4b00 74 20 63 6c 65 61 72 65 64 0d 0a 0d 0a 43 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 65 72 72 6f 72 ┆t cleared Corresponding error┆
0x4b00…4b10 20 6e 75 6d 62 65 72 20 69 73 20 34 38 2e 0d 0a ┆ number is 48. ┆
0x4b10…4b13 FormFeed {
0x4b10…4b13 0c 81 cc ┆ ┆
0x4b10…4b13 }
0x4b13…4b20 0a a1 b0 41 2e 20 52 45 46 45 52 45 4e ┆ A. REFEREN┆
0x4b20…4b40 43 45 53 b0 0d 0a 0d 0a 28 31 29 20 20 52 43 53 4c 2e 20 39 39 31 20 31 30 30 39 32 0d 0a 20 20 ┆CES (1) RCSL. 991 10092 ┆
0x4b40…4b60 20 20 20 52 43 20 33 39 20 53 65 6c 66 74 65 73 74 20 43 6f 6e 63 65 70 74 2c 20 0d 0a 20 20 20 ┆ RC 39 Selftest Concept, ┆
0x4b60…4b80 20 20 55 73 65 72 27 73 20 6d 61 6e 75 61 6c 20 09 20 20 20 20 20 0d 0a 0d 0a 28 32 29 20 20 52 ┆ User's manual (2) R┆
0x4b80…4ba0 43 53 4c 2e 20 39 39 31 20 31 30 30 39 35 0d 0a 20 20 20 20 20 49 54 43 20 36 30 32 20 68 61 72 ┆CSL. 991 10095 ITC 602 har┆
0x4ba0…4bc0 64 77 61 72 65 20 73 65 6c 66 74 65 73 74 2c 20 0d 0a 20 20 20 20 20 55 73 65 72 27 73 20 6d 61 ┆dware selftest, User's ma┆
0x4bc0…4be0 6e 75 61 6c 20 20 09 20 20 20 20 20 0d 0a 0d 0a 28 33 29 20 20 52 43 53 4c 2e 20 39 39 31 20 31 ┆nual (3) RCSL. 991 1┆
0x4be0…4c00 30 30 39 37 0d 0a 20 20 20 20 20 46 36 34 31 20 43 4f 4d 20 36 30 31 20 68 61 72 64 77 61 72 65 ┆0097 F641 COM 601 hardware┆
0x4c00…4c20 (38,) 20 73 65 6c 66 74 65 73 74 2c 20 0d 0a 20 20 20 20 20 55 73 65 72 27 73 20 6d 61 6e 75 61 6c 20 ┆ selftest, User's manual ┆
0x4c20…4c40 20 20 20 0d 0a 0d 0a 28 34 29 20 20 52 43 53 4c 2e 20 39 39 31 20 31 30 30 39 34 0d 0a 20 20 20 ┆ (4) RCSL. 991 10094 ┆
0x4c40…4c60 20 20 52 43 33 39 30 32 20 68 61 72 64 77 61 72 65 20 73 65 6c 66 74 65 73 74 2c 20 0d 0a 20 20 ┆ RC3902 hardware selftest, ┆
0x4c60…4c80 20 20 20 55 73 65 72 27 73 20 6d 61 6e 75 61 6c 09 20 20 20 20 20 0d 0a 0d 0a 28 35 29 20 20 52 ┆ User's manual (5) R┆
0x4c80…4ca0 43 53 4c 2e 20 39 39 31 20 31 30 31 33 34 0d 0a 20 20 20 20 20 52 43 33 39 20 6d 6f 6e 69 74 6f ┆CSL. 991 10134 RC39 monito┆
0x4ca0…4cc0 72 20 38 30 38 36 20 76 65 72 73 69 6f 6e 2c 20 0d 0a 20 20 20 20 20 52 65 66 65 72 65 6e 63 65 ┆r 8086 version, Reference┆
0x4cc0…4ce0 20 6d 61 6e 75 61 6c 09 20 20 20 20 20 0d 0a 0d 0a 28 36 29 20 20 52 43 53 4c 2e 20 39 39 31 20 ┆ manual (6) RCSL. 991 ┆
0x4ce0…4d00 31 30 30 39 33 0d 0a 20 20 20 20 20 52 43 33 39 20 6d 6f 6e 69 74 6f 72 20 38 30 32 38 36 20 76 ┆10093 RC39 monitor 80286 v┆
0x4d00…4d20 65 72 73 69 6f 6e 2c 20 0d 0a 20 20 20 20 20 52 65 66 65 72 65 6e 63 65 20 6d 61 6e 75 61 6c 20 ┆ersion, Reference manual ┆
0x4d20…4d2a 20 20 20 20 0d 0a 0d 0a 0a 0a ┆ ┆
0x4d2a…4d2d FormFeed {
0x4d2a…4d2d 0c 82 d0 ┆ ┆
0x4d2a…4d2d }
0x4d2d…4d2e 0a ┆ ┆
0x4d2e…4d67 Params {
0x4d2e…4d67 04 00 2d 4e 0c 00 06 00 00 00 00 02 01 50 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N P1 ┆
0x4d2e…4d67 00 00 00 00 00 00 00 00 08 10 18 20 28 30 38 40 4a 4b 55 5f 69 73 7d ff 04 ┆ (08@JKU_iså ┆
0x4d2e…4d67 }
0x4d67…4da0 Params {
0x4d67…4da0 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0x4d67…4da0 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x4d67…4da0 }
0x4da0…4dc0 0a a1 b0 42 2e 20 a1 43 6f 6d 70 6c 65 74 65 20 45 72 72 6f 72 20 4c 69 73 74 2e 0d 0a 0d 0a 21 ┆ B. Complete Error List. !┆
0x4dc0…4de0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x4e00…4e20 (39,) 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 45 72 72 2e 20 4e 6f 20 21 09 09 09 09 20 ┆-------------! ! Err. No ! ┆
0x4e20…4e40 20 20 45 72 72 6f 72 20 54 65 78 74 20 20 20 20 20 20 20 20 20 20 20 20 09 09 20 20 20 20 21 0d ┆ Error Text ! ┆
0x4e40…4e60 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ !------------------------------┆
0x4e60…4e80 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x4e80…4ea0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 30 20 20 20 20 21 20 4f 4b ┆---------------! ! 0 ! OK┆
0x4ea0…4ec0 09 09 09 09 09 09 09 09 09 09 09 09 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !---------------┆
0x4ec0…4ee0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x4ee0…4f00 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d ┆------------------------------! ┆
0x4f00…4f20 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ !----------------------------┆
0x4f20…4f40 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x4f40…4f60 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 31 20 20 20 20 21 20 ┆-----------------! ! 1 ! ┆
0x4f60…4f80 43 68 65 63 6b 73 75 6d 20 54 65 73 74 3a 20 73 75 6d 20 65 72 72 6f 72 20 20 20 20 09 09 09 09 ┆Checksum Test: sum error ┆
0x4f80…4fa0 09 09 09 09 09 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !-----------------------┆
0x4fa0…4fc0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x4fc0…4fe0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 21 2d 2d 2d 2d ┆----------------------! !----┆
0x4fe0…5000 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x5020…5040 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 32 09 20 20 20 21 20 52 41 4d 20 54 65 73 74 ┆---------! ! 2 ! RAM Test┆
0x5040…5060 3a 20 52 41 4d 20 65 72 72 6f 72 09 09 09 09 09 09 09 09 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d ┆: RAM error ! !-------┆
0x5060…5080 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x50a0…50c0 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆------! !--------------------┆
0x50c0…50e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x50e0…5100 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 ┆-------------------------! ! ┆
0x5100…5120 20 33 20 20 20 20 21 20 69 41 50 58 31 38 36 20 44 4d 41 20 54 65 73 74 3a 20 64 61 74 61 20 65 ┆ 3 ! iAPX186 DMA Test: data e┆
0x5120…5140 72 72 6f 72 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆rror ! !---------------┆
0x5140…5160 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x5160…5180 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d ┆------------------------------! ┆
0x5180…51a0 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ !----------------------------┆
0x51a0…51c0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x51c0…51e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 34 20 20 20 20 21 20 ┆-----------------! ! 4 ! ┆
0x51e0…5200 69 41 50 58 31 38 36 20 44 4d 41 20 54 65 73 74 3a 20 74 69 6d 65 6f 75 74 09 09 09 09 09 09 20 ┆iAPX186 DMA Test: timeout ┆
0x5200…5220 (41,) 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !-------------------------┆
0x5220…5240 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x5240…5260 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d ┆--------------------! !------┆
0x5260…5280 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x52a0…52c0 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 39 20 20 20 20 21 20 52 41 4d 20 72 65 66 72 65 73 ┆-------! ! 9 ! RAM refres┆
0x52c0…52e0 68 20 54 65 73 74 3a 20 65 72 72 6f 72 09 09 09 09 09 20 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d ┆h Test: error ! !-----┆
0x52e0…5300 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x5320…5340 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------! !------------------┆
0x5340…5360 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x5360…5380 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 ┆---------------------------! ! ┆
0x5380…53a0 20 20 20 31 30 20 20 20 21 20 69 41 50 58 31 38 36 20 54 69 6d 65 72 20 54 65 73 74 3a 20 6d 69 ┆ 10 ! iAPX186 Timer Test: mi┆
0x53a0…53c0 73 73 69 6e 67 20 74 69 6d 65 72 20 30 20 69 6e 74 65 72 72 75 70 74 09 09 09 09 09 20 20 21 0d ┆ssing timer 0 interrupt ! ┆
0x53c0…53e0 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ !------------------------------┆
0x53e0…5400 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x5400…5420 (42,) 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆---------------! !-----------┆
0x5420…5440 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x5460…5480 2d 2d 21 0d 0a 21 20 20 20 20 34 38 20 20 20 21 20 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 ┆--! ! 48 ! Ethernet test 2┆
0x5480…54a0 3a 20 69 6e 74 65 72 72 75 70 74 20 62 75 74 20 63 6f 6d 6d 61 6e 64 20 77 6f 72 64 20 6e 6f 74 ┆: interrupt but command word not┆
0x54a0…54c0 20 63 6c 65 61 72 65 64 09 20 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ cleared ! !--------------┆
0x54c0…54e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x54e0…5500 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 ┆-------------------------------!┆
0x5500…5520 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ !---------------------------┆
0x5520…5540 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x5540…5560 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 36 30 20 20 20 21 ┆------------------! ! 60 !┆
0x5560…5580 20 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 3a 20 64 61 74 61 20 65 72 72 6f 72 20 20 20 20 ┆ Ethernet test 2: data error ┆
0x5580…55a0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 09 20 20 20 ┆ ┆
0x55a0…55c0 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !--------------------------┆
0x55c0…55e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x55e0…5600 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d ┆-------------------! !-------┆
0x5600…5620 (43,) 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x5640…5660 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 36 31 20 20 20 21 20 45 74 68 65 72 6e 65 74 20 74 65 ┆------! ! 61 ! Ethernet te┆
0x5660…5680 73 74 20 32 3a 20 6d 69 73 73 69 6e 67 20 72 65 73 65 74 20 69 6e 74 65 72 72 75 70 74 09 09 09 ┆st 2: missing reset interrupt ┆
0x5680…56a0 09 09 09 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !-----------------------┆
0x56a0…56c0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x56c0…56e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 21 2d 2d 2d 2d ┆----------------------! !----┆
0x56e0…5700 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x5720…5740 2d 2d 2d 2d 2d 2d 2d 2d 2d 3b 0d 0a 21 20 20 20 20 36 32 20 20 20 21 20 45 74 68 65 72 6e 65 74 ┆---------; ! 62 ! Ethernet┆
0x5740…5760 20 74 65 73 74 20 32 3a 20 63 6f 6e 66 69 67 75 72 61 74 69 6f 6e 20 63 6f 6d 6d 61 6e 64 20 6e ┆ test 2: configuration command n┆
0x5760…5780 6f 74 20 61 63 63 65 70 74 65 64 09 09 09 09 09 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ot accepted ! !-----------┆
0x5780…57a0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x57c0…57e0 2d 2d 21 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--! !------------------------┆
0x57e0…5800 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x5800…5820 (44,) 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 36 33 20 ┆---------------------! ! 63 ┆
0x5820…5840 20 20 21 20 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 3a 20 63 6f 6e 66 69 67 75 72 61 74 69 ┆ ! Ethernet test 2: configurati┆
0x5840…5860 6f 6e 20 63 6f 6d 6d 61 6e 64 20 6e 6f 74 20 61 63 63 65 70 74 65 64 09 09 09 09 20 20 21 0d 0a ┆on command not accepted ! ┆
0x5860…5880 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆!-------------------------------┆
0x5880…58a0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x58a0…58c0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------! !------------┆
0x58c0…58e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x5900…5920 2d 21 0d 0a 21 20 20 20 20 36 34 20 20 20 21 20 45 74 68 65 72 6e 65 74 20 74 65 73 74 20 32 3a ┆-! ! 64 ! Ethernet test 2:┆
0x5920…5940 20 74 72 61 6e 73 6d 69 74 20 63 6f 6d 6d 61 6e 64 20 6e 6f 74 20 61 63 63 65 70 74 65 64 20 20 ┆ transmit command not accepted ┆
0x5940…5960 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !----------┆
0x5960…5980 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x59a0…59a6 2d 2d 2d 21 0d 0a ┆---! ┆
0x59a6…59a9 FormFeed {
0x59a6…59a9 0c 83 b8 ┆ ┆
0x59a6…59a9 }
0x59a9…59ac 0a 0d 0a ┆ ┆
0x59ac…59af FormFeed {
0x59ac…59af 0c 80 88 ┆ ┆
0x59ac…59af }
0x59af…59c0 0a 1a 1a 72 6f 72 20 4c 69 73 74 2e 0d 0a 0d 0a 21 ┆ ror List. !┆
0x59c0…59e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]