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Length: 23936 (0x5d80)
Types: RcTekst
Names: »99109863.WP«
└─⟦dedaa6eab⟧ Bits:30005866/disk1.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99109863.WP«
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↲
i↲
↲
┆a1┆┆b0┆CONTENTS PAGE↲
↲
┆f0┆1. INTRODUCTION ........................... 1↲
↲
2. GENERAL DESCRIPTION OF CPU610 .......... 2↲
↲
3. BLOCK DIAGRAM .......................... 3↲
↲
4. FUNCTIONAL DESCRIPTION ................. 4↲
4.1 Onboard CPU ....................... 4↲
4.1.1 80286 CPU ............... 4↲
4.1.2 Optional 80287 Numeric pro-↲
┆84┆cessor ..................... 5↲
4.2 I/O Interface ..................... 5↲
4.2.1 I/O addressing ............. 5↲
4.2.2 Serie ...................... 7↲
4.2.3 Parallel ................... 8↲
4.2.4 Software Reset and Power ↲
Down Commands .............. 10↲
4.3 Clock Generator ................... 10↲
4.4 Interrupt handling ................ 11↲
4.4.1 Interrupt Source ........... 11↲
4.4.2 Interrupt Generator ........ 13↲
4.5 On board clock .................... 14↲
4.6 Memory addressing ................. 14↲
4.6.1 On board EPROM ............. 15↲
4.7 Bus Interface ..................... 16↲
4.7.1 MULTIBUS ................... 16↲
4.7.2 iLBX bus ................... 17↲
4.7.3 iSBX bus ................... 17↲
↲
↲
┆b0┆┆a1┆APPENDIX:↲
↲
A. REFERENCES ............................. 18↲
┆b0┆↓
════════════════════════════════════════════════════════════════════════
↓
↲
ii↲
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆ ┆0b┆↲
↲
┆a1┆┆b0┆┆b0┆┆a1┆┆b0┆┆a1┆1. INTRODUCTION.↲
↲
┆84┆This hardware reference manual describes the CPU610. It ↓
┆19┆┆89┆┄┄shows the interface to internal and external busses. It ↓
┆19┆┆89┆┄┄does not give a detail information of the component and ↓
┆19┆┆89┆┄┄timing on the board. (See CPU610 technical manual litt 5 ↓
┆19┆┆89┆┄┄in the reference list in capter five).↲
┆84┆↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆2. GENERAL DESCRIPTION OF CPU610.↲
↲
┆84┆┆84┆The CPU610 contains:↲
↲
1. INTEL's i APX 80286 Microprocessor.↲
↲
2. MULTIBUS interface.↲
↲
3. ┆84┆iLBX bus interface, the CPU610 acts as a primary ↓
┆19┆┆8c┆┄┄master.↲
↲
4. One iSBX bus without DMA channel support.↲
↲
5. Consol interface. (V24/RS232C).↲
↲
6. Multidrop interface. (RS422A).↲
↲
┆84┆7. ┆84┆Parallel printer interface. (Centronics and RC750 ↓
┆19┆┆8c┆┄┄Partner compatibel).↲
↲
8. ┆84┆Up to 64K bytes (2*32K bytes) EPROM in two standard ↓
┆19┆┆8c┆┄┄JEDEC sockets. 128 bytes (256*4 bit) bipolar PROM.↲
↲
9. ┆84┆A real time clock shows the time of day and the day ↓
┆19┆┆8c┆┄┄of the year.↲
↲
10. ┆84┆As an option the CPU610 includes interface to a ↓
┆19┆┆8c┆┄┄numeric processor 80287 from INTEL.↲
↲
┆84┆This manual does not contain a full description of the ↓
┆19┆┆89┆┄┄elements of the CPU610. (See the reference list in ↓
┆19┆┆89┆┄┄chapter five for further information of the elements).↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆b0┆┆a1┆3. BLOCK DIAGRAM.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆a1┆4. FUNCTIONAL DESCRIPTION.↲
↲
┆a1┆┆b0┆┆f0┆┆e1┆ ┆84┆This chapter describes the use of the elements on the ↓
┆19┆┆89┆┆81┆┄CPU board.↲
↲
↲
┆b0┆┆a1┆4.1 On board CPU.↲
↲
┆b0┆┆a1┆┆f0┆┆e1┆ ┆84┆This part describes the processors on the CPU board. The ↓
┆19┆┆89┆┆81┆┄CPU board use INTEL's 80286 as the central processor. As ↓
┆19┆┆89┆┆81┆┄an option the CPU board includes interface to the 80287 ↓
┆19┆┆89┆┆81┆┄numeric processor. (See litt 1 for futher details of the ↓
┆19┆┆89┆┆81┆┄processors).↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
↲
┆a1┆┆b0┆4.1.1 80286 CPU.↲
↲
┆84┆The INTEL's 80286 (8 MHz) or 80286-6 (6 MHz) is the ↓
┆19┆┆89┆┄┄central processor on the CPU board. The microprocessor ↓
┆19┆┆89┆┄┄work in to different modes:↲
↲
1. The real address mode.↲
↲
2. The protected virtual address mode. (PVAM)↲
↲
┆84┆In mode nr 1 the processor addresses up to 1 Mbytes. In ↓
┆19┆┆89┆┄┄mode nr 2 it addr┆84┆ess up 16 Mbytes.↲
↲
┆84┆The processor makes use of an on chip memory mangement ↓
┆19┆┆89┆┄┄in the protected virtual address mode↲
↲
┆84┆The CPU board begins in the real address mode. When the ↓
┆19┆┆89┆┄┄80286 makes a word Out instrution on I/O address 00CA to ↓
┆19┆┆89┆┄┄the first parallel port, it switches to protected mode. ↓
┆19┆┆89┆┄┄Then it is inpossible to switch back to real address ↓
┆19┆┆89┆┄┄mode.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆4.1.2 Optional 80287 Numeric processor.↲
↲
┆84┆The CPU board can be expanded with a numeric processor ↓
┆19┆┆89┆┄┄INTEL's 80287 (8 MHz) or 80287-3 (5 MHz). The processor ↓
┆19┆┆89┆┄┄is used to floating point operation and other ↓
┆19┆┆89┆┄┄difficulting numeric operations.↲
↲
┆84┆All interface to the numeric processor is on the CPU ↓
┆19┆┆89┆┄┄board.↲
↲
↲
┆f0┆┆a1┆┆b0┆┆a1┆┆b0┆┆a1┆4.2 I/O Interface.↲
┆b0┆┆a1┆↲
┆b0┆┆a1┆┆f0┆┆e1┆ ┆84┆The next part of chapter four describes the use of the i ↓
┆19┆┆89┆┆81┆┄APX's I/O address space.↲
↲
↲
┆b0┆┆a1┆4.2.1 I/O addressing on board.↲
┆b0┆┆a1┆↲
┆b0┆┆a1┆Device Data size I/O address ↲
↲
PAL012. (Interrupt out). Byte : Set 0082↲
PAL012. (Interrupt out). Byte : Reset 0086↲
TBP24S10. (Bipolar PROM). 4 bit 0086↲
RTC. (MM158167A/RTC58321) Byte/4 bit 008A↲
8259A-2 PIC. (Slave2). Byte: Status. 0094┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8259A-2 PIC. (Slave2). Byte: MASK. 0096┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8255A-5 PPI. (Parallel 2) Byte: A 0098┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8255A-5 PPI. (Parallel 2) Byte: Port B In. 009A↲
8255A-5 PPI. (Parallel 2) Byte: Port C Out. 009C┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8255A-5 PPI. (Parallel 2) Byte: Control. 009E┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
iSBX bus. Byte/word 00A0-00BF┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8259A-2 PIC. (Master). Byte: Status. 00C0┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8259A-2 PIC. (Master). Byte: MASK. 00C2┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8259A-2 PIC. (Slave1). Byte: Status. 00C4┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8259A-2 PIC. (Slave1). Byte: MASK. 00C6┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8255A-5 PPI. (Parallel 1) Byte: A 00C8┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8255A-5 PPI. (Parallel 1) Byte: Port B In.↲
word: WR PVAM 00CA↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆Device Data size I/O address ↲
↲
8255A-5 PPI. (Parallel 1) Byte: Port C Out. 00CC┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8255A-5 PPI. (Parallel 1) Byte: Control. 00CE┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8254 PIT. (Timer). Byte: Counter 0 00D0┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8254 PIT. (Timer). Byte: Counter 1 00D2┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8254 PIT. (Timer). Byte: Counter 2 00D4┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8254 PIT. (Timer). Byte: Control. 00D6┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8274 MPSC. CH A. Byte: Data. 00D8┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8274 MPSC. CH B. Byte: Data. 00DA┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8274 MPSC. CH A. Byte: Control. 00DC┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8274 MPSC. CH B. Byte: Control. 00DE┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
80287 Numric Processor. Word: RD status.↲
WR Opcode. 00F8↲
80287 Numric Processor. Word: Data. 00FA┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
80287 Numric Processor. Word: Address. 00FC┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
┆b0┆ ┆a1┆ ↲
↲
Fig 4.2.1 ┆84┆I/O addresses on the CPU board.↲
↲
┆b0┆┆a1┆Target Data size I/O address ↲
↲
MULTIBUS byte/word 0000-007F↲
-"- -"- 0100-FFFF↲
Reserved (TEST) -"- FFEF↲
┆05┆ ┆b0┆ ┆a1┆ ↲
↲
Fig 4.2.2 ┆84┆I/O addresses from i APX 80286 to the ↓
┆19┆┆93┆┄┄MULTIBUS.↲
↲
┆b0┆┆a1┆Target Chip select Data size I/O address ↲
↲
iSBX bus /MCS0 byte 00A0-00AF↲
-"- /MCS1 byte 00B0-00BF↲
iSBX bus /MCS0 word 00A0-00A8↲
-"- /MCS1 word 00A0-00AF↲
┆b0┆ ┆a1┆ ↲
↲
Fig 4.2.3 ┆84┆I/O addresses from i APX 80286 to the iSBX ↓
┆19┆┆93┆┄┄bus.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.2.2 Serie.┆a1┆┆b0┆↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
┆84┆The CPU board has two serie channels A and B. Channel A ↓
┆19┆┆89┆┄┄makes the connection to the multidrop RS422A line. ↓
┆19┆┆89┆┄┄Channel B takes car of the consol with RS232A interface.↲
┆84┆The INTEL's 8274 Multi-protocol Serial Controller (MPSC) ↓
┆19┆┆89┆┄┄takes care of most of the serie communication. Two extra ↓
┆19┆┆89┆┄┄signals in channel B /DSRB (Data Set Ready) and /CIB ↓
┆19┆┆89┆┄┄(Calling Indicator) interface to the parallel port 1.↲
↲
┆84┆The used signals in channel A are :↲
↲
┆b0┆ ┆84┆ ┆b0┆┆a1┆Signal Meaning ↲
↲
TXDA Transmitted Data↲
RXDA Received Data↲
/RTSA Request To Send↲
/CTSA Ready For Sending↲
/CDA Carrier On↲
┆a1┆ ↲
↲
┆84┆The used signals in channal B are :↲
↲
┆b0┆ ┆84┆ ┆b0┆┆a1┆Signal Meaning ↲
↲
TXDB Transmitted Data↲
RXDB Received Data↲
/RTSB Request To Send↲
/CTSB Ready For Sending↲
/DSRB Data Set Ready↲
/CDB Carrier On↲
/CIB Calling Indicator↲
┆a1┆ ↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.2.3 Parallel.↲
↲
┆84┆There are two parallel ports on the board. The INTEL's ↓
┆19┆┆89┆┄┄parallel port 8255A-5 is used in both cases. The port A ↓
┆19┆┆89┆┄┄and C are output ports and B is an input port. ↓
┆19┆┆89┆┄┄┆84┆↲
┆84┆Note that there must be at least six instructions ↓
┆19┆┆89┆┄┄between access to the PPI's. The first parallel port ↓
┆19┆┆89┆┄┄connect a printer to the CPU board. The printer ↓
┆19┆┆89┆┄┄interface must be a RC750 ( "PARTNER") or Centronics ↓
┆19┆┆89┆┄┄compatible interface.↲
┆84┆↲
┆84┆The next parallel port includes the addresses to the ↓
┆19┆┆89┆┄┄Real Time Clock, the bipolar PROM and some special ↓
┆19┆┆89┆┄┄signals. (See the list below).↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
Signals from parallel port nr. 1↲
↲
┆a1┆┆b0┆Pin Signal ↲
↲
PA0 DATA 0 (Printer)↲
PA1 DATA 1 (Printer)↲
PA2 DATA 2 (Printer)↲
PA3 DATA 3 (Printer)↲
PA4 DATA 4 (Printer)↲
PA5 DATA 5 (Printer)↲
PA6 DATA 6 (Printer)↲
PA7 DATA 7 (Printer)↲
↲
PB0 If high then 6 MHz else 8 MHz CPU.↲
PB1 /CIB (Calling Indicator to consol)↲
PB2 /DSRB (Data Set Ready to consol)↲
PB3 BUSY (Printer)↲
PB4 /ACK (Printer)↲
PB5 /FAULT (Printer)↲
PB6 SELECTED (Printer)↲
PB7 PAPER END (Printer)↲
PC0 STROBE (Printer)↲
PC1 /SELECT (Printer)↲
════════════════════════════════════════════════════════════════════════
↓
PC2 /LPINIT┆84┆ (Printer)↲
PC3 /TIMEOUT INT (┆84┆Used to generate a timeout ↓
┆19┆┆a2┆┄┄interrupt).↲
PC4 /AUTOLF (Printer)↲
PC5 /PDMDEN↲
PC6 SER LB (┆84┆Used to loopback with the 8274 multi- ↓
┆19┆┆9c┆┄┄protocol controller).↲
PC7 LPINT (┆84┆Used if /ACK is low to generate an ↓
┆19┆┆9b┆┄┄interrupt from the lineprinter).↲
↲
┆82┆ ┆b0┆-------------------------------------------------------↲
↲
Signals from parallel port nr. 2↲
↲
┆a1┆┆b0┆Pin Signal ↲
↲
PA0 SLIOADR 0 (RTC and BPROM address)↲
PA1 SLIOADR 1 (RTC and BPROM address)↲
PA2 SLIOADR 2 (RTC and BPROM address)↲
PA3 SLIOADR 3 (RTC and BPROM address)↲
PA4 SLIOADR 4 (RTC and BPROM address)↲
PA5 SLIOADR 5 (RTC and BPROM address)↲
PA6 SLIOADR 6 (RTC and BPROM address)↲
PA7 SLIOADR 7 (RTC and BPROM address)↲
↲
PB0 ┆84┆/Testslave. (If two CPU is used, it indicates ↓
┆19┆┆94┆┄┄which is the test master). A testmaster is ↓
┆19┆┆94┆┄┄the multibus board which teststhe ↓
┆19┆┆94┆┄┄multibus.(See litt 7)).↲
PB1 Not in use.↲
PB2 Not in use.↲
PB3 ┆84┆J4-9 (It makes the connection to an external ↓
┆19┆┆94┆┄┄switch).↲
PB4 ┆84┆J4-7 (It makes the connection to an external ↓
┆19┆┆94┆┄┄switch).↲
PB5 ┆84┆XOPT0 (An undefinite signal from the iSBX ↓
┆19┆┆94┆┄┄bus).↲
PB6 ┆84┆XOPT1 (An undefinite signal from the iSBX ↓
┆19┆┆94┆┄┄bus).↲
════════════════════════════════════════════════════════════════════════
↓
PB7 ┆84┆/XPST (If low an iSBX modul is on the CPU ↓
┆19┆┆94┆┄┄board).↲
PC0 ┆84┆/LED1 (The /LED1 signal control a light ↓
┆19┆┆94┆┄┄emiting diode which indicates when the CPU is ↓
┆19┆┆94┆┄┄in test mode).↲
PC1 ┆84┆/LED2 (The /LED2 signal control a light ↓
┆19┆┆94┆┄┄emiting diode which indicates when the CPU ↓
┆19┆┆94┆┄┄makes access to a disk).↲
PC2 ┆84┆ /iLBX (When low it enables the iLBX bus; ↓
┆19┆┆93┆┄┄otherwise the CPU uses the MULTIBUS.↲
PC3 Not in use.↲
PC4 OPTO0 (An undefinite signal to the iSBX bus).↲
PC5 ┆84┆/OPT0EN (When low it enables the signal OPT0 ↓
┆19┆┆94┆┄┄as an output signal to the iSBX bus).↲
PC6 OPTO1 (An undefinite signal to the iSBX bus).↲
PC7 ┆84┆/OPT1EN (When low it enables the signal OPTO1↓
┆19┆┆94┆┄┄as an output signal to the iSBX bus).↲
↲
┆b0┆-------------------------------------------------------↲
↲
↲
┆a1┆┆b0┆4.2.4 Software Reset and Power Down Commands↲
↲
┆84┆An out instruction to I/O address 0082 with data equal ↓
┆19┆┆89┆┄┄zero reset the CPU and the multibus.↲
↲
╞ ┆84┆082 = 0↲
↲
┆84┆When the bit PC5 (signal PDMDEN) enable the off ↓
┆19┆┆89┆┄┄interrupt from the ON/OFF key at the front of the RC39.↲
↲
↲
┆b0┆┆a1┆┆a1┆┆b0┆┆b0┆┆a1┆4.3 Clock Generator.↲
↲
┆84┆The CPU board uses an external clock generator 82284 ↓
┆19┆┆89┆┄┄from INTEL. The clock generator generates CPUCLK and a ↓
┆19┆┆89┆┄┄clock for the 8254 Programmable Interval Timer (PIT). ↓
┆19┆┆89┆┄┄The interval timer includes three programmable counters.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆There is a 10 MHz clock generator to the multibus. This ↓
┆19┆┆89┆┄┄clock is divided by two to generate a 5 Mhz clock ↓
┆19┆┆89┆┄┄signal. The 80287-3 numeric processor extension unit can ↓
┆19┆┆89┆┄┄run with this clock signal.↲
┆a1┆┆b0┆↲
↲
┆b0┆┆a1┆4.4 Interrupt operation.↲
↲
┆84┆The CPU610 includes three programable interrupt ↓
┆19┆┆89┆┄┄controllers (PIC's). The interrupt controllers take care ↓
┆19┆┆89┆┄┄of the interrupt input to the 80286. They are working in ↓
┆19┆┆89┆┄┄master slave relationship. The interrupt controllers ↓
┆19┆┆89┆┄┄make it possible to connect up to 22 interrupts to the ↓
┆19┆┆89┆┄┄80286. The controllers are initiate as shown below. ↓
┆19┆┆89┆┄┄(Futher details are included in litt 6).↲
┆84┆The 80286 is able to generate up to three independent ↓
┆19┆┆89┆┄┄multibus interrupts. A PAL takes care of the interrupt ↓
┆19┆┆89┆┄┄output control.↲
↲
↲
┆a1┆┆b0┆4.4.1 Interrupt Source.↲
↲
┆84┆The interrupt input are showed in fig 4.4.1.1.↲
↲
┆84┆Note that the priority is from top to down, except the ↓
┆19┆┆89┆┄┄input to slave interrupt controller number 2. These inputs ↓
┆19┆┆89┆┄┄have priority between interrupt number 0 and 2.↲
↲
┆b0┆┆a1┆Interrupt nr. Signal Source Destination. ↲
↲
NMI /POWON BBC601 CPU80286↲
0 COUNT 0 Interval timer Master PIC IR 0↲
1 SLINT 2 SLAVE PIC 2 Master PIC IR 1↲
2 MBINT 2 Multibus Master PIC IR 2↲
3 MBINT 3 Multibus Master PIC IR 3↲
4 MBINT 4 Multibus Master PIC IR 4↲
5 MBINT 5 Multibus Master PIC IR 5↲
6 SERINT Serial I/O Master PIC IR 6↲
7 SLINT 1 Slave1 PIC 1 Master PIC IR 7↲
════════════════════════════════════════════════════════════════════════
↓
8 MBINT 6 Multibus Slave1 PIC IR 0↲
9 MBINT 7 Multibus Slave1 PIC IR 1↲
10 TMOUTINT Time out Slave1 PIC IR 2↲
11 XINT 0 iSBX bus Slave1 PIC IR 3↲
12 XINT 1 iSBX bus Slave1 PIC IR 4↲
13 MBINT 0 Multibus Slave1 PIC IR 5↲
14 MBINT 1 Multibus Slave1 PIC IR 6↲
15 LPINT Line printer Slave1 PIC IR 7↲
16 PINTR 2 Key Slave2 PIC IR 0↲
17 MBINT 9 Multibus Slave2 PIC IR 1↲
18 MBINT 10 Multibus Slave2 PIC IR 2↲
19 MBINT 11 Multibus Slave2 PIC IR 3↲
20 MBINT 12 Multibus Slave2 PIC IR 4↲
21 MBINT 13 Multibus Slave2 PIC IR 5↲
22 MBINT 14 Multibus Slave2 PIC IR 6↲
23 MBINT 15 Multibus Slave2 PIC IR 7↲
↲
┆b0┆ --------------------------------------------------------↲
↲
┆84┆Fig 4.4.1.1 Standard interrupts on the board. The NMI ↓
┆19┆┆89┆┄┄is a non maskable interrupt which occurs under power ↓
┆19┆┆89┆┄┄down.↲
↲
┆84┆It is possible to send seven extra multibus interrupts ↓
┆19┆┆89┆┄┄to the CPU from the multibus. (MBINT 9 - MBINT 15). An ↓
┆19┆┆89┆┄┄I/O write with the following format interrupts the CPU.↲
┆f0┆┆e1┆┆a1┆┆b0┆↲
┆84┆Format of a I/O write extended multibus interrupt ↓
┆19┆┆89┆┄┄instruction to the CPU :↲
↲
┆b0┆┆a1┆┆84┆┆f0┆┆e1┆ ┆b0┆┆a1┆MULTIBUS I/O address Destination. ↲
┆b0┆┆a1┆┆f0┆↲
09X0 Testmaster CPU610↲
09X8 Testslave CPU610↲
↲
┆b0┆┆b0┆----------------------------------------↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆84┆MULTIBUS Data field Destination.↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
00CF SET MBINT 9↲
00AF SET MBINT 10↲
008F SET MBINT 11↲
006F SET MBINT 12↲
004F SET MBINT 13↲
002F SET MBINT 14↲
000F SET MBINT 15↲
↲
┆b0┆┆b0┆-------------------------------------↲
↲
↲
┆b0┆┆a1┆4.4.2 Interrupt Generator.↲
↲
┆84┆The CPU is able to set up to three independt multibus ↓
┆19┆┆89┆┄┄interrupts. (Jumpers make the connection). The CPU or ↓
┆19┆┆89┆┄┄another multibus master is able to reset ↓
┆19┆┆89┆┄┄these interrupts.↲
↲
┆84┆Format of a I/O write extended multibus interrupt reset ↓
┆19┆┆89┆┄┄instruction to the CPU :↲
↲
┆b0┆┆a1┆┆84┆MULTIBUS I/O address Destination. ↲
┆b0┆┆a1┆┆f0┆↲
09X0 Testmaster CPU610↲
09X8 Testslave CPU610↲
↲
┆b0┆┆b0┆----------------------------------------↲
↲
┆b0┆┆a1┆┆84┆MULTIBUS Data field Destination.↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
0009 Reset /MBOUT 1↲
000A Reset /MBOUT 1↲
000B Reset /MBOUT 1↲
↲
┆b0┆┆b0┆-------------------------------------↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆Format of an output interrupt reset or set instruction ↓
┆19┆┆89┆┄┄from the CPU :↲
↲
┆b0┆┆a1┆┆84┆CPU I/O address Destination. ↲
┆b0┆┆a1┆┆f0┆↲
0086 Reset MBOUT *↲
0082 Set MBOUT↲
↲
┆b0┆┆b0┆----------------------------------------↲
↲
┆84┆* The data field selects the MBOUT signal.↲
↲
┆b0┆┆a1┆┆84┆CPU Data field Destination.↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
0009 Set /MBOUT 1↲
000A Set /MBOUT 2↲
000B Set /MBOUT 3↲
↲
┆b0┆┆b0┆-------------------------------------↲
↲
↲
┆b0┆┆a1┆4.5 On board clock.↲
↲
┆84┆The CPU board includes a Real Time Clock (RTC) . The RTC ↓
┆19┆┆89┆┄┄IC is the MM158167 (National) (Fist source) or RTC58321 ↓
┆19┆┆89┆┄┄from Suwa Seikosha (second source). The two sources are ↓
┆19┆┆89┆┄┄not compatible. Special programming is necessary in each ↓
┆19┆┆89┆┄┄case. (See the manuals from the factory). The addresses ↓
┆19┆┆89┆┄┄to the RTC come from the second parallel port. The RTC ↓
┆19┆┆89┆┄┄is non sensitive to power fails. The CPU board ↓
┆19┆┆89┆┄┄gives battery backup for at least nine years. In a month ↓
┆19┆┆89┆┄┄the first source will differ at the most 0.2 sec and the ↓
┆19┆┆89┆┄┄second source 40 sec.↲
┆b0┆┆a1┆↲
↲
┆a1┆┆b0┆4.6 Memory addressing.↲
┆b0┆┆a1┆↲
┆84┆The EPROMs are ┆81┆┆82┆the only onboard memories. (The bipolar ↓
┆19┆┆89┆┄┄PROM is in I/O addressing space). Fig 4.6.1-2 shows the ↓
════════════════════════════════════════════════════════════════════════
↓
┆19┆┆89┆┄┄total memory address map of the CPU board in real and ↓
┆19┆┆89┆┄┄protected virtual address mode. ┆b0┆┆a1┆↲
↲
┆b0┆┆a1┆Target memory size Real address space↲
↲
EPROM (UV) 64 K bytes 0F0000-0FFFFF↲
MULTIBUS 66 K bytes 0E0000-0EFFFF↲
iLBX bus 896 K bytes 000000-0DFFFF↲
┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
┆b0┆ -------------------------------------------------------↲
↲
┆84┆Fig 4.6.1 ┆84┆The Memory Map of the CPU in Real Address Mode ↓
┆19┆┆93┆┄┄(PVAM).↲
┆b0┆┆a1┆┆f0┆┆e1┆ ┆b0┆┆a1┆Target memory size Real address space↲
↲
EPROM (UV) 64 K bytes FF0000-FFFFFF↲
MULTIBUS 8128 K bytes 800000-FEFFFF↲
iLBX bus 8192 K bytes 000000-7FFFFF↲
┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
┆b0┆ -------------------------------------------------------↲
↲
Fig 4.6.2 ┆84┆The Memory Map of the CPU in Protected Virtual ↓
┆19┆┆93┆┄┄Address Mode (PVAM).↲
┆b0┆┆a1┆┆81┆↲
↲
┆b0┆┆a1┆4.6.1 On board EPROM.↲
↲
┆84┆The CPU board contains two 28 pins JEDEC sockes to the ↓
┆19┆┆89┆┄┄EROM (UV erasable). In each socket it is possible to ↓
┆19┆┆89┆┄┄mount IC's of the types : 2732 (4k), 2764 (8k), 27128 ↓
┆19┆┆89┆┄┄(16k) og 27256 (32k). A jumper must be insert when the ↓
┆19┆┆89┆┄┄27256 is in use. (All the EPROM's must be 27XXX, ↓
┆19┆┆89┆┄┄27XXX-1, 27XXX-2, 27XXX-3. The EPROM's have to be ↓
┆19┆┆89┆┄┄addressed in the top of the memory adressing space. (See ↓
┆19┆┆89┆┄┄the addressing map below).↲
┆b0┆┆a1┆↲
════════════════════════════════════════════════════════════════════════
↓
EPROM's address map :↲
↲
┆b0┆┆a1┆Type memory size Real address space PVAM space┆b0┆┆a1┆ ↲
↲
2764 16 K bytes 0FC000-0FFFFF FFC000-FFFFFF↲
┆e1┆┆f0┆ 27128 32 K bytes 0F8000-0FFFFF FF8000-FFFFFF↲
┆b0┆┆a1┆┆f0┆┆e1┆ 27256 64 K bytes 0F0000-0FFFFF FF0000-FFFFFF↲
↲
┆b0┆ -------------------------------------------------------↲
↲
↲
┆b0┆┆a1┆┆b0┆┆a1┆4.7 Bus Interface.↲
↲
┆84┆The next part shows the uses of external busses. All the ↓
┆19┆┆89┆┄┄busses are INTEL compatible. (See lit 2,3 and 4 for ↓
┆19┆┆89┆┄┄further information.).↲
↲
The CPU board use tre external buses:↲
↲
1. MULTIBUS.↲
↲
2. iLBX bus.↲
↲
3. iSBX bus.↲
↲
↲
┆a1┆┆b0┆4.7.1 MULTIBUS.↲
↲
┆84┆The interface to the MULTIBUS makes use of:↲
↲
1. ┆84┆One 82289 Bus Arbiter or a replacement with a 8289 ↓
┆19┆┆8c┆┄┄and a PAL.↲
↲
2. One bus controller 82288.↲
↲
3. Three 8259A-2 Interrupt controllers.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.7.2 iLBX bus.↲
↲
┆84┆The iLBX bus is a very fast memory bus. The iLBX bus ↓
┆19┆┆89┆┄┄interfaces to the CPU board with use of standard TTL ↓
┆19┆┆89┆┄┄IC's and PAL'S. The CPU board always acts as a primary ↓
┆19┆┆89┆┄┄master on the iLBX bus. It is possible to disconnect the ↓
┆19┆┆89┆┄┄iLBX bus when the PC2 bit in the second parallel port is ↓
┆19┆┆89┆┄┄high.↲
↲
↲
┆b0┆┆a1┆┆a1┆┆b0┆4.7.3 iSBX bus.↲
↲
┆84┆There is only one iSBX bus on the CPU board. There is no ↓
┆19┆┆89┆┄┄DMA support to the iSBX bus on the board. The iSBX bus ↓
┆19┆┆89┆┄┄interface to the CPU board with a 8255A-5 parallel port ↓
┆19┆┆89┆┄┄and with no extra latch or trancievers.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆a1┆A. REFERENCES.↲
┆b0┆┆a1┆↲
1. ┆84┆INTEL Microsystem Components Handbook . 1984. ↓
┆19┆┆8e┆┄┄230843-001.↲
↲
2. INTEL MULTIBUS Specifikation 9800683-04↲
↲
3. INTEL iLBX Bus Specifikation 145695-REV A↲
↲
4. INTEL iSBX Bus Specifikation 142686-001↲
↲
5. ┆84┆Central Processor Unit CPU610. Rev 1 .Technical ↓
┆19┆┆8e┆┄┄manual. RCSL 99-1 09864↲
↲
6. ┆84┆RC 3900, CPU 610, SBC selftest. User's Guide. ↲
↲
7. ┆84┆RC 3922 Selftest Concept. User's Guide. ↓
┆19┆┆8e┆┄┄RCSL 99-1 09770↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆1a┆┆1a┆Mode ↓
┆19┆┆93┆┄