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Length: 23936 (0x5d80)
Types: RcTekst
Names: »99110095.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110095.WP«
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↓
┆a1┆┆a1┆↲
↲
╞ Edition:╞ 1985.04.09↲
╞ Author: Peter Lundbo↲
╞ RCSL No.:╞ 991 10095↲
↲
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INTERNAL DOCUMENT↲
════════════════════════════════════════════════════════════════════════
↓
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↲
↲
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↲
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↲
Title:↲
↲
┆06┆┆84┆ITC 602 hardware selftest↲
user's manual↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a0006000000000301413140000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000201413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆06┆i↲
↲
┆a1┆┆b0┆TABLE OF CONTENTS╞ ╞ ╞ ┆05┆PAGE ↲
↲
1. INTRODUCTION ......................................... 1↲
↲
2. THE DUAL CHANNEL COMMUNICATION APPROACH .............╞ 2↲
↲
3. THE BAUD RATE DETERMINATION MODE .....................╞ 3↲
↲
4. INTERRUPT HANDLING ................................... 4↲
4.1 Valid Interrupts .................................╞ 4↲
╞ 4.2 Instruction Exceptions ...........................╞ 5↲
4.3 Illegal Slave Interrupts .........................╞ 5↲
4.4 Illegal Master Interrupts ........................╞ 6↲
4.5 Non Maskable Interrupt ...........................╞ 8↲
↲
5. TEST 0 = MEMORY TEST ................................. 9↲
5.1 PROM Checksum Test ...............................╞ 9↲
5.2 RAM Memory Test ..................................╞ 9↲
5.2.1 Memory Test Pattern ........................ 10↲
5.2.2 Memory Test Flow ........................... 10↲
╞ 5.2.3 Loop On Error .............................. 11↲
↲
6. TEST 1 = CHIP SELECT TEST ............................ 12↲
↲
7. TEST 2 = iAPX 186 TIMER TEST ......................... 13↲
↲
8. TEST 3 = iAPX 186 DMA TEST ........................... 14↲
↲
9. TEST 4 = PARELLEL PORT TEST .......................... 15↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆TABLE OF CONTENTS (continued)┆05┆PAGE↲
↲
10. TEST 5 = LINE CONTROL PROCESSOR DATA TEST ............ 16↲
↲
11. TEST 6 = LINE CONTROL PROCESSOR LOOPBACK TEST ........ 17↲
↲
12. TEST 7 = V.24 LINE 1 LOOPBACK TEST .................... 19↲
↲
13. TEST 8 = V.24 LINE 2 LOOPBACK TEST .................... 21↲
↲
14. TEST 9 = V.24 LINE 3 LOOPBACK TEST .................... 23↲
↲
15. LED OUTPUT ............................................ 25↲
↲
↲
┆a1┆┆b0┆APPENDIX↲
↲
A. REFERENCES ............................................. 27↲
↲
════════════════════════════════════════════════════════════════════════
↓
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆╞ ╞ ╞ ╞ ┆0b┆┆a1┆↲
┆a1┆┆a1┆┆b0┆1. INTRODUCTION.↲
↲
The ITC 602 is an Intelligent Terminal Controller, which is an ↓
intelligent Multibus SBC used to interface terminals to the RC 39 ↓
product. A maximum of 32 + 4 terminals may be connected to an ITC ↓
602. Four of these terminals may be connected via standard V.24 ↓
interface, whereas the remaining 32 terminal must be connnected ↓
via the new circuit II serial interface.↲
↲
This manual assume that the reader is familiar with the RC 39 ↓
selftest concept as described in the manual called "The RC 39 ↓
Selftest Concept". The ITC 602 selftest includes 10 different ↓
tests which may be run in several modes. Seven of these tests are ↓
┆b0┆default┆f0┆ tests which allways execute after a power on. The last ↓
┆19┆┄┆81┆┄tree tests are ┆b0┆extended┆b0┆┆f0┆ tests which is run only when requested ↓
┆19┆┄┆83┆┄explicit by an operator. This version of the ITC 602 includes no ↓
┆19┆┄┆83┆┄┆b0┆seperately┆f0┆ run ┆f0┆tests.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆┆b0┆2. THE DUAL CHANNEL COMMUNICATION APPROACH.↲
↲
The ITC 602 SBC selftest supports the Dual Channel Communication ↓
facility as described in the "RC 39 Selftest Concept". If the ↓
strap ST7-23 is inserted the communication goes via the on-board ↓
8274 USART line 0, otherwise if the strap is omitted the ↓
communication goes transparently through the Multibus interface ↓
to a console connected to the "test-master" usually a CPU 691 or ↓
a CPU 610 board.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆3. THE BAUD RATE ┆a1┆DETERMINATION MODE.↲
↲
If the starp ST7-23 is inserted and a terminal is connected to the ↓
V.24 line 0 interface (DSR activ) then the selftest enters the ↓
automatic Baud Rate Determination mode. The USART is initialized ↓
to 9600 Baud and stars (*****) are written to line 0. These stars ↓
may be seen as stars, other mixed characters or not seen at all ↓
depending on the Baud Rate of the attached console. The selftest ↓
waits for the operator to enter one or two upper case U. One ↓
upper case U is enough if the Baud Rate is 9600, 4800 or 2400 ↓
Baud. Baud Rates of 1200, 600 or 300 requires two upper case U.↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆4. INTERRUPT HANDLING.↲
↲
When the ITC 602 SBC selftest has finished the memory test, a set ↓
of default interrupt vectors are loaded into the vector table. ↓
These vectors are used to handle both expected and unexpected ↓
interrupts.↲
↲
↲
┆a1┆┆b0┆4.1 Valid Interrupts.↲
↲
The interrupts that are considered valid during the selftest are:↲
↲
┆a1┆Request line Interrupt name Vector type Event type ↲
↲
internal Step interrupt 1╞ ┆84┆instruction executed ↓
┆19┆┆ac┆┄┄with trap flag set↲
↲
internal╞ Break interrupt╞ 3╞ ┆84┆software interrupt ↓
┆19┆┆ac┆┄┄(debugger entry)↲
↲
internal╞ Timer 0╞ ╞ 8╞ Timer 0 interrupt↲
↲
INT 0╞ USART receive int.╞ 30╞ Keyboard interrupt↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆4.2 Instruction Exceptions.↲
↲
Some of the interrupts will generate an error message like this:↲
↲
┆b0┆┆f0┆1. ┆b0┆>> instruction exception↲
↲
┆a1┆Request line Interrupt name Vector type Event type ↲
↲
internal╞ Divide error╞ 0╞ Divede with zero↲
↲
internal╞ Owerflow╞ ╞ 4╞ INT0↲
↲
internal╞ Array Bounds╞ 5╞ BOUND↲
↲
internal╞ Unused Opcode╞ 6╞ Undefined opcode↲
↲
internal╞ ESC Opcode╞ 7╞ ESC opcodes↲
↲
↲
┆a1┆┆b0┆4.3 Illegal Slave Interrupts.↲
↲
Some of the interrupts will generate an error message like this:↲
↲
┆b0┆┆f0┆2. ┆b0┆illegal interrupt rec.:<rrrr>↲
↲
The secondary error data is the content of the iAPX 186 internal ↓
interrupt In Service Register (ISR) during the interrupt. This ↓
register at I/O address FF2C Hex. indicates which interrupt(s) ↓
are active. The ISR format is like this :↲
↲
┆a1┆15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0↲
0 0 X X X 0 0 0 I3 I2 I1 I0 D1 D2 0 TMR↲
↲
A one indicates that an interrupt is active.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Request line Interrupt name Vector type Event type ↲
↲
reserved╞ ╞ 9↲
↲
internal╞ DMA 0╞ 10╞ DMA ch. 0 complete↲
↲
internal╞ DMA 1╞ 11╞ DMA ch. 1 complete↲
↲
INT 0╞ INT0╞ 12╞ Serial line int.↲
↲
INT 1╞ MBFLAGINT╞ 13╞ flag byte int.↲
↲
INT 2╞ not used╞ 14╞ (acknowledge to INT0)↲
↲
INT 3 ╞ LCPINT╞ 15╞ circuit II interrupt↲
↲
internal╞ not used╞ 16↲
↲
internal╞ not used╞ 17↲
↲
internal╞ timer 2╞ 19╞ timer run out↲
↲
↲
┆a1┆┆b0┆4.4 Illegal Master Interrupts↲
↲
Some of the interrupts will generate an error message like this:↲
↲
┆b0┆┆f0┆3. ┆b0┆illegal line 0-1 interrupt lev.:<00ll> rec.:<rrrr>↲
↲
or↲
┆b0┆┆f0┆↲
4. ┆b0┆illegal line 2-3 interrupt lev.:<00ll> rec.:<rrrr>↲
↲
↲
┆8c┆┆83┆┆98┆↓
The level information is a read of the 8274 internal register RR2 ↓
where the interrupt level is stored. The rec information is a ↓
read of the 8274 RR0 and RR1 where the cause of interrupt may be ↓
further specified. RR1 is stored in the most significant byte of ↓
the received value. Consult INTEL data shets for further ↓
information about the Serial Line Controller 8274.↲
↲
┆a1┆Request line Interrupt name Vector type Event type ↲
↲
INT 0╞ TX empty╞ ╞ 24╞ Line 1 TX empty↲
↲
INT 0╞ Ext. Status ch.╞ 25╞ Line 1 Status change↲
↲
INT 0╞ RX available╞ 26╞ Line 1 RX character↲
↲
INT 0╞ Frame/Parity╞ 27╞ Line 1 Frame/Parity↲
↲
INT 0╞ TX empty╞ ╞ 28╞ Line 0 TX empty↲
↲
INT 0╞ Ext. Status ch.╞ 29╞ Line 0 Status change↲
↲
INT 0╞ Frame/Parity╞ 31╞ Line 0 Frame/Parity↲
↲
INT 0╞ TX empty╞ ╞ 32 Line 3 TX empty↲
↲
INT 0╞ Ext. Status ch.╞ 33╞ Line 3 Status change↲
↲
INT 0╞ RX available╞ 34╞ Line 3 RX character↲
↲
INT 0╞ Frame/Parity╞ 35╞ Line 3 Frame/Parity↲
↲
INT 0╞ TX empty╞ ╞ 36╞ Line 2 TX empty↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Request line Interrupt name Vector type Event type ↲
↲
INT╞ 0╞ Ext. Status ch.╞ 37╞ Line 2 Status change↲
↲
INT 0╞ RX available╞ 38╞ Line 2 RX character↲
↲
INT 0╞ Frame/Parity╞ 39 ╞ Line 3 Frame/Parity↲
↲
↲
┆a1┆┆b0┆4.5 Non Maskable Interrupt.↲
↲
If a non maskable interrupt (NMI) interrupt occur during the ↓
selftest the following message is written to the console and the ↓
processor is halted.↲
↲
┆b0┆┆f0┆5. ┆b0┆NMI interrupt - test HALTED !↲
↲
There is no way to get the selftest out of this halt situation ↓
except reset. Note that the NMI pin on the processor is grounded, ↓
so that it is unlikely that NMI interrupts occur.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5. ┆b0┆Test 0 = ┆f0┆MEMORY TEST.↲
↲
The memory test of the ITC 602 SBC selftest consists of two ↓
parts, a PROM checksum test and a RAM memory test. The PROM ↓
checksum test is only run once after power up or external reset, ↓
whereas the RAM memory test may be run several times, if ↓
requested by the operator.↲
↲
↲
┆b0┆┆a1┆5.1 PROM Checksum Test.↲
↲
The contents of both the odd and the even PROM are summarized ↓
bytewise and the result must be a zero. For that reason the ↓
PROM's contain a compensation byte which is used to bring the sum ↓
to zero.↲
┆a1┆↲
┆b0┆┆f0┆1. ┆b0┆checksum test: sum error exp.:<0000> rec.:<xyzw>↲
↲
Checksum error usually means that the content of the PROM has ↓
been damaged and that the PROM must be changed.↲
↲
↲
┆b0┆┆a1┆5.2 RAM Memory Test.↲
↲
The RAM memory test of the ITC 602 SBC selftest verifies the on-↓
board 64 kbytes memory.↲
↲
The memory test is a register based test and uses no memory space ↓
at all, neither for variables nor stack. The test verifies every ↓
single byte of the on-board memory.↲
↲
This fact lets only one register for test variables survive the ↓
memory test. That variable contains all the test switches and the ↓
test number. ↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5.2.1 Memory Test Pattern.↲
↲
The on-board Dual Ported RAM memory consists of memory chips of 4 ↓
bit * 16 K. The memory test executes 4 passes trough the entire ↓
memory, two times writing and two times reading.↲
↲
The test pattern is the convenient modulus 3 pattern consisting ↓
of three times 0000 followed by three times FFFF ( hexadecimal ).↲
↲
↲
┆a1┆┆b0┆5.2.2 Memory Test Flow.↲
↲
The test starts in the highest RAM addresses and inserts the pattern ↓
towards lower addresses.↲
↲
When all memory words have been written and verified, they are ↓
tested again with the inversed pattern, this means, that all bits ↓
are tested for "zero" and "one" insertion. If an error occur then ↓
an attempt to send the following message, to the "test-output", ↓
is made :↲
↲
┆a1┆┆b0┆┆f0┆2. ┆b0┆RAM test: RAM error segm.:<ssss> addr.:<aaaa> exp.:<eeee>↲
╞ ╞ ╞ ╞ ┆b0┆ rec.:<rrrr>↲
↲
The secondary text is interpreted like this :↲
↲
<ssss> is the segment address↲
<aaaa> is the address offset↲
<eeee> is the expected pattern, should allways be 0000 or FFFF.↲
<rrrr> is the received pattern.↲
↲
┆8c┆┆82┆┆f4┆↓
The above mentioned information may be used to find a defective ↓
RAM memory chip from the knowledge of the RAM-layout. Say the ↓
error message goes like this :↲
↲
┆b0┆RAM test : RAM error segm.:0000 addr.:0002 exp.:0000↲
┆19┆┄┆81┆┆82┆╞ ╞ ╞ ╞ ╞ ┆b0┆rec.:0003↲
↲
The RAM is made of 16K * 4 bit chips. This means that U46, U47, ↓
U48 and U49 builds a low address memory bank (0-7FFF), and that ↓
U56, U57, U58 and U59 builds a high address memory bank (8000-↓
FFFF). Each RAM chip contains a nibble (4 bits) of data ↓
corresponding to one hexadecimal digit in the secondary error ↓
data. The message above might indicate a failure in RAM chip U ↓
63.↲
↲
↲
┆b0┆┆a1┆5.2.3 Loop On Error.↲
↲
When a fault occur during the ram test an error message is ↓
written to the console, and the RAM test starts from the start ↓
again. This will be the case until no error is discovered. If ↓
there is a RAM error and if an L is typed from the keyboard, then ↓
the RAM test will not start from the beginning again, but proceed ↓
trough the RAM test and write all RAM errors to the console, and ↓
finally enter the "test-administrator" to execute other tests.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆6. ┆b0┆Test 1 = ┆f0┆CHIP SELECT TEST.↲
↲
To ease complex debugging, a simple chip select loop, combined ↓
with a RAM write/read, is supplied. ↲
↲
This test generates chip selects to all peripheral devices by ↓
executing input instructions to all relevant I/O-devices. These ↓
are :↲
↲
Port ┆84┆0, 2, 128, 130, 256, 258, 260, 262, 384, 386, 388, 390, 392, ↓
┆19┆┆85┆┄┄394, 396, 398, 512, 514, 516, 518, 640, 642, 644, 646, 648, ↓
┆19┆┆85┆┄┄650, 652, 654.↲
↲
When all the chip selects are made, a pattern AA55 hex. is ↓
written to a RAM cell and immediately read back.↲
↲
This test is unable to generate any error messages. It is meant ↓
only as a special fast scope loop test.↲
════════════════════════════════════════════════════════════════════════
↓
┆a2┆┆e2┆┆a1┆┆b0┆┆b0┆7. ┆b0┆TEST 2┆f0┆ = iAPX 186 TIMER TEST.↲
↲
This test verifies the ability of the iAPX 186 internal timer 0 ↓
to generate interrupts. The internal timer 0 is initialized as a ↓
real time clock which generates interrupt every 20 millisecond. ↓
If no timer interrupt is generated then an error message is ↓
generated like this.↲
↲
┆a1┆┆a1┆┆a1┆┆e1┆┆b0┆┆f0┆1. ┆b0┆iAPX186 timer test : missing timer 0 interrupt↲
↲
This error should indicate a malfunction of the iAPX 186 ↓
processor chip.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆8. ┆b0┆TEST 3┆f0┆ = iAPX 186 DMA TEST.↲
↲
This test verifies the ability of the two iAPX 186 internal DMA ↓
channels to make a data transport and to generate interrupts. The ↓
two iAPX 186 DMA channels are initialized to perform a DMA memory ↓
to memory transport simultaneously. DMA channel 0 copies 8 Kbytes ↓
from a source to a destination buffer in the forward direction, ↓
and DMA channel 1 copies from the same source to another ↓
destination buffer in the reverse direction. All DMA transfers ↓
are syncronized to the internal timer 2 which generates a 250 KHz ↓
clock. The two channels are initialized to the same priority. ↓
This ensures together with the selected internal timer 2 ↓
syncronization that both DMA channels runs simultaneously and ↓
that the CPU may also get memory access. When the DMA transport ↓
is complete both destination buffers are compared to the source ↓
buffer.↲
↲
The test produces the following error messages:↲
↲
┆b0┆┆f0┆1. ┆b0┆DMA test: data error segm.: <ssss> addr.:<aaaa> rec.:<rrrr>↲
┆19┆┄┆82┆┆82┆╞ ╞ ╞ ╞ ╞ ┆b0┆exp.:<eeee>↲
↲
┆b0┆┆f0┆2. ┆b0┆DMA test: transfer timeout↲
↲
The first error indictes that both DMA transports has terminated ↓
but the destination buffer is not equal to the source as ↓
expected. The latter indicates that one of the two or both DMA ↓
interrupts is missing.↲
↲
Both errors should indicate a malfunction of the iAPX 186 ↓
processor chip.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆9.┆b0┆ Test 4 =┆f0┆ PARALLEL PORT TEST.↲
↲
The 8255A PPI test writes a pattern 10100000 binary to the output ↓
port B ( ioadr. A1H ). Then it reads the pattern back and ↓
verifies it. If no error is detected the pattern is shifted one ↓
bit to the right, and the write/read verify procedure is repeated ↓
until the pattern becomes zero. The test may generate this error ↓
message:↲
↲
┆b0┆┆e1┆┆a1┆┆e1┆┆f0┆1. ┆b0┆PPI test: port error exp.:00ee, rec.:00rr↲
↲
Expected and received pattern tells you what bits went wrong with ↓
the test.↲
↲
This error might be caused by malfunction of the 8255A chip, by ↓
an initialization fault ( I/O space error ), or by something ↓
else. ↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆10. ┆b0┆Test 5┆f0┆ = LINE CONTROL PROCESSOR DATA TEST.↲
↲
This test makes a data transport to the Intel 8051 Line Control ↓
Processor, which loops back the data unchanged. The iAPX 186 ↓
internal DMA channel 0 is initialized to transfer 256 bytes of ↓
data to the LCP channel. The LCP test program is started by ↓
writing a command code 1 to the LCP command port (204 Hex.). The ↓
iAPX 186 internal DMA channel 1 is initialized as the receive ↓
channel, and sinks the data looped back from the LCP channel. The ↓
LCP channels signal with an interrupt to the iAPX 186 processor ↓
when the transfer is complete. The iAPX 186 waits for the ↓
interrupt to occur within 1 second, and if not a timeout message ↓
is written to the "test-output". NOTE that the data written to ↓
the LCP is not looped back on the serial line, only an internal ↓
loopback is made.↲
↲
The test may generate the following error messages:↲
↲
┆b0┆┆f0┆1. ┆b0┆LCP data test: command timeout↲
↲
┆b0┆The Line Control Processor did not respond to the command. The ↓
┆19┆┄┆81┆┆82┆signal called CMDACCEPT on the 8255A port A bit 0 was not set ↓
┆19┆┄┆81┆┆82┆within 1 second.↲
↲
┆b0┆┆f0┆2. ┆b0┆LCP data test: missing terminate interrupt↲
↲
The LCP accepted the command, but no terminate interrupt was ↓
generated witin 1 second after the command accept.↲
↲
┆b0┆┆f0┆3. ┆b0┆LCP data test: data error segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆81┆┆82┆ ┆b0┆exp.:<eeee> rec.:<rrrr>↲
↲
┆b0┆The data received was not the equal to the data transmitted as it ↓
┆19┆┄┆81┆┆82┆should be.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆11. ┆b0┆Test 6┆f0┆ = LINE CONTROL PROCESSOR LOOPBACK TEST.↲
↲
This test makes a data transport to the Intel 8051 Line Control ↓
Processor, which loops back the data unchanged. The iAPX 186 ↓
internal DMA channel 0 is initialized to transfer 256 bytes of ↓
data to the LCP channel. The LCP test program is started by ↓
writing a command code 2 to the LCP command port (204 Hex.). The ↓
iAPX 186 internal DMA channel 1 is initialized as the receive ↓
channel, and sinks the data looped back from the LCP channel. The ↓
LCP channels signal with an interrupt to the iAPX 186 processor ↓
when the transfer is complete. The iAPX 186 waits for the ↓
interrupt to occur within 1 second, and if not a timeout message ↓
is written to the "test-output". NOTE that this test loops the ↓
data back from the serial lines also.↲
↲
The test may generate the following error messages:↲
↲
┆b0┆┆f0┆1. ┆b0┆LCP data test: command timeout↲
↲
┆b0┆The Line Control Processor did not respond to the command. The ↓
┆19┆┄┆81┆┆82┆signal called CMDACCEPT on the 8255A port A bit 0 was not set ↓
┆19┆┄┆81┆┆82┆within 1 second.↲
↲
┆b0┆┆f0┆2. ┆b0┆LCP data test: missing terminate interrupt↲
↲
The LCP accepted the command, but no terminate interrupt was ↓
generated witin 1 second after the command accept.↲
↲
┆b0┆┆f0┆3. ┆b0┆LCP data test: transfer error rec.:<00rr>↲
↲
════════════════════════════════════════════════════════════════════════
↓
The LCP test started by this command entered an error condition.↲
The secondary error data is interpreted like this:↲
↲
╞ ╞ 0001 : Timeout - ┆84┆no carrier detected within 50 ↓
┆19┆┆9f┆┄┄microseconds.↲
↲
╞ ╞ 0002 : No Char - ┆84┆carrier detected but no character ↓
┆19┆┆9f┆┄┄received.↲
↲
╞ ╞ 0003 : Parity - 8274 parity error.↲
↲
╞ ╞ 0004 : Framing - 8274 framing error.↲
↲
┆b0┆┆f0┆4. ┆b0┆LCP data test: data error segm.:<ssss> addr.:<aaaa>↲
┆b0┆ ┆b0┆exp.:<eeee> rec.:<rrrr>↲
↲
┆b0┆The data received was not the equal to the data transmitted as it ↓
┆19┆┄┆81┆┆82┆should be.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆12.┆b0┆ Test 7┆f0┆ = V.24 LINE 1 LOOPBACK TEST.↲
↲
This is an ┆b0┆extended┆f0┆ test which must be run with a loop back cable ↓
┆19┆┄┆81┆┄connected. The loop back is made like this:↲
↲
-,TRD1 ------------------------------------- -,RCD1↲
↲
-,RTS1 ------------------------------------- -,RLSD1↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,RFS1↲
↲
-,DTR1 ------------------------------------- -,DSR1↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,CALL1↲
↲
This test makes a data transport of 8 Kbytes of data from a ↓
source buffer to a destination buffer trough the loop back cable. ↓
When the transport is complete the souce and destination buffer ↓
is compared, and if not equal an error message is generated.↲
↲
Before the data transport takes place the status signals are ↓
verified. If a status signal error is discovered an error message ↓
like this is written to the console.↲
↲
┆b0┆┆f0┆1. ┆b0┆Line 1 test: V.24 status error exp.:<000e> rec.:<000r>↲
↲
Only the four least significant bits of the secondary error data ↓
are valid, and each bit corresponds to a status signal like this:↲
↲
Bit 0 = CD , Bit 1 = CTS , Bit 2 = DSR , Bit 3 = CALL↲
↲
Other error messages from this test are:↲
↲
════════════════════════════════════════════════════════════════════════
↓
2. ┆b0┆Line 1 test: transfer timeout↲
↲
The data transport did not complete within 20 seconds.↲
↲
3. ┆b0┆Line 1 test: parity error↲
↲
The 8274 discovered a parity error.↲
↲
4. ┆b0┆Line 1 test: data error segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆81┆┆82┆╞ ╞ ╞ ┆b0┆exp.:<eeee> rec.:<rrrr>↲
↲
The receive buffer is not equal to the transmit buffer as it ↓
should be.↓
↲
The loop back cables have got the RC part number ┆b0┆KBL 630┆f0┆ and ↓
┆19┆┄┆81┆┄interfaces direct to the adapter cable KBL 591.↲
↲
The test is run at app. 4800 baud.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆13. ┆b0┆Test 7┆f0┆ = V.24 LINE 2 LOOPBACK TEST.↲
↲
This is an ┆b0┆extended┆f0┆ test which must be run with a loop back cable ↓
┆19┆┄┆81┆┄connected. The loop back is made like this:↲
↲
-,TRD2 ------------------------------------- -,RCD2↲
↲
-,RTS2 ------------------------------------- -,RLSD2↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,RFS2↲
↲
-,DTR2 ------------------------------------- -,DSR2↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,CALL2↲
↲
This test makes a data transport of 8 Kbytes of data from a ↓
source buffer to a destination buffer trough the loop back cable. ↓
When the transport is complete the souce and destination buffer ↓
is compared, and if not equal an error message is generated.↲
↲
Before the data transport takes place the status signals are ↓
verified. If a status signal error is discovered an error message ↓
like this is written to the console.↲
↲
┆b0┆┆f0┆1. ┆b0┆Line 2 test: V.24 status error exp.:<000e> rec.:<000r>↲
↲
Only the four least significant bits of the secondary error data ↓
are valid, and each bit corresponds to a status signal like this:↲
↲
Bit 0 = CD , Bit 1 = CTS , Bit 2 = DSR , Bit 3 = CALL↲
↲
Other error messages from this test are:↲
↲
════════════════════════════════════════════════════════════════════════
↓
2. ┆b0┆Line 2 test: transfer timeout↲
↲
The data transport did not complete within 20 seconds.↲
↲
3. ┆b0┆Line 2 test: parity error↲
↲
The 8274 discovered a parity error.↲
↲
4. ┆b0┆Line 2 test: data error segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆81┆┆82┆╞ ╞ ╞ ┆b0┆exp.:<eeee> rec.:<rrrr>↲
↲
The receive buffer is not equal to the transmit buffer as it ↓
should be.↲
↲
The loop back cables have got the RC part number ┆b0┆KBL 630┆f0┆ and ↓
┆19┆┄┆81┆┄interfaces direct to the adapter cable KBL 591.↲
↲
The test is run at app. 4800 baud.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆14. ┆b0┆Test 8┆f0┆ = V.24 LINE 3 LOOPBACK TEST.↲
↲
This is an ┆b0┆extended┆f0┆ test which must be run with a loop back cable ↓
┆19┆┄┆81┆┄connected. The loop back is made like this:↲
↲
-,TRD3 ------------------------------------- -,RCD3↲
↲
-,RTS3 ------------------------------------- -,RLSD3↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,RFS3↲
↲
-,DTR3 ------------------------------------- -,DSR3↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,CALL3↲
↲
This test makes a data transport of 8 Kbytes of data from a ↓
source buffer to a destination buffer trough the loop back cable. ↓
When the transport is complete the souce and destination buffer ↓
is compared, and if not equal an error message is generated.↲
↲
Before the data transport takes place the status signals are ↓
verified. If a status signal error is discovered an error message ↓
like this is written to the console.↲
↲
┆b0┆┆f0┆1. ┆b0┆Line 3 test: V.24 status error exp.:<000e> rec.:<000r>↲
↲
Only the four least significant bits of the secondary error data ↓
are valid, and each bit corresponds to a status signal like this:↲
↲
Bit 0 = CD , Bit 1 = CTS , Bit 2 = DSR , Bit 3 = CALL↲
↲
Other error messages from this test are:↲
↲
════════════════════════════════════════════════════════════════════════
↓
2. ┆b0┆Line 3 test: transfer timeout↲
↲
The data transport did not complete within 20 seconds.↲
↲
3. ┆b0┆Line 3 test: parity error↲
↲
The 8274 discovered a parity error.↲
↲
4. ┆b0┆Line 3 test: data error segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆81┆┆82┆╞ ╞ ╞ ┆b0┆exp.:<eeee> rec.:<rrrr>↲
↲
The receive buffer is not equal to the transmit buffer as it ↓
should be.↲
↲
The loop back cables have got the RC part number ┆b0┆KBL 630┆f0┆ and ↓
┆19┆┄┆81┆┄interfaces direct to the adapter cable KBL 591.↲
↲
The test is run at app. 4800 baud.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆15. LED OUTPUT.↲
↲
During the selftest the test numbers are written to the four on-↓
board light emitting diodes (LED's), and if an error occur the ↓
test is halted, and the test number on the LED's will be ↓
flashing.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆A. REFERENCES↲
↲
(1) RCSL. 991 10092↲
RC 39 Selftest Concept, ↲
User's manual ╞ ↲
↲
(2) RCSL. 991 10096↲
RC 3931 ETC611 hardware selftest, ↲
User's manual ↲
↲
(3) RCSL. 991 10097↲
F641 COM 601 hardware selftest, ↲
User's manual ↲
↲
(4) RCSL. 991 10094↲
RC3902 hardware selftest, ↲
User's manual╞ ↲
↲
(5) RCSL. 991 10134↲
RC39 monitor 8086 version, ↲
Reference manual╞ ↲
↲
(6) RCSL. 991 10093↲
RC39 monitor 80286 version, ↲
Reference manual ↲
════════════════════════════════════════════════════════════════════════
↓
↲
┆05┆↓
┆1a┆┆1a┆ignal like this:↲
↲
Bit 0 = CD , Bit 1 = CTS , Bit 2 = DSR , Bit 3 = CALL↲
↲
Other error messages fro