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Length: 23936 (0x5d80)
Types: RcTekst
Names: »99110095.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110095.WP«
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↓
┆a1┆┆a1┆↲
↲
╞ Edition:╞ 1985.04.09↲
╞ Author: Peter Lundbo↲
╞ RCSL No.:╞ 991 10095↲
↲
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INTERNAL DOCUMENT↲
════════════════════════════════════════════════════════════════════════
↓
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↲
↲
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↲
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↲
Title:↲
↲
┆06┆┆84┆ITC 602 hardware selftest↲
user's manual↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a0006000000000301413140000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000201413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆06┆i↲
↲
┆a1┆┆b0┆TABLE OF CONTENTS╞ ╞ ╞ ┆05┆PAGE ↲
↲
1. INTRODUCTION ......................................... 1↲
↲
2. THE DUAL CHANNEL COMMUNICATION APPROACH .............╞ 2↲
↲
3. THE BAUD RATE DETERMINATION MODE .....................╞ 3↲
↲
4. INTERRUPT HANDLING ................................... 4↲
4.1 Valid Interrupts .................................╞ 4↲
╞ 4.2 Instruction Exceptions ...........................╞ 5↲
4.3 Illegal Slave Interrupts .........................╞ 5↲
4.4 Illegal Master Interrupts ........................╞ 6↲
4.5 Non Maskable Interrupt ...........................╞ 8↲
↲
5. TEST 0 = MEMORY TEST ................................. 9↲
5.1 PROM Checksum Test ...............................╞ 9↲
5.2 RAM Memory Test ..................................╞ 9↲
5.2.1 Memory Test Pattern ........................ 10↲
5.2.2 Memory Test Flow ........................... 10↲
╞ 5.2.3 Loop On Error .............................. 11↲
↲
6. TEST 1 = CHIP SELECT TEST ............................ 12↲
↲
7. TEST 2 = iAPX 186 TIMER TEST ......................... 13↲
↲
8. TEST 3 = iAPX 186 DMA TEST ........................... 14↲
↲
9. TEST 4 = PARELLEL PORT TEST .......................... 15↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆TABLE OF CONTENTS (continued)┆05┆PAGE↲
↲
10. TEST 5 = LINE CONTROL PROCESSOR DATA TEST ............ 16↲
↲
11. TEST 6 = LINE CONTROL PROCESSOR LOOPBACK TEST ........ 17↲
↲
12. TEST 7 = V.24 LINE 1 LOOPBACK TEST .................... 19↲
↲
13. TEST 8 = V.24 LINE 2 LOOPBACK TEST .................... 21↲
↲
14. TEST 9 = V.24 LINE 3 LOOPBACK TEST .................... 23↲
↲
15. LED OUTPUT ............................................ 25↲
↲
↲
┆a1┆┆b0┆APPENDIX↲
↲
A. REFERENCES ............................................. 27↲
↲
════════════════════════════════════════════════════════════════════════
↓
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆╞ ╞ ╞ ╞ ┆0b┆┆a1┆↲
┆a1┆┆a1┆┆b0┆1. INTRODUCTION.↲
↲
The ITC 602 is an Intelligent Terminal Controller, which is an ↓
intelligent Multibus SBC used to interface terminals to the RC 39 ↓
product. A maximum of 32 + 4 terminals may be connected to an ITC ↓
602. Four of these terminals may be connected via standard V.24 ↓
interface, whereas the remaining 32 terminal must be connnected ↓
via the new circuit II serial interface.↲
↲
This manual assume that the reader is familiar with the RC 39 ↓
selftest concept as described in the manual called "The RC 39 ↓
Selftest Concept". The ITC 602 selftest includes 10 different ↓
tests which may be run in several modes. Seven of these tests are ↓
┆b0┆default┆f0┆ tests which allways execute after a power on. The last ↓
┆19┆┄┆81┆┄tree tests are ┆b0┆extended┆b0┆┆f0┆ tests which is run only when requested ↓
┆19┆┄┆83┆┄explicit by an operator. This version of the ITC 602 includes no ↓
┆19┆┄┆83┆┄┆b0┆seperately┆f0┆ run ┆f0┆tests.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆┆b0┆2. THE DUAL CHANNEL COMMUNICATION APPROACH.↲
↲
The ITC 602 SBC selftest supports the Dual Channel Communication ↓
facility as described in the "RC 39 Selftest Concept". If the ↓
strap ST7-23 is inserted the communication goes via the on-board ↓
8274 USART line 0, otherwise if the strap is omitted the ↓
communication goes transparently through the Multibus interface ↓
to a console connected to the "test-master" usually a CPU 691 or ↓
a CPU 610 board.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆3. THE BAUD RATE ┆a1┆DETERMINATION MODE.↲
↲
If the starp ST7-23 is inserted and a terminal is connected to the ↓
V.24 line 0 interface (DSR activ) then the selftest enters the ↓
automatic Baud Rate Determination mode. The USART is initialized ↓
to 9600 Baud and stars (*****) are written to line 0. These stars ↓
may be seen as stars, other mixed characters or not seen at all ↓
depending on the Baud Rate of the attached console. The selftest ↓
waits for the operator to enter one or two upper case U. One ↓
upper case U is enough if the Baud Rate is 9600, 4800 or 2400 ↓
Baud. Baud Rates of 1200, 600 or 300 requires two upper case U.↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆4. INTERRUPT HANDLING.↲
↲
When the ITC 602 SBC selftest has finished the memory test, a set ↓
of default interrupt vectors are loaded into the vector table. ↓
These vectors are used to handle both expected and unexpected ↓
interrupts.↲
↲
↲
┆a1┆┆b0┆4.1 Valid Interrupts.↲
↲
The interrupts that are considered valid during the selftest are:↲
↲
┆a1┆Request line Interrupt name Vector type Event type ↲
↲
internal Step interrupt 1╞ ┆84┆instruction executed ↓
┆19┆┆ac┆┄┄with trap flag set↲
↲
internal╞ Break interrupt╞ 3╞ ┆84┆software interrupt ↓
┆19┆┆ac┆┄┄(debugger entry)↲
↲
internal╞ Timer 0╞ ╞ 8╞ Timer 0 interrupt↲
↲
INT 0╞ USART receive int.╞ 30╞ Keyboard interrupt↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆4.2 Instruction Exceptions.↲
↲
Some of the interrupts will generate an error message like this:↲
↲
┆b0┆┆f0┆1. ┆b0┆>> instruction exception↲
↲
┆a1┆Request line Interrupt name Vector type Event type ↲
↲
internal╞ Divide error╞ 0╞ Divede with zero↲
↲
internal╞ Owerflow╞ ╞ 4╞ INT0↲
↲
internal╞ Array Bounds╞ 5╞ BOUND↲
↲
internal╞ Unused Opcode╞ 6╞ Undefined opcode↲
↲
internal╞ ESC Opcode╞ 7╞ ESC opcodes↲
↲
↲
┆a1┆┆b0┆4.3 Illegal Slave Interrupts.↲
↲
Some of the interrupts will generate an error message like this:↲
↲
┆b0┆┆f0┆2. ┆b0┆illegal interrupt rec.:<rrrr>↲
↲
The secondary error data is the content of the iAPX 186 internal ↓
interrupt In Service Register (ISR) during the interrupt. This ↓
register at I/O address FF2C Hex. indicates which interrupt(s) ↓
are active. The ISR format is like this :↲
↲
┆a1┆15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0↲
0 0 X X X 0 0 0 I3 I2 I1 I0 D1 D2 0 TMR↲
↲
A one indicates that an interrupt is active.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Request line Interrupt name Vector type Event type ↲
↲
reserved╞ ╞ 9↲
↲
internal╞ DMA 0╞ 10╞ DMA ch. 0 complete↲
↲
internal╞ DMA 1╞ 11╞ DMA ch. 1 complete↲
↲
INT 0╞ INT0╞ 12╞ Serial line int.↲
↲
INT 1╞ MBFLAGINT╞ 13╞ flag byte int.↲
↲
INT 2╞ not used╞ 14╞ (acknowledge to INT0)↲
↲
INT 3 ╞ LCPINT╞ 15╞ circuit II interrupt↲
↲
internal╞ not used╞ 16↲
↲
internal╞ not used╞ 17↲
↲
internal╞ timer 2╞ 19╞ timer run out↲
↲
↲
┆a1┆┆b0┆4.4 Illegal Master Interrupts↲
↲
Some of the interrupts will generate an error message like this:↲
↲
┆b0┆┆f0┆3. ┆b0┆illegal line 0-1 interrupt lev.:<00ll> rec.:<rrrr>↲
↲
or↲
┆b0┆┆f0┆↲
4. ┆b0┆illegal line 2-3 interrupt lev.:<00ll> rec.:<rrrr>↲
↲
↲
┆8c┆┆83┆┆98┆↓
The level information is a read of the 8274 internal register RR2 ↓
where the interrupt level is stored. The rec information is a ↓
read of the 8274 RR0 and RR1 where the cause of interrupt may be ↓
further specified. RR1 is stored in the most significant byte of ↓
the received value. Consult INTEL data shets for further ↓
information about the Serial Line Controller 8274.↲
↲
┆a1┆Request line Interrupt name Vector type Event type ↲
↲
INT 0╞ TX empty╞ ╞ 24╞ Line 1 TX empty↲
↲
INT 0╞ Ext. Status ch.╞ 25╞ Line 1 Status change↲
↲
INT 0╞ RX available╞ 26╞ Line 1 RX character↲
↲
INT 0╞ Frame/Parity╞ 27╞ Line 1 Frame/Parity↲
↲
INT 0╞ TX empty╞ ╞ 28╞ Line 0 TX empty↲
↲
INT 0╞ Ext. Status ch.╞ 29╞ Line 0 Status change↲
↲
INT 0╞ Frame/Parity╞ 31╞ Line 0 Frame/Parity↲
↲
INT 0╞ TX empty╞ ╞ 32 Line 3 TX empty↲
↲
INT 0╞ Ext. Status ch.╞ 33╞ Line 3 Status change↲
↲
INT 0╞ RX available╞ 34╞ Line 3 RX character↲
↲
INT 0╞ Frame/Parity╞ 35╞ Line 3 Frame/Parity↲
↲
INT 0╞ TX empty╞ ╞ 36╞ Line 2 TX empty↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Request line Interrupt name Vector type Event type ↲
↲
INT╞ 0╞ Ext. Status ch.╞ 37╞ Line 2 Status change↲
↲
INT 0╞ RX available╞ 38╞ Line 2 RX character↲
↲
INT 0╞ Frame/Parity╞ 39 ╞ Line 3 Frame/Parity↲
↲
↲
┆a1┆┆b0┆4.5 Non Maskable Interrupt.↲
↲
If a non maskable interrupt (NMI) interrupt occur during the ↓
selftest the following message is written to the console and the ↓
processor is halted.↲
↲
┆b0┆┆f0┆5. ┆b0┆NMI interrupt - test HALTED !↲
↲
There is no way to get the selftest out of this halt situation ↓
except reset. Note that the NMI pin on the processor is grounded, ↓
so that it is unlikely that NMI interrupts occur.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5. ┆b0┆Test 0 = ┆f0┆MEMORY TEST.↲
↲
The memory test of the ITC 602 SBC selftest consists of two ↓
parts, a PROM checksum test and a RAM memory test. The PROM ↓
checksum test is only run once after power up or external reset, ↓
whereas the RAM memory test may be run several times, if ↓
requested by the operator.↲
↲
↲
┆b0┆┆a1┆5.1 PROM Checksum Test.↲
↲
The contents of both the odd and the even PROM are summarized ↓
bytewise and the result must be a zero. For that reason the ↓
PROM's contain a compensation byte which is used to bring the sum ↓
to zero.↲
┆a1┆↲
┆b0┆┆f0┆1. ┆b0┆checksum test: sum error exp.:<0000> rec.:<xyzw>↲
↲
Checksum error usually means that the content of the PROM has ↓
been damaged and that the PROM must be changed.↲
↲
↲
┆b0┆┆a1┆5.2 RAM Memory Test.↲
↲
The RAM memory test of the ITC 602 SBC selftest verifies the on-↓
board 64 kbytes memory.↲
↲
The memory test is a register based test and uses no memory space ↓
at all, neither for variables nor stack. The test verifies every ↓
single byte of the on-board memory.↲
↲
This fact lets only one register for test variables survive the ↓
memory test. That variable contains all the test switches and the ↓
test number. ↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5.2.1 Memory Test Pattern.↲
↲
The on-board Dual Ported RAM memory consists of memory chips of 4 ↓
bit * 16 K. The memory test executes 4 passes trough the entire ↓
memory, two times writing and two times reading.↲
↲
The test pattern is the convenient modulus 3 pattern consisting ↓
of three times 0000 followed by three times FFFF ( hexadecimal ).↲
↲
↲
┆a1┆┆b0┆5.2.2 Memory Test Flow.↲
↲
The test starts in the highest RAM addresses and inserts the pattern ↓
towards lower addresses.↲
↲
When all memory words have been written and verified, they are ↓
tested again with the inversed pattern, this means, that all bits ↓
are tested for "zero" and "one" insertion. If an error occur then ↓
an attempt to send the following message, to the "test-output", ↓
is made :↲
↲
┆a1┆┆b0┆┆f0┆2. ┆b0┆RAM test: RAM error segm.:<ssss> addr.:<aaaa> exp.:<eeee>↲
╞ ╞ ╞ ╞ ┆b0┆ rec.:<rrrr>↲
↲
The secondary text is interpreted like this :↲
↲
<ssss> is the segment address↲
<aaaa> is the address offset↲
<eeee> is the expected pattern, should allways be 0000 or FFFF.↲
<rrrr> is the received pattern.↲
↲
┆8c┆┆82┆┆f4┆↓
The above mentioned information may be used to find a defective ↓
RAM memory chip from the knowledge of the RAM-layout. Say the ↓
error message goes like this :↲
↲
┆b0┆RAM test : RAM error segm.:0000 addr.:0002 exp.:0000↲
┆19┆┄┆81┆┆82┆╞ ╞ ╞ ╞ ╞ ┆b0┆rec.:0003↲
↲
The RAM is made of 16K * 4 bit chips. This means that U46, U47, ↓
U48 and U49 builds a low address memory bank (0-7FFF), and that ↓
U56, U57, U58 and U59 builds a high address memory bank (8000-↓
FFFF). Each RAM chip contains a nibble (4 bits) of data ↓
corresponding to one hexadecimal digit in the secondary error ↓
data. The message above might indicate a failure in RAM chip U ↓
63.↲
↲
↲
┆b0┆┆a1┆5.2.3 Loop On Error.↲
↲
When a fault occur during the ram test an error message is ↓
written to the console, and the RAM test starts from the start ↓
again. This will be the case until no error is discovered. If ↓
there is a RAM error and if an L is typed from the keyboard, then ↓
the RAM test will not start from the beginning again, but proceed ↓
trough the RAM test and write all RAM errors to the console, and ↓
finally enter the "test-administrator" to execute other tests.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆6. ┆b0┆Test 1 = ┆f0┆CHIP SELECT TEST.↲
↲
To ease complex debugging, a simple chip select loop, combined ↓
with a RAM write/read, is supplied. ↲
↲
This test generates chip selects to all peripheral devices by ↓
executing input instructions to all relevant I/O-devices. These ↓
are :↲
↲
Port ┆84┆0, 2, 128, 130, 256, 258, 260, 262, 384, 386, 388, 390, 392, ↓
┆19┆┆85┆┄┄394, 396, 398, 512, 514, 516, 518, 640, 642, 644, 646, 648, ↓
┆19┆┆85┆┄┄650, 652, 654.↲
↲
When all the chip selects are made, a pattern AA55 hex. is ↓
written to a RAM cell and immediately read back.↲
↲
This test is unable to generate any error messages. It is meant ↓
only as a special fast scope loop test.↲
════════════════════════════════════════════════════════════════════════
↓
┆a2┆┆e2┆┆a1┆┆b0┆┆b0┆7. ┆b0┆TEST 2┆f0┆ = iAPX 186 TIMER TEST.↲
↲
This test verifies the ability of the iAPX 186 internal timer 0 ↓
to generate interrupts. The internal timer 0 is initialized as a ↓
real time clock which generates interrupt every 20 millisecond. ↓
If no timer interrupt is generated then an error message is ↓
generated like this.↲
↲
┆a1┆┆a1┆┆a1┆┆e1┆┆b0┆┆f0┆1. ┆b0┆iAPX186 timer test : missing timer 0 interrupt↲
↲
This error should indicate a malfunction of the iAPX 186 ↓
processor chip.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆8. ┆b0┆TEST 3┆f0┆ = iAPX 186 DMA TEST.↲
↲
This test verifies the ability of the two iAPX 186 internal DMA ↓
channels to make a data transport and to generate interrupts. The ↓
two iAPX 186 DMA channels are initialized to perform a DMA memory ↓
to memory transport simultaneously. DMA channel 0 copies 8 Kbytes ↓
from a source to a destination buffer in the forward direction, ↓
and DMA channel 1 copies from the same source to another ↓
destination buffer in the reverse direction. All DMA transfers ↓
are syncronized to the internal timer 2 which generates a 250 KHz ↓
clock. The two channels are initialized to the same priority. ↓
This ensures together with the selected internal timer 2 ↓
syncronization that both DMA channels runs simultaneously and ↓
that the CPU may also get memory access. When the DMA transport ↓
is complete both destination buffers are compared to the source ↓
buffer.↲
↲
The test produces the following error messages:↲
↲
┆b0┆┆f0┆1. ┆b0┆DMA test: data error segm.: <ssss> addr.:<aaaa> rec.:<rrrr>↲
┆19┆┄┆82┆┆82┆╞ ╞ ╞ ╞ ╞ ┆b0┆exp.:<eeee>↲
↲
┆b0┆┆f0┆2. ┆b0┆DMA test: transfer timeout↲
↲
The first error indictes that both DMA transports has terminated ↓
but the destination buffer is not equal to the source as ↓
expected. The latter indicates that one of the two or both DMA ↓
interrupts is missing.↲
↲
Both errors should indicate a malfunction of the iAPX 186 ↓
processor chip.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆9.┆b0┆ Test 4 =┆f0┆ PARALLEL PORT TEST.↲
↲
The 8255A PPI test writes a pattern 10100000 binary to the output ↓
port B ( ioadr. A1H ). Then it reads the pattern back and ↓
verifies it. If no error is detected the pattern is shifted one ↓
bit to the right, and the write/read verify procedure is repeated ↓
until the pattern becomes zero. The test may generate this error ↓
message:↲
↲
┆b0┆┆e1┆┆a1┆┆e1┆┆f0┆1. ┆b0┆PPI test: port error exp.:00ee, rec.:00rr↲
↲
Expected and received pattern tells you what bits went wrong with ↓
the test.↲
↲
This error might be caused by malfunction of the 8255A chip, by ↓
an initialization fault ( I/O space error ), or by something ↓
else. ↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆10. ┆b0┆Test 5┆f0┆ = LINE CONTROL PROCESSOR DATA TEST.↲
↲
This test makes a data transport to the Intel 8051 Line Control ↓
Processor, which loops back the data unchanged. The iAPX 186 ↓
internal DMA channel 0 is initialized to transfer 256 bytes of ↓
data to the LCP channel. The LCP test program is started by ↓
writing a command code 1 to the LCP command port (204 Hex.). The ↓
iAPX 186 internal DMA channel 1 is initialized as the receive ↓
channel, and sinks the data looped back from the LCP channel. The ↓
LCP channels signal with an interrupt to the iAPX 186 processor ↓
when the transfer is complete. The iAPX 186 waits for the ↓
interrupt to occur within 1 second, and if not a timeout message ↓
is written to the "test-output". NOTE that the data written to ↓
the LCP is not looped back on the serial line, only an internal ↓
loopback is made.↲
↲
The test may generate the following error messages:↲
↲
┆b0┆┆f0┆1. ┆b0┆LCP data test: command timeout↲
↲
┆b0┆The Line Control Processor did not respond to the command. The ↓
┆19┆┄┆81┆┆82┆signal called CMDACCEPT on the 8255A port A bit 0 was not set ↓
┆19┆┄┆81┆┆82┆within 1 second.↲
↲
┆b0┆┆f0┆2. ┆b0┆LCP data test: missing terminate interrupt↲
↲
The LCP accepted the command, but no terminate interrupt was ↓
generated witin 1 second after the command accept.↲
↲
┆b0┆┆f0┆3. ┆b0┆LCP data test: data error segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆81┆┆82┆ ┆b0┆exp.:<eeee> rec.:<rrrr>↲
↲
┆b0┆The data received was not the equal to the data transmitted as it ↓
┆19┆┄┆81┆┆82┆should be.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆11. ┆b0┆Test 6┆f0┆ = LINE CONTROL PROCESSOR LOOPBACK TEST.↲
↲
This test makes a data transport to the Intel 8051 Line Control ↓
Processor, which loops back the data unchanged. The iAPX 186 ↓
internal DMA channel 0 is initialized to transfer 256 bytes of ↓
data to the LCP channel. The LCP test program is started by ↓
writing a command code 2 to the LCP command port (204 Hex.). The ↓
iAPX 186 internal DMA channel 1 is initialized as the receive ↓
channel, and sinks the data looped back from the LCP channel. The ↓
LCP channels signal with an interrupt to the iAPX 186 processor ↓
when the transfer is complete. The iAPX 186 waits for the ↓
interrupt to occur within 1 second, and if not a timeout message ↓
is written to the "test-output". NOTE that this test loops the ↓
data back from the serial lines also.↲
↲
The test may generate the following error messages:↲
↲
┆b0┆┆f0┆1. ┆b0┆LCP data test: command timeout↲
↲
┆b0┆The Line Control Processor did not respond to the command. The ↓
┆19┆┄┆81┆┆82┆signal called CMDACCEPT on the 8255A port A bit 0 was not set ↓
┆19┆┄┆81┆┆82┆within 1 second.↲
↲
┆b0┆┆f0┆2. ┆b0┆LCP data test: missing terminate interrupt↲
↲
The LCP accepted the command, but no terminate interrupt was ↓
generated witin 1 second after the command accept.↲
↲
┆b0┆┆f0┆3. ┆b0┆LCP data test: transfer error rec.:<00rr>↲
↲
════════════════════════════════════════════════════════════════════════
↓
The LCP test started by this command entered an error condition.↲
The secondary error data is interpreted like this:↲
↲
╞ ╞ 0001 : Timeout - ┆84┆no carrier detected within 50 ↓
┆19┆┆9f┆┄┄microseconds.↲
↲
╞ ╞ 0002 : No Char - ┆84┆carrier detected but no character ↓
┆19┆┆9f┆┄┄received.↲
↲
╞ ╞ 0003 : Parity - 8274 parity error.↲
↲
╞ ╞ 0004 : Framing - 8274 framing error.↲
↲
┆b0┆┆f0┆4. ┆b0┆LCP data test: data error segm.:<ssss> addr.:<aaaa>↲
┆b0┆ ┆b0┆exp.:<eeee> rec.:<rrrr>↲
↲
┆b0┆The data received was not the equal to the data transmitted as it ↓
┆19┆┄┆81┆┆82┆should be.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆12.┆b0┆ Test 7┆f0┆ = V.24 LINE 1 LOOPBACK TEST.↲
↲
This is an ┆b0┆extended┆f0┆ test which must be run with a loop back cable ↓
┆19┆┄┆81┆┄connected. The loop back is made like this:↲
↲
-,TRD1 ------------------------------------- -,RCD1↲
↲
-,RTS1 ------------------------------------- -,RLSD1↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,RFS1↲
↲
-,DTR1 ------------------------------------- -,DSR1↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,CALL1↲
↲
This test makes a data transport of 8 Kbytes of data from a ↓
source buffer to a destination buffer trough the loop back cable. ↓
When the transport is complete the souce and destination buffer ↓
is compared, and if not equal an error message is generated.↲
↲
Before the data transport takes place the status signals are ↓
verified. If a status signal error is discovered an error message ↓
like this is written to the console.↲
↲
┆b0┆┆f0┆1. ┆b0┆Line 1 test: V.24 status error exp.:<000e> rec.:<000r>↲
↲
Only the four least significant bits of the secondary error data ↓
are valid, and each bit corresponds to a status signal like this:↲
↲
Bit 0 = CD , Bit 1 = CTS , Bit 2 = DSR , Bit 3 = CALL↲
↲
Other error messages from this test are:↲
↲
════════════════════════════════════════════════════════════════════════
↓
2. ┆b0┆Line 1 test: transfer timeout↲
↲
The data transport did not complete within 20 seconds.↲
↲
3. ┆b0┆Line 1 test: parity error↲
↲
The 8274 discovered a parity error.↲
↲
4. ┆b0┆Line 1 test: data error segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆81┆┆82┆╞ ╞ ╞ ┆b0┆exp.:<eeee> rec.:<rrrr>↲
↲
The receive buffer is not equal to the transmit buffer as it ↓
should be.↓
↲
The loop back cables have got the RC part number ┆b0┆KBL 630┆f0┆ and ↓
┆19┆┄┆81┆┄interfaces direct to the adapter cable KBL 591.↲
↲
The test is run at app. 4800 baud.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆13. ┆b0┆Test 7┆f0┆ = V.24 LINE 2 LOOPBACK TEST.↲
↲
This is an ┆b0┆extended┆f0┆ test which must be run with a loop back cable ↓
┆19┆┄┆81┆┄connected. The loop back is made like this:↲
↲
-,TRD2 ------------------------------------- -,RCD2↲
↲
-,RTS2 ------------------------------------- -,RLSD2↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,RFS2↲
↲
-,DTR2 ------------------------------------- -,DSR2↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,CALL2↲
↲
This test makes a data transport of 8 Kbytes of data from a ↓
source buffer to a destination buffer trough the loop back cable. ↓
When the transport is complete the souce and destination buffer ↓
is compared, and if not equal an error message is generated.↲
↲
Before the data transport takes place the status signals are ↓
verified. If a status signal error is discovered an error message ↓
like this is written to the console.↲
↲
┆b0┆┆f0┆1. ┆b0┆Line 2 test: V.24 status error exp.:<000e> rec.:<000r>↲
↲
Only the four least significant bits of the secondary error data ↓
are valid, and each bit corresponds to a status signal like this:↲
↲
Bit 0 = CD , Bit 1 = CTS , Bit 2 = DSR , Bit 3 = CALL↲
↲
Other error messages from this test are:↲
↲
════════════════════════════════════════════════════════════════════════
↓
2. ┆b0┆Line 2 test: transfer timeout↲
↲
The data transport did not complete within 20 seconds.↲
↲
3. ┆b0┆Line 2 test: parity error↲
↲
The 8274 discovered a parity error.↲
↲
4. ┆b0┆Line 2 test: data error segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆81┆┆82┆╞ ╞ ╞ ┆b0┆exp.:<eeee> rec.:<rrrr>↲
↲
The receive buffer is not equal to the transmit buffer as it ↓
should be.↲
↲
The loop back cables have got the RC part number ┆b0┆KBL 630┆f0┆ and ↓
┆19┆┄┆81┆┄interfaces direct to the adapter cable KBL 591.↲
↲
The test is run at app. 4800 baud.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆14. ┆b0┆Test 8┆f0┆ = V.24 LINE 3 LOOPBACK TEST.↲
↲
This is an ┆b0┆extended┆f0┆ test which must be run with a loop back cable ↓
┆19┆┄┆81┆┄connected. The loop back is made like this:↲
↲
-,TRD3 ------------------------------------- -,RCD3↲
↲
-,RTS3 ------------------------------------- -,RLSD3↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,RFS3↲
↲
-,DTR3 ------------------------------------- -,DSR3↲
╞ ╞ ╞ !↲
╞ ╞ ╞ ------------------- -,CALL3↲
↲
This test makes a data transport of 8 Kbytes of data from a ↓
source buffer to a destination buffer trough the loop back cable. ↓
When the transport is complete the souce and destination buffer ↓
is compared, and if not equal an error message is generated.↲
↲
Before the data transport takes place the status signals are ↓
verified. If a status signal error is discovered an error message ↓
like this is written to the console.↲
↲
┆b0┆┆f0┆1. ┆b0┆Line 3 test: V.24 status error exp.:<000e> rec.:<000r>↲
↲
Only the four least significant bits of the secondary error data ↓
are valid, and each bit corresponds to a status signal like this:↲
↲
Bit 0 = CD , Bit 1 = CTS , Bit 2 = DSR , Bit 3 = CALL↲
↲
Other error messages from this test are:↲
↲
════════════════════════════════════════════════════════════════════════
↓
2. ┆b0┆Line 3 test: transfer timeout↲
↲
The data transport did not complete within 20 seconds.↲
↲
3. ┆b0┆Line 3 test: parity error↲
↲
The 8274 discovered a parity error.↲
↲
4. ┆b0┆Line 3 test: data error segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆81┆┆82┆╞ ╞ ╞ ┆b0┆exp.:<eeee> rec.:<rrrr>↲
↲
The receive buffer is not equal to the transmit buffer as it ↓
should be.↲
↲
The loop back cables have got the RC part number ┆b0┆KBL 630┆f0┆ and ↓
┆19┆┄┆81┆┄interfaces direct to the adapter cable KBL 591.↲
↲
The test is run at app. 4800 baud.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆15. LED OUTPUT.↲
↲
During the selftest the test numbers are written to the four on-↓
board light emitting diodes (LED's), and if an error occur the ↓
test is halted, and the test number on the LED's will be ↓
flashing.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆A. REFERENCES↲
↲
(1) RCSL. 991 10092↲
RC 39 Selftest Concept, ↲
User's manual ╞ ↲
↲
(2) RCSL. 991 10096↲
RC 3931 ETC611 hardware selftest, ↲
User's manual ↲
↲
(3) RCSL. 991 10097↲
F641 COM 601 hardware selftest, ↲
User's manual ↲
↲
(4) RCSL. 991 10094↲
RC3902 hardware selftest, ↲
User's manual╞ ↲
↲
(5) RCSL. 991 10134↲
RC39 monitor 8086 version, ↲
Reference manual╞ ↲
↲
(6) RCSL. 991 10093↲
RC39 monitor 80286 version, ↲
Reference manual ↲
════════════════════════════════════════════════════════════════════════
↓
↲
┆05┆↓
┆1a┆┆1a┆ignal like this:↲
↲
Bit 0 = CD , Bit 1 = CTS , Bit 2 = DSR , Bit 3 = CALL↲
↲
Other error messages fro
0x0000…0020 (0,) 00 00 00 00 00 00 00 00 42 03 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4e 00 00 00 ┆ B N ┆
0x0020…0040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
0x0040…0047 00 00 00 00 00 00 00 ┆ ┆
0x0047…0080 Params {
0x0047…0080 04 00 2d 4e 0a 00 06 00 00 00 00 02 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0x0047…0080 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x0047…0080 }
0x0080…0083 FormFeed {
0x0080…0083 0c 80 82 ┆ ┆
0x0080…0083 }
0x0083…00a0 0a a1 a1 0d 0a 0d 0a 09 45 64 69 74 69 6f 6e 3a 09 31 39 38 35 2e 30 34 2e 30 39 0d 0a ┆ Edition: 1985.04.09 ┆
0x00a0…00c0 09 41 75 74 68 6f 72 3a 20 20 20 50 65 74 65 72 20 4c 75 6e 64 62 6f 0d 0a 09 52 43 53 4c 20 4e ┆ Author: Peter Lundbo RCSL N┆
0x00c0…00e0 6f 2e 3a 09 39 39 31 20 31 30 30 39 35 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 20 ┆o.: 991 10095 ┆
0x00e0…0100 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 49 4e 54 45 52 4e 41 4c ┆ INTERNAL┆
0x0100…010b 20 44 4f 43 55 4d 45 4e 54 0d 0a ┆ DOCUMENT ┆
0x010b…010e FormFeed {
0x010b…010e 0c 80 f0 ┆ ┆
0x010b…010e }
0x010e…0120 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 54 ┆ T┆
0x0120…0140 69 74 6c 65 3a 0d 0a 0d 0a 06 84 49 54 43 20 36 30 32 20 68 61 72 64 77 61 72 65 20 73 65 6c 66 ┆itle: ITC 602 hardware self┆
0x0140…0160 74 65 73 74 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆test ┆
0x0160…016f 75 73 65 72 27 73 20 6d 61 6e 75 61 6c 0d 0a ┆user's manual ┆
0x016f…0172 FormFeed {
0x016f…0172 0c 80 e0 ┆ ┆
0x016f…0172 }
0x0172…0173 0a ┆ ┆
0x0173…01ac Params {
0x0173…01ac 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 41 31 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1@ ┆
0x0173…01ac 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x0173…01ac }
0x01ac…01e5 Params {
0x01ac…01e5 04 00 2d 4e 0a 00 06 00 00 00 00 02 01 41 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1 ┆
0x01ac…01e5 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x01ac…01e5 }
0x01e5…0200 0a 06 69 0d 0a 0d 0a a1 b0 54 41 42 4c 45 20 4f 46 20 43 4f 4e 54 45 4e 54 53 09 ┆ i TABLE OF CONTENTS ┆
0x0200…0220 (1,) 09 09 20 20 20 20 20 05 50 41 47 45 20 20 0d 0a 0d 0a 31 2e 20 20 49 4e 54 52 4f 44 55 43 54 49 ┆ PAGE 1. INTRODUCTI┆
0x0220…0240 4f 4e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ON .............................┆
0x0240…0260 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 20 20 31 0d 0a 0d 0a 32 2e 20 20 54 48 45 20 44 ┆............ 1 2. THE D┆
0x0260…0280 55 41 4c 20 43 48 41 4e 4e 45 4c 20 43 4f 4d 4d 55 4e 49 43 41 54 49 4f 4e 20 41 50 50 52 4f 41 ┆UAL CHANNEL COMMUNICATION APPROA┆
0x0280…02a0 43 48 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 09 32 0d 0a 0d 0a 33 2e 20 20 54 48 45 20 42 41 ┆CH ............. 2 3. THE BA┆
0x02a0…02c0 55 44 20 52 41 54 45 20 44 45 54 45 52 4d 49 4e 41 54 49 4f 4e 20 4d 4f 44 45 20 2e 2e 2e 2e 2e ┆UD RATE DETERMINATION MODE .....┆
0x02c0…02e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 09 33 0d 0a 0d 0a 34 2e 20 20 49 4e 54 45 52 52 ┆................ 3 4. INTERR┆
0x02e0…0300 55 50 54 20 48 41 4e 44 4c 49 4e 47 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆UPT HANDLING ...................┆
0x0300…0320 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 20 20 34 0d 0a 20 20 20 20 34 2e 31 ┆................ 4 4.1┆
0x0320…0340 20 56 61 6c 69 64 20 49 6e 74 65 72 72 75 70 74 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ Valid Interrupts ..............┆
0x0340…0360 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 09 34 0d 0a 09 34 2e 32 20 49 6e 73 74 ┆................... 4 4.2 Inst┆
0x0360…0380 72 75 63 74 69 6f 6e 20 45 78 63 65 70 74 69 6f 6e 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ruction Exceptions .............┆
0x0380…03a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 09 35 0d 0a 20 20 20 20 34 2e 33 20 49 6c 6c 65 67 61 ┆.............. 5 4.3 Illega┆
0x03a0…03c0 6c 20 53 6c 61 76 65 20 49 6e 74 65 72 72 75 70 74 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆l Slave Interrupts .............┆
0x03c0…03e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 09 35 0d 0a 20 20 20 20 34 2e 34 20 49 6c 6c 65 67 61 6c 20 ┆............ 5 4.4 Illegal ┆
0x03e0…0400 4d 61 73 74 65 72 20 49 6e 74 65 72 72 75 70 74 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆Master Interrupts ..............┆
0x0400…0420 (2,) 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 09 36 0d 0a 20 20 20 20 34 2e 35 20 4e 6f 6e 20 4d 61 73 6b 61 62 ┆.......... 6 4.5 Non Maskab┆
0x0420…0440 6c 65 20 49 6e 74 65 72 72 75 70 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆le Interrupt ...................┆
0x0440…0460 2e 2e 2e 2e 2e 2e 2e 2e 09 38 0d 0a 0d 0a 35 2e 20 20 54 45 53 54 20 30 20 3d 20 4d 45 4d 4f 52 ┆........ 8 5. TEST 0 = MEMOR┆
0x0460…0480 59 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆Y TEST .........................┆
0x0480…04a0 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 20 20 39 0d 0a 20 20 20 20 35 2e 31 20 50 52 4f 4d 20 43 68 ┆........ 9 5.1 PROM Ch┆
0x04a0…04c0 65 63 6b 73 75 6d 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ecksum Test ....................┆
0x04c0…04e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 09 39 0d 0a 20 20 20 20 35 2e 32 20 52 41 4d 20 4d 65 6d 6f 72 ┆........... 9 5.2 RAM Memor┆
0x04e0…0500 79 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆y Test .........................┆
0x0500…0520 2e 2e 2e 2e 2e 2e 2e 2e 2e 09 39 0d 0a 20 20 20 20 20 20 20 20 35 2e 32 2e 31 20 4d 65 6d 6f 72 ┆......... 9 5.2.1 Memor┆
0x0520…0540 79 20 54 65 73 74 20 50 61 74 74 65 72 6e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆y Test Pattern .................┆
0x0540…0560 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 20 31 30 0d 0a 20 20 20 20 20 20 20 20 35 2e 32 2e 32 20 4d 65 ┆....... 10 5.2.2 Me┆
0x0560…0580 6d 6f 72 79 20 54 65 73 74 20 46 6c 6f 77 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆mory Test Flow .................┆
0x0580…05a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 20 31 30 0d 0a 09 20 20 20 20 35 2e 32 2e 33 20 4c 6f ┆.......... 10 5.2.3 Lo┆
0x05a0…05c0 6f 70 20 4f 6e 20 45 72 72 6f 72 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆op On Error ....................┆
0x05c0…05e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 20 31 31 0d 0a 0d 0a 36 2e 20 20 54 45 53 54 20 31 20 ┆.......... 11 6. TEST 1 ┆
0x05e0…0600 3d 20 43 48 49 50 20 53 45 4c 45 43 54 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆= CHIP SELECT TEST .............┆
0x0600…0620 (3,) 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 20 31 32 0d 0a 0d 0a 37 2e 20 20 54 45 ┆............... 12 7. TE┆
0x0620…0640 53 54 20 32 20 3d 20 69 41 50 58 20 31 38 36 20 54 49 4d 45 52 20 54 45 53 54 20 2e 2e 2e 2e 2e ┆ST 2 = iAPX 186 TIMER TEST .....┆
0x0640…0660 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 20 31 33 0d 0a 0d 0a 38 ┆.................... 13 8┆
0x0660…0680 2e 20 20 54 45 53 54 20 33 20 3d 20 69 41 50 58 20 31 38 36 20 44 4d 41 20 54 45 53 54 20 2e 2e ┆. TEST 3 = iAPX 186 DMA TEST ..┆
0x0680…06a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 20 31 34 ┆......................... 14┆
0x06a0…06c0 0d 0a 0d 0a 39 2e 20 20 54 45 53 54 20 34 20 3d 20 50 41 52 45 4c 4c 45 4c 20 50 4f 52 54 20 54 ┆ 9. TEST 4 = PARELLEL PORT T┆
0x06c0…06e0 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 ┆EST .......................... ┆
0x06e0…06e9 20 20 20 31 35 0d 0a 0d 0a ┆ 15 ┆
0x06e9…06ec FormFeed {
0x06e9…06ec 0c 83 80 ┆ ┆
0x06e9…06ec }
0x06ec…0700 0a a1 b0 54 41 42 4c 45 20 4f 46 20 43 4f 4e 54 45 4e 54 53 ┆ TABLE OF CONTENTS┆
0x0700…0720 20 28 63 6f 6e 74 69 6e 75 65 64 29 05 50 41 47 45 0d 0a 0d 0a 31 30 2e 20 54 45 53 54 20 35 20 ┆ (continued) PAGE 10. TEST 5 ┆
0x0720…0740 3d 20 4c 49 4e 45 20 43 4f 4e 54 52 4f 4c 20 50 52 4f 43 45 53 53 4f 52 20 44 41 54 41 20 54 45 ┆= LINE CONTROL PROCESSOR DATA TE┆
0x0740…0760 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 20 31 36 0d 0a 0d 0a 31 31 2e 20 54 45 ┆ST ............ 16 11. TE┆
0x0760…0780 53 54 20 36 20 3d 20 4c 49 4e 45 20 43 4f 4e 54 52 4f 4c 20 50 52 4f 43 45 53 53 4f 52 20 4c 4f ┆ST 6 = LINE CONTROL PROCESSOR LO┆
0x0780…07a0 4f 50 42 41 43 4b 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 20 31 37 0d 0a 0d 0a 31 ┆OPBACK TEST ........ 17 1┆
0x07a0…07c0 32 2e 20 54 45 53 54 20 37 20 3d 20 56 2e 32 34 20 4c 49 4e 45 20 31 20 4c 4f 4f 50 42 41 43 4b ┆2. TEST 7 = V.24 LINE 1 LOOPBACK┆
0x07c0…07e0 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 31 39 ┆ TEST .................... 19┆
0x07e0…0800 0d 0a 0d 0a 31 33 2e 20 54 45 53 54 20 38 20 3d 20 56 2e 32 34 20 4c 49 4e 45 20 32 20 4c 4f 4f ┆ 13. TEST 8 = V.24 LINE 2 LOO┆
0x0800…0820 (4,) 50 42 41 43 4b 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 ┆PBACK TEST .................... ┆
0x0820…0840 20 20 20 32 31 0d 0a 0d 0a 31 34 2e 20 54 45 53 54 20 39 20 3d 20 56 2e 32 34 20 4c 49 4e 45 20 ┆ 21 14. TEST 9 = V.24 LINE ┆
0x0840…0860 33 20 4c 4f 4f 50 42 41 43 4b 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆3 LOOPBACK TEST ................┆
0x0860…0880 2e 2e 2e 2e 20 20 20 20 32 33 0d 0a 0d 0a 31 35 2e 20 4c 45 44 20 4f 55 54 50 55 54 20 2e 2e 2e ┆.... 23 15. LED OUTPUT ...┆
0x0880…08a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x08a0…08c0 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 32 35 0d 0a 0d 0a 0d 0a a1 b0 41 50 50 45 4e 44 49 58 0d ┆......... 25 APPENDIX ┆
0x08c0…08e0 0a 0d 0a 41 2e 20 52 45 46 45 52 45 4e 43 45 53 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ A. REFERENCES ...............┆
0x08e0…0900 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 ┆.............................. ┆
0x0900…0908 20 20 32 37 0d 0a 0d 0a ┆ 27 ┆
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0x090f…0920 0a 14 b3 09 09 09 09 0b a1 0d 0a a1 a1 b0 31 2e 20 ┆ 1. ┆
0x0920…0940 49 4e 54 52 4f 44 55 43 54 49 4f 4e 2e 0d 0a 0d 0a 54 68 65 20 49 54 43 20 36 30 32 20 69 73 20 ┆INTRODUCTION. The ITC 602 is ┆
0x0940…0960 61 6e 20 49 6e 74 65 6c 6c 69 67 65 6e 74 20 54 65 72 6d 69 6e 61 6c 20 43 6f 6e 74 72 6f 6c 6c ┆an Intelligent Terminal Controll┆
0x0960…0980 65 72 2c 20 77 68 69 63 68 20 69 73 20 61 6e 20 0a 69 6e 74 65 6c 6c 69 67 65 6e 74 20 4d 75 6c ┆er, which is an intelligent Mul┆
0x0980…09a0 74 69 62 75 73 20 53 42 43 20 75 73 65 64 20 74 6f 20 69 6e 74 65 72 66 61 63 65 20 74 65 72 6d ┆tibus SBC used to interface term┆
0x09a0…09c0 69 6e 61 6c 73 20 74 6f 20 74 68 65 20 52 43 20 33 39 20 0a 70 72 6f 64 75 63 74 2e 20 41 20 6d ┆inals to the RC 39 product. A m┆
0x09c0…09e0 61 78 69 6d 75 6d 20 6f 66 20 33 32 20 2b 20 34 20 74 65 72 6d 69 6e 61 6c 73 20 6d 61 79 20 62 ┆aximum of 32 + 4 terminals may b┆
0x09e0…0a00 65 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 61 6e 20 49 54 43 20 0a 36 30 32 2e 20 46 6f 75 72 ┆e connected to an ITC 602. Four┆
0x0a00…0a20 (5,) 20 6f 66 20 74 68 65 73 65 20 74 65 72 6d 69 6e 61 6c 73 20 6d 61 79 20 62 65 20 63 6f 6e 6e 65 ┆ of these terminals may be conne┆
0x0a20…0a40 63 74 65 64 20 76 69 61 20 73 74 61 6e 64 61 72 64 20 56 2e 32 34 20 0a 69 6e 74 65 72 66 61 63 ┆cted via standard V.24 interfac┆
0x0a40…0a60 65 2c 20 77 68 65 72 65 61 73 20 74 68 65 20 72 65 6d 61 69 6e 69 6e 67 20 33 32 20 74 65 72 6d ┆e, whereas the remaining 32 term┆
0x0a60…0a80 69 6e 61 6c 20 6d 75 73 74 20 62 65 20 63 6f 6e 6e 6e 65 63 74 65 64 20 0a 76 69 61 20 74 68 65 ┆inal must be connnected via the┆
0x0a80…0aa0 20 6e 65 77 20 63 69 72 63 75 69 74 20 49 49 20 73 65 72 69 61 6c 20 69 6e 74 65 72 66 61 63 65 ┆ new circuit II serial interface┆
0x0aa0…0ac0 2e 0d 0a 0d 0a 54 68 69 73 20 6d 61 6e 75 61 6c 20 61 73 73 75 6d 65 20 74 68 61 74 20 74 68 65 ┆. This manual assume that the┆
0x0ac0…0ae0 20 72 65 61 64 65 72 20 69 73 20 66 61 6d 69 6c 69 61 72 20 77 69 74 68 20 74 68 65 20 52 43 20 ┆ reader is familiar with the RC ┆
0x0ae0…0b00 33 39 20 0a 73 65 6c 66 74 65 73 74 20 63 6f 6e 63 65 70 74 20 61 73 20 64 65 73 63 72 69 62 65 ┆39 selftest concept as describe┆
0x0b00…0b20 64 20 69 6e 20 74 68 65 20 6d 61 6e 75 61 6c 20 63 61 6c 6c 65 64 20 22 54 68 65 20 52 43 20 33 ┆d in the manual called "The RC 3┆
0x0b20…0b40 39 20 0a 53 65 6c 66 74 65 73 74 20 43 6f 6e 63 65 70 74 22 2e 20 54 68 65 20 49 54 43 20 36 30 ┆9 Selftest Concept". The ITC 60┆
0x0b40…0b60 32 20 73 65 6c 66 74 65 73 74 20 69 6e 63 6c 75 64 65 73 20 31 30 20 64 69 66 66 65 72 65 6e 74 ┆2 selftest includes 10 different┆
0x0b60…0b80 20 0a 74 65 73 74 73 20 77 68 69 63 68 20 6d 61 79 20 62 65 20 72 75 6e 20 69 6e 20 73 65 76 65 ┆ tests which may be run in seve┆
0x0b80…0ba0 72 61 6c 20 6d 6f 64 65 73 2e 20 53 65 76 65 6e 20 6f 66 20 74 68 65 73 65 20 74 65 73 74 73 20 ┆ral modes. Seven of these tests ┆
0x0ba0…0bc0 61 72 65 20 0a b0 64 65 66 61 75 6c 74 f0 20 74 65 73 74 73 20 77 68 69 63 68 20 61 6c 6c 77 61 ┆are default tests which allwa┆
0x0bc0…0be0 79 73 20 65 78 65 63 75 74 65 20 61 66 74 65 72 20 61 20 70 6f 77 65 72 20 6f 6e 2e 20 54 68 65 ┆ys execute after a power on. The┆
0x0be0…0c00 20 6c 61 73 74 20 0a 19 80 81 80 74 72 65 65 20 74 65 73 74 73 20 61 72 65 20 b0 65 78 74 65 6e ┆ last tree tests are exten┆
0x0c00…0c20 (6,) 64 65 64 b0 f0 20 74 65 73 74 73 20 77 68 69 63 68 20 69 73 20 72 75 6e 20 6f 6e 6c 79 20 77 68 ┆ded tests which is run only wh┆
0x0c20…0c40 65 6e 20 72 65 71 75 65 73 74 65 64 20 0a 19 80 83 80 65 78 70 6c 69 63 69 74 20 62 79 20 61 6e ┆en requested explicit by an┆
0x0c40…0c60 20 6f 70 65 72 61 74 6f 72 2e 20 54 68 69 73 20 76 65 72 73 69 6f 6e 20 6f 66 20 74 68 65 20 49 ┆ operator. This version of the I┆
0x0c60…0c80 54 43 20 36 30 32 20 69 6e 63 6c 75 64 65 73 20 6e 6f 20 0a 19 80 83 80 b0 73 65 70 65 72 61 74 ┆TC 602 includes no seperat┆
0x0c80…0c92 65 6c 79 f0 20 72 75 6e 20 f0 74 65 73 74 73 2e 0d 0a ┆ely run tests. ┆
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0x0c95…0ca0 0a a1 a1 b0 32 2e 20 54 48 45 20 ┆ 2. THE ┆
0x0ca0…0cc0 44 55 41 4c 20 43 48 41 4e 4e 45 4c 20 43 4f 4d 4d 55 4e 49 43 41 54 49 4f 4e 20 41 50 50 52 4f ┆DUAL CHANNEL COMMUNICATION APPRO┆
0x0cc0…0ce0 41 43 48 2e 0d 0a 0d 0a 54 68 65 20 49 54 43 20 36 30 32 20 53 42 43 20 73 65 6c 66 74 65 73 74 ┆ACH. The ITC 602 SBC selftest┆
0x0ce0…0d00 20 73 75 70 70 6f 72 74 73 20 74 68 65 20 44 75 61 6c 20 43 68 61 6e 6e 65 6c 20 43 6f 6d 6d 75 ┆ supports the Dual Channel Commu┆
0x0d00…0d20 6e 69 63 61 74 69 6f 6e 20 0a 66 61 63 69 6c 69 74 79 20 61 73 20 64 65 73 63 72 69 62 65 64 20 ┆nication facility as described ┆
0x0d20…0d40 69 6e 20 74 68 65 20 22 52 43 20 33 39 20 53 65 6c 66 74 65 73 74 20 43 6f 6e 63 65 70 74 22 2e ┆in the "RC 39 Selftest Concept".┆
0x0d40…0d60 20 49 66 20 74 68 65 20 0a 73 74 72 61 70 20 53 54 37 2d 32 33 20 69 73 20 69 6e 73 65 72 74 65 ┆ If the strap ST7-23 is inserte┆
0x0d60…0d80 64 20 74 68 65 20 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 67 6f 65 73 20 76 69 61 20 74 68 65 ┆d the communication goes via the┆
0x0d80…0da0 20 6f 6e 2d 62 6f 61 72 64 20 0a 38 32 37 34 20 55 53 41 52 54 20 6c 69 6e 65 20 30 2c 20 6f 74 ┆ on-board 8274 USART line 0, ot┆
0x0da0…0dc0 68 65 72 77 69 73 65 20 69 66 20 74 68 65 20 73 74 72 61 70 20 69 73 20 6f 6d 69 74 74 65 64 20 ┆herwise if the strap is omitted ┆
0x0dc0…0de0 74 68 65 20 0a 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 67 6f 65 73 20 74 72 61 6e 73 70 61 72 ┆the communication goes transpar┆
0x0de0…0e00 65 6e 74 6c 79 20 74 68 72 6f 75 67 68 20 74 68 65 20 4d 75 6c 74 69 62 75 73 20 69 6e 74 65 72 ┆ently through the Multibus inter┆
0x0e00…0e20 (7,) 66 61 63 65 20 0a 74 6f 20 61 20 63 6f 6e 73 6f 6c 65 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 ┆face to a console connected to ┆
0x0e20…0e40 74 68 65 20 22 74 65 73 74 2d 6d 61 73 74 65 72 22 20 75 73 75 61 6c 6c 79 20 61 20 43 50 55 20 ┆the "test-master" usually a CPU ┆
0x0e40…0e5a 36 39 31 20 6f 72 20 0a 61 20 43 50 55 20 36 31 30 20 62 6f 61 72 64 2e 0d 0a ┆691 or a CPU 610 board. ┆
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0x0e60…0e80 33 2e 20 54 48 45 20 42 41 55 44 20 52 41 54 45 20 a1 44 45 54 45 52 4d 49 4e 41 54 49 4f 4e 20 ┆3. THE BAUD RATE DETERMINATION ┆
0x0e80…0ea0 4d 4f 44 45 2e 0d 0a 0d 0a 49 66 20 74 68 65 20 73 74 61 72 70 20 53 54 37 2d 32 33 20 69 73 20 ┆MODE. If the starp ST7-23 is ┆
0x0ea0…0ec0 69 6e 73 65 72 74 65 64 20 61 6e 64 20 61 20 74 65 72 6d 69 6e 61 6c 20 69 73 20 63 6f 6e 6e 65 ┆inserted and a terminal is conne┆
0x0ec0…0ee0 63 74 65 64 20 74 6f 20 74 68 65 20 0a 56 2e 32 34 20 6c 69 6e 65 20 30 20 69 6e 74 65 72 66 61 ┆cted to the V.24 line 0 interfa┆
0x0ee0…0f00 63 65 20 28 44 53 52 20 61 63 74 69 76 29 20 74 68 65 6e 20 74 68 65 20 73 65 6c 66 74 65 73 74 ┆ce (DSR activ) then the selftest┆
0x0f00…0f20 20 65 6e 74 65 72 73 20 74 68 65 20 0a 61 75 74 6f 6d 61 74 69 63 20 42 61 75 64 20 52 61 74 65 ┆ enters the automatic Baud Rate┆
0x0f20…0f40 20 44 65 74 65 72 6d 69 6e 61 74 69 6f 6e 20 6d 6f 64 65 2e 20 54 68 65 20 55 53 41 52 54 20 69 ┆ Determination mode. The USART i┆
0x0f40…0f60 73 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 0a 74 6f 20 39 36 30 30 20 42 61 75 64 20 61 6e 64 20 ┆s initialized to 9600 Baud and ┆
0x0f60…0f80 73 74 61 72 73 20 28 2a 2a 2a 2a 2a 29 20 61 72 65 20 77 72 69 74 74 65 6e 20 74 6f 20 6c 69 6e ┆stars (*****) are written to lin┆
0x0f80…0fa0 65 20 30 2e 20 54 68 65 73 65 20 73 74 61 72 73 20 0a 6d 61 79 20 62 65 20 73 65 65 6e 20 61 73 ┆e 0. These stars may be seen as┆
0x0fa0…0fc0 20 73 74 61 72 73 2c 20 6f 74 68 65 72 20 6d 69 78 65 64 20 63 68 61 72 61 63 74 65 72 73 20 6f ┆ stars, other mixed characters o┆
0x0fc0…0fe0 72 20 6e 6f 74 20 73 65 65 6e 20 61 74 20 61 6c 6c 20 0a 64 65 70 65 6e 64 69 6e 67 20 6f 6e 20 ┆r not seen at all depending on ┆
0x0fe0…1000 74 68 65 20 42 61 75 64 20 52 61 74 65 20 6f 66 20 74 68 65 20 61 74 74 61 63 68 65 64 20 63 6f ┆the Baud Rate of the attached co┆
0x1000…1020 (8,) 6e 73 6f 6c 65 2e 20 54 68 65 20 73 65 6c 66 74 65 73 74 20 0a 77 61 69 74 73 20 66 6f 72 20 74 ┆nsole. The selftest waits for t┆
0x1020…1040 68 65 20 6f 70 65 72 61 74 6f 72 20 74 6f 20 65 6e 74 65 72 20 6f 6e 65 20 6f 72 20 74 77 6f 20 ┆he operator to enter one or two ┆
0x1040…1060 75 70 70 65 72 20 63 61 73 65 20 55 2e 20 4f 6e 65 20 0a 75 70 70 65 72 20 63 61 73 65 20 55 20 ┆upper case U. One upper case U ┆
0x1060…1080 69 73 20 65 6e 6f 75 67 68 20 69 66 20 74 68 65 20 42 61 75 64 20 52 61 74 65 20 69 73 20 39 36 ┆is enough if the Baud Rate is 96┆
0x1080…10a0 30 30 2c 20 34 38 30 30 20 6f 72 20 32 34 30 30 20 0a 42 61 75 64 2e 20 42 61 75 64 20 52 61 74 ┆00, 4800 or 2400 Baud. Baud Rat┆
0x10a0…10c0 65 73 20 6f 66 20 31 32 30 30 2c 20 36 30 30 20 6f 72 20 33 30 30 20 72 65 71 75 69 72 65 73 20 ┆es of 1200, 600 or 300 requires ┆
0x10c0…10d2 74 77 6f 20 75 70 70 65 72 20 63 61 73 65 20 55 2e 0a ┆two upper case U. ┆
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0x10d5…10e0 0a a1 b0 34 2e 20 49 4e 54 45 52 ┆ 4. INTER┆
0x10e0…1100 52 55 50 54 20 48 41 4e 44 4c 49 4e 47 2e 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 49 54 43 20 36 ┆RUPT HANDLING. When the ITC 6┆
0x1100…1120 30 32 20 53 42 43 20 73 65 6c 66 74 65 73 74 20 68 61 73 20 66 69 6e 69 73 68 65 64 20 74 68 65 ┆02 SBC selftest has finished the┆
0x1120…1140 20 6d 65 6d 6f 72 79 20 74 65 73 74 2c 20 61 20 73 65 74 20 0a 6f 66 20 64 65 66 61 75 6c 74 20 ┆ memory test, a set of default ┆
0x1140…1160 69 6e 74 65 72 72 75 70 74 20 76 65 63 74 6f 72 73 20 61 72 65 20 6c 6f 61 64 65 64 20 69 6e 74 ┆interrupt vectors are loaded int┆
0x1160…1180 6f 20 74 68 65 20 76 65 63 74 6f 72 20 74 61 62 6c 65 2e 20 0a 54 68 65 73 65 20 76 65 63 74 6f ┆o the vector table. These vecto┆
0x1180…11a0 72 73 20 61 72 65 20 75 73 65 64 20 74 6f 20 68 61 6e 64 6c 65 20 62 6f 74 68 20 65 78 70 65 63 ┆rs are used to handle both expec┆
0x11a0…11c0 74 65 64 20 61 6e 64 20 75 6e 65 78 70 65 63 74 65 64 20 0a 69 6e 74 65 72 72 75 70 74 73 2e 0d ┆ted and unexpected interrupts. ┆
0x11c0…11e0 0a 0d 0a 0d 0a a1 b0 34 2e 31 20 56 61 6c 69 64 20 49 6e 74 65 72 72 75 70 74 73 2e 0d 0a 0d 0a ┆ 4.1 Valid Interrupts. ┆
0x11e0…1200 54 68 65 20 69 6e 74 65 72 72 75 70 74 73 20 74 68 61 74 20 61 72 65 20 63 6f 6e 73 69 64 65 72 ┆The interrupts that are consider┆
0x1200…1220 (9,) 65 64 20 76 61 6c 69 64 20 64 75 72 69 6e 67 20 74 68 65 20 73 65 6c 66 74 65 73 74 20 61 72 65 ┆ed valid during the selftest are┆
0x1220…1240 3a 0d 0a 0d 0a a1 52 65 71 75 65 73 74 20 6c 69 6e 65 20 20 49 6e 74 65 72 72 75 70 74 20 6e 61 ┆: Request line Interrupt na┆
0x1240…1260 6d 65 20 20 56 65 63 74 6f 72 20 74 79 70 65 20 20 20 20 20 20 20 20 20 20 20 20 20 45 76 65 6e ┆me Vector type Even┆
0x1260…1280 74 20 74 79 70 65 20 20 0d 0a 0d 0a 69 6e 74 65 72 6e 61 6c 20 20 20 20 20 20 53 74 65 70 20 69 ┆t type internal Step i┆
0x1280…12a0 6e 74 65 72 72 75 70 74 20 20 20 20 20 20 31 09 84 69 6e 73 74 72 75 63 74 69 6f 6e 20 65 78 65 ┆nterrupt 1 instruction exe┆
0x12a0…12c0 63 75 74 65 64 20 0a 19 ac 80 80 77 69 74 68 20 74 72 61 70 20 66 6c 61 67 20 73 65 74 0d 0a 0d ┆cuted with trap flag set ┆
0x12c0…12e0 0a 69 6e 74 65 72 6e 61 6c 09 42 72 65 61 6b 20 69 6e 74 65 72 72 75 70 74 09 33 09 84 73 6f 66 ┆ internal Break interrupt 3 sof┆
0x12e0…1300 74 77 61 72 65 20 69 6e 74 65 72 72 75 70 74 20 0a 19 ac 80 80 28 64 65 62 75 67 67 65 72 20 65 ┆tware interrupt (debugger e┆
0x1300…1320 6e 74 72 79 29 0d 0a 0d 0a 69 6e 74 65 72 6e 61 6c 09 54 69 6d 65 72 20 30 09 09 38 09 54 69 6d ┆ntry) internal Timer 0 8 Tim┆
0x1320…1340 65 72 20 30 20 69 6e 74 65 72 72 75 70 74 0d 0a 0d 0a 49 4e 54 20 30 09 55 53 41 52 54 20 72 65 ┆er 0 interrupt INT 0 USART re┆
0x1340…1360 63 65 69 76 65 20 69 6e 74 2e 09 33 30 09 4b 65 79 62 6f 61 72 64 20 69 6e 74 65 72 72 75 70 74 ┆ceive int. 30 Keyboard interrupt┆
0x1360…1366 0d 0a 0d 0a 0d 0a ┆ ┆
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0x1369…1380 0a a1 b0 34 2e 32 20 49 6e 73 74 72 75 63 74 69 6f 6e 20 45 78 63 65 ┆ 4.2 Instruction Exce┆
0x1380…13a0 70 74 69 6f 6e 73 2e 0d 0a 0d 0a 53 6f 6d 65 20 6f 66 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 ┆ptions. Some of the interrupt┆
0x13a0…13c0 73 20 77 69 6c 6c 20 67 65 6e 65 72 61 74 65 20 61 6e 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 ┆s will generate an error message┆
0x13c0…13e0 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a b0 f0 31 2e 20 b0 3e 3e 20 69 6e 73 74 72 75 63 74 ┆ like this: 1. >> instruct┆
0x13e0…1400 69 6f 6e 20 65 78 63 65 70 74 69 6f 6e 0d 0a 0d 0a a1 52 65 71 75 65 73 74 20 6c 69 6e 65 20 20 ┆ion exception Request line ┆
0x1400…1420 (10,) 49 6e 74 65 72 72 75 70 74 20 6e 61 6d 65 20 20 56 65 63 74 6f 72 20 74 79 70 65 20 20 20 20 20 ┆Interrupt name Vector type ┆
0x1420…1440 20 20 20 20 20 20 20 20 45 76 65 6e 74 20 74 79 70 65 20 20 0d 0a 0d 0a 69 6e 74 65 72 6e 61 6c ┆ Event type internal┆
0x1440…1460 09 44 69 76 69 64 65 20 65 72 72 6f 72 09 30 09 44 69 76 65 64 65 20 77 69 74 68 20 7a 65 72 6f ┆ Divide error 0 Divede with zero┆
0x1460…1480 0d 0a 0d 0a 69 6e 74 65 72 6e 61 6c 09 4f 77 65 72 66 6c 6f 77 09 09 34 09 49 4e 54 30 0d 0a 0d ┆ internal Owerflow 4 INT0 ┆
0x1480…14a0 0a 69 6e 74 65 72 6e 61 6c 09 41 72 72 61 79 20 42 6f 75 6e 64 73 09 35 09 42 4f 55 4e 44 0d 0a ┆ internal Array Bounds 5 BOUND ┆
0x14a0…14c0 0d 0a 69 6e 74 65 72 6e 61 6c 09 55 6e 75 73 65 64 20 4f 70 63 6f 64 65 09 36 09 55 6e 64 65 66 ┆ internal Unused Opcode 6 Undef┆
0x14c0…14e0 69 6e 65 64 20 6f 70 63 6f 64 65 0d 0a 0d 0a 69 6e 74 65 72 6e 61 6c 09 45 53 43 20 4f 70 63 6f ┆ined opcode internal ESC Opco┆
0x14e0…1500 64 65 09 37 09 45 53 43 20 6f 70 63 6f 64 65 73 0d 0a 0d 0a 0d 0a a1 b0 34 2e 33 20 49 6c 6c 65 ┆de 7 ESC opcodes 4.3 Ille┆
0x1500…1520 67 61 6c 20 53 6c 61 76 65 20 49 6e 74 65 72 72 75 70 74 73 2e 0d 0a 0d 0a 53 6f 6d 65 20 6f 66 ┆gal Slave Interrupts. Some of┆
0x1520…1540 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 73 20 77 69 6c 6c 20 67 65 6e 65 72 61 74 65 20 61 6e ┆ the interrupts will generate an┆
0x1540…1560 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a b0 f0 32 ┆ error message like this: 2┆
0x1560…1580 2e 20 b0 69 6c 6c 65 67 61 6c 20 69 6e 74 65 72 72 75 70 74 20 20 20 72 65 63 2e 3a 3c 72 72 72 ┆. illegal interrupt rec.:<rrr┆
0x1580…15a0 72 3e 0d 0a 0d 0a 54 68 65 20 73 65 63 6f 6e 64 61 72 79 20 65 72 72 6f 72 20 64 61 74 61 20 69 ┆r> The secondary error data i┆
0x15a0…15c0 73 20 74 68 65 20 63 6f 6e 74 65 6e 74 20 6f 66 20 74 68 65 20 69 41 50 58 20 31 38 36 20 69 6e ┆s the content of the iAPX 186 in┆
0x15c0…15e0 74 65 72 6e 61 6c 20 0a 69 6e 74 65 72 72 75 70 74 20 49 6e 20 53 65 72 76 69 63 65 20 52 65 67 ┆ternal interrupt In Service Reg┆
0x15e0…1600 69 73 74 65 72 20 28 49 53 52 29 20 64 75 72 69 6e 67 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 ┆ister (ISR) during the interrupt┆
0x1600…1620 (11,) 2e 20 54 68 69 73 20 0a 72 65 67 69 73 74 65 72 20 61 74 20 49 2f 4f 20 61 64 64 72 65 73 73 20 ┆. This register at I/O address ┆
0x1620…1640 46 46 32 43 20 48 65 78 2e 20 69 6e 64 69 63 61 74 65 73 20 77 68 69 63 68 20 69 6e 74 65 72 72 ┆FF2C Hex. indicates which interr┆
0x1640…1660 75 70 74 28 73 29 20 0a 61 72 65 20 61 63 74 69 76 65 2e 20 54 68 65 20 49 53 52 20 66 6f 72 6d ┆upt(s) are active. The ISR form┆
0x1660…1680 61 74 20 69 73 20 6c 69 6b 65 20 74 68 69 73 20 3a 0d 0a 0d 0a a1 31 35 20 20 31 34 20 20 31 33 ┆at is like this : 15 14 13┆
0x1680…16a0 20 20 31 32 20 20 31 31 20 20 31 30 20 20 20 39 20 20 20 38 20 20 20 37 20 20 20 36 20 20 20 35 ┆ 12 11 10 9 8 7 6 5┆
0x16a0…16c0 20 20 20 34 20 20 20 33 20 20 20 32 20 20 20 31 20 20 20 30 0d 0a 20 30 20 20 20 30 20 20 20 58 ┆ 4 3 2 1 0 0 0 X┆
0x16c0…16e0 20 20 20 58 20 20 20 58 20 20 20 30 20 20 20 30 20 20 20 30 20 20 49 33 20 20 49 32 20 20 49 31 ┆ X X 0 0 0 I3 I2 I1┆
0x16e0…1700 20 20 49 30 20 20 44 31 20 20 44 32 20 20 20 30 20 54 4d 52 0d 0a 0d 0a 41 20 6f 6e 65 20 69 6e ┆ I0 D1 D2 0 TMR A one in┆
0x1700…1720 64 69 63 61 74 65 73 20 74 68 61 74 20 61 6e 20 69 6e 74 65 72 72 75 70 74 20 69 73 20 61 63 74 ┆dicates that an interrupt is act┆
0x1720…1726 69 76 65 2e 0d 0a ┆ive. ┆
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0x1729…1740 0a a1 52 65 71 75 65 73 74 20 6c 69 6e 65 20 20 49 6e 74 65 72 72 75 ┆ Request line Interru┆
0x1740…1760 70 74 20 6e 61 6d 65 20 20 56 65 63 74 6f 72 20 74 79 70 65 20 20 20 20 20 20 20 20 20 20 20 20 ┆pt name Vector type ┆
0x1760…1780 20 45 76 65 6e 74 20 74 79 70 65 20 20 0d 0a 0d 0a 72 65 73 65 72 76 65 64 09 09 20 20 20 20 20 ┆ Event type reserved ┆
0x1780…17a0 20 20 20 20 20 39 0d 0a 0d 0a 69 6e 74 65 72 6e 61 6c 09 44 4d 41 20 30 09 20 20 20 20 20 20 20 ┆ 9 internal DMA 0 ┆
0x17a0…17c0 20 20 31 30 09 44 4d 41 20 63 68 2e 20 30 20 63 6f 6d 70 6c 65 74 65 0d 0a 0d 0a 69 6e 74 65 72 ┆ 10 DMA ch. 0 complete inter┆
0x17c0…17e0 6e 61 6c 09 44 4d 41 20 31 09 20 20 20 20 20 20 20 20 20 31 31 09 44 4d 41 20 63 68 2e 20 31 20 ┆nal DMA 1 11 DMA ch. 1 ┆
0x17e0…1800 63 6f 6d 70 6c 65 74 65 0d 0a 0d 0a 49 4e 54 20 30 09 49 4e 54 30 09 20 20 20 20 20 20 20 20 20 ┆complete INT 0 INT0 ┆
0x1800…1820 (12,) 31 32 09 53 65 72 69 61 6c 20 6c 69 6e 65 20 69 6e 74 2e 0d 0a 0d 0a 49 4e 54 20 31 09 4d 42 46 ┆12 Serial line int. INT 1 MBF┆
0x1820…1840 4c 41 47 49 4e 54 09 20 20 20 20 20 20 20 20 20 31 33 09 66 6c 61 67 20 62 79 74 65 20 69 6e 74 ┆LAGINT 13 flag byte int┆
0x1840…1860 2e 0d 0a 0d 0a 49 4e 54 20 32 09 6e 6f 74 20 75 73 65 64 09 20 20 20 20 20 20 20 20 20 31 34 09 ┆. INT 2 not used 14 ┆
0x1860…1880 28 61 63 6b 6e 6f 77 6c 65 64 67 65 20 74 6f 20 49 4e 54 30 29 0d 0a 0d 0a 49 4e 54 20 33 20 09 ┆(acknowledge to INT0) INT 3 ┆
0x1880…18a0 4c 43 50 49 4e 54 09 20 20 20 20 20 20 20 20 20 31 35 09 63 69 72 63 75 69 74 20 49 49 20 69 6e ┆LCPINT 15 circuit II in┆
0x18a0…18c0 74 65 72 72 75 70 74 0d 0a 0d 0a 69 6e 74 65 72 6e 61 6c 09 6e 6f 74 20 75 73 65 64 09 20 20 20 ┆terrupt internal not used ┆
0x18c0…18e0 20 20 20 20 20 20 31 36 0d 0a 0d 0a 69 6e 74 65 72 6e 61 6c 09 6e 6f 74 20 75 73 65 64 09 20 20 ┆ 16 internal not used ┆
0x18e0…1900 20 20 20 20 20 20 20 31 37 0d 0a 0d 0a 69 6e 74 65 72 6e 61 6c 09 74 69 6d 65 72 20 32 09 20 20 ┆ 17 internal timer 2 ┆
0x1900…1920 20 20 20 20 20 20 20 31 39 09 74 69 6d 65 72 20 72 75 6e 20 6f 75 74 0d 0a 0d 0a 0d 0a a1 b0 34 ┆ 19 timer run out 4┆
0x1920…1940 2e 34 20 49 6c 6c 65 67 61 6c 20 4d 61 73 74 65 72 20 49 6e 74 65 72 72 75 70 74 73 0d 0a 0d 0a ┆.4 Illegal Master Interrupts ┆
0x1940…1960 53 6f 6d 65 20 6f 66 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 73 20 77 69 6c 6c 20 67 65 6e 65 ┆Some of the interrupts will gene┆
0x1960…1980 72 61 74 65 20 61 6e 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 6c 69 6b 65 20 74 68 69 73 3a ┆rate an error message like this:┆
0x1980…19a0 0d 0a 0d 0a b0 f0 33 2e 20 b0 69 6c 6c 65 67 61 6c 20 6c 69 6e 65 20 30 2d 31 20 69 6e 74 65 72 ┆ 3. illegal line 0-1 inter┆
0x19a0…19c0 72 75 70 74 20 20 20 6c 65 76 2e 3a 3c 30 30 6c 6c 3e 20 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d ┆rupt lev.:<00ll> rec.:<rrrr> ┆
0x19c0…19e0 0a 0d 0a 20 20 20 6f 72 0d 0a b0 f0 0d 0a 34 2e 20 b0 69 6c 6c 65 67 61 6c 20 6c 69 6e 65 20 32 ┆ or 4. illegal line 2┆
0x19e0…1a00 2d 33 20 69 6e 74 65 72 72 75 70 74 20 20 20 6c 65 76 2e 3a 3c 30 30 6c 6c 3e 20 20 72 65 63 2e ┆-3 interrupt lev.:<00ll> rec.┆
0x1a00…1a20 (13,) 3a 3c 72 72 72 72 3e 0d 0a 0d 0a 0d 0a 8c 83 98 0a 54 68 65 20 6c 65 76 65 6c 20 69 6e 66 6f 72 ┆:<rrrr> The level infor┆
0x1a20…1a40 6d 61 74 69 6f 6e 20 69 73 20 61 20 72 65 61 64 20 6f 66 20 74 68 65 20 38 32 37 34 20 69 6e 74 ┆mation is a read of the 8274 int┆
0x1a40…1a60 65 72 6e 61 6c 20 72 65 67 69 73 74 65 72 20 52 52 32 20 0a 77 68 65 72 65 20 74 68 65 20 69 6e ┆ernal register RR2 where the in┆
0x1a60…1a80 74 65 72 72 75 70 74 20 6c 65 76 65 6c 20 69 73 20 73 74 6f 72 65 64 2e 20 54 68 65 20 72 65 63 ┆terrupt level is stored. The rec┆
0x1a80…1aa0 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 20 69 73 20 61 20 0a 72 65 61 64 20 6f 66 20 74 68 65 20 38 ┆ information is a read of the 8┆
0x1aa0…1ac0 32 37 34 20 52 52 30 20 61 6e 64 20 52 52 31 20 77 68 65 72 65 20 74 68 65 20 63 61 75 73 65 20 ┆274 RR0 and RR1 where the cause ┆
0x1ac0…1ae0 6f 66 20 69 6e 74 65 72 72 75 70 74 20 6d 61 79 20 62 65 20 0a 66 75 72 74 68 65 72 20 73 70 65 ┆of interrupt may be further spe┆
0x1ae0…1b00 63 69 66 69 65 64 2e 20 52 52 31 20 69 73 20 73 74 6f 72 65 64 20 69 6e 20 74 68 65 20 6d 6f 73 ┆cified. RR1 is stored in the mos┆
0x1b00…1b20 74 20 73 69 67 6e 69 66 69 63 61 6e 74 20 62 79 74 65 20 6f 66 20 0a 74 68 65 20 72 65 63 65 69 ┆t significant byte of the recei┆
0x1b20…1b40 76 65 64 20 76 61 6c 75 65 2e 20 43 6f 6e 73 75 6c 74 20 49 4e 54 45 4c 20 64 61 74 61 20 73 68 ┆ved value. Consult INTEL data sh┆
0x1b40…1b60 65 74 73 20 66 6f 72 20 66 75 72 74 68 65 72 20 0a 69 6e 66 6f 72 6d 61 74 69 6f 6e 20 61 62 6f ┆ets for further information abo┆
0x1b60…1b80 75 74 20 74 68 65 20 53 65 72 69 61 6c 20 4c 69 6e 65 20 43 6f 6e 74 72 6f 6c 6c 65 72 20 38 32 ┆ut the Serial Line Controller 82┆
0x1b80…1ba0 37 34 2e 0d 0a 0d 0a a1 52 65 71 75 65 73 74 20 6c 69 6e 65 20 20 49 6e 74 65 72 72 75 70 74 20 ┆74. Request line Interrupt ┆
0x1ba0…1bc0 6e 61 6d 65 20 20 56 65 63 74 6f 72 20 74 79 70 65 20 20 20 20 20 20 20 20 20 20 20 20 20 45 76 ┆name Vector type Ev┆
0x1bc0…1be0 65 6e 74 20 74 79 70 65 20 20 0d 0a 0d 0a 49 4e 54 20 30 09 54 58 20 65 6d 70 74 79 09 09 32 34 ┆ent type INT 0 TX empty 24┆
0x1be0…1c00 09 4c 69 6e 65 20 31 20 54 58 20 65 6d 70 74 79 0d 0a 0d 0a 49 4e 54 20 30 09 45 78 74 2e 20 53 ┆ Line 1 TX empty INT 0 Ext. S┆
0x1c00…1c20 (14,) 74 61 74 75 73 20 63 68 2e 09 32 35 09 4c 69 6e 65 20 31 20 53 74 61 74 75 73 20 63 68 61 6e 67 ┆tatus ch. 25 Line 1 Status chang┆
0x1c20…1c40 65 0d 0a 0d 0a 49 4e 54 20 30 09 52 58 20 61 76 61 69 6c 61 62 6c 65 09 32 36 09 4c 69 6e 65 20 ┆e INT 0 RX available 26 Line ┆
0x1c40…1c60 31 20 52 58 20 63 68 61 72 61 63 74 65 72 0d 0a 0d 0a 49 4e 54 20 30 09 46 72 61 6d 65 2f 50 61 ┆1 RX character INT 0 Frame/Pa┆
0x1c60…1c80 72 69 74 79 09 32 37 09 4c 69 6e 65 20 31 20 46 72 61 6d 65 2f 50 61 72 69 74 79 0d 0a 0d 0a 49 ┆rity 27 Line 1 Frame/Parity I┆
0x1c80…1ca0 4e 54 20 30 09 54 58 20 65 6d 70 74 79 09 09 32 38 09 4c 69 6e 65 20 30 20 54 58 20 65 6d 70 74 ┆NT 0 TX empty 28 Line 0 TX empt┆
0x1ca0…1cc0 79 0d 0a 0d 0a 49 4e 54 20 30 09 45 78 74 2e 20 53 74 61 74 75 73 20 63 68 2e 09 32 39 09 4c 69 ┆y INT 0 Ext. Status ch. 29 Li┆
0x1cc0…1ce0 6e 65 20 30 20 53 74 61 74 75 73 20 63 68 61 6e 67 65 0d 0a 0d 0a 49 4e 54 20 30 09 46 72 61 6d ┆ne 0 Status change INT 0 Fram┆
0x1ce0…1d00 65 2f 50 61 72 69 74 79 09 33 31 09 4c 69 6e 65 20 30 20 46 72 61 6d 65 2f 50 61 72 69 74 79 0d ┆e/Parity 31 Line 0 Frame/Parity ┆
0x1d00…1d20 0a 0d 0a 49 4e 54 20 30 09 54 58 20 65 6d 70 74 79 09 09 33 32 20 20 20 20 20 20 20 20 4c 69 6e ┆ INT 0 TX empty 32 Lin┆
0x1d20…1d40 65 20 33 20 54 58 20 65 6d 70 74 79 0d 0a 0d 0a 49 4e 54 20 30 09 45 78 74 2e 20 53 74 61 74 75 ┆e 3 TX empty INT 0 Ext. Statu┆
0x1d40…1d60 73 20 63 68 2e 09 33 33 09 4c 69 6e 65 20 33 20 53 74 61 74 75 73 20 63 68 61 6e 67 65 0d 0a 0d ┆s ch. 33 Line 3 Status change ┆
0x1d60…1d80 0a 49 4e 54 20 30 09 52 58 20 61 76 61 69 6c 61 62 6c 65 09 33 34 09 4c 69 6e 65 20 33 20 52 58 ┆ INT 0 RX available 34 Line 3 RX┆
0x1d80…1da0 20 63 68 61 72 61 63 74 65 72 0d 0a 0d 0a 49 4e 54 20 30 09 46 72 61 6d 65 2f 50 61 72 69 74 79 ┆ character INT 0 Frame/Parity┆
0x1da0…1dc0 09 33 35 09 4c 69 6e 65 20 33 20 46 72 61 6d 65 2f 50 61 72 69 74 79 0d 0a 0d 0a 49 4e 54 20 30 ┆ 35 Line 3 Frame/Parity INT 0┆
0x1dc0…1de0 09 54 58 20 65 6d 70 74 79 09 09 33 36 09 4c 69 6e 65 20 32 20 54 58 20 65 6d 70 74 79 0d 0a 0d ┆ TX empty 36 Line 2 TX empty ┆
0x1de0…1de1 0a ┆ ┆
0x1de1…1de4 FormFeed {
0x1de1…1de4 0c 83 8c ┆ ┆
0x1de1…1de4 }
0x1de4…1e00 0a a1 52 65 71 75 65 73 74 20 6c 69 6e 65 20 20 49 6e 74 65 72 72 75 70 74 20 6e 61 ┆ Request line Interrupt na┆
0x1e00…1e20 (15,) 6d 65 20 20 56 65 63 74 6f 72 20 74 79 70 65 20 20 20 20 20 20 20 20 20 20 20 20 20 45 76 65 6e ┆me Vector type Even┆
0x1e20…1e40 74 20 74 79 70 65 20 20 0d 0a 0d 0a 49 4e 54 09 30 09 45 78 74 2e 20 53 74 61 74 75 73 20 63 68 ┆t type INT 0 Ext. Status ch┆
0x1e40…1e60 2e 09 33 37 09 4c 69 6e 65 20 32 20 53 74 61 74 75 73 20 63 68 61 6e 67 65 0d 0a 0d 0a 49 4e 54 ┆. 37 Line 2 Status change INT┆
0x1e60…1e80 20 30 09 52 58 20 61 76 61 69 6c 61 62 6c 65 09 33 38 09 4c 69 6e 65 20 32 20 52 58 20 63 68 61 ┆ 0 RX available 38 Line 2 RX cha┆
0x1e80…1ea0 72 61 63 74 65 72 0d 0a 0d 0a 49 4e 54 20 30 09 46 72 61 6d 65 2f 50 61 72 69 74 79 09 33 39 20 ┆racter INT 0 Frame/Parity 39 ┆
0x1ea0…1ec0 09 4c 69 6e 65 20 33 20 46 72 61 6d 65 2f 50 61 72 69 74 79 0d 0a 0d 0a 0d 0a a1 b0 34 2e 35 20 ┆ Line 3 Frame/Parity 4.5 ┆
0x1ec0…1ee0 4e 6f 6e 20 4d 61 73 6b 61 62 6c 65 20 49 6e 74 65 72 72 75 70 74 2e 0d 0a 0d 0a 49 66 20 61 20 ┆Non Maskable Interrupt. If a ┆
0x1ee0…1f00 6e 6f 6e 20 6d 61 73 6b 61 62 6c 65 20 69 6e 74 65 72 72 75 70 74 20 28 4e 4d 49 29 20 69 6e 74 ┆non maskable interrupt (NMI) int┆
0x1f00…1f20 65 72 72 75 70 74 20 6f 63 63 75 72 20 64 75 72 69 6e 67 20 74 68 65 20 0a 73 65 6c 66 74 65 73 ┆errupt occur during the selftes┆
0x1f20…1f40 74 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 6d 65 73 73 61 67 65 20 69 73 20 77 72 69 74 74 ┆t the following message is writt┆
0x1f40…1f60 65 6e 20 74 6f 20 74 68 65 20 63 6f 6e 73 6f 6c 65 20 61 6e 64 20 74 68 65 20 0a 70 72 6f 63 65 ┆en to the console and the proce┆
0x1f60…1f80 73 73 6f 72 20 69 73 20 68 61 6c 74 65 64 2e 0d 0a 0d 0a b0 f0 35 2e 20 b0 4e 4d 49 20 69 6e 74 ┆ssor is halted. 5. NMI int┆
0x1f80…1fa0 65 72 72 75 70 74 20 2d 20 74 65 73 74 20 48 41 4c 54 45 44 20 21 0d 0a 0d 0a 54 68 65 72 65 20 ┆errupt - test HALTED ! There ┆
0x1fa0…1fc0 69 73 20 6e 6f 20 77 61 79 20 74 6f 20 67 65 74 20 74 68 65 20 73 65 6c 66 74 65 73 74 20 6f 75 ┆is no way to get the selftest ou┆
0x1fc0…1fe0 74 20 6f 66 20 74 68 69 73 20 68 61 6c 74 20 73 69 74 75 61 74 69 6f 6e 20 0a 65 78 63 65 70 74 ┆t of this halt situation except┆
0x1fe0…2000 20 72 65 73 65 74 2e 20 4e 6f 74 65 20 74 68 61 74 20 74 68 65 20 4e 4d 49 20 70 69 6e 20 6f 6e ┆ reset. Note that the NMI pin on┆
0x2000…2020 (16,) 20 74 68 65 20 70 72 6f 63 65 73 73 6f 72 20 69 73 20 67 72 6f 75 6e 64 65 64 2c 20 0a 73 6f 20 ┆ the processor is grounded, so ┆
0x2020…2040 74 68 61 74 20 69 74 20 69 73 20 75 6e 6c 69 6b 65 6c 79 20 74 68 61 74 20 4e 4d 49 20 69 6e 74 ┆that it is unlikely that NMI int┆
0x2040…2050 65 72 72 75 70 74 73 20 6f 63 63 75 72 2e 0d 0a ┆errupts occur. ┆
0x2050…2053 FormFeed {
0x2050…2053 0c 81 f0 ┆ ┆
0x2050…2053 }
0x2053…2060 0a a1 b0 35 2e 20 b0 54 65 73 74 20 30 ┆ 5. Test 0┆
0x2060…2080 20 3d 20 f0 4d 45 4d 4f 52 59 20 54 45 53 54 2e 0d 0a 0d 0a 54 68 65 20 6d 65 6d 6f 72 79 20 74 ┆ = MEMORY TEST. The memory t┆
0x2080…20a0 65 73 74 20 6f 66 20 74 68 65 20 49 54 43 20 36 30 32 20 53 42 43 20 73 65 6c 66 74 65 73 74 20 ┆est of the ITC 602 SBC selftest ┆
0x20a0…20c0 63 6f 6e 73 69 73 74 73 20 6f 66 20 74 77 6f 20 0a 70 61 72 74 73 2c 20 61 20 50 52 4f 4d 20 63 ┆consists of two parts, a PROM c┆
0x20c0…20e0 68 65 63 6b 73 75 6d 20 74 65 73 74 20 61 6e 64 20 61 20 52 41 4d 20 6d 65 6d 6f 72 79 20 74 65 ┆hecksum test and a RAM memory te┆
0x20e0…2100 73 74 2e 20 54 68 65 20 50 52 4f 4d 20 0a 63 68 65 63 6b 73 75 6d 20 74 65 73 74 20 69 73 20 6f ┆st. The PROM checksum test is o┆
0x2100…2120 6e 6c 79 20 72 75 6e 20 6f 6e 63 65 20 61 66 74 65 72 20 70 6f 77 65 72 20 75 70 20 6f 72 20 65 ┆nly run once after power up or e┆
0x2120…2140 78 74 65 72 6e 61 6c 20 72 65 73 65 74 2c 20 0a 77 68 65 72 65 61 73 20 74 68 65 20 52 41 4d 20 ┆xternal reset, whereas the RAM ┆
0x2140…2160 6d 65 6d 6f 72 79 20 74 65 73 74 20 6d 61 79 20 62 65 20 72 75 6e 20 73 65 76 65 72 61 6c 20 74 ┆memory test may be run several t┆
0x2160…2180 69 6d 65 73 2c 20 69 66 20 0a 72 65 71 75 65 73 74 65 64 20 62 79 20 74 68 65 20 6f 70 65 72 61 ┆imes, if requested by the opera┆
0x2180…21a0 74 6f 72 2e 0d 0a 0d 0a 0d 0a b0 a1 35 2e 31 20 50 52 4f 4d 20 43 68 65 63 6b 73 75 6d 20 54 65 ┆tor. 5.1 PROM Checksum Te┆
0x21a0…21c0 73 74 2e 0d 0a 0d 0a 54 68 65 20 63 6f 6e 74 65 6e 74 73 20 6f 66 20 62 6f 74 68 20 74 68 65 20 ┆st. The contents of both the ┆
0x21c0…21e0 6f 64 64 20 61 6e 64 20 74 68 65 20 65 76 65 6e 20 50 52 4f 4d 20 61 72 65 20 73 75 6d 6d 61 72 ┆odd and the even PROM are summar┆
0x21e0…2200 69 7a 65 64 20 0a 62 79 74 65 77 69 73 65 20 61 6e 64 20 74 68 65 20 72 65 73 75 6c 74 20 6d 75 ┆ized bytewise and the result mu┆
0x2200…2220 (17,) 73 74 20 62 65 20 61 20 7a 65 72 6f 2e 20 46 6f 72 20 74 68 61 74 20 72 65 61 73 6f 6e 20 74 68 ┆st be a zero. For that reason th┆
0x2220…2240 65 20 0a 50 52 4f 4d 27 73 20 63 6f 6e 74 61 69 6e 20 61 20 63 6f 6d 70 65 6e 73 61 74 69 6f 6e ┆e PROM's contain a compensation┆
0x2240…2260 20 62 79 74 65 20 77 68 69 63 68 20 69 73 20 75 73 65 64 20 74 6f 20 62 72 69 6e 67 20 74 68 65 ┆ byte which is used to bring the┆
0x2260…2280 20 73 75 6d 20 0a 74 6f 20 7a 65 72 6f 2e 0d 0a a1 0d 0a b0 f0 31 2e 20 b0 63 68 65 63 6b 73 75 ┆ sum to zero. 1. checksu┆
0x2280…22a0 6d 20 74 65 73 74 3a 20 73 75 6d 20 65 72 72 6f 72 20 20 65 78 70 2e 3a 3c 30 30 30 30 3e 20 20 ┆m test: sum error exp.:<0000> ┆
0x22a0…22c0 72 65 63 2e 3a 3c 78 79 7a 77 3e 0d 0a 0d 0a 43 68 65 63 6b 73 75 6d 20 65 72 72 6f 72 20 75 73 ┆rec.:<xyzw> Checksum error us┆
0x22c0…22e0 75 61 6c 6c 79 20 6d 65 61 6e 73 20 74 68 61 74 20 74 68 65 20 63 6f 6e 74 65 6e 74 20 6f 66 20 ┆ually means that the content of ┆
0x22e0…2300 74 68 65 20 50 52 4f 4d 20 68 61 73 20 0a 62 65 65 6e 20 64 61 6d 61 67 65 64 20 61 6e 64 20 74 ┆the PROM has been damaged and t┆
0x2300…2320 68 61 74 20 74 68 65 20 50 52 4f 4d 20 6d 75 73 74 20 62 65 20 63 68 61 6e 67 65 64 2e 0d 0a 0d ┆hat the PROM must be changed. ┆
0x2320…2340 0a 0d 0a b0 a1 35 2e 32 20 52 41 4d 20 4d 65 6d 6f 72 79 20 54 65 73 74 2e 0d 0a 0d 0a 54 68 65 ┆ 5.2 RAM Memory Test. The┆
0x2340…2360 20 52 41 4d 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 6f 66 20 74 68 65 20 49 54 43 20 36 30 32 20 ┆ RAM memory test of the ITC 602 ┆
0x2360…2380 53 42 43 20 73 65 6c 66 74 65 73 74 20 76 65 72 69 66 69 65 73 20 74 68 65 20 6f 6e 2d 0a 62 6f ┆SBC selftest verifies the on- bo┆
0x2380…23a0 61 72 64 20 36 34 20 6b 62 79 74 65 73 20 6d 65 6d 6f 72 79 2e 0d 0a 0d 0a 54 68 65 20 6d 65 6d ┆ard 64 kbytes memory. The mem┆
0x23a0…23c0 6f 72 79 20 74 65 73 74 20 69 73 20 61 20 72 65 67 69 73 74 65 72 20 62 61 73 65 64 20 74 65 73 ┆ory test is a register based tes┆
0x23c0…23e0 74 20 61 6e 64 20 75 73 65 73 20 6e 6f 20 6d 65 6d 6f 72 79 20 73 70 61 63 65 20 0a 61 74 20 61 ┆t and uses no memory space at a┆
0x23e0…2400 6c 6c 2c 20 6e 65 69 74 68 65 72 20 66 6f 72 20 76 61 72 69 61 62 6c 65 73 20 6e 6f 72 20 73 74 ┆ll, neither for variables nor st┆
0x2400…2420 (18,) 61 63 6b 2e 20 54 68 65 20 74 65 73 74 20 76 65 72 69 66 69 65 73 20 65 76 65 72 79 20 0a 73 69 ┆ack. The test verifies every si┆
0x2420…2440 6e 67 6c 65 20 62 79 74 65 20 6f 66 20 74 68 65 20 6f 6e 2d 62 6f 61 72 64 20 6d 65 6d 6f 72 79 ┆ngle byte of the on-board memory┆
0x2440…2460 2e 0d 0a 0d 0a 54 68 69 73 20 66 61 63 74 20 6c 65 74 73 20 6f 6e 6c 79 20 6f 6e 65 20 72 65 67 ┆. This fact lets only one reg┆
0x2460…2480 69 73 74 65 72 20 66 6f 72 20 74 65 73 74 20 76 61 72 69 61 62 6c 65 73 20 73 75 72 76 69 76 65 ┆ister for test variables survive┆
0x2480…24a0 20 74 68 65 20 0a 6d 65 6d 6f 72 79 20 74 65 73 74 2e 20 54 68 61 74 20 76 61 72 69 61 62 6c 65 ┆ the memory test. That variable┆
0x24a0…24c0 20 63 6f 6e 74 61 69 6e 73 20 61 6c 6c 20 74 68 65 20 74 65 73 74 20 73 77 69 74 63 68 65 73 20 ┆ contains all the test switches ┆
0x24c0…24dd 61 6e 64 20 74 68 65 20 0a 74 65 73 74 20 6e 75 6d 62 65 72 2e 20 20 0d 0a 0d 0a 0d 0a ┆and the test number. ┆
0x24dd…24e0 FormFeed {
0x24dd…24e0 0c 83 b0 ┆ ┆
0x24dd…24e0 }
0x24e0…2500 0a a1 b0 35 2e 32 2e 31 20 4d 65 6d 6f 72 79 20 54 65 73 74 20 50 61 74 74 65 72 6e 2e 0d 0a 0d ┆ 5.2.1 Memory Test Pattern. ┆
0x2500…2520 0a 54 68 65 20 6f 6e 2d 62 6f 61 72 64 20 44 75 61 6c 20 50 6f 72 74 65 64 20 52 41 4d 20 6d 65 ┆ The on-board Dual Ported RAM me┆
0x2520…2540 6d 6f 72 79 20 63 6f 6e 73 69 73 74 73 20 6f 66 20 6d 65 6d 6f 72 79 20 63 68 69 70 73 20 6f 66 ┆mory consists of memory chips of┆
0x2540…2560 20 34 20 0a 62 69 74 20 2a 20 31 36 20 4b 2e 20 54 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 ┆ 4 bit * 16 K. The memory test ┆
0x2560…2580 65 78 65 63 75 74 65 73 20 34 20 70 61 73 73 65 73 20 74 72 6f 75 67 68 20 74 68 65 20 65 6e 74 ┆executes 4 passes trough the ent┆
0x2580…25a0 69 72 65 20 0a 6d 65 6d 6f 72 79 2c 20 74 77 6f 20 74 69 6d 65 73 20 77 72 69 74 69 6e 67 20 61 ┆ire memory, two times writing a┆
0x25a0…25c0 6e 64 20 74 77 6f 20 74 69 6d 65 73 20 72 65 61 64 69 6e 67 2e 0d 0a 0d 0a 54 68 65 20 74 65 73 ┆nd two times reading. The tes┆
0x25c0…25e0 74 20 70 61 74 74 65 72 6e 20 69 73 20 74 68 65 20 63 6f 6e 76 65 6e 69 65 6e 74 20 6d 6f 64 75 ┆t pattern is the convenient modu┆
0x25e0…2600 6c 75 73 20 33 20 70 61 74 74 65 72 6e 20 63 6f 6e 73 69 73 74 69 6e 67 20 0a 6f 66 20 74 68 72 ┆lus 3 pattern consisting of thr┆
0x2600…2620 (19,) 65 65 20 74 69 6d 65 73 20 30 30 30 30 20 66 6f 6c 6c 6f 77 65 64 20 62 79 20 74 68 72 65 65 20 ┆ee times 0000 followed by three ┆
0x2620…2640 74 69 6d 65 73 20 46 46 46 46 20 28 20 68 65 78 61 64 65 63 69 6d 61 6c 20 29 2e 0d 0a 0d 0a 0d ┆times FFFF ( hexadecimal ). ┆
0x2640…2660 0a a1 b0 35 2e 32 2e 32 20 4d 65 6d 6f 72 79 20 54 65 73 74 20 46 6c 6f 77 2e 0d 0a 0d 0a 54 68 ┆ 5.2.2 Memory Test Flow. Th┆
0x2660…2680 65 20 74 65 73 74 20 73 74 61 72 74 73 20 69 6e 20 74 68 65 20 68 69 67 68 65 73 74 20 52 41 4d ┆e test starts in the highest RAM┆
0x2680…26a0 20 61 64 64 72 65 73 73 65 73 20 61 6e 64 20 69 6e 73 65 72 74 73 20 74 68 65 20 70 61 74 74 65 ┆ addresses and inserts the patte┆
0x26a0…26c0 72 6e 20 0a 74 6f 77 61 72 64 73 20 6c 6f 77 65 72 20 61 64 64 72 65 73 73 65 73 2e 0d 0a 0d 0a ┆rn towards lower addresses. ┆
0x26c0…26e0 57 68 65 6e 20 61 6c 6c 20 6d 65 6d 6f 72 79 20 77 6f 72 64 73 20 68 61 76 65 20 62 65 65 6e 20 ┆When all memory words have been ┆
0x26e0…2700 77 72 69 74 74 65 6e 20 61 6e 64 20 76 65 72 69 66 69 65 64 2c 20 74 68 65 79 20 61 72 65 20 0a ┆written and verified, they are ┆
0x2700…2720 74 65 73 74 65 64 20 61 67 61 69 6e 20 77 69 74 68 20 74 68 65 20 69 6e 76 65 72 73 65 64 20 70 ┆tested again with the inversed p┆
0x2720…2740 61 74 74 65 72 6e 2c 20 74 68 69 73 20 6d 65 61 6e 73 2c 20 74 68 61 74 20 61 6c 6c 20 62 69 74 ┆attern, this means, that all bit┆
0x2740…2760 73 20 0a 61 72 65 20 74 65 73 74 65 64 20 66 6f 72 20 22 7a 65 72 6f 22 20 61 6e 64 20 22 6f 6e ┆s are tested for "zero" and "on┆
0x2760…2780 65 22 20 69 6e 73 65 72 74 69 6f 6e 2e 20 49 66 20 61 6e 20 65 72 72 6f 72 20 6f 63 63 75 72 20 ┆e" insertion. If an error occur ┆
0x2780…27a0 74 68 65 6e 20 0a 61 6e 20 61 74 74 65 6d 70 74 20 74 6f 20 73 65 6e 64 20 74 68 65 20 66 6f 6c ┆then an attempt to send the fol┆
0x27a0…27c0 6c 6f 77 69 6e 67 20 6d 65 73 73 61 67 65 2c 20 74 6f 20 74 68 65 20 22 74 65 73 74 2d 6f 75 74 ┆lowing message, to the "test-out┆
0x27c0…27e0 70 75 74 22 2c 20 0a 69 73 20 6d 61 64 65 20 3a 0d 0a 0d 0a a1 b0 f0 32 2e 20 b0 52 41 4d 20 74 ┆put", is made : 2. RAM t┆
0x27e0…2800 65 73 74 3a 20 52 41 4d 20 65 72 72 6f 72 20 20 73 65 67 6d 2e 3a 3c 73 73 73 73 3e 20 20 61 64 ┆est: RAM error segm.:<ssss> ad┆
0x2800…2820 (20,) 64 72 2e 3a 3c 61 61 61 61 3e 20 20 65 78 70 2e 3a 3c 65 65 65 65 3e 0d 0a 09 20 09 09 09 20 20 ┆dr.:<aaaa> exp.:<eeee> ┆
0x2820…2840 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 b0 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 0d 0a ┆ rec.:<rrrr> ┆
0x2840…2860 54 68 65 20 73 65 63 6f 6e 64 61 72 79 20 74 65 78 74 20 69 73 20 69 6e 74 65 72 70 72 65 74 65 ┆The secondary text is interprete┆
0x2860…2880 64 20 6c 69 6b 65 20 74 68 69 73 20 3a 0d 0a 0d 0a 3c 73 73 73 73 3e 20 69 73 20 74 68 65 20 73 ┆d like this : <ssss> is the s┆
0x2880…28a0 65 67 6d 65 6e 74 20 61 64 64 72 65 73 73 0d 0a 3c 61 61 61 61 3e 20 69 73 20 74 68 65 20 61 64 ┆egment address <aaaa> is the ad┆
0x28a0…28c0 64 72 65 73 73 20 6f 66 66 73 65 74 0d 0a 3c 65 65 65 65 3e 20 69 73 20 74 68 65 20 65 78 70 65 ┆dress offset <eeee> is the expe┆
0x28c0…28e0 63 74 65 64 20 70 61 74 74 65 72 6e 2c 20 73 68 6f 75 6c 64 20 61 6c 6c 77 61 79 73 20 62 65 20 ┆cted pattern, should allways be ┆
0x28e0…2900 30 30 30 30 20 6f 72 20 46 46 46 46 2e 0d 0a 3c 72 72 72 72 3e 20 69 73 20 74 68 65 20 72 65 63 ┆0000 or FFFF. <rrrr> is the rec┆
0x2900…2920 65 69 76 65 64 20 70 61 74 74 65 72 6e 2e 0d 0a 0d 0a 8c 82 f4 0a 54 68 65 20 61 62 6f 76 65 20 ┆eived pattern. The above ┆
0x2920…2940 6d 65 6e 74 69 6f 6e 65 64 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 20 6d 61 79 20 62 65 20 75 73 65 ┆mentioned information may be use┆
0x2940…2960 64 20 74 6f 20 66 69 6e 64 20 61 20 64 65 66 65 63 74 69 76 65 20 0a 52 41 4d 20 6d 65 6d 6f 72 ┆d to find a defective RAM memor┆
0x2960…2980 79 20 63 68 69 70 20 66 72 6f 6d 20 74 68 65 20 6b 6e 6f 77 6c 65 64 67 65 20 6f 66 20 74 68 65 ┆y chip from the knowledge of the┆
0x2980…29a0 20 52 41 4d 2d 6c 61 79 6f 75 74 2e 20 53 61 79 20 74 68 65 20 0a 65 72 72 6f 72 20 6d 65 73 73 ┆ RAM-layout. Say the error mess┆
0x29a0…29c0 61 67 65 20 67 6f 65 73 20 6c 69 6b 65 20 74 68 69 73 20 3a 0d 0a 0d 0a b0 52 41 4d 20 74 65 73 ┆age goes like this : RAM tes┆
0x29c0…29e0 74 20 3a 20 52 41 4d 20 65 72 72 6f 72 20 20 20 73 65 67 6d 2e 3a 30 30 30 30 20 20 61 64 64 72 ┆t : RAM error segm.:0000 addr┆
0x29e0…2a00 2e 3a 30 30 30 32 20 20 65 78 70 2e 3a 30 30 30 30 0d 0a 19 80 81 82 09 09 09 09 09 20 20 20 b0 ┆.:0002 exp.:0000 ┆
0x2a00…2a20 (21,) 72 65 63 2e 3a 30 30 30 33 0d 0a 0d 0a 54 68 65 20 52 41 4d 20 69 73 20 6d 61 64 65 20 6f 66 20 ┆rec.:0003 The RAM is made of ┆
0x2a20…2a40 31 36 4b 20 2a 20 34 20 62 69 74 20 63 68 69 70 73 2e 20 54 68 69 73 20 6d 65 61 6e 73 20 74 68 ┆16K * 4 bit chips. This means th┆
0x2a40…2a60 61 74 20 55 34 36 2c 20 55 34 37 2c 20 0a 55 34 38 20 61 6e 64 20 55 34 39 20 62 75 69 6c 64 73 ┆at U46, U47, U48 and U49 builds┆
0x2a60…2a80 20 61 20 6c 6f 77 20 61 64 64 72 65 73 73 20 6d 65 6d 6f 72 79 20 62 61 6e 6b 20 28 30 2d 37 46 ┆ a low address memory bank (0-7F┆
0x2a80…2aa0 46 46 29 2c 20 61 6e 64 20 74 68 61 74 20 0a 55 35 36 2c 20 55 35 37 2c 20 55 35 38 20 61 6e 64 ┆FF), and that U56, U57, U58 and┆
0x2aa0…2ac0 20 55 35 39 20 62 75 69 6c 64 73 20 61 20 68 69 67 68 20 61 64 64 72 65 73 73 20 6d 65 6d 6f 72 ┆ U59 builds a high address memor┆
0x2ac0…2ae0 79 20 62 61 6e 6b 20 28 38 30 30 30 2d 0a 46 46 46 46 29 2e 20 45 61 63 68 20 52 41 4d 20 63 68 ┆y bank (8000- FFFF). Each RAM ch┆
0x2ae0…2b00 69 70 20 63 6f 6e 74 61 69 6e 73 20 61 20 6e 69 62 62 6c 65 20 28 34 20 62 69 74 73 29 20 6f 66 ┆ip contains a nibble (4 bits) of┆
0x2b00…2b20 20 64 61 74 61 20 0a 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 74 6f 20 6f 6e 65 20 68 65 78 61 ┆ data corresponding to one hexa┆
0x2b20…2b40 64 65 63 69 6d 61 6c 20 64 69 67 69 74 20 69 6e 20 74 68 65 20 73 65 63 6f 6e 64 61 72 79 20 65 ┆decimal digit in the secondary e┆
0x2b40…2b60 72 72 6f 72 20 0a 64 61 74 61 2e 20 54 68 65 20 6d 65 73 73 61 67 65 20 61 62 6f 76 65 20 6d 69 ┆rror data. The message above mi┆
0x2b60…2b80 67 68 74 20 69 6e 64 69 63 61 74 65 20 61 20 66 61 69 6c 75 72 65 20 69 6e 20 52 41 4d 20 63 68 ┆ght indicate a failure in RAM ch┆
0x2b80…2ba0 69 70 20 55 20 0a 36 33 2e 0d 0a 0d 0a 0d 0a b0 a1 35 2e 32 2e 33 20 4c 6f 6f 70 20 4f 6e 20 45 ┆ip U 63. 5.2.3 Loop On E┆
0x2ba0…2bc0 72 72 6f 72 2e 0d 0a 0d 0a 57 68 65 6e 20 61 20 66 61 75 6c 74 20 6f 63 63 75 72 20 64 75 72 69 ┆rror. When a fault occur duri┆
0x2bc0…2be0 6e 67 20 74 68 65 20 72 61 6d 20 74 65 73 74 20 61 6e 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 ┆ng the ram test an error message┆
0x2be0…2c00 20 69 73 20 0a 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 63 6f 6e 73 6f 6c 65 2c 20 61 6e 64 ┆ is written to the console, and┆
0x2c00…2c20 (22,) 20 74 68 65 20 52 41 4d 20 74 65 73 74 20 73 74 61 72 74 73 20 66 72 6f 6d 20 74 68 65 20 73 74 ┆ the RAM test starts from the st┆
0x2c20…2c40 61 72 74 20 0a 61 67 61 69 6e 2e 20 54 68 69 73 20 77 69 6c 6c 20 62 65 20 74 68 65 20 63 61 73 ┆art again. This will be the cas┆
0x2c40…2c60 65 20 75 6e 74 69 6c 20 6e 6f 20 65 72 72 6f 72 20 69 73 20 64 69 73 63 6f 76 65 72 65 64 2e 20 ┆e until no error is discovered. ┆
0x2c60…2c80 49 66 20 0a 74 68 65 72 65 20 69 73 20 61 20 52 41 4d 20 65 72 72 6f 72 20 61 6e 64 20 69 66 20 ┆If there is a RAM error and if ┆
0x2c80…2ca0 61 6e 20 4c 20 69 73 20 74 79 70 65 64 20 66 72 6f 6d 20 74 68 65 20 6b 65 79 62 6f 61 72 64 2c ┆an L is typed from the keyboard,┆
0x2ca0…2cc0 20 74 68 65 6e 20 0a 74 68 65 20 52 41 4d 20 74 65 73 74 20 77 69 6c 6c 20 6e 6f 74 20 73 74 61 ┆ then the RAM test will not sta┆
0x2cc0…2ce0 72 74 20 66 72 6f 6d 20 74 68 65 20 62 65 67 69 6e 6e 69 6e 67 20 61 67 61 69 6e 2c 20 62 75 74 ┆rt from the beginning again, but┆
0x2ce0…2d00 20 70 72 6f 63 65 65 64 20 0a 74 72 6f 75 67 68 20 74 68 65 20 52 41 4d 20 74 65 73 74 20 61 6e ┆ proceed trough the RAM test an┆
0x2d00…2d20 64 20 77 72 69 74 65 20 61 6c 6c 20 52 41 4d 20 65 72 72 6f 72 73 20 74 6f 20 74 68 65 20 63 6f ┆d write all RAM errors to the co┆
0x2d20…2d40 6e 73 6f 6c 65 2c 20 61 6e 64 20 0a 66 69 6e 61 6c 6c 79 20 65 6e 74 65 72 20 74 68 65 20 22 74 ┆nsole, and finally enter the "t┆
0x2d40…2d60 65 73 74 2d 61 64 6d 69 6e 69 73 74 72 61 74 6f 72 22 20 74 6f 20 65 78 65 63 75 74 65 20 6f 74 ┆est-administrator" to execute ot┆
0x2d60…2d6c 68 65 72 20 74 65 73 74 73 2e 0d 0a ┆her tests. ┆
0x2d6c…2d6f FormFeed {
0x2d6c…2d6f 0c 82 ac ┆ ┆
0x2d6c…2d6f }
0x2d6f…2d80 0a a1 b0 36 2e 20 b0 54 65 73 74 20 31 20 3d 20 f0 ┆ 6. Test 1 = ┆
0x2d80…2da0 43 48 49 50 20 53 45 4c 45 43 54 20 54 45 53 54 2e 0d 0a 0d 0a 54 6f 20 65 61 73 65 20 63 6f 6d ┆CHIP SELECT TEST. To ease com┆
0x2da0…2dc0 70 6c 65 78 20 64 65 62 75 67 67 69 6e 67 2c 20 61 20 73 69 6d 70 6c 65 20 63 68 69 70 20 73 65 ┆plex debugging, a simple chip se┆
0x2dc0…2de0 6c 65 63 74 20 6c 6f 6f 70 2c 20 63 6f 6d 62 69 6e 65 64 20 0a 77 69 74 68 20 61 20 52 41 4d 20 ┆lect loop, combined with a RAM ┆
0x2de0…2e00 77 72 69 74 65 2f 72 65 61 64 2c 20 69 73 20 73 75 70 70 6c 69 65 64 2e 20 0d 0a 0d 0a 54 68 69 ┆write/read, is supplied. Thi┆
0x2e00…2e20 (23,) 73 20 74 65 73 74 20 67 65 6e 65 72 61 74 65 73 20 63 68 69 70 20 73 65 6c 65 63 74 73 20 74 6f ┆s test generates chip selects to┆
0x2e20…2e40 20 61 6c 6c 20 70 65 72 69 70 68 65 72 61 6c 20 64 65 76 69 63 65 73 20 62 79 20 0a 65 78 65 63 ┆ all peripheral devices by exec┆
0x2e40…2e60 75 74 69 6e 67 20 69 6e 70 75 74 20 69 6e 73 74 72 75 63 74 69 6f 6e 73 20 74 6f 20 61 6c 6c 20 ┆uting input instructions to all ┆
0x2e60…2e80 72 65 6c 65 76 61 6e 74 20 49 2f 4f 2d 64 65 76 69 63 65 73 2e 20 54 68 65 73 65 20 0a 61 72 65 ┆relevant I/O-devices. These are┆
0x2e80…2ea0 20 3a 0d 0a 0d 0a 50 6f 72 74 20 84 30 2c 20 32 2c 20 31 32 38 2c 20 31 33 30 2c 20 32 35 36 2c ┆ : Port 0, 2, 128, 130, 256,┆
0x2ea0…2ec0 20 32 35 38 2c 20 32 36 30 2c 20 32 36 32 2c 20 33 38 34 2c 20 33 38 36 2c 20 33 38 38 2c 20 33 ┆ 258, 260, 262, 384, 386, 388, 3┆
0x2ec0…2ee0 39 30 2c 20 33 39 32 2c 20 0a 19 85 80 80 33 39 34 2c 20 33 39 36 2c 20 33 39 38 2c 20 35 31 32 ┆90, 392, 394, 396, 398, 512┆
0x2ee0…2f00 2c 20 35 31 34 2c 20 35 31 36 2c 20 35 31 38 2c 20 36 34 30 2c 20 36 34 32 2c 20 36 34 34 2c 20 ┆, 514, 516, 518, 640, 642, 644, ┆
0x2f00…2f20 36 34 36 2c 20 36 34 38 2c 20 0a 19 85 80 80 36 35 30 2c 20 36 35 32 2c 20 36 35 34 2e 0d 0a 0d ┆646, 648, 650, 652, 654. ┆
0x2f20…2f40 0a 57 68 65 6e 20 61 6c 6c 20 74 68 65 20 63 68 69 70 20 73 65 6c 65 63 74 73 20 61 72 65 20 6d ┆ When all the chip selects are m┆
0x2f40…2f60 61 64 65 2c 20 61 20 70 61 74 74 65 72 6e 20 41 41 35 35 20 68 65 78 2e 20 69 73 20 0a 77 72 69 ┆ade, a pattern AA55 hex. is wri┆
0x2f60…2f80 74 74 65 6e 20 74 6f 20 61 20 52 41 4d 20 63 65 6c 6c 20 61 6e 64 20 69 6d 6d 65 64 69 61 74 65 ┆tten to a RAM cell and immediate┆
0x2f80…2fa0 6c 79 20 72 65 61 64 20 62 61 63 6b 2e 0d 0a 0d 0a 54 68 69 73 20 74 65 73 74 20 69 73 20 75 6e ┆ly read back. This test is un┆
0x2fa0…2fc0 61 62 6c 65 20 74 6f 20 67 65 6e 65 72 61 74 65 20 61 6e 79 20 65 72 72 6f 72 20 6d 65 73 73 61 ┆able to generate any error messa┆
0x2fc0…2fe0 67 65 73 2e 20 49 74 20 69 73 20 6d 65 61 6e 74 20 0a 6f 6e 6c 79 20 61 73 20 61 20 73 70 65 63 ┆ges. It is meant only as a spec┆
0x2fe0…2ffb 69 61 6c 20 66 61 73 74 20 73 63 6f 70 65 20 6c 6f 6f 70 20 74 65 73 74 2e 0d 0a ┆ial fast scope loop test. ┆
0x2ffb…2ffe FormFeed {
0x2ffb…2ffe 0c 81 d8 ┆ ┆
0x2ffb…2ffe }
0x2ffe…3000 0a a2 ┆ ┆
0x3000…3020 (24,) e2 a1 b0 b0 37 2e 20 b0 54 45 53 54 20 32 f0 20 3d 20 69 41 50 58 20 31 38 36 20 54 49 4d 45 52 ┆ 7. TEST 2 = iAPX 186 TIMER┆
0x3020…3040 20 54 45 53 54 2e 0d 0a 0d 0a 54 68 69 73 20 74 65 73 74 20 76 65 72 69 66 69 65 73 20 74 68 65 ┆ TEST. This test verifies the┆
0x3040…3060 20 61 62 69 6c 69 74 79 20 6f 66 20 74 68 65 20 69 41 50 58 20 31 38 36 20 69 6e 74 65 72 6e 61 ┆ ability of the iAPX 186 interna┆
0x3060…3080 6c 20 74 69 6d 65 72 20 30 20 0a 74 6f 20 67 65 6e 65 72 61 74 65 20 69 6e 74 65 72 72 75 70 74 ┆l timer 0 to generate interrupt┆
0x3080…30a0 73 2e 20 54 68 65 20 69 6e 74 65 72 6e 61 6c 20 74 69 6d 65 72 20 30 20 69 73 20 69 6e 69 74 69 ┆s. The internal timer 0 is initi┆
0x30a0…30c0 61 6c 69 7a 65 64 20 61 73 20 61 20 0a 72 65 61 6c 20 74 69 6d 65 20 63 6c 6f 63 6b 20 77 68 69 ┆alized as a real time clock whi┆
0x30c0…30e0 63 68 20 67 65 6e 65 72 61 74 65 73 20 69 6e 74 65 72 72 75 70 74 20 65 76 65 72 79 20 32 30 20 ┆ch generates interrupt every 20 ┆
0x30e0…3100 6d 69 6c 6c 69 73 65 63 6f 6e 64 2e 20 0a 49 66 20 6e 6f 20 74 69 6d 65 72 20 69 6e 74 65 72 72 ┆millisecond. If no timer interr┆
0x3100…3120 75 70 74 20 69 73 20 67 65 6e 65 72 61 74 65 64 20 74 68 65 6e 20 61 6e 20 65 72 72 6f 72 20 6d ┆upt is generated then an error m┆
0x3120…3140 65 73 73 61 67 65 20 69 73 20 0a 67 65 6e 65 72 61 74 65 64 20 6c 69 6b 65 20 74 68 69 73 2e 0d ┆essage is generated like this. ┆
0x3140…3160 0a 0d 0a a1 a1 a1 e1 b0 f0 31 2e 20 b0 69 41 50 58 31 38 36 20 74 69 6d 65 72 20 74 65 73 74 20 ┆ 1. iAPX186 timer test ┆
0x3160…3180 3a 20 6d 69 73 73 69 6e 67 20 74 69 6d 65 72 20 30 20 69 6e 74 65 72 72 75 70 74 0d 0a 0d 0a 54 ┆: missing timer 0 interrupt T┆
0x3180…31a0 68 69 73 20 65 72 72 6f 72 20 73 68 6f 75 6c 64 20 69 6e 64 69 63 61 74 65 20 61 20 6d 61 6c 66 ┆his error should indicate a malf┆
0x31a0…31c0 75 6e 63 74 69 6f 6e 20 6f 66 20 74 68 65 20 69 41 50 58 20 31 38 36 20 0a 70 72 6f 63 65 73 73 ┆unction of the iAPX 186 process┆
0x31c0…31ca 6f 72 20 63 68 69 70 2e 0d 0a ┆or chip. ┆
0x31ca…31cd FormFeed {
0x31ca…31cd 0c 81 90 ┆ ┆
0x31ca…31cd }
0x31cd…31e0 0a a1 b0 38 2e 20 b0 54 45 53 54 20 33 f0 20 3d 20 69 41 ┆ 8. TEST 3 = iA┆
0x31e0…3200 50 58 20 31 38 36 20 44 4d 41 20 54 45 53 54 2e 0d 0a 0d 0a 54 68 69 73 20 74 65 73 74 20 76 65 ┆PX 186 DMA TEST. This test ve┆
0x3200…3220 (25,) 72 69 66 69 65 73 20 74 68 65 20 61 62 69 6c 69 74 79 20 6f 66 20 74 68 65 20 74 77 6f 20 69 41 ┆rifies the ability of the two iA┆
0x3220…3240 50 58 20 31 38 36 20 69 6e 74 65 72 6e 61 6c 20 44 4d 41 20 0a 63 68 61 6e 6e 65 6c 73 20 74 6f ┆PX 186 internal DMA channels to┆
0x3240…3260 20 6d 61 6b 65 20 61 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 61 6e 64 20 74 6f 20 67 65 ┆ make a data transport and to ge┆
0x3260…3280 6e 65 72 61 74 65 20 69 6e 74 65 72 72 75 70 74 73 2e 20 54 68 65 20 0a 74 77 6f 20 69 41 50 58 ┆nerate interrupts. The two iAPX┆
0x3280…32a0 20 31 38 36 20 44 4d 41 20 63 68 61 6e 6e 65 6c 73 20 61 72 65 20 69 6e 69 74 69 61 6c 69 7a 65 ┆ 186 DMA channels are initialize┆
0x32a0…32c0 64 20 74 6f 20 70 65 72 66 6f 72 6d 20 61 20 44 4d 41 20 6d 65 6d 6f 72 79 20 0a 74 6f 20 6d 65 ┆d to perform a DMA memory to me┆
0x32c0…32e0 6d 6f 72 79 20 74 72 61 6e 73 70 6f 72 74 20 73 69 6d 75 6c 74 61 6e 65 6f 75 73 6c 79 2e 20 44 ┆mory transport simultaneously. D┆
0x32e0…3300 4d 41 20 63 68 61 6e 6e 65 6c 20 30 20 63 6f 70 69 65 73 20 38 20 4b 62 79 74 65 73 20 0a 66 72 ┆MA channel 0 copies 8 Kbytes fr┆
0x3300…3320 6f 6d 20 61 20 73 6f 75 72 63 65 20 74 6f 20 61 20 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 66 ┆om a source to a destination buf┆
0x3320…3340 66 65 72 20 69 6e 20 74 68 65 20 66 6f 72 77 61 72 64 20 64 69 72 65 63 74 69 6f 6e 2c 20 0a 61 ┆fer in the forward direction, a┆
0x3340…3360 6e 64 20 44 4d 41 20 63 68 61 6e 6e 65 6c 20 31 20 63 6f 70 69 65 73 20 66 72 6f 6d 20 74 68 65 ┆nd DMA channel 1 copies from the┆
0x3360…3380 20 73 61 6d 65 20 73 6f 75 72 63 65 20 74 6f 20 61 6e 6f 74 68 65 72 20 0a 64 65 73 74 69 6e 61 ┆ same source to another destina┆
0x3380…33a0 74 69 6f 6e 20 62 75 66 66 65 72 20 69 6e 20 74 68 65 20 72 65 76 65 72 73 65 20 64 69 72 65 63 ┆tion buffer in the reverse direc┆
0x33a0…33c0 74 69 6f 6e 2e 20 41 6c 6c 20 44 4d 41 20 74 72 61 6e 73 66 65 72 73 20 0a 61 72 65 20 73 79 6e ┆tion. All DMA transfers are syn┆
0x33c0…33e0 63 72 6f 6e 69 7a 65 64 20 74 6f 20 74 68 65 20 69 6e 74 65 72 6e 61 6c 20 74 69 6d 65 72 20 32 ┆cronized to the internal timer 2┆
0x33e0…3400 20 77 68 69 63 68 20 67 65 6e 65 72 61 74 65 73 20 61 20 32 35 30 20 4b 48 7a 20 0a 63 6c 6f 63 ┆ which generates a 250 KHz cloc┆
0x3400…3420 (26,) 6b 2e 20 54 68 65 20 74 77 6f 20 63 68 61 6e 6e 65 6c 73 20 61 72 65 20 69 6e 69 74 69 61 6c 69 ┆k. The two channels are initiali┆
0x3420…3440 7a 65 64 20 74 6f 20 74 68 65 20 73 61 6d 65 20 70 72 69 6f 72 69 74 79 2e 20 0a 54 68 69 73 20 ┆zed to the same priority. This ┆
0x3440…3460 65 6e 73 75 72 65 73 20 74 6f 67 65 74 68 65 72 20 77 69 74 68 20 74 68 65 20 73 65 6c 65 63 74 ┆ensures together with the select┆
0x3460…3480 65 64 20 69 6e 74 65 72 6e 61 6c 20 74 69 6d 65 72 20 32 20 0a 73 79 6e 63 72 6f 6e 69 7a 61 74 ┆ed internal timer 2 syncronizat┆
0x3480…34a0 69 6f 6e 20 74 68 61 74 20 62 6f 74 68 20 44 4d 41 20 63 68 61 6e 6e 65 6c 73 20 72 75 6e 73 20 ┆ion that both DMA channels runs ┆
0x34a0…34c0 73 69 6d 75 6c 74 61 6e 65 6f 75 73 6c 79 20 61 6e 64 20 0a 74 68 61 74 20 74 68 65 20 43 50 55 ┆simultaneously and that the CPU┆
0x34c0…34e0 20 6d 61 79 20 61 6c 73 6f 20 67 65 74 20 6d 65 6d 6f 72 79 20 61 63 63 65 73 73 2e 20 57 68 65 ┆ may also get memory access. Whe┆
0x34e0…3500 6e 20 74 68 65 20 44 4d 41 20 74 72 61 6e 73 70 6f 72 74 20 0a 69 73 20 63 6f 6d 70 6c 65 74 65 ┆n the DMA transport is complete┆
0x3500…3520 20 62 6f 74 68 20 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 66 66 65 72 73 20 61 72 65 20 63 6f ┆ both destination buffers are co┆
0x3520…3540 6d 70 61 72 65 64 20 74 6f 20 74 68 65 20 73 6f 75 72 63 65 20 0a 62 75 66 66 65 72 2e 0d 0a 0d ┆mpared to the source buffer. ┆
0x3540…3560 0a 54 68 65 20 74 65 73 74 20 70 72 6f 64 75 63 65 73 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 ┆ The test produces the following┆
0x3560…3580 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 73 3a 0d 0a 0d 0a b0 f0 31 2e 20 b0 44 4d 41 20 74 65 ┆ error messages: 1. DMA te┆
0x3580…35a0 73 74 3a 20 64 61 74 61 20 65 72 72 6f 72 20 20 73 65 67 6d 2e 3a 20 3c 73 73 73 73 3e 20 61 64 ┆st: data error segm.: <ssss> ad┆
0x35a0…35c0 64 72 2e 3a 3c 61 61 61 61 3e 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 19 80 82 82 09 09 09 09 ┆dr.:<aaaa> rec.:<rrrr> ┆
0x35c0…35e0 09 20 20 20 20 20 20 20 20 b0 65 78 70 2e 3a 3c 65 65 65 65 3e 0d 0a 0d 0a b0 f0 32 2e 20 b0 44 ┆ exp.:<eeee> 2. D┆
0x35e0…3600 4d 41 20 74 65 73 74 3a 20 74 72 61 6e 73 66 65 72 20 74 69 6d 65 6f 75 74 0d 0a 0d 0a 54 68 65 ┆MA test: transfer timeout The┆
0x3600…3620 (27,) 20 66 69 72 73 74 20 65 72 72 6f 72 20 69 6e 64 69 63 74 65 73 20 74 68 61 74 20 62 6f 74 68 20 ┆ first error indictes that both ┆
0x3620…3640 44 4d 41 20 74 72 61 6e 73 70 6f 72 74 73 20 68 61 73 20 74 65 72 6d 69 6e 61 74 65 64 20 0a 62 ┆DMA transports has terminated b┆
0x3640…3660 75 74 20 74 68 65 20 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 66 66 65 72 20 69 73 20 6e 6f 74 ┆ut the destination buffer is not┆
0x3660…3680 20 65 71 75 61 6c 20 74 6f 20 74 68 65 20 73 6f 75 72 63 65 20 61 73 20 0a 65 78 70 65 63 74 65 ┆ equal to the source as expecte┆
0x3680…36a0 64 2e 20 54 68 65 20 6c 61 74 74 65 72 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 6f 6e 65 ┆d. The latter indicates that one┆
0x36a0…36c0 20 6f 66 20 74 68 65 20 74 77 6f 20 6f 72 20 62 6f 74 68 20 44 4d 41 20 0a 69 6e 74 65 72 72 75 ┆ of the two or both DMA interru┆
0x36c0…36e0 70 74 73 20 69 73 20 6d 69 73 73 69 6e 67 2e 0d 0a 0d 0a 42 6f 74 68 20 65 72 72 6f 72 73 20 73 ┆pts is missing. Both errors s┆
0x36e0…3700 68 6f 75 6c 64 20 69 6e 64 69 63 61 74 65 20 61 20 6d 61 6c 66 75 6e 63 74 69 6f 6e 20 6f 66 20 ┆hould indicate a malfunction of ┆
0x3700…371f 74 68 65 20 69 41 50 58 20 31 38 36 20 0a 70 72 6f 63 65 73 73 6f 72 20 63 68 69 70 2e 0d 0a ┆the iAPX 186 processor chip. ┆
0x371f…3722 FormFeed {
0x371f…3722 0c 82 f4 ┆ ┆
0x371f…3722 }
0x3722…3740 0a a1 b0 39 2e b0 20 54 65 73 74 20 34 20 3d f0 20 50 41 52 41 4c 4c 45 4c 20 50 4f 52 54 ┆ 9. Test 4 = PARALLEL PORT┆
0x3740…3760 20 54 45 53 54 2e 0d 0a 0d 0a 54 68 65 20 38 32 35 35 41 20 50 50 49 20 74 65 73 74 20 77 72 69 ┆ TEST. The 8255A PPI test wri┆
0x3760…3780 74 65 73 20 61 20 70 61 74 74 65 72 6e 20 31 30 31 30 30 30 30 30 20 62 69 6e 61 72 79 20 74 6f ┆tes a pattern 10100000 binary to┆
0x3780…37a0 20 74 68 65 20 6f 75 74 70 75 74 20 0a 70 6f 72 74 20 42 20 28 20 69 6f 61 64 72 2e 20 41 31 48 ┆ the output port B ( ioadr. A1H┆
0x37a0…37c0 20 29 2e 20 54 68 65 6e 20 69 74 20 72 65 61 64 73 20 74 68 65 20 70 61 74 74 65 72 6e 20 62 61 ┆ ). Then it reads the pattern ba┆
0x37c0…37e0 63 6b 20 61 6e 64 20 0a 76 65 72 69 66 69 65 73 20 69 74 2e 20 49 66 20 6e 6f 20 65 72 72 6f 72 ┆ck and verifies it. If no error┆
0x37e0…3800 20 69 73 20 64 65 74 65 63 74 65 64 20 74 68 65 20 70 61 74 74 65 72 6e 20 69 73 20 73 68 69 66 ┆ is detected the pattern is shif┆
0x3800…3820 (28,) 74 65 64 20 6f 6e 65 20 0a 62 69 74 20 74 6f 20 74 68 65 20 72 69 67 68 74 2c 20 61 6e 64 20 74 ┆ted one bit to the right, and t┆
0x3820…3840 68 65 20 77 72 69 74 65 2f 72 65 61 64 20 76 65 72 69 66 79 20 70 72 6f 63 65 64 75 72 65 20 69 ┆he write/read verify procedure i┆
0x3840…3860 73 20 72 65 70 65 61 74 65 64 20 0a 75 6e 74 69 6c 20 74 68 65 20 70 61 74 74 65 72 6e 20 62 65 ┆s repeated until the pattern be┆
0x3860…3880 63 6f 6d 65 73 20 7a 65 72 6f 2e 20 54 68 65 20 74 65 73 74 20 6d 61 79 20 67 65 6e 65 72 61 74 ┆comes zero. The test may generat┆
0x3880…38a0 65 20 74 68 69 73 20 65 72 72 6f 72 20 0a 6d 65 73 73 61 67 65 3a 0d 0a 0d 0a b0 e1 a1 e1 f0 31 ┆e this error message: 1┆
0x38a0…38c0 2e 20 b0 50 50 49 20 74 65 73 74 3a 20 70 6f 72 74 20 65 72 72 6f 72 20 20 65 78 70 2e 3a 30 30 ┆. PPI test: port error exp.:00┆
0x38c0…38e0 65 65 2c 20 72 65 63 2e 3a 30 30 72 72 0d 0a 0d 0a 45 78 70 65 63 74 65 64 20 61 6e 64 20 72 65 ┆ee, rec.:00rr Expected and re┆
0x38e0…3900 63 65 69 76 65 64 20 70 61 74 74 65 72 6e 20 74 65 6c 6c 73 20 79 6f 75 20 77 68 61 74 20 62 69 ┆ceived pattern tells you what bi┆
0x3900…3920 74 73 20 77 65 6e 74 20 77 72 6f 6e 67 20 77 69 74 68 20 0a 74 68 65 20 74 65 73 74 2e 0d 0a 0d ┆ts went wrong with the test. ┆
0x3920…3940 0a 54 68 69 73 20 65 72 72 6f 72 20 6d 69 67 68 74 20 62 65 20 63 61 75 73 65 64 20 62 79 20 6d ┆ This error might be caused by m┆
0x3940…3960 61 6c 66 75 6e 63 74 69 6f 6e 20 6f 66 20 74 68 65 20 38 32 35 35 41 20 63 68 69 70 2c 20 62 79 ┆alfunction of the 8255A chip, by┆
0x3960…3980 20 0a 61 6e 20 69 6e 69 74 69 61 6c 69 7a 61 74 69 6f 6e 20 66 61 75 6c 74 20 28 20 49 2f 4f 20 ┆ an initialization fault ( I/O ┆
0x3980…39a0 73 70 61 63 65 20 65 72 72 6f 72 20 29 2c 20 6f 72 20 62 79 20 73 6f 6d 65 74 68 69 6e 67 20 0a ┆space error ), or by something ┆
0x39a0…39a7 65 6c 73 65 2e 20 0a ┆else. ┆
0x39a7…39aa FormFeed {
0x39a7…39aa 0c 81 cc ┆ ┆
0x39a7…39aa }
0x39aa…39c0 0a a1 b0 31 30 2e 20 b0 54 65 73 74 20 35 f0 20 3d 20 4c 49 4e 45 ┆ 10. Test 5 = LINE┆
0x39c0…39e0 20 43 4f 4e 54 52 4f 4c 20 50 52 4f 43 45 53 53 4f 52 20 44 41 54 41 20 54 45 53 54 2e 0d 0a 0d ┆ CONTROL PROCESSOR DATA TEST. ┆
0x39e0…3a00 0a 54 68 69 73 20 74 65 73 74 20 6d 61 6b 65 73 20 61 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 ┆ This test makes a data transpor┆
0x3a00…3a20 (29,) 74 20 74 6f 20 74 68 65 20 49 6e 74 65 6c 20 38 30 35 31 20 4c 69 6e 65 20 43 6f 6e 74 72 6f 6c ┆t to the Intel 8051 Line Control┆
0x3a20…3a40 20 0a 50 72 6f 63 65 73 73 6f 72 2c 20 77 68 69 63 68 20 6c 6f 6f 70 73 20 62 61 63 6b 20 74 68 ┆ Processor, which loops back th┆
0x3a40…3a60 65 20 64 61 74 61 20 75 6e 63 68 61 6e 67 65 64 2e 20 54 68 65 20 69 41 50 58 20 31 38 36 20 0a ┆e data unchanged. The iAPX 186 ┆
0x3a60…3a80 69 6e 74 65 72 6e 61 6c 20 44 4d 41 20 63 68 61 6e 6e 65 6c 20 30 20 69 73 20 69 6e 69 74 69 61 ┆internal DMA channel 0 is initia┆
0x3a80…3aa0 6c 69 7a 65 64 20 74 6f 20 74 72 61 6e 73 66 65 72 20 32 35 36 20 62 79 74 65 73 20 6f 66 20 0a ┆lized to transfer 256 bytes of ┆
0x3aa0…3ac0 64 61 74 61 20 74 6f 20 74 68 65 20 4c 43 50 20 63 68 61 6e 6e 65 6c 2e 20 54 68 65 20 4c 43 50 ┆data to the LCP channel. The LCP┆
0x3ac0…3ae0 20 74 65 73 74 20 70 72 6f 67 72 61 6d 20 69 73 20 73 74 61 72 74 65 64 20 62 79 20 0a 77 72 69 ┆ test program is started by wri┆
0x3ae0…3b00 74 69 6e 67 20 61 20 63 6f 6d 6d 61 6e 64 20 63 6f 64 65 20 31 20 74 6f 20 74 68 65 20 4c 43 50 ┆ting a command code 1 to the LCP┆
0x3b00…3b20 20 63 6f 6d 6d 61 6e 64 20 70 6f 72 74 20 28 32 30 34 20 48 65 78 2e 29 2e 20 54 68 65 20 0a 69 ┆ command port (204 Hex.). The i┆
0x3b20…3b40 41 50 58 20 31 38 36 20 69 6e 74 65 72 6e 61 6c 20 44 4d 41 20 63 68 61 6e 6e 65 6c 20 31 20 69 ┆APX 186 internal DMA channel 1 i┆
0x3b40…3b60 73 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 61 73 20 74 68 65 20 72 65 63 65 69 76 65 20 0a 63 68 ┆s initialized as the receive ch┆
0x3b60…3b80 61 6e 6e 65 6c 2c 20 61 6e 64 20 73 69 6e 6b 73 20 74 68 65 20 64 61 74 61 20 6c 6f 6f 70 65 64 ┆annel, and sinks the data looped┆
0x3b80…3ba0 20 62 61 63 6b 20 66 72 6f 6d 20 74 68 65 20 4c 43 50 20 63 68 61 6e 6e 65 6c 2e 20 54 68 65 20 ┆ back from the LCP channel. The ┆
0x3ba0…3bc0 0a 4c 43 50 20 63 68 61 6e 6e 65 6c 73 20 73 69 67 6e 61 6c 20 77 69 74 68 20 61 6e 20 69 6e 74 ┆ LCP channels signal with an int┆
0x3bc0…3be0 65 72 72 75 70 74 20 74 6f 20 74 68 65 20 69 41 50 58 20 31 38 36 20 70 72 6f 63 65 73 73 6f 72 ┆errupt to the iAPX 186 processor┆
0x3be0…3c00 20 0a 77 68 65 6e 20 74 68 65 20 74 72 61 6e 73 66 65 72 20 69 73 20 63 6f 6d 70 6c 65 74 65 2e ┆ when the transfer is complete.┆
0x3c00…3c20 (30,) 20 54 68 65 20 69 41 50 58 20 31 38 36 20 77 61 69 74 73 20 66 6f 72 20 74 68 65 20 0a 69 6e 74 ┆ The iAPX 186 waits for the int┆
0x3c20…3c40 65 72 72 75 70 74 20 74 6f 20 6f 63 63 75 72 20 77 69 74 68 69 6e 20 31 20 73 65 63 6f 6e 64 2c ┆errupt to occur within 1 second,┆
0x3c40…3c60 20 61 6e 64 20 69 66 20 6e 6f 74 20 61 20 74 69 6d 65 6f 75 74 20 6d 65 73 73 61 67 65 20 0a 69 ┆ and if not a timeout message i┆
0x3c60…3c80 73 20 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 22 74 65 73 74 2d 6f 75 74 70 75 74 22 2e 20 ┆s written to the "test-output". ┆
0x3c80…3ca0 4e 4f 54 45 20 74 68 61 74 20 74 68 65 20 64 61 74 61 20 77 72 69 74 74 65 6e 20 74 6f 20 0a 74 ┆NOTE that the data written to t┆
0x3ca0…3cc0 68 65 20 4c 43 50 20 69 73 20 6e 6f 74 20 6c 6f 6f 70 65 64 20 62 61 63 6b 20 6f 6e 20 74 68 65 ┆he LCP is not looped back on the┆
0x3cc0…3ce0 20 73 65 72 69 61 6c 20 6c 69 6e 65 2c 20 6f 6e 6c 79 20 61 6e 20 69 6e 74 65 72 6e 61 6c 20 0a ┆ serial line, only an internal ┆
0x3ce0…3d00 6c 6f 6f 70 62 61 63 6b 20 69 73 20 6d 61 64 65 2e 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 6d 61 ┆loopback is made. The test ma┆
0x3d00…3d20 79 20 67 65 6e 65 72 61 74 65 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 65 72 72 6f 72 20 6d ┆y generate the following error m┆
0x3d20…3d40 65 73 73 61 67 65 73 3a 0d 0a 0d 0a b0 f0 31 2e 20 b0 4c 43 50 20 64 61 74 61 20 74 65 73 74 3a ┆essages: 1. LCP data test:┆
0x3d40…3d60 20 63 6f 6d 6d 61 6e 64 20 74 69 6d 65 6f 75 74 0d 0a 0d 0a b0 54 68 65 20 4c 69 6e 65 20 43 6f ┆ command timeout The Line Co┆
0x3d60…3d80 6e 74 72 6f 6c 20 50 72 6f 63 65 73 73 6f 72 20 64 69 64 20 6e 6f 74 20 72 65 73 70 6f 6e 64 20 ┆ntrol Processor did not respond ┆
0x3d80…3da0 74 6f 20 74 68 65 20 63 6f 6d 6d 61 6e 64 2e 20 54 68 65 20 0a 19 80 81 82 73 69 67 6e 61 6c 20 ┆to the command. The signal ┆
0x3da0…3dc0 63 61 6c 6c 65 64 20 43 4d 44 41 43 43 45 50 54 20 6f 6e 20 74 68 65 20 38 32 35 35 41 20 70 6f ┆called CMDACCEPT on the 8255A po┆
0x3dc0…3de0 72 74 20 41 20 62 69 74 20 30 20 77 61 73 20 6e 6f 74 20 73 65 74 20 0a 19 80 81 82 77 69 74 68 ┆rt A bit 0 was not set with┆
0x3de0…3e00 69 6e 20 31 20 73 65 63 6f 6e 64 2e 0d 0a 0d 0a b0 f0 32 2e 20 b0 4c 43 50 20 64 61 74 61 20 74 ┆in 1 second. 2. LCP data t┆
0x3e00…3e20 (31,) 65 73 74 3a 20 6d 69 73 73 69 6e 67 20 74 65 72 6d 69 6e 61 74 65 20 69 6e 74 65 72 72 75 70 74 ┆est: missing terminate interrupt┆
0x3e20…3e40 0d 0a 0d 0a 54 68 65 20 4c 43 50 20 61 63 63 65 70 74 65 64 20 74 68 65 20 63 6f 6d 6d 61 6e 64 ┆ The LCP accepted the command┆
0x3e40…3e60 2c 20 62 75 74 20 6e 6f 20 74 65 72 6d 69 6e 61 74 65 20 69 6e 74 65 72 72 75 70 74 20 77 61 73 ┆, but no terminate interrupt was┆
0x3e60…3e80 20 0a 67 65 6e 65 72 61 74 65 64 20 77 69 74 69 6e 20 31 20 73 65 63 6f 6e 64 20 61 66 74 65 72 ┆ generated witin 1 second after┆
0x3e80…3ea0 20 74 68 65 20 63 6f 6d 6d 61 6e 64 20 61 63 63 65 70 74 2e 0d 0a 0d 0a b0 f0 33 2e 20 b0 4c 43 ┆ the command accept. 3. LC┆
0x3ea0…3ec0 50 20 64 61 74 61 20 74 65 73 74 3a 20 64 61 74 61 20 65 72 72 6f 72 20 20 73 65 67 6d 2e 3a 3c ┆P data test: data error segm.:<┆
0x3ec0…3ee0 73 73 73 73 3e 20 20 61 64 64 72 2e 3a 3c 61 61 61 61 3e 0d 0a 19 80 81 82 20 20 20 20 20 20 20 ┆ssss> addr.:<aaaa> ┆
0x3ee0…3f00 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 b0 65 78 70 2e 3a 3c ┆ exp.:<┆
0x3f00…3f20 65 65 65 65 3e 20 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 0d 0a b0 54 68 65 20 64 61 74 61 20 ┆eeee> rec.:<rrrr> The data ┆
0x3f20…3f40 72 65 63 65 69 76 65 64 20 77 61 73 20 6e 6f 74 20 74 68 65 20 65 71 75 61 6c 20 74 6f 20 74 68 ┆received was not the equal to th┆
0x3f40…3f60 65 20 64 61 74 61 20 74 72 61 6e 73 6d 69 74 74 65 64 20 61 73 20 69 74 20 0a 19 80 81 82 73 68 ┆e data transmitted as it sh┆
0x3f60…3f6a 6f 75 6c 64 20 62 65 2e 0d 0a ┆ould be. ┆
0x3f6a…3f6d FormFeed {
0x3f6a…3f6d 0c 83 98 ┆ ┆
0x3f6a…3f6d }
0x3f6d…3f80 0a a1 b0 31 31 2e 20 b0 54 65 73 74 20 36 f0 20 3d 20 4c ┆ 11. Test 6 = L┆
0x3f80…3fa0 49 4e 45 20 43 4f 4e 54 52 4f 4c 20 50 52 4f 43 45 53 53 4f 52 20 4c 4f 4f 50 42 41 43 4b 20 54 ┆INE CONTROL PROCESSOR LOOPBACK T┆
0x3fa0…3fc0 45 53 54 2e 0d 0a 0d 0a 54 68 69 73 20 74 65 73 74 20 6d 61 6b 65 73 20 61 20 64 61 74 61 20 74 ┆EST. This test makes a data t┆
0x3fc0…3fe0 72 61 6e 73 70 6f 72 74 20 74 6f 20 74 68 65 20 49 6e 74 65 6c 20 38 30 35 31 20 4c 69 6e 65 20 ┆ransport to the Intel 8051 Line ┆
0x3fe0…4000 43 6f 6e 74 72 6f 6c 20 0a 50 72 6f 63 65 73 73 6f 72 2c 20 77 68 69 63 68 20 6c 6f 6f 70 73 20 ┆Control Processor, which loops ┆
0x4000…4020 (32,) 62 61 63 6b 20 74 68 65 20 64 61 74 61 20 75 6e 63 68 61 6e 67 65 64 2e 20 54 68 65 20 69 41 50 ┆back the data unchanged. The iAP┆
0x4020…4040 58 20 31 38 36 20 0a 69 6e 74 65 72 6e 61 6c 20 44 4d 41 20 63 68 61 6e 6e 65 6c 20 30 20 69 73 ┆X 186 internal DMA channel 0 is┆
0x4040…4060 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 74 6f 20 74 72 61 6e 73 66 65 72 20 32 35 36 20 62 79 74 ┆ initialized to transfer 256 byt┆
0x4060…4080 65 73 20 6f 66 20 0a 64 61 74 61 20 74 6f 20 74 68 65 20 4c 43 50 20 63 68 61 6e 6e 65 6c 2e 20 ┆es of data to the LCP channel. ┆
0x4080…40a0 54 68 65 20 4c 43 50 20 74 65 73 74 20 70 72 6f 67 72 61 6d 20 69 73 20 73 74 61 72 74 65 64 20 ┆The LCP test program is started ┆
0x40a0…40c0 62 79 20 0a 77 72 69 74 69 6e 67 20 61 20 63 6f 6d 6d 61 6e 64 20 63 6f 64 65 20 32 20 74 6f 20 ┆by writing a command code 2 to ┆
0x40c0…40e0 74 68 65 20 4c 43 50 20 63 6f 6d 6d 61 6e 64 20 70 6f 72 74 20 28 32 30 34 20 48 65 78 2e 29 2e ┆the LCP command port (204 Hex.).┆
0x40e0…4100 20 54 68 65 20 0a 69 41 50 58 20 31 38 36 20 69 6e 74 65 72 6e 61 6c 20 44 4d 41 20 63 68 61 6e ┆ The iAPX 186 internal DMA chan┆
0x4100…4120 6e 65 6c 20 31 20 69 73 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 61 73 20 74 68 65 20 72 65 63 65 ┆nel 1 is initialized as the rece┆
0x4120…4140 69 76 65 20 0a 63 68 61 6e 6e 65 6c 2c 20 61 6e 64 20 73 69 6e 6b 73 20 74 68 65 20 64 61 74 61 ┆ive channel, and sinks the data┆
0x4140…4160 20 6c 6f 6f 70 65 64 20 62 61 63 6b 20 66 72 6f 6d 20 74 68 65 20 4c 43 50 20 63 68 61 6e 6e 65 ┆ looped back from the LCP channe┆
0x4160…4180 6c 2e 20 54 68 65 20 0a 4c 43 50 20 63 68 61 6e 6e 65 6c 73 20 73 69 67 6e 61 6c 20 77 69 74 68 ┆l. The LCP channels signal with┆
0x4180…41a0 20 61 6e 20 69 6e 74 65 72 72 75 70 74 20 74 6f 20 74 68 65 20 69 41 50 58 20 31 38 36 20 70 72 ┆ an interrupt to the iAPX 186 pr┆
0x41a0…41c0 6f 63 65 73 73 6f 72 20 0a 77 68 65 6e 20 74 68 65 20 74 72 61 6e 73 66 65 72 20 69 73 20 63 6f ┆ocessor when the transfer is co┆
0x41c0…41e0 6d 70 6c 65 74 65 2e 20 54 68 65 20 69 41 50 58 20 31 38 36 20 77 61 69 74 73 20 66 6f 72 20 74 ┆mplete. The iAPX 186 waits for t┆
0x41e0…4200 68 65 20 0a 69 6e 74 65 72 72 75 70 74 20 74 6f 20 6f 63 63 75 72 20 77 69 74 68 69 6e 20 31 20 ┆he interrupt to occur within 1 ┆
0x4200…4220 (33,) 73 65 63 6f 6e 64 2c 20 61 6e 64 20 69 66 20 6e 6f 74 20 61 20 74 69 6d 65 6f 75 74 20 6d 65 73 ┆second, and if not a timeout mes┆
0x4220…4240 73 61 67 65 20 0a 69 73 20 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 22 74 65 73 74 2d 6f 75 ┆sage is written to the "test-ou┆
0x4240…4260 74 70 75 74 22 2e 20 4e 4f 54 45 20 74 68 61 74 20 74 68 69 73 20 74 65 73 74 20 6c 6f 6f 70 73 ┆tput". NOTE that this test loops┆
0x4260…4280 20 74 68 65 20 0a 64 61 74 61 20 62 61 63 6b 20 66 72 6f 6d 20 74 68 65 20 73 65 72 69 61 6c 20 ┆ the data back from the serial ┆
0x4280…42a0 6c 69 6e 65 73 20 61 6c 73 6f 2e 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 6d 61 79 20 67 65 6e 65 ┆lines also. The test may gene┆
0x42a0…42c0 72 61 74 65 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 ┆rate the following error message┆
0x42c0…42e0 73 3a 0d 0a 0d 0a b0 f0 31 2e 20 b0 4c 43 50 20 64 61 74 61 20 74 65 73 74 3a 20 63 6f 6d 6d 61 ┆s: 1. LCP data test: comma┆
0x42e0…4300 6e 64 20 74 69 6d 65 6f 75 74 0d 0a 0d 0a b0 54 68 65 20 4c 69 6e 65 20 43 6f 6e 74 72 6f 6c 20 ┆nd timeout The Line Control ┆
0x4300…4320 50 72 6f 63 65 73 73 6f 72 20 64 69 64 20 6e 6f 74 20 72 65 73 70 6f 6e 64 20 74 6f 20 74 68 65 ┆Processor did not respond to the┆
0x4320…4340 20 63 6f 6d 6d 61 6e 64 2e 20 54 68 65 20 0a 19 80 81 82 73 69 67 6e 61 6c 20 63 61 6c 6c 65 64 ┆ command. The signal called┆
0x4340…4360 20 43 4d 44 41 43 43 45 50 54 20 6f 6e 20 74 68 65 20 38 32 35 35 41 20 70 6f 72 74 20 41 20 62 ┆ CMDACCEPT on the 8255A port A b┆
0x4360…4380 69 74 20 30 20 77 61 73 20 6e 6f 74 20 73 65 74 20 0a 19 80 81 82 77 69 74 68 69 6e 20 31 20 73 ┆it 0 was not set within 1 s┆
0x4380…43a0 65 63 6f 6e 64 2e 0d 0a 0d 0a b0 f0 32 2e 20 b0 4c 43 50 20 64 61 74 61 20 74 65 73 74 3a 20 6d ┆econd. 2. LCP data test: m┆
0x43a0…43c0 69 73 73 69 6e 67 20 74 65 72 6d 69 6e 61 74 65 20 69 6e 74 65 72 72 75 70 74 0d 0a 0d 0a 54 68 ┆issing terminate interrupt Th┆
0x43c0…43e0 65 20 4c 43 50 20 61 63 63 65 70 74 65 64 20 74 68 65 20 63 6f 6d 6d 61 6e 64 2c 20 62 75 74 20 ┆e LCP accepted the command, but ┆
0x43e0…4400 6e 6f 20 74 65 72 6d 69 6e 61 74 65 20 69 6e 74 65 72 72 75 70 74 20 77 61 73 20 0a 67 65 6e 65 ┆no terminate interrupt was gene┆
0x4400…4420 (34,) 72 61 74 65 64 20 77 69 74 69 6e 20 31 20 73 65 63 6f 6e 64 20 61 66 74 65 72 20 74 68 65 20 63 ┆rated witin 1 second after the c┆
0x4420…4440 6f 6d 6d 61 6e 64 20 61 63 63 65 70 74 2e 0d 0a 0d 0a b0 f0 33 2e 20 b0 4c 43 50 20 64 61 74 61 ┆ommand accept. 3. LCP data┆
0x4440…4460 20 74 65 73 74 3a 20 74 72 61 6e 73 66 65 72 20 65 72 72 6f 72 20 20 72 65 63 2e 3a 3c 30 30 72 ┆ test: transfer error rec.:<00r┆
0x4460…4466 72 3e 0d 0a 0d 0a ┆r> ┆
0x4466…4469 FormFeed {
0x4466…4469 0c 82 e8 ┆ ┆
0x4466…4469 }
0x4469…4480 0a 54 68 65 20 4c 43 50 20 74 65 73 74 20 73 74 61 72 74 65 64 20 62 ┆ The LCP test started b┆
0x4480…44a0 79 20 74 68 69 73 20 63 6f 6d 6d 61 6e 64 20 65 6e 74 65 72 65 64 20 61 6e 20 65 72 72 6f 72 20 ┆y this command entered an error ┆
0x44a0…44c0 63 6f 6e 64 69 74 69 6f 6e 2e 0d 0a 54 68 65 20 73 65 63 6f 6e 64 61 72 79 20 65 72 72 6f 72 20 ┆condition. The secondary error ┆
0x44c0…44e0 64 61 74 61 20 69 73 20 69 6e 74 65 72 70 72 65 74 65 64 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a ┆data is interpreted like this: ┆
0x44e0…4500 0d 0a 09 09 30 30 30 31 20 3a 20 54 69 6d 65 6f 75 74 20 2d 20 84 6e 6f 20 63 61 72 72 69 65 72 ┆ 0001 : Timeout - no carrier┆
0x4500…4520 20 64 65 74 65 63 74 65 64 20 77 69 74 68 69 6e 20 35 30 20 0a 19 9f 80 80 6d 69 63 72 6f 73 65 ┆ detected within 50 microse┆
0x4520…4540 63 6f 6e 64 73 2e 0d 0a 0d 0a 09 09 30 30 30 32 20 3a 20 4e 6f 20 43 68 61 72 20 2d 20 84 63 61 ┆conds. 0002 : No Char - ca┆
0x4540…4560 72 72 69 65 72 20 64 65 74 65 63 74 65 64 20 62 75 74 20 6e 6f 20 63 68 61 72 61 63 74 65 72 20 ┆rrier detected but no character ┆
0x4560…4580 0a 19 9f 80 80 72 65 63 65 69 76 65 64 2e 0d 0a 0d 0a 09 09 30 30 30 33 20 3a 20 50 61 72 69 74 ┆ received. 0003 : Parit┆
0x4580…45a0 79 20 20 2d 20 38 32 37 34 20 70 61 72 69 74 79 20 65 72 72 6f 72 2e 0d 0a 0d 0a 09 09 30 30 30 ┆y - 8274 parity error. 000┆
0x45a0…45c0 34 20 3a 20 46 72 61 6d 69 6e 67 20 2d 20 38 32 37 34 20 66 72 61 6d 69 6e 67 20 65 72 72 6f 72 ┆4 : Framing - 8274 framing error┆
0x45c0…45e0 2e 0d 0a 0d 0a b0 f0 34 2e 20 b0 4c 43 50 20 64 61 74 61 20 74 65 73 74 3a 20 64 61 74 61 20 65 ┆. 4. LCP data test: data e┆
0x45e0…4600 72 72 6f 72 20 20 73 65 67 6d 2e 3a 3c 73 73 73 73 3e 20 20 61 64 64 72 2e 3a 3c 61 61 61 61 3e ┆rror segm.:<ssss> addr.:<aaaa>┆
0x4600…4620 (35,) 0d 0a b0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x4620…4640 20 20 20 b0 65 78 70 2e 3a 3c 65 65 65 65 3e 20 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 0d 0a ┆ exp.:<eeee> rec.:<rrrr> ┆
0x4640…4660 b0 54 68 65 20 64 61 74 61 20 72 65 63 65 69 76 65 64 20 77 61 73 20 6e 6f 74 20 74 68 65 20 65 ┆ The data received was not the e┆
0x4660…4680 71 75 61 6c 20 74 6f 20 74 68 65 20 64 61 74 61 20 74 72 61 6e 73 6d 69 74 74 65 64 20 61 73 20 ┆qual to the data transmitted as ┆
0x4680…4694 69 74 20 0a 19 80 81 82 73 68 6f 75 6c 64 20 62 65 2e 0d 0a ┆it should be. ┆
0x4694…4697 FormFeed {
0x4694…4697 0c 81 d8 ┆ ┆
0x4694…4697 }
0x4697…46a0 0a a1 b0 31 32 2e b0 20 54 ┆ 12. T┆
0x46a0…46c0 65 73 74 20 37 f0 20 3d 20 56 2e 32 34 20 4c 49 4e 45 20 31 20 4c 4f 4f 50 42 41 43 4b 20 54 45 ┆est 7 = V.24 LINE 1 LOOPBACK TE┆
0x46c0…46e0 53 54 2e 0d 0a 0d 0a 54 68 69 73 20 69 73 20 61 6e 20 b0 65 78 74 65 6e 64 65 64 f0 20 74 65 73 ┆ST. This is an extended tes┆
0x46e0…4700 74 20 77 68 69 63 68 20 6d 75 73 74 20 62 65 20 72 75 6e 20 77 69 74 68 20 61 20 6c 6f 6f 70 20 ┆t which must be run with a loop ┆
0x4700…4720 62 61 63 6b 20 63 61 62 6c 65 20 0a 19 80 81 80 63 6f 6e 6e 65 63 74 65 64 2e 20 54 68 65 20 6c ┆back cable connected. The l┆
0x4720…4740 6f 6f 70 20 62 61 63 6b 20 69 73 20 6d 61 64 65 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a 20 ┆oop back is made like this: ┆
0x4740…4760 20 2d 2c 54 52 44 31 20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ -,TRD1 ------------------------┆
0x4760…4780 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 20 2d 2c 52 43 44 31 0d 0a 0d 0a 20 20 2d 2c 52 54 53 31 ┆------------- -,RCD1 -,RTS1┆
0x4780…47a0 20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ -------------------------------┆
0x47a0…47c0 2d 2d 2d 2d 2d 2d 20 2d 2c 52 4c 53 44 31 0d 0a 09 09 09 20 20 20 21 0d 0a 09 09 09 20 20 20 2d ┆------ -,RLSD1 ! -┆
0x47c0…47e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 20 2d 2c 52 46 53 31 0d 0a 0d 0a 20 20 2d ┆------------------ -,RFS1 -┆
0x47e0…4800 2c 44 54 52 31 20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆,DTR1 --------------------------┆
0x4800…4820 (36,) 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 20 2d 2c 44 53 52 31 0d 0a 09 09 09 20 20 20 21 0d 0a 09 09 09 ┆----------- -,DSR1 ! ┆
0x4820…4840 20 20 20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 20 2d 2c 43 41 4c 4c 31 0d 0a ┆ ------------------- -,CALL1 ┆
0x4840…4860 0d 0a 54 68 69 73 20 74 65 73 74 20 6d 61 6b 65 73 20 61 20 64 61 74 61 20 74 72 61 6e 73 70 6f ┆ This test makes a data transpo┆
0x4860…4880 72 74 20 6f 66 20 38 20 4b 62 79 74 65 73 20 6f 66 20 64 61 74 61 20 66 72 6f 6d 20 61 20 0a 73 ┆rt of 8 Kbytes of data from a s┆
0x4880…48a0 6f 75 72 63 65 20 62 75 66 66 65 72 20 74 6f 20 61 20 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 ┆ource buffer to a destination bu┆
0x48a0…48c0 66 66 65 72 20 74 72 6f 75 67 68 20 74 68 65 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 2e ┆ffer trough the loop back cable.┆
0x48c0…48e0 20 0a 57 68 65 6e 20 74 68 65 20 74 72 61 6e 73 70 6f 72 74 20 69 73 20 63 6f 6d 70 6c 65 74 65 ┆ When the transport is complete┆
0x48e0…4900 20 74 68 65 20 73 6f 75 63 65 20 61 6e 64 20 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 66 66 65 ┆ the souce and destination buffe┆
0x4900…4920 72 20 0a 69 73 20 63 6f 6d 70 61 72 65 64 2c 20 61 6e 64 20 69 66 20 6e 6f 74 20 65 71 75 61 6c ┆r is compared, and if not equal┆
0x4920…4940 20 61 6e 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 2e 0d ┆ an error message is generated. ┆
0x4940…4960 0a 0d 0a 42 65 66 6f 72 65 20 74 68 65 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 74 61 6b ┆ Before the data transport tak┆
0x4960…4980 65 73 20 70 6c 61 63 65 20 74 68 65 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 73 20 61 72 65 20 ┆es place the status signals are ┆
0x4980…49a0 0a 76 65 72 69 66 69 65 64 2e 20 49 66 20 61 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 20 65 72 ┆ verified. If a status signal er┆
0x49a0…49c0 72 6f 72 20 69 73 20 64 69 73 63 6f 76 65 72 65 64 20 61 6e 20 65 72 72 6f 72 20 6d 65 73 73 61 ┆ror is discovered an error messa┆
0x49c0…49e0 67 65 20 0a 6c 69 6b 65 20 74 68 69 73 20 69 73 20 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 ┆ge like this is written to the ┆
0x49e0…4a00 63 6f 6e 73 6f 6c 65 2e 0d 0a 0d 0a b0 f0 31 2e 20 b0 4c 69 6e 65 20 31 20 74 65 73 74 3a 20 56 ┆console. 1. Line 1 test: V┆
0x4a00…4a20 (37,) 2e 32 34 20 73 74 61 74 75 73 20 65 72 72 6f 72 20 20 65 78 70 2e 3a 3c 30 30 30 65 3e 20 20 72 ┆.24 status error exp.:<000e> r┆
0x4a20…4a40 65 63 2e 3a 3c 30 30 30 72 3e 0d 0a 0d 0a 4f 6e 6c 79 20 74 68 65 20 66 6f 75 72 20 6c 65 61 73 ┆ec.:<000r> Only the four leas┆
0x4a40…4a60 74 20 73 69 67 6e 69 66 69 63 61 6e 74 20 62 69 74 73 20 6f 66 20 74 68 65 20 73 65 63 6f 6e 64 ┆t significant bits of the second┆
0x4a60…4a80 61 72 79 20 65 72 72 6f 72 20 64 61 74 61 20 0a 61 72 65 20 76 61 6c 69 64 2c 20 61 6e 64 20 65 ┆ary error data are valid, and e┆
0x4a80…4aa0 61 63 68 20 62 69 74 20 63 6f 72 72 65 73 70 6f 6e 64 73 20 74 6f 20 61 20 73 74 61 74 75 73 20 ┆ach bit corresponds to a status ┆
0x4aa0…4ac0 73 69 67 6e 61 6c 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a 42 69 74 20 30 20 3d 20 43 44 20 ┆signal like this: Bit 0 = CD ┆
0x4ac0…4ae0 2c 20 42 69 74 20 31 20 3d 20 43 54 53 20 2c 20 42 69 74 20 32 20 3d 20 44 53 52 20 2c 20 42 69 ┆, Bit 1 = CTS , Bit 2 = DSR , Bi┆
0x4ae0…4b00 74 20 33 20 3d 20 43 41 4c 4c 0d 0a 0d 0a 4f 74 68 65 72 20 65 72 72 6f 72 20 6d 65 73 73 61 67 ┆t 3 = CALL Other error messag┆
0x4b00…4b1a 65 73 20 66 72 6f 6d 20 74 68 69 73 20 74 65 73 74 20 61 72 65 3a 0d 0a 0d 0a ┆es from this test are: ┆
0x4b1a…4b1d FormFeed {
0x4b1a…4b1d 0c 83 8c ┆ ┆
0x4b1a…4b1d }
0x4b1d…4b20 0a 32 2e ┆ 2.┆
0x4b20…4b40 20 b0 4c 69 6e 65 20 31 20 74 65 73 74 3a 20 74 72 61 6e 73 66 65 72 20 74 69 6d 65 6f 75 74 0d ┆ Line 1 test: transfer timeout ┆
0x4b40…4b60 0a 0d 0a 54 68 65 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 64 69 64 20 6e 6f 74 20 63 6f ┆ The data transport did not co┆
0x4b60…4b80 6d 70 6c 65 74 65 20 77 69 74 68 69 6e 20 32 30 20 73 65 63 6f 6e 64 73 2e 0d 0a 0d 0a 33 2e 20 ┆mplete within 20 seconds. 3. ┆
0x4b80…4ba0 b0 4c 69 6e 65 20 31 20 74 65 73 74 3a 20 70 61 72 69 74 79 20 65 72 72 6f 72 0d 0a 0d 0a 54 68 ┆ Line 1 test: parity error Th┆
0x4ba0…4bc0 65 20 38 32 37 34 20 64 69 73 63 6f 76 65 72 65 64 20 61 20 70 61 72 69 74 79 20 65 72 72 6f 72 ┆e 8274 discovered a parity error┆
0x4bc0…4be0 2e 0d 0a 0d 0a 34 2e 20 b0 4c 69 6e 65 20 31 20 74 65 73 74 3a 20 64 61 74 61 20 65 72 72 6f 72 ┆. 4. Line 1 test: data error┆
0x4be0…4c00 20 20 73 65 67 6d 2e 3a 3c 73 73 73 73 3e 20 20 61 64 64 72 2e 3a 3c 61 61 61 61 3e 0d 0a 19 80 ┆ segm.:<ssss> addr.:<aaaa> ┆
0x4c00…4c20 (38,) 81 82 09 09 09 20 20 20 20 20 20 b0 65 78 70 2e 3a 3c 65 65 65 65 3e 20 20 72 65 63 2e 3a 3c 72 ┆ exp.:<eeee> rec.:<r┆
0x4c20…4c40 72 72 72 3e 0d 0a 0d 0a 54 68 65 20 72 65 63 65 69 76 65 20 62 75 66 66 65 72 20 69 73 20 6e 6f ┆rrr> The receive buffer is no┆
0x4c40…4c60 74 20 65 71 75 61 6c 20 74 6f 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 62 75 66 66 65 72 20 61 ┆t equal to the transmit buffer a┆
0x4c60…4c80 73 20 69 74 20 0a 73 68 6f 75 6c 64 20 62 65 2e 0a 0d 0a 54 68 65 20 6c 6f 6f 70 20 62 61 63 6b ┆s it should be. The loop back┆
0x4c80…4ca0 20 63 61 62 6c 65 73 20 68 61 76 65 20 67 6f 74 20 74 68 65 20 52 43 20 70 61 72 74 20 6e 75 6d ┆ cables have got the RC part num┆
0x4ca0…4cc0 62 65 72 20 b0 4b 42 4c 20 36 33 30 f0 20 61 6e 64 20 0a 19 80 81 80 69 6e 74 65 72 66 61 63 65 ┆ber KBL 630 and interface┆
0x4cc0…4ce0 73 20 64 69 72 65 63 74 20 74 6f 20 74 68 65 20 61 64 61 70 74 65 72 20 63 61 62 6c 65 20 4b 42 ┆s direct to the adapter cable KB┆
0x4ce0…4d00 4c 20 35 39 31 2e 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 69 73 20 72 75 6e 20 61 74 20 61 70 70 ┆L 591. The test is run at app┆
0x4d00…4d0e 2e 20 34 38 30 30 20 62 61 75 64 2e 0d 0a ┆. 4800 baud. ┆
0x4d0e…4d11 FormFeed {
0x4d0e…4d11 0c 81 d8 ┆ ┆
0x4d0e…4d11 }
0x4d11…4d20 0a a1 b0 31 33 2e 20 b0 54 65 73 74 20 37 f0 ┆ 13. Test 7 ┆
0x4d20…4d40 20 3d 20 56 2e 32 34 20 4c 49 4e 45 20 32 20 4c 4f 4f 50 42 41 43 4b 20 54 45 53 54 2e 0d 0a 0d ┆ = V.24 LINE 2 LOOPBACK TEST. ┆
0x4d40…4d60 0a 54 68 69 73 20 69 73 20 61 6e 20 b0 65 78 74 65 6e 64 65 64 f0 20 74 65 73 74 20 77 68 69 63 ┆ This is an extended test whic┆
0x4d60…4d80 68 20 6d 75 73 74 20 62 65 20 72 75 6e 20 77 69 74 68 20 61 20 6c 6f 6f 70 20 62 61 63 6b 20 63 ┆h must be run with a loop back c┆
0x4d80…4da0 61 62 6c 65 20 0a 19 80 81 80 63 6f 6e 6e 65 63 74 65 64 2e 20 54 68 65 20 6c 6f 6f 70 20 62 61 ┆able connected. The loop ba┆
0x4da0…4dc0 63 6b 20 69 73 20 6d 61 64 65 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a 20 20 2d 2c 54 52 44 ┆ck is made like this: -,TRD┆
0x4dc0…4de0 32 20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆2 ------------------------------┆
0x4de0…4e00 2d 2d 2d 2d 2d 2d 2d 20 2d 2c 52 43 44 32 0d 0a 0d 0a 20 20 2d 2c 52 54 53 32 20 2d 2d 2d 2d 2d ┆------- -,RCD2 -,RTS2 -----┆
0x4e00…4e20 (39,) 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x4e20…4e40 20 2d 2c 52 4c 53 44 32 0d 0a 09 09 09 20 20 20 21 0d 0a 09 09 09 20 20 20 2d 2d 2d 2d 2d 2d 2d ┆ -,RLSD2 ! -------┆
0x4e40…4e60 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 20 2d 2c 52 46 53 32 0d 0a 0d 0a 20 20 2d 2c 44 54 52 32 20 ┆------------ -,RFS2 -,DTR2 ┆
0x4e60…4e80 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x4e80…4ea0 2d 2d 2d 2d 2d 20 2d 2c 44 53 52 32 0d 0a 09 09 09 20 20 20 21 0d 0a 09 09 09 20 20 20 2d 2d 2d ┆----- -,DSR2 ! ---┆
0x4ea0…4ec0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 20 2d 2c 43 41 4c 4c 32 0d 0a 0d 0a 54 68 69 73 ┆---------------- -,CALL2 This┆
0x4ec0…4ee0 20 74 65 73 74 20 6d 61 6b 65 73 20 61 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 6f 66 20 ┆ test makes a data transport of ┆
0x4ee0…4f00 38 20 4b 62 79 74 65 73 20 6f 66 20 64 61 74 61 20 66 72 6f 6d 20 61 20 0a 73 6f 75 72 63 65 20 ┆8 Kbytes of data from a source ┆
0x4f00…4f20 62 75 66 66 65 72 20 74 6f 20 61 20 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 66 66 65 72 20 74 ┆buffer to a destination buffer t┆
0x4f20…4f40 72 6f 75 67 68 20 74 68 65 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 2e 20 0a 57 68 65 6e ┆rough the loop back cable. When┆
0x4f40…4f60 20 74 68 65 20 74 72 61 6e 73 70 6f 72 74 20 69 73 20 63 6f 6d 70 6c 65 74 65 20 74 68 65 20 73 ┆ the transport is complete the s┆
0x4f60…4f80 6f 75 63 65 20 61 6e 64 20 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 66 66 65 72 20 0a 69 73 20 ┆ouce and destination buffer is ┆
0x4f80…4fa0 63 6f 6d 70 61 72 65 64 2c 20 61 6e 64 20 69 66 20 6e 6f 74 20 65 71 75 61 6c 20 61 6e 20 65 72 ┆compared, and if not equal an er┆
0x4fa0…4fc0 72 6f 72 20 6d 65 73 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 2e 0d 0a 0d 0a 42 65 66 ┆ror message is generated. Bef┆
0x4fc0…4fe0 6f 72 65 20 74 68 65 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 74 61 6b 65 73 20 70 6c 61 ┆ore the data transport takes pla┆
0x4fe0…5000 63 65 20 74 68 65 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 73 20 61 72 65 20 0a 76 65 72 69 66 ┆ce the status signals are verif┆
0x5000…5020 (40,) 69 65 64 2e 20 49 66 20 61 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 20 65 72 72 6f 72 20 69 73 ┆ied. If a status signal error is┆
0x5020…5040 20 64 69 73 63 6f 76 65 72 65 64 20 61 6e 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 0a 6c 69 ┆ discovered an error message li┆
0x5040…5060 6b 65 20 74 68 69 73 20 69 73 20 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 63 6f 6e 73 6f 6c ┆ke this is written to the consol┆
0x5060…5080 65 2e 0d 0a 0d 0a b0 f0 31 2e 20 b0 4c 69 6e 65 20 32 20 74 65 73 74 3a 20 56 2e 32 34 20 73 74 ┆e. 1. Line 2 test: V.24 st┆
0x5080…50a0 61 74 75 73 20 65 72 72 6f 72 20 20 65 78 70 2e 3a 3c 30 30 30 65 3e 20 20 72 65 63 2e 3a 3c 30 ┆atus error exp.:<000e> rec.:<0┆
0x50a0…50c0 30 30 72 3e 0d 0a 0d 0a 4f 6e 6c 79 20 74 68 65 20 66 6f 75 72 20 6c 65 61 73 74 20 73 69 67 6e ┆00r> Only the four least sign┆
0x50c0…50e0 69 66 69 63 61 6e 74 20 62 69 74 73 20 6f 66 20 74 68 65 20 73 65 63 6f 6e 64 61 72 79 20 65 72 ┆ificant bits of the secondary er┆
0x50e0…5100 72 6f 72 20 64 61 74 61 20 0a 61 72 65 20 76 61 6c 69 64 2c 20 61 6e 64 20 65 61 63 68 20 62 69 ┆ror data are valid, and each bi┆
0x5100…5120 74 20 63 6f 72 72 65 73 70 6f 6e 64 73 20 74 6f 20 61 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c ┆t corresponds to a status signal┆
0x5120…5140 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a 42 69 74 20 30 20 3d 20 43 44 20 2c 20 42 69 74 20 ┆ like this: Bit 0 = CD , Bit ┆
0x5140…5160 31 20 3d 20 43 54 53 20 2c 20 42 69 74 20 32 20 3d 20 44 53 52 20 2c 20 42 69 74 20 33 20 3d 20 ┆1 = CTS , Bit 2 = DSR , Bit 3 = ┆
0x5160…5180 43 41 4c 4c 0d 0a 0d 0a 4f 74 68 65 72 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 73 20 66 72 6f ┆CALL Other error messages fro┆
0x5180…5194 6d 20 74 68 69 73 20 74 65 73 74 20 61 72 65 3a 0d 0a 0d 0a ┆m this test are: ┆
0x5194…5197 FormFeed {
0x5194…5197 0c 83 8c ┆ ┆
0x5194…5197 }
0x5197…51a0 0a 32 2e 20 b0 4c 69 6e 65 ┆ 2. Line┆
0x51a0…51c0 20 32 20 74 65 73 74 3a 20 74 72 61 6e 73 66 65 72 20 74 69 6d 65 6f 75 74 0d 0a 0d 0a 54 68 65 ┆ 2 test: transfer timeout The┆
0x51c0…51e0 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 64 69 64 20 6e 6f 74 20 63 6f 6d 70 6c 65 74 65 ┆ data transport did not complete┆
0x51e0…5200 20 77 69 74 68 69 6e 20 32 30 20 73 65 63 6f 6e 64 73 2e 0d 0a 0d 0a 33 2e 20 b0 4c 69 6e 65 20 ┆ within 20 seconds. 3. Line ┆
0x5200…5220 (41,) 32 20 74 65 73 74 3a 20 70 61 72 69 74 79 20 65 72 72 6f 72 0d 0a 0d 0a 54 68 65 20 38 32 37 34 ┆2 test: parity error The 8274┆
0x5220…5240 20 64 69 73 63 6f 76 65 72 65 64 20 61 20 70 61 72 69 74 79 20 65 72 72 6f 72 2e 0d 0a 0d 0a 34 ┆ discovered a parity error. 4┆
0x5240…5260 2e 20 b0 4c 69 6e 65 20 32 20 74 65 73 74 3a 20 64 61 74 61 20 65 72 72 6f 72 20 20 73 65 67 6d ┆. Line 2 test: data error segm┆
0x5260…5280 2e 3a 3c 73 73 73 73 3e 20 20 61 64 64 72 2e 3a 3c 61 61 61 61 3e 0d 0a 19 80 81 82 09 09 09 20 ┆.:<ssss> addr.:<aaaa> ┆
0x5280…52a0 20 20 20 20 20 b0 65 78 70 2e 3a 3c 65 65 65 65 3e 20 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a ┆ exp.:<eeee> rec.:<rrrr> ┆
0x52a0…52c0 0d 0a 54 68 65 20 72 65 63 65 69 76 65 20 62 75 66 66 65 72 20 69 73 20 6e 6f 74 20 65 71 75 61 ┆ The receive buffer is not equa┆
0x52c0…52e0 6c 20 74 6f 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 62 75 66 66 65 72 20 61 73 20 69 74 20 0a ┆l to the transmit buffer as it ┆
0x52e0…5300 73 68 6f 75 6c 64 20 62 65 2e 0d 0a 0d 0a 54 68 65 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c ┆should be. The loop back cabl┆
0x5300…5320 65 73 20 68 61 76 65 20 67 6f 74 20 74 68 65 20 52 43 20 70 61 72 74 20 6e 75 6d 62 65 72 20 b0 ┆es have got the RC part number ┆
0x5320…5340 4b 42 4c 20 36 33 30 f0 20 61 6e 64 20 0a 19 80 81 80 69 6e 74 65 72 66 61 63 65 73 20 64 69 72 ┆KBL 630 and interfaces dir┆
0x5340…5360 65 63 74 20 74 6f 20 74 68 65 20 61 64 61 70 74 65 72 20 63 61 62 6c 65 20 4b 42 4c 20 35 39 31 ┆ect to the adapter cable KBL 591┆
0x5360…5380 2e 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 69 73 20 72 75 6e 20 61 74 20 61 70 70 2e 20 34 38 30 ┆. The test is run at app. 480┆
0x5380…5389 30 20 62 61 75 64 2e 0d 0a ┆0 baud. ┆
0x5389…538c FormFeed {
0x5389…538c 0c 81 d8 ┆ ┆
0x5389…538c }
0x538c…53a0 0a a1 b0 31 34 2e 20 b0 54 65 73 74 20 38 f0 20 3d 20 56 2e ┆ 14. Test 8 = V.┆
0x53a0…53c0 32 34 20 4c 49 4e 45 20 33 20 4c 4f 4f 50 42 41 43 4b 20 54 45 53 54 2e 0d 0a 0d 0a 54 68 69 73 ┆24 LINE 3 LOOPBACK TEST. This┆
0x53c0…53e0 20 69 73 20 61 6e 20 b0 65 78 74 65 6e 64 65 64 f0 20 74 65 73 74 20 77 68 69 63 68 20 6d 75 73 ┆ is an extended test which mus┆
0x53e0…5400 74 20 62 65 20 72 75 6e 20 77 69 74 68 20 61 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 20 ┆t be run with a loop back cable ┆
0x5400…5420 (42,) 0a 19 80 81 80 63 6f 6e 6e 65 63 74 65 64 2e 20 54 68 65 20 6c 6f 6f 70 20 62 61 63 6b 20 69 73 ┆ connected. The loop back is┆
0x5420…5440 20 6d 61 64 65 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a 20 20 2d 2c 54 52 44 33 20 2d 2d 2d ┆ made like this: -,TRD3 ---┆
0x5440…5460 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x5460…5480 2d 2d 20 2d 2c 52 43 44 33 0d 0a 0d 0a 20 20 2d 2c 52 54 53 33 20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆-- -,RCD3 -,RTS3 ----------┆
0x5480…54a0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 20 2d 2c 52 4c ┆--------------------------- -,RL┆
0x54a0…54c0 53 44 33 0d 0a 09 09 09 20 20 20 21 0d 0a 09 09 09 20 20 20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆SD3 ! ------------┆
0x54c0…54e0 2d 2d 2d 2d 2d 2d 2d 20 2d 2c 52 46 53 33 0d 0a 0d 0a 20 20 2d 2c 44 54 52 33 20 2d 2d 2d 2d 2d ┆------- -,RFS3 -,DTR3 -----┆
0x54e0…5500 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x5500…5520 20 2d 2c 44 53 52 33 0d 0a 09 09 09 20 20 20 21 0d 0a 09 09 09 20 20 20 2d 2d 2d 2d 2d 2d 2d 2d ┆ -,DSR3 ! --------┆
0x5520…5540 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 20 2d 2c 43 41 4c 4c 33 0d 0a 0d 0a 54 68 69 73 20 74 65 73 74 ┆----------- -,CALL3 This test┆
0x5540…5560 20 6d 61 6b 65 73 20 61 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 6f 66 20 38 20 4b 62 79 ┆ makes a data transport of 8 Kby┆
0x5560…5580 74 65 73 20 6f 66 20 64 61 74 61 20 66 72 6f 6d 20 61 20 0a 73 6f 75 72 63 65 20 62 75 66 66 65 ┆tes of data from a source buffe┆
0x5580…55a0 72 20 74 6f 20 61 20 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 66 66 65 72 20 74 72 6f 75 67 68 ┆r to a destination buffer trough┆
0x55a0…55c0 20 74 68 65 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 2e 20 0a 57 68 65 6e 20 74 68 65 20 ┆ the loop back cable. When the ┆
0x55c0…55e0 74 72 61 6e 73 70 6f 72 74 20 69 73 20 63 6f 6d 70 6c 65 74 65 20 74 68 65 20 73 6f 75 63 65 20 ┆transport is complete the souce ┆
0x55e0…5600 61 6e 64 20 64 65 73 74 69 6e 61 74 69 6f 6e 20 62 75 66 66 65 72 20 0a 69 73 20 63 6f 6d 70 61 ┆and destination buffer is compa┆
0x5600…5620 (43,) 72 65 64 2c 20 61 6e 64 20 69 66 20 6e 6f 74 20 65 71 75 61 6c 20 61 6e 20 65 72 72 6f 72 20 6d ┆red, and if not equal an error m┆
0x5620…5640 65 73 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 2e 0d 0a 0d 0a 42 65 66 6f 72 65 20 74 ┆essage is generated. Before t┆
0x5640…5660 68 65 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 74 61 6b 65 73 20 70 6c 61 63 65 20 74 68 ┆he data transport takes place th┆
0x5660…5680 65 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 73 20 61 72 65 20 0a 76 65 72 69 66 69 65 64 2e 20 ┆e status signals are verified. ┆
0x5680…56a0 49 66 20 61 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 20 65 72 72 6f 72 20 69 73 20 64 69 73 63 ┆If a status signal error is disc┆
0x56a0…56c0 6f 76 65 72 65 64 20 61 6e 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 0a 6c 69 6b 65 20 74 68 ┆overed an error message like th┆
0x56c0…56e0 69 73 20 69 73 20 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 63 6f 6e 73 6f 6c 65 2e 0d 0a 0d ┆is is written to the console. ┆
0x56e0…5700 0a b0 f0 31 2e 20 b0 4c 69 6e 65 20 33 20 74 65 73 74 3a 20 56 2e 32 34 20 73 74 61 74 75 73 20 ┆ 1. Line 3 test: V.24 status ┆
0x5700…5720 65 72 72 6f 72 20 20 65 78 70 2e 3a 3c 30 30 30 65 3e 20 20 72 65 63 2e 3a 3c 30 30 30 72 3e 0d ┆error exp.:<000e> rec.:<000r> ┆
0x5720…5740 0a 0d 0a 4f 6e 6c 79 20 74 68 65 20 66 6f 75 72 20 6c 65 61 73 74 20 73 69 67 6e 69 66 69 63 61 ┆ Only the four least significa┆
0x5740…5760 6e 74 20 62 69 74 73 20 6f 66 20 74 68 65 20 73 65 63 6f 6e 64 61 72 79 20 65 72 72 6f 72 20 64 ┆nt bits of the secondary error d┆
0x5760…5780 61 74 61 20 0a 61 72 65 20 76 61 6c 69 64 2c 20 61 6e 64 20 65 61 63 68 20 62 69 74 20 63 6f 72 ┆ata are valid, and each bit cor┆
0x5780…57a0 72 65 73 70 6f 6e 64 73 20 74 6f 20 61 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 20 6c 69 6b 65 ┆responds to a status signal like┆
0x57a0…57c0 20 74 68 69 73 3a 0d 0a 0d 0a 42 69 74 20 30 20 3d 20 43 44 20 2c 20 42 69 74 20 31 20 3d 20 43 ┆ this: Bit 0 = CD , Bit 1 = C┆
0x57c0…57e0 54 53 20 2c 20 42 69 74 20 32 20 3d 20 44 53 52 20 2c 20 42 69 74 20 33 20 3d 20 43 41 4c 4c 0d ┆TS , Bit 2 = DSR , Bit 3 = CALL ┆
0x57e0…5800 0a 0d 0a 4f 74 68 65 72 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 73 20 66 72 6f 6d 20 74 68 69 ┆ Other error messages from thi┆
0x5800…580f (44,) 73 20 74 65 73 74 20 61 72 65 3a 0d 0a 0d 0a ┆s test are: ┆
0x580f…5812 FormFeed {
0x580f…5812 0c 83 8c ┆ ┆
0x580f…5812 }
0x5812…5820 0a 32 2e 20 b0 4c 69 6e 65 20 33 20 74 65 ┆ 2. Line 3 te┆
0x5820…5840 73 74 3a 20 74 72 61 6e 73 66 65 72 20 74 69 6d 65 6f 75 74 0d 0a 0d 0a 54 68 65 20 64 61 74 61 ┆st: transfer timeout The data┆
0x5840…5860 20 74 72 61 6e 73 70 6f 72 74 20 64 69 64 20 6e 6f 74 20 63 6f 6d 70 6c 65 74 65 20 77 69 74 68 ┆ transport did not complete with┆
0x5860…5880 69 6e 20 32 30 20 73 65 63 6f 6e 64 73 2e 0d 0a 0d 0a 33 2e 20 b0 4c 69 6e 65 20 33 20 74 65 73 ┆in 20 seconds. 3. Line 3 tes┆
0x5880…58a0 74 3a 20 70 61 72 69 74 79 20 65 72 72 6f 72 0d 0a 0d 0a 54 68 65 20 38 32 37 34 20 64 69 73 63 ┆t: parity error The 8274 disc┆
0x58a0…58c0 6f 76 65 72 65 64 20 61 20 70 61 72 69 74 79 20 65 72 72 6f 72 2e 0d 0a 0d 0a 34 2e 20 b0 4c 69 ┆overed a parity error. 4. Li┆
0x58c0…58e0 6e 65 20 33 20 74 65 73 74 3a 20 64 61 74 61 20 65 72 72 6f 72 20 20 73 65 67 6d 2e 3a 3c 73 73 ┆ne 3 test: data error segm.:<ss┆
0x58e0…5900 73 73 3e 20 20 61 64 64 72 2e 3a 3c 61 61 61 61 3e 0d 0a 19 80 81 82 09 09 09 20 20 20 20 20 20 ┆ss> addr.:<aaaa> ┆
0x5900…5920 b0 65 78 70 2e 3a 3c 65 65 65 65 3e 20 20 72 65 63 2e 3a 3c 72 72 72 72 3e 0d 0a 0d 0a 54 68 65 ┆ exp.:<eeee> rec.:<rrrr> The┆
0x5920…5940 20 72 65 63 65 69 76 65 20 62 75 66 66 65 72 20 69 73 20 6e 6f 74 20 65 71 75 61 6c 20 74 6f 20 ┆ receive buffer is not equal to ┆
0x5940…5960 74 68 65 20 74 72 61 6e 73 6d 69 74 20 62 75 66 66 65 72 20 61 73 20 69 74 20 0a 73 68 6f 75 6c ┆the transmit buffer as it shoul┆
0x5960…5980 64 20 62 65 2e 0d 0a 0d 0a 54 68 65 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 73 20 68 61 ┆d be. The loop back cables ha┆
0x5980…59a0 76 65 20 67 6f 74 20 74 68 65 20 52 43 20 70 61 72 74 20 6e 75 6d 62 65 72 20 b0 4b 42 4c 20 36 ┆ve got the RC part number KBL 6┆
0x59a0…59c0 33 30 f0 20 61 6e 64 20 0a 19 80 81 80 69 6e 74 65 72 66 61 63 65 73 20 64 69 72 65 63 74 20 74 ┆30 and interfaces direct t┆
0x59c0…59e0 6f 20 74 68 65 20 61 64 61 70 74 65 72 20 63 61 62 6c 65 20 4b 42 4c 20 35 39 31 2e 0d 0a 0d 0a ┆o the adapter cable KBL 591. ┆
0x59e0…5a00 54 68 65 20 74 65 73 74 20 69 73 20 72 75 6e 20 61 74 20 61 70 70 2e 20 34 38 30 30 20 62 61 75 ┆The test is run at app. 4800 bau┆
0x5a00…5a04 (45,) 64 2e 0d 0a ┆d. ┆
0x5a04…5a07 FormFeed {
0x5a04…5a07 0c 81 d8 ┆ ┆
0x5a04…5a07 }
0x5a07…5a20 0a a1 b0 31 35 2e 20 4c 45 44 20 4f 55 54 50 55 54 2e 0d 0a 0d 0a 44 75 72 ┆ 15. LED OUTPUT. Dur┆
0x5a20…5a40 69 6e 67 20 74 68 65 20 73 65 6c 66 74 65 73 74 20 74 68 65 20 74 65 73 74 20 6e 75 6d 62 65 72 ┆ing the selftest the test number┆
0x5a40…5a60 73 20 61 72 65 20 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 66 6f 75 72 20 6f 6e 2d 0a 62 6f ┆s are written to the four on- bo┆
0x5a60…5a80 61 72 64 20 6c 69 67 68 74 20 65 6d 69 74 74 69 6e 67 20 64 69 6f 64 65 73 20 28 4c 45 44 27 73 ┆ard light emitting diodes (LED's┆
0x5a80…5aa0 29 2c 20 61 6e 64 20 69 66 20 61 6e 20 65 72 72 6f 72 20 6f 63 63 75 72 20 74 68 65 20 0a 74 65 ┆), and if an error occur the te┆
0x5aa0…5ac0 73 74 20 69 73 20 68 61 6c 74 65 64 2c 20 61 6e 64 20 74 68 65 20 74 65 73 74 20 6e 75 6d 62 65 ┆st is halted, and the test numbe┆
0x5ac0…5ae0 72 20 6f 6e 20 74 68 65 20 4c 45 44 27 73 20 77 69 6c 6c 20 62 65 20 0a 66 6c 61 73 68 69 6e 67 ┆r on the LED's will be flashing┆
0x5ae0…5ae3 2e 0d 0a ┆. ┆
0x5ae3…5ae6 FormFeed {
0x5ae3…5ae6 0c 80 c8 ┆ ┆
0x5ae3…5ae6 }
0x5ae6…5ae9 0a 0d 0a ┆ ┆
0x5ae9…5aec FormFeed {
0x5ae9…5aec 0c 80 8c ┆ ┆
0x5ae9…5aec }
0x5aec…5b00 0a a1 b0 41 2e 20 52 45 46 45 52 45 4e 43 45 53 0d 0a 0d 0a ┆ A. REFERENCES ┆
0x5b00…5b20 28 31 29 20 20 20 52 43 53 4c 2e 20 39 39 31 20 31 30 30 39 32 0d 0a 20 20 20 20 20 20 52 43 20 ┆(1) RCSL. 991 10092 RC ┆
0x5b20…5b40 33 39 20 53 65 6c 66 74 65 73 74 20 43 6f 6e 63 65 70 74 2c 20 0d 0a 20 20 20 20 20 20 55 73 65 ┆39 Selftest Concept, Use┆
0x5b40…5b60 72 27 73 20 6d 61 6e 75 61 6c 20 09 20 20 20 20 20 0d 0a 0d 0a 28 32 29 20 20 20 52 43 53 4c 2e ┆r's manual (2) RCSL.┆
0x5b60…5b80 20 39 39 31 20 31 30 30 39 36 0d 0a 20 20 20 20 20 20 52 43 20 33 39 33 31 20 45 54 43 36 31 31 ┆ 991 10096 RC 3931 ETC611┆
0x5b80…5ba0 20 68 61 72 64 77 61 72 65 20 73 65 6c 66 74 65 73 74 2c 20 0d 0a 20 20 20 20 20 20 55 73 65 72 ┆ hardware selftest, User┆
0x5ba0…5bc0 27 73 20 6d 61 6e 75 61 6c 20 20 0d 0a 0d 0a 28 33 29 20 20 20 52 43 53 4c 2e 20 39 39 31 20 31 ┆'s manual (3) RCSL. 991 1┆
0x5bc0…5be0 30 30 39 37 0d 0a 20 20 20 20 20 20 46 36 34 31 20 43 4f 4d 20 36 30 31 20 68 61 72 64 77 61 72 ┆0097 F641 COM 601 hardwar┆
0x5be0…5c00 65 20 73 65 6c 66 74 65 73 74 2c 20 0d 0a 20 20 20 20 20 20 55 73 65 72 27 73 20 6d 61 6e 75 61 ┆e selftest, User's manua┆
0x5c00…5c20 (46,) 6c 20 20 20 20 0d 0a 0d 0a 28 34 29 20 20 20 52 43 53 4c 2e 20 39 39 31 20 31 30 30 39 34 0d 0a ┆l (4) RCSL. 991 10094 ┆
0x5c20…5c40 20 20 20 20 20 20 52 43 33 39 30 32 20 68 61 72 64 77 61 72 65 20 73 65 6c 66 74 65 73 74 2c 20 ┆ RC3902 hardware selftest, ┆
0x5c40…5c60 0d 0a 20 20 20 20 20 20 55 73 65 72 27 73 20 6d 61 6e 75 61 6c 09 20 20 20 20 20 0d 0a 0d 0a 28 ┆ User's manual (┆
0x5c60…5c80 35 29 20 20 20 52 43 53 4c 2e 20 39 39 31 20 31 30 31 33 34 0d 0a 20 20 20 20 20 20 52 43 33 39 ┆5) RCSL. 991 10134 RC39┆
0x5c80…5ca0 20 6d 6f 6e 69 74 6f 72 20 38 30 38 36 20 76 65 72 73 69 6f 6e 2c 20 0d 0a 20 20 20 20 20 20 52 ┆ monitor 8086 version, R┆
0x5ca0…5cc0 65 66 65 72 65 6e 63 65 20 6d 61 6e 75 61 6c 09 20 20 20 20 20 0d 0a 0d 0a 28 36 29 20 20 20 52 ┆eference manual (6) R┆
0x5cc0…5ce0 43 53 4c 2e 20 39 39 31 20 31 30 30 39 33 0d 0a 20 20 20 20 20 20 52 43 33 39 20 6d 6f 6e 69 74 ┆CSL. 991 10093 RC39 monit┆
0x5ce0…5d00 6f 72 20 38 30 32 38 36 20 76 65 72 73 69 6f 6e 2c 20 0d 0a 20 20 20 20 20 20 52 65 66 65 72 65 ┆or 80286 version, Refere┆
0x5d00…5d11 6e 63 65 20 6d 61 6e 75 61 6c 20 20 20 20 20 0d 0a ┆nce manual ┆
0x5d11…5d14 FormFeed {
0x5d11…5d14 0c 82 ac ┆ ┆
0x5d11…5d14 }
0x5d14…5d20 0a 0d 0a 05 0a 1a 1a 69 67 6e 61 6c ┆ ignal┆
0x5d20…5d40 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a 42 69 74 20 30 20 3d 20 43 44 20 2c 20 42 69 74 20 ┆ like this: Bit 0 = CD , Bit ┆
0x5d40…5d60 31 20 3d 20 43 54 53 20 2c 20 42 69 74 20 32 20 3d 20 44 53 52 20 2c 20 42 69 74 20 33 20 3d 20 ┆1 = CTS , Bit 2 = DSR , Bit 3 = ┆
0x5d60…5d80 43 41 4c 4c 0d 0a 0d 0a 4f 74 68 65 72 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 73 20 66 72 6f ┆CALL Other error messages fro┆