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Length: 47616 (0xba00)
Types: RcTekst
Names: »99110097.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110097.WP«
╱0400274e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆↲
↲
╞ Edition:╞ May 1985↲
╞ Author: Peter Lundbo↲
╞ RCSL No.:╞ 991 10097↲
↲
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INTERNAL DOCUMENT↲
↲
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↲
↲
Title:↲
↲
┆06┆┆84┆F641 COM 601 hardware selftest↲
user's manual↲
════════════════════════════════════════════════════════════════════════
↓
════════════════════════════════════════════════════════════════════════
↓
KEYWORDS:↲
╞ ╞ ┆84┆RC 39, XENIX, Host Communication, BSC, SDLC, CIRCUIT I, ↓
┆19┆┆89┆┄┄Hardware Selftest, COM 601.↲
↲
↲
↲
↲
↲
↲
↲
ABSTRACT:↲
╞ ╞ ┆84┆This manual documents the COM601 SBC selftest program which ↓
┆19┆┆89┆┄┄contain several programs for verifying hardware components of ↓
┆19┆┆89┆┄┄the Intelligent Communication Controller. The COM601 is an ↓
┆19┆┆89┆┄┄INTEL Multibus compatible slave controller, based upon an 8 bit ↓
┆19┆┆89┆┄┄iAPX 88 microprocessor.↲
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
╞ ╞ ╞ ╞ ╞ ╞ i↲
┆a1┆┆b0┆TABLE OF CONTENTS ┆05┆PAGE ↲
↲
1. INTRODUCTION ...................................... 1↲
1.2 Selftest Equipment ............................ 1↲
↲
2. THE DUAL CHANNEL COMMUNICATION APPROACH ........... 2↲
↲
3. INTERRUPT HANDLING ................................ 3↲
3.1 Instruction Exception ......................... 3↲
3.2 Illegal Interrupts ............................ 3↲
↲
4. BUSTEST ........................................... 6↲
↲
5. ┆b0┆┆f0┆TEST 0 = MEMORY TEST .............................. 7↲
5.1 PROM Checksum Test ............................ 7↲
5.2 RAM Memory Test ............................... 8↲
┆84┆5.2.1 Memory Test Pattern ..................... 8↲
┆84┆5.2.2 Memory Test Flow ........................ 8↲
↲
6. TEST 1 = CHIP SELECT TEST ........................ 11↲
↲
7. TEST 2 = 8255A PARALLEL PORT TEST ................ 12↲
↲
8. TEST 3 = 8254 PROGRAMMABLE INTERVAL TIMER TEST ... 13↲
↲
9. TEST 4 = 8237A DIRECT MEMORY ACCESS CONTROLLER TEST 14↲
↲
10. TEST 5 = 8274 CHANNEL A TEST ..................... 16↲
↲
11. TEST 6 = 8274 CHANNEL B TEST ..................... 18↲
11.1 Status Signal Check ......................... 18↲
11.2 V.24/X.21 Select ............................ 20↲
11.3 Loop Back Test .............................. 20↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆06┆ii↲
┆b0┆┆a1┆TABLE OF CONTENTS (continued)┆05┆PAGE↲
↲
12. TEST 7 = 8273 CHANNEL C TEST ..................... 22↲
11.1 Status Signal Check ......................... 22↲
11.2 V.24/X.21 Select ............................ 24↲
11.3 Loop Back Test .............................. 24↲
↲
↲
┆a1┆┆b0┆Appendixes↲
↲
A. REFERENCES ....................................... 29↲
↲
B. LOOP BACK CABLE .................................. 30↲
↲
C. COMPLETE ERROR LIST .............................. 32↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆╞ ╞ ╞ ╞ ╞ ╞ ┆0b┆┆a1┆↲
┆a1┆┆a1┆┆b0┆┆b0┆1. INTRODUCTION↲
↲
The COM 601 is an Intelligent Communication Controller, which ↓
is an intelligent Multibus SBC used to interface mainframes ↓
or minicomputers to the RC 39 product. The communication may ↓
be the IBM BSC and the IBM SDLC protocols. The communication ↓
is synchronous and operates either onX.21 or V.24 interface ↓
circuits.↲
↲
This manual assume that the reader is familiar with the RC 39 ↓
selftest concept as described in the manual called "The RC 39 ↓
Selftest Concept". The COM 601 selftest includes 8 different ↓
tests which may be run in several modes. Five of these tests ↓
are ┆b0┆default┆f0┆ tests which allways execute after a power on. The ↓
┆19┆┄┆81┆┄last three tests are ┆b0┆extended┆b0┆┆f0┆ tests which is run only when ↓
┆19┆┄┆83┆┄requested explicit by an operator. This version of the COM ↓
┆19┆┄┆83┆┄610 SBC selftest includes no ┆b0┆seperately┆f0┆ run ┆f0┆tests.↲
↲
↲
┆a1┆┆b0┆1.2 Selftest Equipment.↲
↲
The default power on test, which is an integrated part of the ↓
system, does naturally not require any special test equipment ↓
installed.↲
↲
The ┆b0┆extended part ┆f0┆of the selftest in contrast requires a ↓
┆19┆┄┆81┆┄special loop back cable connected (see appendix A). This loop ↓
┆19┆┄┆81┆┄back cable is used by the 8273 SDLC controller test and by ↓
┆19┆┄┆81┆┄the 8274 MPSC/HDLC controller channel B test. The extended ↓
┆19┆┄┆81┆┄part of the test is only run as a result of commands given to ↓
┆19┆┄┆81┆┄the "test-host" via a connected console.These tests are used ↓
┆19┆┄┆81┆┄in the ┆a1┆┆b0┆┆e1┆burn in ┆f0┆phase by the manufacturing department or by ↓
┆19┆┄┆82┆┄technicians as part of their debugging tool.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆┆b0┆┆b0┆2. THE DUAL CHANNEL COMMUNICATION APPROACH↲
↲
The COM 601 SBC selftest ┆b0┆does not┆f0┆ supports the Dual Channel ↓
┆19┆┄┆81┆┄Communication facility as described in the "RC 39 Selftest ↓
┆19┆┄┆81┆┄Concept". The reason to this is that the COM 601 is an old ↓
┆19┆┄┆81┆┄board designed without an asynchronous V.24 interface.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆┆a1┆3. INTERRUPT HANDLING↲
↲
When the RC 39, COM 601, SBC selftest has finished the memory ↓
test, a set of default interrupt vectors are placed in the ↓
memory. These vectors are used to handle both expected and ↓
unexpected interrupts. There are two kind of unexpected ↓
interrupts. One is handled by the interrupt procedure for ↓
internal iAPX 8088 instruction interrupts, and the other is ↓
handled by the interrupt procedure for illegal device ↓
interrupts.↲
↲
↲
┆b0┆┆a1┆3.1 Instruction Exception.↲
↲
If an Instruction Exception interrupt occurs, it is likely to ↓
believe that this was caused by a malfunction of the iAPX ↓
8088, because this interrupt is related to some CPU ↓
instruction. If this error happens the test program writes ↓
the following message to the buffer :↲
↲
┆b0┆EXCEPTION : instruction interrupt↲
↲
↲
┆a1┆┆b0┆3.2 Illegal Interrupts.↲
↲
Once upon completion of each test program the reception of ↓
interrupts are enabeled. Only two of the interrupt request ↓
lines will be used in the selftest as legal interrupts. This ↓
is the timer0 and the timer1 interrupts, they are both real ↓
time clocks generated by the 8254 progammable interval ↓
timer.Timer 0 is connected to interrupt request IR0 amd ↓
timer1 to IR4. All the other interrupts will be decoded as ↓
illegal, and the following message are copied to the buffer :↲
↲
┆b0┆EXCEPTION : illegal interrupt level IRSR↲
↲
┆8c┆┆83┆┆b0┆↓
The level information is ┆b0┆not┆f0┆ corresponding to the interrupt ↓
┆19┆┄┆81┆┄request level. Instead "SR" is the hexadecimal content of the ↓
┆19┆┄┆81┆┄8259A interrupt controllers interrupt In Service Register ↓
┆19┆┄┆81┆┄(ISR), and "IR" is the hexadecimal content of the Interrupt ↓
┆19┆┄┆81┆┄Request Register (IRR). In both ISR and IRR interrupt request ↓
┆19┆┄┆81┆┄0 corresponds to bit 0 (least significant bit), IR7 to bit 7 ↓
┆19┆┄┆81┆┄and so on. When an interrupt is serviced thecorresponding bit ↓
┆19┆┄┆81┆┄in the ISR register should be set, and when an interrupt is ↓
┆19┆┄┆81┆┄requested the corresponding bit in the IRR registers should ↓
┆19┆┄┆81┆┄be set. If an illegal interrupt is srviced and the content of ↓
┆19┆┄┆81┆┄the ISR register is 00, indicating no interrupt in service, ↓
┆19┆┄┆81┆┄then the interrupt is a result of a spike on one of the 8 ↓
┆19┆┄┆81┆┄interrupt request lines, and ↓
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0c0008000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
┆a1┆Request line Interrupt name Vector type Related instructions ↲
↲
internal Divide error╞ ╞ 0 ╞ ╞ ╞ DIV, IDIV↲
↲
internal Single step╞ ╞ 1 ╞ ╞ ╞ ALL↲
↲
internal NMI╞ ╞ ╞ 2╞ ╞ ╞ ALL↲
↲
internal Breakpoint╞ 3 ╞ ╞ ╞ INT 3↲
↲
internal Owerflow┆07┆╞ 4 ╞ ╞ ╞ INT0↲
↲
internal not used╞ ╞ ╞ 5↲
↲
not used╞ ╞ 6↲
↲
not used╞ ╞ 7↲
┆a1┆ ↲
↲
↲
↲
R┆a1┆equest line Interrupt name Vector type Related interrupt level ↲
↲
IR0 timer0╞ ╞ ╞ 32 ╞ 32↲
↲
IR1 8274int╞ ╞ ╞ 33╞ ╞ ╞ 33↲
↲
IR2 8273RXint 34╞ ╞ ╞ 34↲
↲
IR3 8273TXint╞ ╞ 35╞ ╞ ╞ 35↲
↲
IR4 timer1 36 36↲
↲
IR5 OB flag int╞ 37╞ ╞ ╞ 37↲
↲
IR6 SBX int0 or SBX int1 38╞ ╞ ╞ 38↲
↲
IR7 EOP int 39╞ ╞ ╞ 39↲
┆a1┆ ↲
↲
↲
┆a1┆┆e1┆╞ ╞ ┆a1┆Interrupt Level Table.↲
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0c0008000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆4 BUSTEST.↲
↲
As a part of the initialization a simple CPU to memory ↓
bustest is made.↲
↲
The bustest uses one word in RAM-memory. This word is ↓
initialized with a zero, whereafter a one-bit is shifted ↓
from the LSB towards the MSB. For every shift, the pattern ↓
is read back and checked. Should it happen, that the pattern ↓
was not written, the program will loop countinuosly trying ↓
to read the correct pattern. This means that if the ↓
bussignals are checked by an oscilloscope and the word read ↓
is found to have bits 0 and 1 to the one level and the rest ↓
to the zero level, it must be bit 2, that contains the ↓
error.↲
↲
When the one bit has been shifted trough the entire word, ↓
this word is reinitialized to all ones and a zero-bit is ↓
shifted trough it. ↲
↲
This test is unable to produce any error-message, and is ↓
only run as a result of power on or external reset.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5. ┆b0┆Test 0 = ┆f0┆┆b0┆MEMORY TEST.↲
↲
The memory test of the RC 39, COM 601 SBC selftest consists ↓
of two parts, a PROM checksum test and a RAM memory test. ↓
The PROM checksum test is only run once at power up or ↓
external reset, whereas the RAM memory test may be run ↓
several times, if requested by the operator.↲
↲
↲
┆b0┆┆a1┆5.1 PROM Checksum Test.↲
↲
The content of the PROM are summarized bytewise and the ↓
result must be a zero. For that reason the PROM contains a ↓
compensation byte in the second byte of the PROM. Below is ↓
shown the error description that may be generated by the ↓
checksum test.↲
↲
╱0400274e0c0008000000000301503160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
↲
┆a1┆┆a1┆┆e1┆┆a2┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆┆84┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! AUXILLARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! !↲
┆a1┆! 1 ! 1 ! RAM/ROM test : ! checksum error ! exp.=0000 rec.=00XX !↲
╱0400274e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0c0008000000000301503160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
↲
↲
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
Error 1, checksum error, usually means that the content of ↓
the PROM has not been maintained and that the PROM must be ↓
changed.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5.2 RAM Memory Test.↲
↲
The RAM memory test of the RC 39, COM 601 SBC selftest ↓
verifies the on board memory.↲
↲
The RAM memory size is fixed and is 64 K-bytes.↲
↲
The memory test is a register based test and uses no memory ↓
space at all, neither for variables nor stack. The test ↓
verifies every single byte of the on-board memory.↲
↲
This fact lets only one register for test variables survive ↓
the memory test. That variable contains all the test ↓
switches and the test number. ↲
↲
↲
┆a1┆┆b0┆5.2.1 Memory Test Pattern.↲
↲
The on board Dual Ported RAM memory consists of memory chips ↓
of 1 bit * 64 K. The memory test executes 4 passes trough ↓
the entire memory, two times writing and two times reading.↲
↲
The test pattern is the convenient modulus 3 pattern ↓
consisting of three times 0000 followed by three times FFFF ↓
(hexadecimal).↲
↲
↲
┆b0┆┆a1┆5.2.2 Memory Test Flow.↲
↲
The test starts in the highest RAM addresses and inserts the ↓
pattern towards lower addresses.↲
↲
When all memory words have been written and verified, they ↓
are tested again with the inversed pattern, this means, that ↓
all bits are tested for "zero" and "one" insertion. If an ↓
error occur an attempt to send the following message, to the ↓
"test-master", is made :↲
↲
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001060b10151a1f24292e33383d4247ff04╱
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
┆8c┆┆83┆┆c8┆↓
┆84┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! SECONDARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! segm.:<ssss>,adr.:<aaaa>┆07┆!↲
┆a1┆! 2 ! 2 ! RAM/ROM test : ! RAM error ! exp.:<eeee>, rec.:<rrrr> !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001060b10151a1f24292e33383d4247ff04╱
↓
↲
The secondary text is interpreted like this :↲
↲
<ssss> is the segment address↲
<aaaa> is the offset address↲
<eeee> ┆84┆is the expected pattern, should allways be 0000 or ↓
┆19┆┆87┆┄┄FFFF.↲
<rrrr> is the received pattern.↲
↲
The above mentioned information may be used to find a ↓
defective RAM memory chip from the knowledge of the RAM-↓
layout. Say the error message goes like this :↲
↲
╱0400274e0c00060000000003014b316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆b0┆RAM/ROM test : RAM error segm.:0000, addr.:0002, exp.:0000, rec.:0101↲
↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c00060000000003014b316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
Allthough the memory test is based on 16 bit word ↓
manipulation, the memory is organized bytewise, bit 0 and 8 ↓
is stored in chip U 200, bit 1 and 9 in U201 and so on. The ↓
above error might indicate that chip U 200 is defect.↲
↲
NOTE that the error message routines are based on RAM memory ↓
buffers, therefore some peculiar situation may occur during ↓
RAM faults. ↲
↲
The error message is always written to the light emitting ↓
diodes, this means that if the message communication fails, ↓
there is still written a led error code = 2 to the leds. ↓
This means that led number 2 from the right will be lit, and ↓
the 3 others blank when a RAM error occur.↲
↲
════════════════════════════════════════════════════════════════════════
↓
When the RAM error message passing goes wrong, there is a ↓
possibility to force the RAM test to loop on error. This is ↓
done by strapping W11 low. Then the RAM test will try again ↓
and again to read from the first erronous cell is finds. If ↓
the pattern sometime happens to be correct the test will ↓
proceed further trough the test, and if the RAM is OK, the ↓
test will enter the testadministrator when it terminates. ↲
↲
Upon succesful completion of the RAM test, the ↓
testadministrator always takes over and controls the flow of ↓
the rest of the test.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆6. ┆b0┆TEST 1 = ┆f0┆┆b0┆CHIP SELECT TEST↲
↲
To ease complex debugging, a simple chip select loop, ↓
combined with a RAM write/read, is supplied. ↲
↲
This test generates chip selects to all peripheral devices ↓
by executing input instructions to all relevant I/O-devices. ↓
These are :↲
↲
Port A0H, E1H, 90H, 80H, D0H, F0H, C0H , B0H↲
↲
When all the chip selects are made, a pattern AA55 hex. is ↓
written to a RAM cell and immediately read back.↲
↲
This test is unable to generate any error messages. It is ↓
meant only as a special fast scope loop test.↲
↲
There are several ways to make this test loop. One is to set ↓
the loop-bit = "Y" and the test number to 1, then the test ↓
will loop and write OK to the console whenever the test has ↓
finished. In this case the console output increases the loop ↓
time significantly. The console output routine may be ↓
suppressed by setting the suppress data check = "Y" and the ↓
suppress status check = "Y". Note that now there is only one ↓
way back to the console output, to press RESET. This loop ↓
runs even faster if you strap W11 low. Note that this is the ↓
same strap that causes the RAM test to loop on error.↲
════════════════════════════════════════════════════════════════════════
↓
┆a2┆┆e2┆┆a1┆┆b0┆7.┆b0┆ TEST 2 =┆f0┆ ┆b0┆8255A PARALLEL PORT TEST↲
↲
The 8255A PPI test writes a pattern 10100000 binary to the ↓
output port B ( ioadr. A1H ). Then it reads the pattern back ↓
and verifies it. If no error is detected the pattern is ↓
shifted one bit to the right, and the write/read verify ↓
procedure is repeated until the pattern becomes zero. If an ↓
error is detected this message is written to the ↓
communication buffer :↲
↲
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆e1┆┆a2┆┆b0┆┆e2┆┆b0┆┆84┆┆a2┆┆e2┆┆a1┆┆f0┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! SECONDARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! !↲
┆a1┆! 3 ! 3 ! PPI test : ! port error ! exp.:00ee, rec.:00rr !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
Expected and received pattern tells you what bits went wrong ↓
with the test.↲
↲
This error might be caused by malfunction of the 8255A chip, ↓
by an initialization fault (I/O space error ), or by ↓
something else. ↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆8. ┆b0┆TEST 3 =┆f0┆ ┆b0┆8254 PROGRAMMABLE INTERVAL TIMER TEST↲
↲
The 8254 timer test verifies that both the real time timers ↓
generated interrupts. This means that both the 8254 timer ↓
chip and the timer interrupt request IR0 and IR4 on the ↓
8259A interrupt controller is checked. The test may produce ↓
the following error text.↲
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
┆84┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! AUXILLARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! both interrupts ! !↲
┆a1┆! 4 ! 4 ! PIT test: ! missing ! !↲
! ! ! ! one interrupt ! !↲
┆a2┆┆e2┆┆a1┆! 5 ! 5 ! PIT test: ! missing ! !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆9. ┆b0┆TEST 4 =┆f0┆┆b0┆ 8237A DIRECT MEMORY ACCESS CONTROLLER TEST↲
↲
The 8237A DMA test is the last test that is run by default, ↓
the rest of the tests are ┆b0┆extended tests ┆f0┆and are only run ↓
┆19┆┄┆81┆┄when requested explicit by a test person. ↲
↲
The DMA test performs a memory to memory data transport ↓
between channel 0 and channel 1. An 8 K-byte buffer ↓
initialized with a counting pattern is transferred to ↓
another buffer, which is cleared before the transfer begins. ↓
The test also verifies the DMA terminal count interrupt, ↓
which must occur on the 8259A interrupt controller IR7. If ↓
the DMA transport, when started, dont sets the terminal ↓
count bit high within 100 milliseconds, the routine ↓
generates a timeout message. The terminal count bit is also ↓
checked not to be set high before the transport is started. ↲
↲
If the DMA transport turns out to be successful, and the ↓
terminal count interrupt has been serviced, then the receive ↓
buffer is compared with the transmit buffer, and if not ↓
equal an error message is issued, otherwise the DMA chip is ↓
said to be OK.↲
↲
If the memory size is 192 K-bytes, the DMA transfer is made ↓
in 3 passes. One in each 64 K-byte segment. Note that 8255A ↓
portc bit 4 and 5 is used to select the DMA transfer page. ↓
The DMA test may produce the following error messages.↲
↲
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆84┆┆e2┆┆e2┆┆e2┆┆a1┆┆e1┆┆a2┆┆a1┆┆f0┆┆e1┆┆e2┆┆e2┆┆a1┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! AUXILLARY !↲
┆e2┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! !↲
┆a1┆! 8 ! 8 ! DMA test: ! TC before start ! !↲
! ! ! ! ! !↲
┆a2┆┆e2┆┆a1┆! 9 ! 9 ! DMA test: ! timeout ! exp.:<0000>, rec.:<rrrr> !↲
! ! ! ! ! segm.:<ssss>, adr.:<aaaa>!↲
┆a1┆! 10 ! 10 ! DMA test: ! data error ! exp.:<eeee>, rec.:<rrrr> !↲
! ! ! ! ! !↲
┆a1┆! 11 ! 11 ! DMA test: ! missing interrupt ! level.:0007 !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
Error message 9, timeout, writes the DMA count value as ↓
auxillary data. The initial count value is 1FBA hex. (8 K-↓
bytes), and the expected count is zero, when all transfers ↓
have been made. ↲
↲
Note that the other DMA channels are not tested by this ↓
routine, the are tested by the controllers, to whom they are ↓
dedicated.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆10. ┆b0┆TEST 5 =┆f0┆ ┆f0┆┆b0┆8274 CHANNEL A TEST↲
↲
The rest of the tests are ┆b0┆extended tests ┆f0┆and are only run ↓
┆19┆┄┆81┆┄when requested explicit by a test person. NOTE that it may ↓
┆19┆┄┆81┆┄disturb seriel lines seriously if the communication line ↓
┆19┆┄┆81┆┄tests are started when the lines are connected to MODEMS. ↓
┆19┆┄┆81┆┄The circuit line must be open, and a loop back cable must be ↓
┆19┆┄┆81┆┄connected to J3 and J4. See appendix A.↲
↲
The 8274 chA implements the RC-circuit communication line. ↓
This test must be executed with an open J2 connector, or ↓
with the connected terminals shut off, otherwise some ↓
terminal migth disturb the line.↲
↲
The 8274 chA RC-circuit test perform a serial transport of ↓
an 8 K-byte buffer with a counting pattern to a receive ↓
buffer, which is cleared before the transport takes place.↲
↲
The 8274 chA is initialized to SDLC mode, with DMA receive, ↓
and polled data transmit. When the chip has completed a ↓
transfer it also generates an end of message interrupt. The ↓
test naturally verifies if this interrupt really is serviced ↓
or not.↲
↲
A timeout message is generated if the transmit buffer never ↓
gets empty during the polled transmission. ↲
↲
When all characters have been send, and the interrupt also ↓
has been serviced, then the transmit and receive buffers are ↓
compared. If an error is detected, an error message is ↓
written to the "test-master", otherwise the RC-circuit ↓
channel is said to be OK. Below is a list of all possible ↓
error messages generated by this test :↲
↲
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆e2┆┆e1┆┆f0┆┆e2┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆┆84┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! SECONDARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! segm.:<ssss>, adr.:<aaaa>!↲
┆a1┆! 20 ! 20 ! 8274 chA test: ! data error ! exp.:<eeee>, rec.:<rrrr> !↲
! ! ! ! ! !↲
┆a2┆┆e2┆┆a1┆! 21 ! 21 ! 8274 chA test: ! timeout ! !↲
! ! ! ! ! !↲
┆a1┆! 22 ! 22 ! 8274 chA test: ! transfer error ! rec.:<rrrr> !↲
! ! ! ! ! !↲
┆a1┆! 23 ! 23 ! 8274 chA test: ! missing interrupt ! !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
The test is run at full speed, 250 K baud.↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆11. ┆b0┆TEST 6 =┆f0┆ ┆b0┆8274 CHANNEL B TEST↲
↲
The 8274 chB implements the BSC communication line. This ↓
test must be executed with a loopback cable connected. See ↓
appendix A.↲
↲
↲
┆b0┆┆a1┆11.1 Status Signals Check.↲
↲
Before any serial data transport is started, the V.24 ↓
interface status signals as well as the X.21 status signals ↓
are checked. The status signals are connected like this : ↲
┆82┆┆82┆↲
┆a1┆┆b0┆V.24 Status Signals.↲
↲
Request To Send, RTSb --->┆84┆┆84┆-┆84┆↓
┆81┆↲
Clear To Send, CTSb ---<-↓
↲
Data Set Ready, DSRb ---<-↓
↲
↲
Data Terminal Ready, DTRB --->-↓
↲
Data Carrier Detect, DCDB ---<-↓
↲
Calling Indicator, CIB ---<-↓
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆81┆ ┆a1┆┆b0┆X.21 Status Signals.↲
↲
Control (A), C(A)B -->-↓
↲
Indication (A), I(A)B --<- ↓
↲
Control (B), C(B)B -->- ↓
↲
Indication (B), I(B)B --<-↓
↲
A status error during V.24 test might look like this :↲
↲
┆b0┆8274 chB test: V24 status error rec.: 0001 exp.: 0000↲
↲
Only the three least significant bits are used, and must be ↓
interpreted like this :↲
↲
Bit 0 = -,DSRB ; Bit 1 = -,CIB ; Bit 2 = -,CTSB↲
↲
The message above indicates that something is wrong with the ↓
V.24 Data Set Ready status signal, which is toggled by the ↓
Request To Send signal by the test program.↲
↲
A status error during the X.21 test allways looks like this:↲
↲
┆b0┆8274 chB test: X21 Control-Indication error↲
↲
This message indicates that something is wrong with the X.21 ↓
status signal I = Clear To Send, which is controlled by the ↓
signal called C = Data Terminal Ready.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆11.2 V.24/X.21 Select.↲
↲
Selection of V.24/-,X.21 mode is done from the 8273 SDLC ↓
controller via the loopback cable, see below.↲
↲
┆a1┆ J3. ┆e1┆ ┆84┆┆a1┆ J4. ↲
↲
-,X.21B ---<----------- ---<- RTSC↲
↲
The diode and the resistor prevents negative voltage on the ↓
-,X.21 pin.↲
↲
NOTE that the 8273 chip may desturb the 8274 chB test ↓
seriously if the V.24/X.21 selection logic fails.↲
↲
↲
┆a1┆┆b0┆11.3 Loop Back Test.↲
↲
The 8274 chB BSC test perform a serial data transport of an ↓
8 K-byte buffer initialized with a counting pattern to a ↓
receive buffer, which is cleared before the transport takes ↓
place. First the transport is made trough the V.24 ↓
interface, and then repeated trough the X.21 interface ↓
circuits.↲
↲
The 8274 chB is initialized to SDLC mode, with polled data ↓
transmit, and interrupt controlled data receive. ↲
↲
If the transmit buffer internal to the 8274 chip never gets ↓
empty during polled transmit, a timeout error message is ↓
generated.↲
↲
If none interrupts from the 8274 chip is serviced, a missing ↓
interrupt message is generated.↲
↲
════════════════════════════════════════════════════════════════════════
↓
When all data has been sent, and also the interrupts has ↓
been serviced, the test program compares the transmit and ↓
the receive buffer. If an error is detected a data error ↓
message is reported to the "test-master", otherwise the BSC ↓
channel is said to be OK.↲
↲
Below is a complete list of possible error messages ↓
generated by this test.↲
↲
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆a1┆-┆e2┆┆e1┆┆f0┆┆e2┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆ -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! SECONDARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT╞ !↲
! ! ! ! ! segm.:<ssss>, adr.:<aaaa>!↲
┆a1┆! 24 ! 24 ! 8274 chB test: ! data error ! exp.:<eeee>, rec.:<rrrr> !↲
! ! ! ! ! !↲
┆a2┆┆e2┆┆a1┆! 25 ! 25 ! 8274 chB test: ! timeout ! !↲
! ! ! ! ! !↲
┆a1┆! 26 ! 26 ! 8274 chB test: ! transfer error ! rec.:<rrrr> !↲
! ! ! ! ! !↲
┆a1┆! 27 ! 27 ! 8274 chB test: ! missing interrupt ! !↲
! ! ! ! ! !↲
┆a1┆! 28 ! 28 ! 8274 chB test: ! V.24 status error ! exp.:<000e>, rec.:<000r> !↲
! ! ! ! X.21 Control- ! !↲
┆a1┆! 29 ! 29 ! 8274 chB test: ! Indication-error ! !↲
! ! ! ! X.21 dial error !╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
┆a1┆! 30 ! 30 ! 8274 chB test: ! circuit failure ! !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
The test is run at a baud rate of 64 Kb/s.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆12. ┆b0┆TEST 7 =┆f0┆┆b0┆ 8273 CHANNEL C TEST↲
↲
The 8273 chC implements the SDLC communication line. This ↓
test must be executed with a loop back cable connected. See ↓
appendix A.↲
↲
↲
┆a1┆┆b0┆12.1 Status Signal Check.↲
↲
Before any serial data transport is started, the V.24 ↓
interface status signals as well as the X.21 status signals ↓
are checked. The status signals are connected like this : ↲
┆82┆┆82┆↲
┆a1┆┆b0┆V.24 Status Signals.↲
↲
Request To Send, RTSC --->┆84┆┆84┆-┆84┆┆81┆↲
Clear To Send, CTSC ---<-↲
Data Set Ready, DSRC ---<-↲
↲
Data Terminal Ready, DTRC --->-↲
Calling Indicator, CIC ---<-↲
↲
╱0400274e0c00060000000003014e316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆81┆ Data Carrier Detect, DCDC ---<---------<--- DTRB, Data Terminal Ready↲
↲
╱0400274e0a00060000000003013d316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c00060000000003014e316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
NOTE that the DCDC signal is toggled from the 8274 chip via ↓
the loopback cable.↲
↲
┆a1┆┆b0┆X.21 Status Signals.↲
↲
Control (A), C(A)B -->-↲
Indication (A), I(A)B --<- ↲
↲
┆8c┆┆83┆┄↓
Control (B), C(B)B -->- ↲
Indication (B), I(B)B --<-↲
↲
A status error during V.24 test might look like this :↲
↲
┆b0┆8273 chC test: V.24 status error rec.:0008 exp.: 0000↲
↲
Only the four least significant bits are used, and must be ↓
interpreted like this :↲
↲
Bit 0 = -,CTSC ; Bit 1 = -;CDC ; Bit 2 = -,CICC ; ↲
Bit 3 = -,DSRC↲
↲
The message above indicates that something is wrong with the ↓
V.24 Data Set Ready status signal, which is toggled from the ↓
Request To Send signal by the test program.↲
↲
An X.21 status error may look like this :↲
↲
┆b0┆8273 chC test: X.21 status error rec.: 0003 exp.: 0002↲
↲
Only the two least significant bits are used and must be ↓
interpreted like this :↲
↲
Bit 0 = -,CTSC ; Bit 1 = -,CDC↲
↲
The message above indicates that something is wrong with the ↓
X.21 status signal I = Clear To Send, which is toggled from ↓
the Data Terminal Ready signal by the test program.↲
↲
↲
┆8c┆┆82┆┆f4┆↓
┆a1┆┆b0┆12.2 V.24/X.21 Select.↲
↲
NOTE that the V.24/-,X.21 test select is done from the 8274 ↓
MPSC controller, see below.↲
↲
┆a1┆ J4. ┆e1┆ ┆e1┆┆a1┆┆84┆ J3. ↲
↲
-,X.21C ---<---------- ----<- RTSB↲
↲
The diode and the resistor prevents negative voltage on the -↓
,X.21 pin. NOTE that the 8274 chip may desturb the 8273 chC ↓
test seriously if the V.24/-,X.21 selection logic fails.↲
↲
The 8273 chC is initialized to SDLC mode, with both DMA ↓
controlled data transmit and receive. The DMA channel 1 is ↓
dedicated as receive channel, and DMA channel 2 as transmit ↓
channel.↲
↲
↲
┆a2┆┆a1┆┆e2┆┆b0┆12.3 Loop Back Test.↲
↲
The 8273 chC SDLC test perform a serial data transport of an ↓
8 K-byte buffer initialized with a counting pattern to a ↓
receive buffer, which is cleared before the transport takes ↓
place. First the transport is made trough the V.24 interface, ↓
and then repeated trough the X.21 interface circuits.↲
↲
The 8273 SDLC controller also generates both an RX- and a TX-↓
interrupt result, when it has finished a command, or expired ↓
some unusual condition.↲
↲
════════════════════════════════════════════════════════════════════════
↓
The only valid RX-interrupt result is the generel receive ↓
result, which indicates that a valid SDLC frame has been ↓
detected, and transferred to memory by the DMA channel, ↓
hopefully.↲
↲
If an RX-interrupt result is read, and if it dont indicate ↓
transfer complete, the following error message is generated :↲
↲
┆b0┆┆b0┆8273 chC test: RX error rec.: 00rr↲
↲
The RX-interrupt result must be interpreted this way :↲
↲
Result = B7,B6,B5,B4,B3,B2,B1,B0 binary = rr hex↲
╱0400274e0c00060000000003014d316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013d316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
┆a2┆┆e2┆┆a1┆- -↲
┆a1┆B7 , B6 , B5 , B4 , B3 , B2 , B1 , B0 ! RX-interrupt result code !↲
D7 , D6 , D5 , 0 , 0 , 0 , 0 , 0 ! A1 match or generel receive↲
D7 , D6 , D5 , 0 , 0 , 0 , 0 , 1 ! A2 match↲
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 ! CRC error↲
0 , 0 , 0 , 0 , 0 , 1 , 0 , 0 ! Abort detected↲
0 , 0 , 0 , 0 , 0 , 1 , 0 , 1 ! Idle detect↲
0 , 0 , 0 , 0 , 0 , 1 , 1 , 0 ! EOP detected↲
0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 ! Frame less than 32 bit↲
0 , 0 , 0 , 0 , 1 , 0 , 0 , 0 ! DMA overrun detected↲
0 , 0 , 0 , 0 , 1 , 0 , 0 , 1 ! Memory buffer overflow↲
0 , 0 , 0 , 0 , 1 , 0 , 1 , 0 ! Carrier Detect failure↲
0 , 0 , 0 , 0 , 1 , 0 , 1 , 1 ! Receive Interrupt overrun↲
↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c00060000000003014d316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
D7,D6 and D5 must be taken from the table below.↲
↲
┆a1┆- -↲
┆a1┆D7 , D6 , D5 ! Bits received in last byte ↲
1 , 1 , 1 ! All 8 bits received↲
0 , 0 , 0 ! D0 received↲
1 , 0 , 0 ! D1-D0 received↲
0 , 1 , 0 ! D2-D0 received↲
1 , 1 , 0 ! D3-D0 received↲
0 , 0 , 1 ! D4-D0 received↲
1 , 0 , 1 ! D5-D0 received↲
0 , 1 , 1 ! D6-D0 received↲
↲
The only allowed RX-interrupt result in this test is the E0 ↓
hex. result, which means 8 bits in last byte received and ↓
frame OK. ↲
↲
The only valid TX-interrupt result is the Frame Transmit ↓
Complete result, which indicates that transmit frame is ↓
complete. If another result is read the following error ↓
message is generated.↲
↲
┆b0┆8273 chC test: TX error rec.: 00rr↲
↲
The low order byte of the received data is significant, and ↓
must be interpreted like this :↲
↲
Result = B7,B6,B5,B4,B3,B2,B1,B0 binary = rr hex.↲
╱0400274e0c00060000000003014b316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
┆a2┆┆e2┆┆a1┆┆a1┆- -↲
┆a1┆B7 , B6 , B5 , B4 , B3 , B2 , B1 , B0 ! TX-interrupt result code !↲
0 , 0 , 0 , 0 , 1 , 1 , 0 , 0 ! Early transmit interrupt↲
0 , 0 , 0 , 0 , 1 , 1 , 0 , 1 ! Frame transmit complete↲
0 , 0 , 0 , 0 , 1 , 1 , 1 , 0 ! DMA underrun↲
0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 ! Clear To Send (CTS) error↲
0 , 0 , 0 , 1 , 0 , 0 , 0 , 0 ! Abort complete↲
↲
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c00060000000003014b316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
The only valid TX-interrupt result in this program is D0 ↓
hex., the rest are treated like errors.↲
↲
If none interrupts from the 8273 controller is serviced, a ↓
missing interrupt message is generated.↲
↲
When commands are written to, or parameters read from the ↓
8273 SDLC controller, the program must wait until parameters ↓
are valid, or until the controller is ready to accept ↓
commands. If the controller dont get ready to accept a ↓
command, or deliver some parameters, in a reasonable time, ↓
the following error massage is generated :↲
↲
┆b0┆8273 chC test: command timeout↲
↲
When all data has been sent, and also the interrupts has ↓
been serviced, then the test program compares the transmit ↓
and the receive buffer. If an error is detected a data error ↓
message is reported to the "test-master", otherwise the SDLC ↓
channel is said to be OK.↲
↲
Below is a complete list of possible error messages ↓
generated by this test.↲
↲
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆e2┆┆e2┆┆e1┆┆f0┆┆e2┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! SECONDARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! !↲
┆a1┆! 12 ! 12 ! 8273 chC test: ! command timeout ! !↲
! ! ! ! ! !↲
┆a2┆┆e2┆┆a1┆! 13 ! 13 ! 8273 chC test: ! transfer timeout ! !↲
! ! ! ! ! !↲
┆a1┆! 14 ! 14 ! 8273 chC test: ! RX error ! rec.:<00rr> !↲
! ! ! ! ! !↲
┆a1┆! 15 ! 15 ! 8273 chC test: ! TX error ! rec.:<00rr> !↲
! ! ! ! ! !↲
┆a1┆! 16 ! 16 ! 8273 chC test: ! V.24 status error ! exp.:<000e>, rec.:<000r> !↲
! ! ! ! ! !↲
┆a1┆! 17 ! 17 ! 8273 chC test: ! X.21 status error ! exp.:<000e>, rec.:<000r> !↲
! ! ! ! ! !↲
┆a2┆┆e2┆┆a1┆! 18 ! 18 ! 8273 chC test: ! missing interrupt ! rec.:<00rr> !↲
! ! ! ! ! adr.:<aaaa>, rec.:<rrrr> !↲
┆a1┆! 19 ! 19 ! 8273 chC test: ! data error ! exp.:<eeee> !↲
! ! ! ! X.21 dial error ! !↲
┆a1┆! 31 ! 31 ! 8273 chC test: ! circuit failure ! !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
The test is run at a baud rate of 64 Kb/s.↲
════════════════════════════════════════════════════════════════════════
↓
┆a2┆┆e2┆┆a1┆┆a1┆┆b0┆┆b0┆A. REFERENCES↲
↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
RCSL. 991 10092↲
RC 39 Selftest Concept, ↲
User's manual ╞ ╞ ↲
↲
RCSL. 991 10096↲
RC 3931 ETC611 hardware selftest, ↲
User's manual ↲
↲
RCSL. 991 10095↲
ITC 602 hardware selftest, ↲
User's manual ╞ ↲
↲
RCSL. 991 10094↲
RC3902 CPU 691 hardware selftest, ↲
User's manual ↲
↲
RCSL. 991 10134↲
RC39 monitor 8086 version, ↲
Reference manual╞ ↲
↲
RCSL. 991 10093↲
RC39 monitor 80286 version, ↲
Reference manual ↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆B. ┆b0┆LOOP BACK CABLE↲
↲
Both the 8274 channel B and the 8273 test relies on the fact ↓
that a loop back cable is connected to the COM 601 edge ↓
connectors J3 and J4. On the next page you will find diagram ↓
and part number of the loop back cable.↲
╱0400274e0c0007000000000301503160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆ J3 pin pin J4 ↲
↲
RTSB 7 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 7 RTSC↲
CTSB 9 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 9 CTSC↲
DSRB 11 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 11 DSRC↲
↲
TXDB╞ ╞ ╞ 3 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 3 TXDC↲
RXDB╞ ╞ ╞ 5 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 5 RXDC↲
↲
DTRB╞ ╞ ╞ 14 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 14 DTRC↲
DCDB╞ ╞ ╞ 15 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 15 DCDC↲
CIB╞ ╞ ╞ ╞ 18 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 18 CIC↲
↲
GND╞ ╞ ╞ ╞ 13 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 13 GND↲
↲
R(A)B ╞ ╞ ╞ 16 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 16 R(A)C↲
T(A)B╞ ╞ ╞ 17 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 17 T(A)C↲
↲
R(B)B╞ ╞ ╞ 12 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 12 R(B)C↲
T(B)B ╞ ╞ ╞ 23 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 23 T(B)C↲
↲
C(A)B╞ ╞ ╞ 24 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 24 C(A)C↲
I(A)B╞ ╞ ╞ 19 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 19 I(A)C↲
↲
C(B)B╞ ╞ ╞ 2 -╞ ╞ ╞ ╞ ╞ ╞ - 2 C(B)C↲
I(B)B╞ ╞ ╞ 22 -╞ ╞ ╞ ╞ ╞ ╞ - 22 I(B)C↲
↲
S(A)B╞ ╞ ╞ 10 -╞ ╞ ╞ ╞ ╞ ╞ - 10 S(A)C↲
S(B)B╞ ╞ ╞ 6 -╞ ╞ ╞ ╞ ╞ ╞ - 6 S(B)C↲
X.21 TEST CLK. B╞ 20 -╞ ╞ ╞ ╞ ╞ ╞ - 20 X.21 TEST CLK. C↲
↲
V.24 TEST CLK. B╞ 25 -╞ ╞ ╞ ╞ ╞ ╞ - 25 V.24 TEST CLK. C↲
REC. CLK. B╞ ╞ 8 -╞ ╞ ╞ ╞ ╞ ╞ - 8 REC. CLK. C ↲
TRANS. CLK. B╞ ╞ 4 -╞ ╞ ╞ ╞ ╞ ╞ - 4 TRANS. CLK. C↲
↲
X.21 SEL. B 21 -╞ ╞ ╞ ╞ ╞ ╞ - 21 X.21 SEL. C↲
↲
┆b0┆part number : KBL 609↲
↲
╞ ╞ ╞ ╞ ┆a1┆COM 601 Card edge loop back cable. ↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆┆a1┆┆b0┆C. COMPLETE ERROR LIST↲
↲
!-----------------------------------------------------------------------------!↲
! Err. No !╞ ╞ ╞ ╞ Error Text╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
! 0 ! OK╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
No error detected.↲
↲
!-----------------------------------------------------------------------------!↲
! 1 ! RAM/ROM test : checksum error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The calculated EPROM checksum was not zero.↲
↲
!-----------------------------------------------------------------------------!↲
! 2╞ ! RAM/ROM test : RAM error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The RAM-test did not read back the same pattern as written.↲
↲
!-----------------------------------------------------------------------------!↲
! 3 ! PPI test: port error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The parallel port test did not read back the same pattern as written.↲
↲
!-----------------------------------------------------------------------------!↲
! 4 ! PIT test: both interrupts missing ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
Both 8254 timer interrupts were either not generated or serviced.↲
↲
!-----------------------------------------------------------------------------!↲
! 5 ! PIT test: one interrupt missing╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
One of the 8254 timer interrupts was not generated or serviced.↲
↲
════════════════════════════════════════════════════════════════════════
↓
!-----------------------------------------------------------------------------!↲
! 8 ! DMA test: TC before start╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The 8237A DMA chip indicates Terminal Count reached before any transport is ↲
started.↲
↲
!-----------------------------------------------------------------------------!↲
! 9 ! DMA test: timeout╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The DMA transport has not finished within app. 100 milliseconds.↲
↲
!-----------------------------------------------------------------------------;↲
! 10 ! DMA test: data error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The DMA data transport has finished, but the received data is different from ↲
the data sent.↲
↲
!-----------------------------------------------------------------------------!↲
! 11 ! DMA test: missing interrupt╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
No DMA Terminal Count interrupt generated or serviced.↲
↲
!-----------------------------------------------------------------------------!↲
! 12 ! 8273 chC test: command timeout╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The 8273 SDLC controller chip did not accept the command issued.↲
↲
!-----------------------------------------------------------------------------!↲
! 13 ! 8273 chC test: transfer timeout╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The serial data transport (DMA controlled) did not complete within 2.5 seconds.↲
↲
!-----------------------------------------------------------------------------!↲
! 14 ! 8273 chC test: RX error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The RX-interrupt result was not a general frame received result as expected.↲
↲
!-----------------------------------------------------------------------------!↲
┆8c┆┆83┆┆c2┆↓
! 15 ! 8273 chC test: TX error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The TX-interrupt result was not a frame transmit completed result as expected.↲
↲
!-----------------------------------------------------------------------------!↲
! 16 ! 8273 chC test: V.24 status error╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The V.24 status signals, which is toggled via the loop back cable, fails.↲
↲
!-----------------------------------------------------------------------------!↲
! 17 ! 8273 chC test: X.21 status error╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The X.21 status signals, which is toggled via the loop back cable, fails.↲
↲
!-----------------------------------------------------------------------------!↲
! 18 ! 8273 chC test: missing interrupt╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
RX-interrupt or TX-interrupt or both are missing.↲
↲
!-----------------------------------------------------------------------------!↲
! 19 ! 8273 chC test: data error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The data transmitted via the loop back cable in full duplex mode was not recei-↲
ved properly.↲
↲
!-----------------------------------------------------------------------------!↲
! 20 ! 8274 chA test: data error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The data transmitted in full duplex mode was not received properly.↲
↲
!-----------------------------------------------------------------------------!↲
! 21 ! 8274 chA test: timeout╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
════════════════════════════════════════════════════════════════════════
↓
The 8274 HDLC/MPSC chip did not get ready for data within app. 5 milliseconds (↲
polled transmit).↲
↲
!-----------------------------------------------------------------------------!↲
! 22 ! 8274 chA test: transfer error ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
Illegal interrupt condition has arised during the data transfer.↲
↲
!-----------------------------------------------------------------------------!↲
! 23 ! 8274 chA test: missing interrupt╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
No 8274 HDLC/MPSC chip interrupt was generated or serviced.↲
↲
!-----------------------------------------------------------------------------!↲
! 24 ! 8274 chB test: data error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The data transmitted via the loop back cable in full duplex mode was not ↓
received properly.↲
↲
!-----------------------------------------------------------------------------!↲
! 25 ! 8274 chB test: timeout╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The 8274 HDLC/MPSC chip did not get ready for data within app. 5 milliseconds (↲
polled transmit).↲
↲
!-----------------------------------------------------------------------------!↲
! 26 ! 8274 chB test: transfer error╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
Illegal interrupt condition has arised during the data transfer.↲
↲
!-----------------------------------------------------------------------------!↲
! 27 ! 8274 chB test: missing interrupt╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
No 8274 HDLC/MPSC chip interrupt was generated or serviced.↲
↲
!-----------------------------------------------------------------------------!↲
! 28 ! 8274 chB test: V.24 status error╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
════════════════════════════════════════════════════════════════════════
↓
The V.24 status signals, which is toggled via the loop back cable, fails.↲
↲
!-----------------------------------------------------------------------------!↲
! 29 ! 8274 chB test: X.21 Control-Indication error╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The X.21 status signals, which is toggled via the loop back cable, fails.↲
┆1a┆┆1a┆---------!↲
!