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Length: 47616 (0xba00)
Types: RcTekst
Names: »99110097.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110097.WP«
╱0400274e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆↲
↲
╞ Edition:╞ May 1985↲
╞ Author: Peter Lundbo↲
╞ RCSL No.:╞ 991 10097↲
↲
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INTERNAL DOCUMENT↲
↲
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↲
↲
Title:↲
↲
┆06┆┆84┆F641 COM 601 hardware selftest↲
user's manual↲
════════════════════════════════════════════════════════════════════════
↓
════════════════════════════════════════════════════════════════════════
↓
KEYWORDS:↲
╞ ╞ ┆84┆RC 39, XENIX, Host Communication, BSC, SDLC, CIRCUIT I, ↓
┆19┆┆89┆┄┄Hardware Selftest, COM 601.↲
↲
↲
↲
↲
↲
↲
↲
ABSTRACT:↲
╞ ╞ ┆84┆This manual documents the COM601 SBC selftest program which ↓
┆19┆┆89┆┄┄contain several programs for verifying hardware components of ↓
┆19┆┆89┆┄┄the Intelligent Communication Controller. The COM601 is an ↓
┆19┆┆89┆┄┄INTEL Multibus compatible slave controller, based upon an 8 bit ↓
┆19┆┆89┆┄┄iAPX 88 microprocessor.↲
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
╞ ╞ ╞ ╞ ╞ ╞ i↲
┆a1┆┆b0┆TABLE OF CONTENTS ┆05┆PAGE ↲
↲
1. INTRODUCTION ...................................... 1↲
1.2 Selftest Equipment ............................ 1↲
↲
2. THE DUAL CHANNEL COMMUNICATION APPROACH ........... 2↲
↲
3. INTERRUPT HANDLING ................................ 3↲
3.1 Instruction Exception ......................... 3↲
3.2 Illegal Interrupts ............................ 3↲
↲
4. BUSTEST ........................................... 6↲
↲
5. ┆b0┆┆f0┆TEST 0 = MEMORY TEST .............................. 7↲
5.1 PROM Checksum Test ............................ 7↲
5.2 RAM Memory Test ............................... 8↲
┆84┆5.2.1 Memory Test Pattern ..................... 8↲
┆84┆5.2.2 Memory Test Flow ........................ 8↲
↲
6. TEST 1 = CHIP SELECT TEST ........................ 11↲
↲
7. TEST 2 = 8255A PARALLEL PORT TEST ................ 12↲
↲
8. TEST 3 = 8254 PROGRAMMABLE INTERVAL TIMER TEST ... 13↲
↲
9. TEST 4 = 8237A DIRECT MEMORY ACCESS CONTROLLER TEST 14↲
↲
10. TEST 5 = 8274 CHANNEL A TEST ..................... 16↲
↲
11. TEST 6 = 8274 CHANNEL B TEST ..................... 18↲
11.1 Status Signal Check ......................... 18↲
11.2 V.24/X.21 Select ............................ 20↲
11.3 Loop Back Test .............................. 20↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆06┆ii↲
┆b0┆┆a1┆TABLE OF CONTENTS (continued)┆05┆PAGE↲
↲
12. TEST 7 = 8273 CHANNEL C TEST ..................... 22↲
11.1 Status Signal Check ......................... 22↲
11.2 V.24/X.21 Select ............................ 24↲
11.3 Loop Back Test .............................. 24↲
↲
↲
┆a1┆┆b0┆Appendixes↲
↲
A. REFERENCES ....................................... 29↲
↲
B. LOOP BACK CABLE .................................. 30↲
↲
C. COMPLETE ERROR LIST .............................. 32↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆╞ ╞ ╞ ╞ ╞ ╞ ┆0b┆┆a1┆↲
┆a1┆┆a1┆┆b0┆┆b0┆1. INTRODUCTION↲
↲
The COM 601 is an Intelligent Communication Controller, which ↓
is an intelligent Multibus SBC used to interface mainframes ↓
or minicomputers to the RC 39 product. The communication may ↓
be the IBM BSC and the IBM SDLC protocols. The communication ↓
is synchronous and operates either onX.21 or V.24 interface ↓
circuits.↲
↲
This manual assume that the reader is familiar with the RC 39 ↓
selftest concept as described in the manual called "The RC 39 ↓
Selftest Concept". The COM 601 selftest includes 8 different ↓
tests which may be run in several modes. Five of these tests ↓
are ┆b0┆default┆f0┆ tests which allways execute after a power on. The ↓
┆19┆┄┆81┆┄last three tests are ┆b0┆extended┆b0┆┆f0┆ tests which is run only when ↓
┆19┆┄┆83┆┄requested explicit by an operator. This version of the COM ↓
┆19┆┄┆83┆┄610 SBC selftest includes no ┆b0┆seperately┆f0┆ run ┆f0┆tests.↲
↲
↲
┆a1┆┆b0┆1.2 Selftest Equipment.↲
↲
The default power on test, which is an integrated part of the ↓
system, does naturally not require any special test equipment ↓
installed.↲
↲
The ┆b0┆extended part ┆f0┆of the selftest in contrast requires a ↓
┆19┆┄┆81┆┄special loop back cable connected (see appendix A). This loop ↓
┆19┆┄┆81┆┄back cable is used by the 8273 SDLC controller test and by ↓
┆19┆┄┆81┆┄the 8274 MPSC/HDLC controller channel B test. The extended ↓
┆19┆┄┆81┆┄part of the test is only run as a result of commands given to ↓
┆19┆┄┆81┆┄the "test-host" via a connected console.These tests are used ↓
┆19┆┄┆81┆┄in the ┆a1┆┆b0┆┆e1┆burn in ┆f0┆phase by the manufacturing department or by ↓
┆19┆┄┆82┆┄technicians as part of their debugging tool.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆┆b0┆┆b0┆2. THE DUAL CHANNEL COMMUNICATION APPROACH↲
↲
The COM 601 SBC selftest ┆b0┆does not┆f0┆ supports the Dual Channel ↓
┆19┆┄┆81┆┄Communication facility as described in the "RC 39 Selftest ↓
┆19┆┄┆81┆┄Concept". The reason to this is that the COM 601 is an old ↓
┆19┆┄┆81┆┄board designed without an asynchronous V.24 interface.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆┆a1┆3. INTERRUPT HANDLING↲
↲
When the RC 39, COM 601, SBC selftest has finished the memory ↓
test, a set of default interrupt vectors are placed in the ↓
memory. These vectors are used to handle both expected and ↓
unexpected interrupts. There are two kind of unexpected ↓
interrupts. One is handled by the interrupt procedure for ↓
internal iAPX 8088 instruction interrupts, and the other is ↓
handled by the interrupt procedure for illegal device ↓
interrupts.↲
↲
↲
┆b0┆┆a1┆3.1 Instruction Exception.↲
↲
If an Instruction Exception interrupt occurs, it is likely to ↓
believe that this was caused by a malfunction of the iAPX ↓
8088, because this interrupt is related to some CPU ↓
instruction. If this error happens the test program writes ↓
the following message to the buffer :↲
↲
┆b0┆EXCEPTION : instruction interrupt↲
↲
↲
┆a1┆┆b0┆3.2 Illegal Interrupts.↲
↲
Once upon completion of each test program the reception of ↓
interrupts are enabeled. Only two of the interrupt request ↓
lines will be used in the selftest as legal interrupts. This ↓
is the timer0 and the timer1 interrupts, they are both real ↓
time clocks generated by the 8254 progammable interval ↓
timer.Timer 0 is connected to interrupt request IR0 amd ↓
timer1 to IR4. All the other interrupts will be decoded as ↓
illegal, and the following message are copied to the buffer :↲
↲
┆b0┆EXCEPTION : illegal interrupt level IRSR↲
↲
┆8c┆┆83┆┆b0┆↓
The level information is ┆b0┆not┆f0┆ corresponding to the interrupt ↓
┆19┆┄┆81┆┄request level. Instead "SR" is the hexadecimal content of the ↓
┆19┆┄┆81┆┄8259A interrupt controllers interrupt In Service Register ↓
┆19┆┄┆81┆┄(ISR), and "IR" is the hexadecimal content of the Interrupt ↓
┆19┆┄┆81┆┄Request Register (IRR). In both ISR and IRR interrupt request ↓
┆19┆┄┆81┆┄0 corresponds to bit 0 (least significant bit), IR7 to bit 7 ↓
┆19┆┄┆81┆┄and so on. When an interrupt is serviced thecorresponding bit ↓
┆19┆┄┆81┆┄in the ISR register should be set, and when an interrupt is ↓
┆19┆┄┆81┆┄requested the corresponding bit in the IRR registers should ↓
┆19┆┄┆81┆┄be set. If an illegal interrupt is srviced and the content of ↓
┆19┆┄┆81┆┄the ISR register is 00, indicating no interrupt in service, ↓
┆19┆┄┆81┆┄then the interrupt is a result of a spike on one of the 8 ↓
┆19┆┄┆81┆┄interrupt request lines, and ↓
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0c0008000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
┆a1┆Request line Interrupt name Vector type Related instructions ↲
↲
internal Divide error╞ ╞ 0 ╞ ╞ ╞ DIV, IDIV↲
↲
internal Single step╞ ╞ 1 ╞ ╞ ╞ ALL↲
↲
internal NMI╞ ╞ ╞ 2╞ ╞ ╞ ALL↲
↲
internal Breakpoint╞ 3 ╞ ╞ ╞ INT 3↲
↲
internal Owerflow┆07┆╞ 4 ╞ ╞ ╞ INT0↲
↲
internal not used╞ ╞ ╞ 5↲
↲
not used╞ ╞ 6↲
↲
not used╞ ╞ 7↲
┆a1┆ ↲
↲
↲
↲
R┆a1┆equest line Interrupt name Vector type Related interrupt level ↲
↲
IR0 timer0╞ ╞ ╞ 32 ╞ 32↲
↲
IR1 8274int╞ ╞ ╞ 33╞ ╞ ╞ 33↲
↲
IR2 8273RXint 34╞ ╞ ╞ 34↲
↲
IR3 8273TXint╞ ╞ 35╞ ╞ ╞ 35↲
↲
IR4 timer1 36 36↲
↲
IR5 OB flag int╞ 37╞ ╞ ╞ 37↲
↲
IR6 SBX int0 or SBX int1 38╞ ╞ ╞ 38↲
↲
IR7 EOP int 39╞ ╞ ╞ 39↲
┆a1┆ ↲
↲
↲
┆a1┆┆e1┆╞ ╞ ┆a1┆Interrupt Level Table.↲
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0c0008000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆4 BUSTEST.↲
↲
As a part of the initialization a simple CPU to memory ↓
bustest is made.↲
↲
The bustest uses one word in RAM-memory. This word is ↓
initialized with a zero, whereafter a one-bit is shifted ↓
from the LSB towards the MSB. For every shift, the pattern ↓
is read back and checked. Should it happen, that the pattern ↓
was not written, the program will loop countinuosly trying ↓
to read the correct pattern. This means that if the ↓
bussignals are checked by an oscilloscope and the word read ↓
is found to have bits 0 and 1 to the one level and the rest ↓
to the zero level, it must be bit 2, that contains the ↓
error.↲
↲
When the one bit has been shifted trough the entire word, ↓
this word is reinitialized to all ones and a zero-bit is ↓
shifted trough it. ↲
↲
This test is unable to produce any error-message, and is ↓
only run as a result of power on or external reset.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5. ┆b0┆Test 0 = ┆f0┆┆b0┆MEMORY TEST.↲
↲
The memory test of the RC 39, COM 601 SBC selftest consists ↓
of two parts, a PROM checksum test and a RAM memory test. ↓
The PROM checksum test is only run once at power up or ↓
external reset, whereas the RAM memory test may be run ↓
several times, if requested by the operator.↲
↲
↲
┆b0┆┆a1┆5.1 PROM Checksum Test.↲
↲
The content of the PROM are summarized bytewise and the ↓
result must be a zero. For that reason the PROM contains a ↓
compensation byte in the second byte of the PROM. Below is ↓
shown the error description that may be generated by the ↓
checksum test.↲
↲
╱0400274e0c0008000000000301503160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
↲
┆a1┆┆a1┆┆e1┆┆a2┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆┆84┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! AUXILLARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! !↲
┆a1┆! 1 ! 1 ! RAM/ROM test : ! checksum error ! exp.=0000 rec.=00XX !↲
╱0400274e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0c0008000000000301503160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
↲
↲
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0c0006000000000301483160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
Error 1, checksum error, usually means that the content of ↓
the PROM has not been maintained and that the PROM must be ↓
changed.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5.2 RAM Memory Test.↲
↲
The RAM memory test of the RC 39, COM 601 SBC selftest ↓
verifies the on board memory.↲
↲
The RAM memory size is fixed and is 64 K-bytes.↲
↲
The memory test is a register based test and uses no memory ↓
space at all, neither for variables nor stack. The test ↓
verifies every single byte of the on-board memory.↲
↲
This fact lets only one register for test variables survive ↓
the memory test. That variable contains all the test ↓
switches and the test number. ↲
↲
↲
┆a1┆┆b0┆5.2.1 Memory Test Pattern.↲
↲
The on board Dual Ported RAM memory consists of memory chips ↓
of 1 bit * 64 K. The memory test executes 4 passes trough ↓
the entire memory, two times writing and two times reading.↲
↲
The test pattern is the convenient modulus 3 pattern ↓
consisting of three times 0000 followed by three times FFFF ↓
(hexadecimal).↲
↲
↲
┆b0┆┆a1┆5.2.2 Memory Test Flow.↲
↲
The test starts in the highest RAM addresses and inserts the ↓
pattern towards lower addresses.↲
↲
When all memory words have been written and verified, they ↓
are tested again with the inversed pattern, this means, that ↓
all bits are tested for "zero" and "one" insertion. If an ↓
error occur an attempt to send the following message, to the ↓
"test-master", is made :↲
↲
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001060b10151a1f24292e33383d4247ff04╱
╱0400274e0a00060000000003013c3160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
↓
┆8c┆┆83┆┆c8┆↓
┆84┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! SECONDARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! segm.:<ssss>,adr.:<aaaa>┆07┆!↲
┆a1┆! 2 ! 2 ! RAM/ROM test : ! RAM error ! exp.:<eeee>, rec.:<rrrr> !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001060b10151a1f24292e33383d4247ff04╱
↓
↲
The secondary text is interpreted like this :↲
↲
<ssss> is the segment address↲
<aaaa> is the offset address↲
<eeee> ┆84┆is the expected pattern, should allways be 0000 or ↓
┆19┆┆87┆┄┄FFFF.↲
<rrrr> is the received pattern.↲
↲
The above mentioned information may be used to find a ↓
defective RAM memory chip from the knowledge of the RAM-↓
layout. Say the error message goes like this :↲
↲
╱0400274e0c00060000000003014b316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆b0┆RAM/ROM test : RAM error segm.:0000, addr.:0002, exp.:0000, rec.:0101↲
↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c00060000000003014b316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
Allthough the memory test is based on 16 bit word ↓
manipulation, the memory is organized bytewise, bit 0 and 8 ↓
is stored in chip U 200, bit 1 and 9 in U201 and so on. The ↓
above error might indicate that chip U 200 is defect.↲
↲
NOTE that the error message routines are based on RAM memory ↓
buffers, therefore some peculiar situation may occur during ↓
RAM faults. ↲
↲
The error message is always written to the light emitting ↓
diodes, this means that if the message communication fails, ↓
there is still written a led error code = 2 to the leds. ↓
This means that led number 2 from the right will be lit, and ↓
the 3 others blank when a RAM error occur.↲
↲
════════════════════════════════════════════════════════════════════════
↓
When the RAM error message passing goes wrong, there is a ↓
possibility to force the RAM test to loop on error. This is ↓
done by strapping W11 low. Then the RAM test will try again ↓
and again to read from the first erronous cell is finds. If ↓
the pattern sometime happens to be correct the test will ↓
proceed further trough the test, and if the RAM is OK, the ↓
test will enter the testadministrator when it terminates. ↲
↲
Upon succesful completion of the RAM test, the ↓
testadministrator always takes over and controls the flow of ↓
the rest of the test.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆6. ┆b0┆TEST 1 = ┆f0┆┆b0┆CHIP SELECT TEST↲
↲
To ease complex debugging, a simple chip select loop, ↓
combined with a RAM write/read, is supplied. ↲
↲
This test generates chip selects to all peripheral devices ↓
by executing input instructions to all relevant I/O-devices. ↓
These are :↲
↲
Port A0H, E1H, 90H, 80H, D0H, F0H, C0H , B0H↲
↲
When all the chip selects are made, a pattern AA55 hex. is ↓
written to a RAM cell and immediately read back.↲
↲
This test is unable to generate any error messages. It is ↓
meant only as a special fast scope loop test.↲
↲
There are several ways to make this test loop. One is to set ↓
the loop-bit = "Y" and the test number to 1, then the test ↓
will loop and write OK to the console whenever the test has ↓
finished. In this case the console output increases the loop ↓
time significantly. The console output routine may be ↓
suppressed by setting the suppress data check = "Y" and the ↓
suppress status check = "Y". Note that now there is only one ↓
way back to the console output, to press RESET. This loop ↓
runs even faster if you strap W11 low. Note that this is the ↓
same strap that causes the RAM test to loop on error.↲
════════════════════════════════════════════════════════════════════════
↓
┆a2┆┆e2┆┆a1┆┆b0┆7.┆b0┆ TEST 2 =┆f0┆ ┆b0┆8255A PARALLEL PORT TEST↲
↲
The 8255A PPI test writes a pattern 10100000 binary to the ↓
output port B ( ioadr. A1H ). Then it reads the pattern back ↓
and verifies it. If no error is detected the pattern is ↓
shifted one bit to the right, and the write/read verify ↓
procedure is repeated until the pattern becomes zero. If an ↓
error is detected this message is written to the ↓
communication buffer :↲
↲
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆e1┆┆a2┆┆b0┆┆e2┆┆b0┆┆84┆┆a2┆┆e2┆┆a1┆┆f0┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! SECONDARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! !↲
┆a1┆! 3 ! 3 ! PPI test : ! port error ! exp.:00ee, rec.:00rr !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
Expected and received pattern tells you what bits went wrong ↓
with the test.↲
↲
This error might be caused by malfunction of the 8255A chip, ↓
by an initialization fault (I/O space error ), or by ↓
something else. ↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆8. ┆b0┆TEST 3 =┆f0┆ ┆b0┆8254 PROGRAMMABLE INTERVAL TIMER TEST↲
↲
The 8254 timer test verifies that both the real time timers ↓
generated interrupts. This means that both the 8254 timer ↓
chip and the timer interrupt request IR0 and IR4 on the ↓
8259A interrupt controller is checked. The test may produce ↓
the following error text.↲
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
┆84┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! AUXILLARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! both interrupts ! !↲
┆a1┆! 4 ! 4 ! PIT test: ! missing ! !↲
! ! ! ! one interrupt ! !↲
┆a2┆┆e2┆┆a1┆! 5 ! 5 ! PIT test: ! missing ! !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆9. ┆b0┆TEST 4 =┆f0┆┆b0┆ 8237A DIRECT MEMORY ACCESS CONTROLLER TEST↲
↲
The 8237A DMA test is the last test that is run by default, ↓
the rest of the tests are ┆b0┆extended tests ┆f0┆and are only run ↓
┆19┆┄┆81┆┄when requested explicit by a test person. ↲
↲
The DMA test performs a memory to memory data transport ↓
between channel 0 and channel 1. An 8 K-byte buffer ↓
initialized with a counting pattern is transferred to ↓
another buffer, which is cleared before the transfer begins. ↓
The test also verifies the DMA terminal count interrupt, ↓
which must occur on the 8259A interrupt controller IR7. If ↓
the DMA transport, when started, dont sets the terminal ↓
count bit high within 100 milliseconds, the routine ↓
generates a timeout message. The terminal count bit is also ↓
checked not to be set high before the transport is started. ↲
↲
If the DMA transport turns out to be successful, and the ↓
terminal count interrupt has been serviced, then the receive ↓
buffer is compared with the transmit buffer, and if not ↓
equal an error message is issued, otherwise the DMA chip is ↓
said to be OK.↲
↲
If the memory size is 192 K-bytes, the DMA transfer is made ↓
in 3 passes. One in each 64 K-byte segment. Note that 8255A ↓
portc bit 4 and 5 is used to select the DMA transfer page. ↓
The DMA test may produce the following error messages.↲
↲
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆84┆┆e2┆┆e2┆┆e2┆┆a1┆┆e1┆┆a2┆┆a1┆┆f0┆┆e1┆┆e2┆┆e2┆┆a1┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! AUXILLARY !↲
┆e2┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! !↲
┆a1┆! 8 ! 8 ! DMA test: ! TC before start ! !↲
! ! ! ! ! !↲
┆a2┆┆e2┆┆a1┆! 9 ! 9 ! DMA test: ! timeout ! exp.:<0000>, rec.:<rrrr> !↲
! ! ! ! ! segm.:<ssss>, adr.:<aaaa>!↲
┆a1┆! 10 ! 10 ! DMA test: ! data error ! exp.:<eeee>, rec.:<rrrr> !↲
! ! ! ! ! !↲
┆a1┆! 11 ! 11 ! DMA test: ! missing interrupt ! level.:0007 !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
Error message 9, timeout, writes the DMA count value as ↓
auxillary data. The initial count value is 1FBA hex. (8 K-↓
bytes), and the expected count is zero, when all transfers ↓
have been made. ↲
↲
Note that the other DMA channels are not tested by this ↓
routine, the are tested by the controllers, to whom they are ↓
dedicated.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆10. ┆b0┆TEST 5 =┆f0┆ ┆f0┆┆b0┆8274 CHANNEL A TEST↲
↲
The rest of the tests are ┆b0┆extended tests ┆f0┆and are only run ↓
┆19┆┄┆81┆┄when requested explicit by a test person. NOTE that it may ↓
┆19┆┄┆81┆┄disturb seriel lines seriously if the communication line ↓
┆19┆┄┆81┆┄tests are started when the lines are connected to MODEMS. ↓
┆19┆┄┆81┆┄The circuit line must be open, and a loop back cable must be ↓
┆19┆┄┆81┆┄connected to J3 and J4. See appendix A.↲
↲
The 8274 chA implements the RC-circuit communication line. ↓
This test must be executed with an open J2 connector, or ↓
with the connected terminals shut off, otherwise some ↓
terminal migth disturb the line.↲
↲
The 8274 chA RC-circuit test perform a serial transport of ↓
an 8 K-byte buffer with a counting pattern to a receive ↓
buffer, which is cleared before the transport takes place.↲
↲
The 8274 chA is initialized to SDLC mode, with DMA receive, ↓
and polled data transmit. When the chip has completed a ↓
transfer it also generates an end of message interrupt. The ↓
test naturally verifies if this interrupt really is serviced ↓
or not.↲
↲
A timeout message is generated if the transmit buffer never ↓
gets empty during the polled transmission. ↲
↲
When all characters have been send, and the interrupt also ↓
has been serviced, then the transmit and receive buffers are ↓
compared. If an error is detected, an error message is ↓
written to the "test-master", otherwise the RC-circuit ↓
channel is said to be OK. Below is a list of all possible ↓
error messages generated by this test :↲
↲
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆e2┆┆e1┆┆f0┆┆e2┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆┆84┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! SECONDARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! segm.:<ssss>, adr.:<aaaa>!↲
┆a1┆! 20 ! 20 ! 8274 chA test: ! data error ! exp.:<eeee>, rec.:<rrrr> !↲
! ! ! ! ! !↲
┆a2┆┆e2┆┆a1┆! 21 ! 21 ! 8274 chA test: ! timeout ! !↲
! ! ! ! ! !↲
┆a1┆! 22 ! 22 ! 8274 chA test: ! transfer error ! rec.:<rrrr> !↲
! ! ! ! ! !↲
┆a1┆! 23 ! 23 ! 8274 chA test: ! missing interrupt ! !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
The test is run at full speed, 250 K baud.↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆11. ┆b0┆TEST 6 =┆f0┆ ┆b0┆8274 CHANNEL B TEST↲
↲
The 8274 chB implements the BSC communication line. This ↓
test must be executed with a loopback cable connected. See ↓
appendix A.↲
↲
↲
┆b0┆┆a1┆11.1 Status Signals Check.↲
↲
Before any serial data transport is started, the V.24 ↓
interface status signals as well as the X.21 status signals ↓
are checked. The status signals are connected like this : ↲
┆82┆┆82┆↲
┆a1┆┆b0┆V.24 Status Signals.↲
↲
Request To Send, RTSb --->┆84┆┆84┆-┆84┆↓
┆81┆↲
Clear To Send, CTSb ---<-↓
↲
Data Set Ready, DSRb ---<-↓
↲
↲
Data Terminal Ready, DTRB --->-↓
↲
Data Carrier Detect, DCDB ---<-↓
↲
Calling Indicator, CIB ---<-↓
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆81┆ ┆a1┆┆b0┆X.21 Status Signals.↲
↲
Control (A), C(A)B -->-↓
↲
Indication (A), I(A)B --<- ↓
↲
Control (B), C(B)B -->- ↓
↲
Indication (B), I(B)B --<-↓
↲
A status error during V.24 test might look like this :↲
↲
┆b0┆8274 chB test: V24 status error rec.: 0001 exp.: 0000↲
↲
Only the three least significant bits are used, and must be ↓
interpreted like this :↲
↲
Bit 0 = -,DSRB ; Bit 1 = -,CIB ; Bit 2 = -,CTSB↲
↲
The message above indicates that something is wrong with the ↓
V.24 Data Set Ready status signal, which is toggled by the ↓
Request To Send signal by the test program.↲
↲
A status error during the X.21 test allways looks like this:↲
↲
┆b0┆8274 chB test: X21 Control-Indication error↲
↲
This message indicates that something is wrong with the X.21 ↓
status signal I = Clear To Send, which is controlled by the ↓
signal called C = Data Terminal Ready.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆11.2 V.24/X.21 Select.↲
↲
Selection of V.24/-,X.21 mode is done from the 8273 SDLC ↓
controller via the loopback cable, see below.↲
↲
┆a1┆ J3. ┆e1┆ ┆84┆┆a1┆ J4. ↲
↲
-,X.21B ---<----------- ---<- RTSC↲
↲
The diode and the resistor prevents negative voltage on the ↓
-,X.21 pin.↲
↲
NOTE that the 8273 chip may desturb the 8274 chB test ↓
seriously if the V.24/X.21 selection logic fails.↲
↲
↲
┆a1┆┆b0┆11.3 Loop Back Test.↲
↲
The 8274 chB BSC test perform a serial data transport of an ↓
8 K-byte buffer initialized with a counting pattern to a ↓
receive buffer, which is cleared before the transport takes ↓
place. First the transport is made trough the V.24 ↓
interface, and then repeated trough the X.21 interface ↓
circuits.↲
↲
The 8274 chB is initialized to SDLC mode, with polled data ↓
transmit, and interrupt controlled data receive. ↲
↲
If the transmit buffer internal to the 8274 chip never gets ↓
empty during polled transmit, a timeout error message is ↓
generated.↲
↲
If none interrupts from the 8274 chip is serviced, a missing ↓
interrupt message is generated.↲
↲
════════════════════════════════════════════════════════════════════════
↓
When all data has been sent, and also the interrupts has ↓
been serviced, the test program compares the transmit and ↓
the receive buffer. If an error is detected a data error ↓
message is reported to the "test-master", otherwise the BSC ↓
channel is said to be OK.↲
↲
Below is a complete list of possible error messages ↓
generated by this test.↲
↲
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆a1┆-┆e2┆┆e1┆┆f0┆┆e2┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆ -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! SECONDARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT╞ !↲
! ! ! ! ! segm.:<ssss>, adr.:<aaaa>!↲
┆a1┆! 24 ! 24 ! 8274 chB test: ! data error ! exp.:<eeee>, rec.:<rrrr> !↲
! ! ! ! ! !↲
┆a2┆┆e2┆┆a1┆! 25 ! 25 ! 8274 chB test: ! timeout ! !↲
! ! ! ! ! !↲
┆a1┆! 26 ! 26 ! 8274 chB test: ! transfer error ! rec.:<rrrr> !↲
! ! ! ! ! !↲
┆a1┆! 27 ! 27 ! 8274 chB test: ! missing interrupt ! !↲
! ! ! ! ! !↲
┆a1┆! 28 ! 28 ! 8274 chB test: ! V.24 status error ! exp.:<000e>, rec.:<000r> !↲
! ! ! ! X.21 Control- ! !↲
┆a1┆! 29 ! 29 ! 8274 chB test: ! Indication-error ! !↲
! ! ! ! X.21 dial error !╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
┆a1┆! 30 ! 30 ! 8274 chB test: ! circuit failure ! !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
The test is run at a baud rate of 64 Kb/s.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆12. ┆b0┆TEST 7 =┆f0┆┆b0┆ 8273 CHANNEL C TEST↲
↲
The 8273 chC implements the SDLC communication line. This ↓
test must be executed with a loop back cable connected. See ↓
appendix A.↲
↲
↲
┆a1┆┆b0┆12.1 Status Signal Check.↲
↲
Before any serial data transport is started, the V.24 ↓
interface status signals as well as the X.21 status signals ↓
are checked. The status signals are connected like this : ↲
┆82┆┆82┆↲
┆a1┆┆b0┆V.24 Status Signals.↲
↲
Request To Send, RTSC --->┆84┆┆84┆-┆84┆┆81┆↲
Clear To Send, CTSC ---<-↲
Data Set Ready, DSRC ---<-↲
↲
Data Terminal Ready, DTRC --->-↲
Calling Indicator, CIC ---<-↲
↲
╱0400274e0c00060000000003014e316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆81┆ Data Carrier Detect, DCDC ---<---------<--- DTRB, Data Terminal Ready↲
↲
╱0400274e0a00060000000003013d316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c00060000000003014e316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
NOTE that the DCDC signal is toggled from the 8274 chip via ↓
the loopback cable.↲
↲
┆a1┆┆b0┆X.21 Status Signals.↲
↲
Control (A), C(A)B -->-↲
Indication (A), I(A)B --<- ↲
↲
┆8c┆┆83┆┄↓
Control (B), C(B)B -->- ↲
Indication (B), I(B)B --<-↲
↲
A status error during V.24 test might look like this :↲
↲
┆b0┆8273 chC test: V.24 status error rec.:0008 exp.: 0000↲
↲
Only the four least significant bits are used, and must be ↓
interpreted like this :↲
↲
Bit 0 = -,CTSC ; Bit 1 = -;CDC ; Bit 2 = -,CICC ; ↲
Bit 3 = -,DSRC↲
↲
The message above indicates that something is wrong with the ↓
V.24 Data Set Ready status signal, which is toggled from the ↓
Request To Send signal by the test program.↲
↲
An X.21 status error may look like this :↲
↲
┆b0┆8273 chC test: X.21 status error rec.: 0003 exp.: 0002↲
↲
Only the two least significant bits are used and must be ↓
interpreted like this :↲
↲
Bit 0 = -,CTSC ; Bit 1 = -,CDC↲
↲
The message above indicates that something is wrong with the ↓
X.21 status signal I = Clear To Send, which is toggled from ↓
the Data Terminal Ready signal by the test program.↲
↲
↲
┆8c┆┆82┆┆f4┆↓
┆a1┆┆b0┆12.2 V.24/X.21 Select.↲
↲
NOTE that the V.24/-,X.21 test select is done from the 8274 ↓
MPSC controller, see below.↲
↲
┆a1┆ J4. ┆e1┆ ┆e1┆┆a1┆┆84┆ J3. ↲
↲
-,X.21C ---<---------- ----<- RTSB↲
↲
The diode and the resistor prevents negative voltage on the -↓
,X.21 pin. NOTE that the 8274 chip may desturb the 8273 chC ↓
test seriously if the V.24/-,X.21 selection logic fails.↲
↲
The 8273 chC is initialized to SDLC mode, with both DMA ↓
controlled data transmit and receive. The DMA channel 1 is ↓
dedicated as receive channel, and DMA channel 2 as transmit ↓
channel.↲
↲
↲
┆a2┆┆a1┆┆e2┆┆b0┆12.3 Loop Back Test.↲
↲
The 8273 chC SDLC test perform a serial data transport of an ↓
8 K-byte buffer initialized with a counting pattern to a ↓
receive buffer, which is cleared before the transport takes ↓
place. First the transport is made trough the V.24 interface, ↓
and then repeated trough the X.21 interface circuits.↲
↲
The 8273 SDLC controller also generates both an RX- and a TX-↓
interrupt result, when it has finished a command, or expired ↓
some unusual condition.↲
↲
════════════════════════════════════════════════════════════════════════
↓
The only valid RX-interrupt result is the generel receive ↓
result, which indicates that a valid SDLC frame has been ↓
detected, and transferred to memory by the DMA channel, ↓
hopefully.↲
↲
If an RX-interrupt result is read, and if it dont indicate ↓
transfer complete, the following error message is generated :↲
↲
┆b0┆┆b0┆8273 chC test: RX error rec.: 00rr↲
↲
The RX-interrupt result must be interpreted this way :↲
↲
Result = B7,B6,B5,B4,B3,B2,B1,B0 binary = rr hex↲
╱0400274e0c00060000000003014d316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013d316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
┆a2┆┆e2┆┆a1┆- -↲
┆a1┆B7 , B6 , B5 , B4 , B3 , B2 , B1 , B0 ! RX-interrupt result code !↲
D7 , D6 , D5 , 0 , 0 , 0 , 0 , 0 ! A1 match or generel receive↲
D7 , D6 , D5 , 0 , 0 , 0 , 0 , 1 ! A2 match↲
0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 ! CRC error↲
0 , 0 , 0 , 0 , 0 , 1 , 0 , 0 ! Abort detected↲
0 , 0 , 0 , 0 , 0 , 1 , 0 , 1 ! Idle detect↲
0 , 0 , 0 , 0 , 0 , 1 , 1 , 0 ! EOP detected↲
0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 ! Frame less than 32 bit↲
0 , 0 , 0 , 0 , 1 , 0 , 0 , 0 ! DMA overrun detected↲
0 , 0 , 0 , 0 , 1 , 0 , 0 , 1 ! Memory buffer overflow↲
0 , 0 , 0 , 0 , 1 , 0 , 1 , 0 ! Carrier Detect failure↲
0 , 0 , 0 , 0 , 1 , 0 , 1 , 1 ! Receive Interrupt overrun↲
↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c00060000000003014d316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
D7,D6 and D5 must be taken from the table below.↲
↲
┆a1┆- -↲
┆a1┆D7 , D6 , D5 ! Bits received in last byte ↲
1 , 1 , 1 ! All 8 bits received↲
0 , 0 , 0 ! D0 received↲
1 , 0 , 0 ! D1-D0 received↲
0 , 1 , 0 ! D2-D0 received↲
1 , 1 , 0 ! D3-D0 received↲
0 , 0 , 1 ! D4-D0 received↲
1 , 0 , 1 ! D5-D0 received↲
0 , 1 , 1 ! D6-D0 received↲
↲
The only allowed RX-interrupt result in this test is the E0 ↓
hex. result, which means 8 bits in last byte received and ↓
frame OK. ↲
↲
The only valid TX-interrupt result is the Frame Transmit ↓
Complete result, which indicates that transmit frame is ↓
complete. If another result is read the following error ↓
message is generated.↲
↲
┆b0┆8273 chC test: TX error rec.: 00rr↲
↲
The low order byte of the received data is significant, and ↓
must be interpreted like this :↲
↲
Result = B7,B6,B5,B4,B3,B2,B1,B0 binary = rr hex.↲
╱0400274e0c00060000000003014b316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
┆a2┆┆e2┆┆a1┆┆a1┆- -↲
┆a1┆B7 , B6 , B5 , B4 , B3 , B2 , B1 , B0 ! TX-interrupt result code !↲
0 , 0 , 0 , 0 , 1 , 1 , 0 , 0 ! Early transmit interrupt↲
0 , 0 , 0 , 0 , 1 , 1 , 0 , 1 ! Frame transmit complete↲
0 , 0 , 0 , 0 , 1 , 1 , 1 , 0 ! DMA underrun↲
0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 ! Clear To Send (CTS) error↲
0 , 0 , 0 , 1 , 0 , 0 , 0 , 0 ! Abort complete↲
↲
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c00060000000003014b316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
The only valid TX-interrupt result in this program is D0 ↓
hex., the rest are treated like errors.↲
↲
If none interrupts from the 8273 controller is serviced, a ↓
missing interrupt message is generated.↲
↲
When commands are written to, or parameters read from the ↓
8273 SDLC controller, the program must wait until parameters ↓
are valid, or until the controller is ready to accept ↓
commands. If the controller dont get ready to accept a ↓
command, or deliver some parameters, in a reasonable time, ↓
the following error massage is generated :↲
↲
┆b0┆8273 chC test: command timeout↲
↲
When all data has been sent, and also the interrupts has ↓
been serviced, then the test program compares the transmit ↓
and the receive buffer. If an error is detected a data error ↓
message is reported to the "test-master", otherwise the SDLC ↓
channel is said to be OK.↲
↲
Below is a complete list of possible error messages ↓
generated by this test.↲
↲
════════════════════════════════════════════════════════════════════════
↓
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
┆e2┆┆e2┆┆e1┆┆f0┆┆e2┆┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆- -↲
! ERR.! LED ! INTRODUCTION ! ERROR ! SECONDARY !↲
┆a1┆┆e1┆┆a2┆┆e2┆┆a1┆! NO. ! NO. ! TEXT ! TEXT ! TEXT !↲
! ! ! ! ! !↲
┆a1┆! 12 ! 12 ! 8273 chC test: ! command timeout ! !↲
! ! ! ! ! !↲
┆a2┆┆e2┆┆a1┆! 13 ! 13 ! 8273 chC test: ! transfer timeout ! !↲
! ! ! ! ! !↲
┆a1┆! 14 ! 14 ! 8273 chC test: ! RX error ! rec.:<00rr> !↲
! ! ! ! ! !↲
┆a1┆! 15 ! 15 ! 8273 chC test: ! TX error ! rec.:<00rr> !↲
! ! ! ! ! !↲
┆a1┆! 16 ! 16 ! 8273 chC test: ! V.24 status error ! exp.:<000e>, rec.:<000r> !↲
! ! ! ! ! !↲
┆a1┆! 17 ! 17 ! 8273 chC test: ! X.21 status error ! exp.:<000e>, rec.:<000r> !↲
! ! ! ! ! !↲
┆a2┆┆e2┆┆a1┆! 18 ! 18 ! 8273 chC test: ! missing interrupt ! rec.:<00rr> !↲
! ! ! ! ! adr.:<aaaa>, rec.:<rrrr> !↲
┆a1┆! 19 ! 19 ! 8273 chC test: ! data error ! exp.:<eeee> !↲
! ! ! ! X.21 dial error ! !↲
┆a1┆! 31 ! 31 ! 8273 chC test: ! circuit failure ! !↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0c000800000000030150316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
↲
The test is run at a baud rate of 64 Kb/s.↲
════════════════════════════════════════════════════════════════════════
↓
┆a2┆┆e2┆┆a1┆┆a1┆┆b0┆┆b0┆A. REFERENCES↲
↲
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
RCSL. 991 10092↲
RC 39 Selftest Concept, ↲
User's manual ╞ ╞ ↲
↲
RCSL. 991 10096↲
RC 3931 ETC611 hardware selftest, ↲
User's manual ↲
↲
RCSL. 991 10095↲
ITC 602 hardware selftest, ↲
User's manual ╞ ↲
↲
RCSL. 991 10094↲
RC3902 CPU 691 hardware selftest, ↲
User's manual ↲
↲
RCSL. 991 10134↲
RC39 monitor 8086 version, ↲
Reference manual╞ ↲
↲
RCSL. 991 10093↲
RC39 monitor 80286 version, ↲
Reference manual ↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆B. ┆b0┆LOOP BACK CABLE↲
↲
Both the 8274 channel B and the 8273 test relies on the fact ↓
that a loop back cable is connected to the COM 601 edge ↓
connectors J3 and J4. On the next page you will find diagram ↓
and part number of the loop back cable.↲
╱0400274e0c0007000000000301503160000000000000000000000000000000000000000000000000050a0f14191e23282d32373c41464bff04╱
╱0400274e0a00060000000003013c316000000000000000000000000000000000000000000000000001050a0f14191e23282d32373c4146ff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆ J3 pin pin J4 ↲
↲
RTSB 7 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 7 RTSC↲
CTSB 9 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 9 CTSC↲
DSRB 11 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 11 DSRC↲
↲
TXDB╞ ╞ ╞ 3 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 3 TXDC↲
RXDB╞ ╞ ╞ 5 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 5 RXDC↲
↲
DTRB╞ ╞ ╞ 14 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 14 DTRC↲
DCDB╞ ╞ ╞ 15 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 15 DCDC↲
CIB╞ ╞ ╞ ╞ 18 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 18 CIC↲
↲
GND╞ ╞ ╞ ╞ 13 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 13 GND↲
↲
R(A)B ╞ ╞ ╞ 16 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 16 R(A)C↲
T(A)B╞ ╞ ╞ 17 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 17 T(A)C↲
↲
R(B)B╞ ╞ ╞ 12 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 12 R(B)C↲
T(B)B ╞ ╞ ╞ 23 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 23 T(B)C↲
↲
C(A)B╞ ╞ ╞ 24 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 24 C(A)C↲
I(A)B╞ ╞ ╞ 19 -╞ ╞ ╞ ╞ ╞ ╞ -╞ 19 I(A)C↲
↲
C(B)B╞ ╞ ╞ 2 -╞ ╞ ╞ ╞ ╞ ╞ - 2 C(B)C↲
I(B)B╞ ╞ ╞ 22 -╞ ╞ ╞ ╞ ╞ ╞ - 22 I(B)C↲
↲
S(A)B╞ ╞ ╞ 10 -╞ ╞ ╞ ╞ ╞ ╞ - 10 S(A)C↲
S(B)B╞ ╞ ╞ 6 -╞ ╞ ╞ ╞ ╞ ╞ - 6 S(B)C↲
X.21 TEST CLK. B╞ 20 -╞ ╞ ╞ ╞ ╞ ╞ - 20 X.21 TEST CLK. C↲
↲
V.24 TEST CLK. B╞ 25 -╞ ╞ ╞ ╞ ╞ ╞ - 25 V.24 TEST CLK. C↲
REC. CLK. B╞ ╞ 8 -╞ ╞ ╞ ╞ ╞ ╞ - 8 REC. CLK. C ↲
TRANS. CLK. B╞ ╞ 4 -╞ ╞ ╞ ╞ ╞ ╞ - 4 TRANS. CLK. C↲
↲
X.21 SEL. B 21 -╞ ╞ ╞ ╞ ╞ ╞ - 21 X.21 SEL. C↲
↲
┆b0┆part number : KBL 609↲
↲
╞ ╞ ╞ ╞ ┆a1┆COM 601 Card edge loop back cable. ↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆┆a1┆┆b0┆C. COMPLETE ERROR LIST↲
↲
!-----------------------------------------------------------------------------!↲
! Err. No !╞ ╞ ╞ ╞ Error Text╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
! 0 ! OK╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
No error detected.↲
↲
!-----------------------------------------------------------------------------!↲
! 1 ! RAM/ROM test : checksum error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The calculated EPROM checksum was not zero.↲
↲
!-----------------------------------------------------------------------------!↲
! 2╞ ! RAM/ROM test : RAM error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The RAM-test did not read back the same pattern as written.↲
↲
!-----------------------------------------------------------------------------!↲
! 3 ! PPI test: port error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The parallel port test did not read back the same pattern as written.↲
↲
!-----------------------------------------------------------------------------!↲
! 4 ! PIT test: both interrupts missing ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
Both 8254 timer interrupts were either not generated or serviced.↲
↲
!-----------------------------------------------------------------------------!↲
! 5 ! PIT test: one interrupt missing╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
One of the 8254 timer interrupts was not generated or serviced.↲
↲
════════════════════════════════════════════════════════════════════════
↓
!-----------------------------------------------------------------------------!↲
! 8 ! DMA test: TC before start╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The 8237A DMA chip indicates Terminal Count reached before any transport is ↲
started.↲
↲
!-----------------------------------------------------------------------------!↲
! 9 ! DMA test: timeout╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The DMA transport has not finished within app. 100 milliseconds.↲
↲
!-----------------------------------------------------------------------------;↲
! 10 ! DMA test: data error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The DMA data transport has finished, but the received data is different from ↲
the data sent.↲
↲
!-----------------------------------------------------------------------------!↲
! 11 ! DMA test: missing interrupt╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
No DMA Terminal Count interrupt generated or serviced.↲
↲
!-----------------------------------------------------------------------------!↲
! 12 ! 8273 chC test: command timeout╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The 8273 SDLC controller chip did not accept the command issued.↲
↲
!-----------------------------------------------------------------------------!↲
! 13 ! 8273 chC test: transfer timeout╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The serial data transport (DMA controlled) did not complete within 2.5 seconds.↲
↲
!-----------------------------------------------------------------------------!↲
! 14 ! 8273 chC test: RX error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The RX-interrupt result was not a general frame received result as expected.↲
↲
!-----------------------------------------------------------------------------!↲
┆8c┆┆83┆┆c2┆↓
! 15 ! 8273 chC test: TX error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The TX-interrupt result was not a frame transmit completed result as expected.↲
↲
!-----------------------------------------------------------------------------!↲
! 16 ! 8273 chC test: V.24 status error╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The V.24 status signals, which is toggled via the loop back cable, fails.↲
↲
!-----------------------------------------------------------------------------!↲
! 17 ! 8273 chC test: X.21 status error╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The X.21 status signals, which is toggled via the loop back cable, fails.↲
↲
!-----------------------------------------------------------------------------!↲
! 18 ! 8273 chC test: missing interrupt╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
RX-interrupt or TX-interrupt or both are missing.↲
↲
!-----------------------------------------------------------------------------!↲
! 19 ! 8273 chC test: data error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The data transmitted via the loop back cable in full duplex mode was not recei-↲
ved properly.↲
↲
!-----------------------------------------------------------------------------!↲
! 20 ! 8274 chA test: data error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The data transmitted in full duplex mode was not received properly.↲
↲
!-----------------------------------------------------------------------------!↲
! 21 ! 8274 chA test: timeout╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
════════════════════════════════════════════════════════════════════════
↓
The 8274 HDLC/MPSC chip did not get ready for data within app. 5 milliseconds (↲
polled transmit).↲
↲
!-----------------------------------------------------------------------------!↲
! 22 ! 8274 chA test: transfer error ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
Illegal interrupt condition has arised during the data transfer.↲
↲
!-----------------------------------------------------------------------------!↲
! 23 ! 8274 chA test: missing interrupt╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
No 8274 HDLC/MPSC chip interrupt was generated or serviced.↲
↲
!-----------------------------------------------------------------------------!↲
! 24 ! 8274 chB test: data error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The data transmitted via the loop back cable in full duplex mode was not ↓
received properly.↲
↲
!-----------------------------------------------------------------------------!↲
! 25 ! 8274 chB test: timeout╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The 8274 HDLC/MPSC chip did not get ready for data within app. 5 milliseconds (↲
polled transmit).↲
↲
!-----------------------------------------------------------------------------!↲
! 26 ! 8274 chB test: transfer error╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
Illegal interrupt condition has arised during the data transfer.↲
↲
!-----------------------------------------------------------------------------!↲
! 27 ! 8274 chB test: missing interrupt╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
No 8274 HDLC/MPSC chip interrupt was generated or serviced.↲
↲
!-----------------------------------------------------------------------------!↲
! 28 ! 8274 chB test: V.24 status error╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
════════════════════════════════════════════════════════════════════════
↓
The V.24 status signals, which is toggled via the loop back cable, fails.↲
↲
!-----------------------------------------------------------------------------!↲
! 29 ! 8274 chB test: X.21 Control-Indication error╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
The X.21 status signals, which is toggled via the loop back cable, fails.↲
┆1a┆┆1a┆---------!↲
!
0x0000…0020 (0,) 00 00 00 00 00 00 00 00 42 05 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 4e 00 00 00 ┆ B N ┆
0x0020…0040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
0x0040…0047 00 00 00 00 00 00 00 ┆ ┆
0x0047…0080 Params {
0x0047…0080 04 00 27 4e 0c 00 06 00 00 00 00 03 01 48 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N H1` ┆
0x0047…0080 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x0047…0080 }
0x0080…0083 FormFeed {
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0x0083…00a0 0a a1 a1 0d 0a 0d 0a 09 45 64 69 74 69 6f 6e 3a 09 4d 61 79 20 31 39 38 35 0d 0a 09 41 ┆ Edition: May 1985 A┆
0x00a0…00c0 75 74 68 6f 72 3a 20 20 20 50 65 74 65 72 20 4c 75 6e 64 62 6f 0d 0a 09 52 43 53 4c 20 4e 6f 2e ┆uthor: Peter Lundbo RCSL No.┆
0x00c0…00e0 3a 09 39 39 31 20 31 30 30 39 37 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 20 20 20 ┆: 991 10097 ┆
0x00e0…0100 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 49 4e 54 45 52 4e 41 4c 20 44 ┆ INTERNAL D┆
0x0100…0120 4f 43 55 4d 45 4e 54 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 54 69 74 6c 65 3a 0d 0a 0d ┆OCUMENT Title: ┆
0x0120…0140 0a 06 84 46 36 34 31 20 43 4f 4d 20 36 30 31 20 68 61 72 64 77 61 72 65 20 73 65 6c 66 74 65 73 ┆ F641 COM 601 hardware selftes┆
0x0140…0160 74 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆t ┆
0x0160…016f 75 73 65 72 27 73 20 6d 61 6e 75 61 6c 0d 0a ┆user's manual ┆
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0x016f…0172 }
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0x0173…0176 }
0x0176…0180 0a 4b 45 59 57 4f 52 44 53 3a ┆ KEYWORDS:┆
0x0180…01a0 0d 0a 09 09 84 52 43 20 33 39 2c 20 58 45 4e 49 58 2c 20 48 6f 73 74 20 43 6f 6d 6d 75 6e 69 63 ┆ RC 39, XENIX, Host Communic┆
0x01a0…01c0 61 74 69 6f 6e 2c 20 42 53 43 2c 20 53 44 4c 43 2c 20 43 49 52 43 55 49 54 20 49 2c 20 0a 19 89 ┆ation, BSC, SDLC, CIRCUIT I, ┆
0x01c0…01e0 80 80 48 61 72 64 77 61 72 65 20 53 65 6c 66 74 65 73 74 2c 20 43 4f 4d 20 36 30 31 2e 0d 0a 0d ┆ Hardware Selftest, COM 601. ┆
0x01e0…0200 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 41 42 53 54 52 41 43 54 3a 0d 0a 09 09 84 54 68 69 73 20 ┆ ABSTRACT: This ┆
0x0200…0220 (1,) 6d 61 6e 75 61 6c 20 64 6f 63 75 6d 65 6e 74 73 20 74 68 65 20 43 4f 4d 36 30 31 20 53 42 43 20 ┆manual documents the COM601 SBC ┆
0x0220…0240 73 65 6c 66 74 65 73 74 20 70 72 6f 67 72 61 6d 20 77 68 69 63 68 20 0a 19 89 80 80 63 6f 6e 74 ┆selftest program which cont┆
0x0240…0260 61 69 6e 20 73 65 76 65 72 61 6c 20 70 72 6f 67 72 61 6d 73 20 66 6f 72 20 76 65 72 69 66 79 69 ┆ain several programs for verifyi┆
0x0260…0280 6e 67 20 68 61 72 64 77 61 72 65 20 63 6f 6d 70 6f 6e 65 6e 74 73 20 6f 66 20 0a 19 89 80 80 74 ┆ng hardware components of t┆
0x0280…02a0 68 65 20 49 6e 74 65 6c 6c 69 67 65 6e 74 20 43 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 43 6f 6e ┆he Intelligent Communication Con┆
0x02a0…02c0 74 72 6f 6c 6c 65 72 2e 20 54 68 65 20 43 4f 4d 36 30 31 20 69 73 20 61 6e 20 0a 19 89 80 80 49 ┆troller. The COM601 is an I┆
0x02c0…02e0 4e 54 45 4c 20 4d 75 6c 74 69 62 75 73 20 63 6f 6d 70 61 74 69 62 6c 65 20 73 6c 61 76 65 20 63 ┆NTEL Multibus compatible slave c┆
0x02e0…0300 6f 6e 74 72 6f 6c 6c 65 72 2c 20 62 61 73 65 64 20 75 70 6f 6e 20 61 6e 20 38 20 62 69 74 20 0a ┆ontroller, based upon an 8 bit ┆
0x0300…031d 19 89 80 80 69 41 50 58 20 38 38 20 6d 69 63 72 6f 70 72 6f 63 65 73 73 6f 72 2e 0d 0a ┆ iAPX 88 microprocessor. ┆
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0x035a…0393 Params {
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0x03a0…03c0 41 42 4c 45 20 4f 46 20 43 4f 4e 54 45 4e 54 53 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ABLE OF CONTENTS ┆
0x03c0…03e0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 05 50 41 47 45 20 20 0d 0a 0d 0a 31 2e ┆ PAGE 1.┆
0x03e0…0400 20 49 4e 54 52 4f 44 55 43 54 49 4f 4e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ INTRODUCTION ..................┆
0x0400…0420 (2,) 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 0d 0a 20 20 20 31 2e 32 ┆.................... 1 1.2┆
0x0420…0440 20 53 65 6c 66 74 65 73 74 20 45 71 75 69 70 6d 65 6e 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ Selftest Equipment ............┆
0x0440…0460 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 0d 0a 0d 0a 32 2e 20 54 48 45 20 44 ┆................ 1 2. THE D┆
0x0460…0480 55 41 4c 20 43 48 41 4e 4e 45 4c 20 43 4f 4d 4d 55 4e 49 43 41 54 49 4f 4e 20 41 50 50 52 4f 41 ┆UAL CHANNEL COMMUNICATION APPROA┆
0x0480…04a0 43 48 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 32 0d 0a 0d 0a 33 2e 20 49 4e 54 45 52 52 55 ┆CH ........... 2 3. INTERRU┆
0x04a0…04c0 50 54 20 48 41 4e 44 4c 49 4e 47 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆PT HANDLING ....................┆
0x04c0…04e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 33 0d 0a 20 20 20 33 2e 31 20 49 6e 73 74 72 75 63 ┆............ 3 3.1 Instruc┆
0x04e0…0500 74 69 6f 6e 20 45 78 63 65 70 74 69 6f 6e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆tion Exception .................┆
0x0500…0520 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 33 0d 0a 20 20 20 33 2e 32 20 49 6c 6c 65 67 61 6c 20 49 6e 74 ┆........ 3 3.2 Illegal Int┆
0x0520…0540 65 72 72 75 70 74 73 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆errupts ........................┆
0x0540…0560 2e 2e 2e 2e 20 20 20 33 0d 0a 0d 0a 34 2e 20 42 55 53 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆.... 3 4. BUSTEST .........┆
0x0560…0580 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0580…05a0 2e 2e 20 20 20 36 0d 0a 0d 0a 35 2e 20 b0 f0 54 45 53 54 20 30 20 3d 20 4d 45 4d 4f 52 59 20 54 ┆.. 6 5. TEST 0 = MEMORY T┆
0x05a0…05c0 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆EST ............................┆
0x05c0…05e0 2e 2e 20 20 20 37 0d 0a 20 20 20 35 2e 31 20 50 52 4f 4d 20 43 68 65 63 6b 73 75 6d 20 54 65 73 ┆.. 7 5.1 PROM Checksum Tes┆
0x05e0…0600 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 ┆t ............................ ┆
0x0600…0620 (3,) 20 37 0d 0a 20 20 20 35 2e 32 20 52 41 4d 20 4d 65 6d 6f 72 79 20 54 65 73 74 20 2e 2e 2e 2e 2e ┆ 7 5.2 RAM Memory Test .....┆
0x0620…0640 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 38 0d 0a ┆.......................... 8 ┆
0x0640…0660 20 20 20 20 20 20 20 84 35 2e 32 2e 31 20 4d 65 6d 6f 72 79 20 54 65 73 74 20 50 61 74 74 65 72 ┆ 5.2.1 Memory Test Patter┆
0x0660…0680 6e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 38 0d 0a 20 20 20 ┆n ..................... 8 ┆
0x0680…06a0 20 20 20 20 84 35 2e 32 2e 32 20 4d 65 6d 6f 72 79 20 54 65 73 74 20 46 6c 6f 77 20 2e 2e 2e 2e ┆ 5.2.2 Memory Test Flow ....┆
0x06a0…06c0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 38 0d 0a 0d 0a 36 2e 20 54 ┆.................... 8 6. T┆
0x06c0…06e0 45 53 54 20 31 20 3d 20 43 48 49 50 20 53 45 4c 45 43 54 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e ┆EST 1 = CHIP SELECT TEST .......┆
0x06e0…0700 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 31 0d 0a 0d 0a 37 2e 20 54 45 53 ┆................. 11 7. TES┆
0x0700…0720 54 20 32 20 3d 20 38 32 35 35 41 20 50 41 52 41 4c 4c 45 4c 20 50 4f 52 54 20 54 45 53 54 20 2e ┆T 2 = 8255A PARALLEL PORT TEST .┆
0x0720…0740 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 32 0d 0a 0d 0a 38 2e 20 54 45 53 54 20 ┆............... 12 8. TEST ┆
0x0740…0760 33 20 3d 20 38 32 35 34 20 50 52 4f 47 52 41 4d 4d 41 42 4c 45 20 49 4e 54 45 52 56 41 4c 20 54 ┆3 = 8254 PROGRAMMABLE INTERVAL T┆
0x0760…0780 49 4d 45 52 20 54 45 53 54 20 2e 2e 2e 20 20 20 31 33 0d 0a 0d 0a 39 2e 20 54 45 53 54 20 34 20 ┆IMER TEST ... 13 9. TEST 4 ┆
0x0780…07a0 3d 20 38 32 33 37 41 20 44 49 52 45 43 54 20 4d 45 4d 4f 52 59 20 41 43 43 45 53 53 20 43 4f 4e ┆= 8237A DIRECT MEMORY ACCESS CON┆
0x07a0…07c0 54 52 4f 4c 4c 45 52 20 54 45 53 54 20 20 31 34 0d 0a 0d 0a 31 30 2e 20 54 45 53 54 20 35 20 3d ┆TROLLER TEST 14 10. TEST 5 =┆
0x07c0…07e0 20 38 32 37 34 20 43 48 41 4e 4e 45 4c 20 41 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ 8274 CHANNEL A TEST ...........┆
0x07e0…0800 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 36 0d 0a 0d 0a 31 31 2e 20 54 45 53 54 20 36 20 3d 20 38 ┆.......... 16 11. TEST 6 = 8┆
0x0800…0820 (4,) 32 37 34 20 43 48 41 4e 4e 45 4c 20 42 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆274 CHANNEL B TEST .............┆
0x0820…0840 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 38 0d 0a 20 20 20 20 31 31 2e 31 20 53 74 61 74 75 73 20 53 69 ┆........ 18 11.1 Status Si┆
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0x0860…0880 2e 2e 2e 2e 20 20 31 38 0d 0a 20 20 20 20 31 31 2e 32 20 56 2e 32 34 2f 58 2e 32 31 20 53 65 6c ┆.... 18 11.2 V.24/X.21 Sel┆
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0x08a0…08c0 20 20 32 30 0d 0a 20 20 20 20 31 31 2e 33 20 4c 6f 6f 70 20 42 61 63 6b 20 54 65 73 74 20 2e 2e ┆ 20 11.3 Loop Back Test ..┆
0x08c0…08e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 30 ┆............................ 20┆
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0x08e7…0900 0a 06 69 69 0d 0a b0 a1 54 41 42 4c 45 20 4f 46 20 43 4f 4e 54 45 4e 54 53 ┆ ii TABLE OF CONTENTS┆
0x0900…0920 20 28 63 6f 6e 74 69 6e 75 65 64 29 05 50 41 47 45 0d 0a 0d 0a 31 32 2e 20 54 45 53 54 20 37 20 ┆ (continued) PAGE 12. TEST 7 ┆
0x0920…0940 3d 20 38 32 37 33 20 43 48 41 4e 4e 45 4c 20 43 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆= 8273 CHANNEL C TEST ..........┆
0x0940…0960 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 32 0d 0a 20 20 20 20 31 31 2e 31 20 53 74 61 74 75 73 ┆........... 22 11.1 Status┆
0x0960…0980 20 53 69 67 6e 61 6c 20 43 68 65 63 6b 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ Signal Check ..................┆
0x0980…09a0 2e 2e 2e 2e 2e 2e 2e 20 20 32 32 0d 0a 20 20 20 20 31 31 2e 32 20 56 2e 32 34 2f 58 2e 32 31 20 ┆....... 22 11.2 V.24/X.21 ┆
0x09a0…09c0 53 65 6c 65 63 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆Select .........................┆
0x09c0…09e0 2e 2e 2e 20 20 32 34 0d 0a 20 20 20 20 31 31 2e 33 20 4c 6f 6f 70 20 42 61 63 6b 20 54 65 73 74 ┆... 24 11.3 Loop Back Test┆
0x09e0…0a00 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 ┆ .............................. ┆
0x0a00…0a20 (5,) 20 32 34 0d 0a 0d 0a 0d 0a a1 b0 41 70 70 65 6e 64 69 78 65 73 0d 0a 0d 0a 41 2e 20 20 52 45 46 ┆ 24 Appendixes A. REF┆
0x0a20…0a40 45 52 45 4e 43 45 53 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ERENCES ........................┆
0x0a40…0a60 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 32 39 0d 0a 0d 0a 42 2e 20 20 4c 4f 4f 50 20 ┆............... 29 B. LOOP ┆
0x0a60…0a80 42 41 43 4b 20 43 41 42 4c 45 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆BACK CABLE .....................┆
0x0a80…0aa0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 33 30 0d 0a 0d 0a 43 2e 20 20 43 4f 4d 50 4c 45 54 ┆............. 30 C. COMPLET┆
0x0aa0…0ac0 45 20 45 52 52 4f 52 20 4c 49 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆E ERROR LIST ...................┆
0x0ac0…0ad3 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 33 32 0d 0a 0d 0a ┆........... 32 ┆
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0x0ae0…0b00 a1 0d 0a a1 a1 b0 b0 31 2e 20 49 4e 54 52 4f 44 55 43 54 49 4f 4e 0d 0a 0d 0a 54 68 65 20 43 4f ┆ 1. INTRODUCTION The CO┆
0x0b00…0b20 4d 20 36 30 31 20 69 73 20 61 6e 20 49 6e 74 65 6c 6c 69 67 65 6e 74 20 43 6f 6d 6d 75 6e 69 63 ┆M 601 is an Intelligent Communic┆
0x0b20…0b40 61 74 69 6f 6e 20 43 6f 6e 74 72 6f 6c 6c 65 72 2c 20 77 68 69 63 68 20 0a 69 73 20 61 6e 20 69 ┆ation Controller, which is an i┆
0x0b40…0b60 6e 74 65 6c 6c 69 67 65 6e 74 20 4d 75 6c 74 69 62 75 73 20 53 42 43 20 75 73 65 64 20 74 6f 20 ┆ntelligent Multibus SBC used to ┆
0x0b60…0b80 69 6e 74 65 72 66 61 63 65 20 6d 61 69 6e 66 72 61 6d 65 73 20 0a 6f 72 20 6d 69 6e 69 63 6f 6d ┆interface mainframes or minicom┆
0x0b80…0ba0 70 75 74 65 72 73 20 74 6f 20 74 68 65 20 52 43 20 33 39 20 70 72 6f 64 75 63 74 2e 20 54 68 65 ┆puters to the RC 39 product. The┆
0x0ba0…0bc0 20 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 6d 61 79 20 0a 62 65 20 74 68 65 20 49 42 4d 20 42 ┆ communication may be the IBM B┆
0x0bc0…0be0 53 43 20 61 6e 64 20 74 68 65 20 49 42 4d 20 53 44 4c 43 20 70 72 6f 74 6f 63 6f 6c 73 2e 20 54 ┆SC and the IBM SDLC protocols. T┆
0x0be0…0c00 68 65 20 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 0a 69 73 20 73 79 6e 63 68 72 6f 6e 6f 75 73 ┆he communication is synchronous┆
0x0c00…0c20 (6,) 20 61 6e 64 20 6f 70 65 72 61 74 65 73 20 65 69 74 68 65 72 20 6f 6e 58 2e 32 31 20 6f 72 20 56 ┆ and operates either onX.21 or V┆
0x0c20…0c40 2e 32 34 20 69 6e 74 65 72 66 61 63 65 20 0a 63 69 72 63 75 69 74 73 2e 0d 0a 0d 0a 54 68 69 73 ┆.24 interface circuits. This┆
0x0c40…0c60 20 6d 61 6e 75 61 6c 20 61 73 73 75 6d 65 20 74 68 61 74 20 74 68 65 20 72 65 61 64 65 72 20 69 ┆ manual assume that the reader i┆
0x0c60…0c80 73 20 66 61 6d 69 6c 69 61 72 20 77 69 74 68 20 74 68 65 20 52 43 20 33 39 20 0a 73 65 6c 66 74 ┆s familiar with the RC 39 selft┆
0x0c80…0ca0 65 73 74 20 63 6f 6e 63 65 70 74 20 61 73 20 64 65 73 63 72 69 62 65 64 20 69 6e 20 74 68 65 20 ┆est concept as described in the ┆
0x0ca0…0cc0 6d 61 6e 75 61 6c 20 63 61 6c 6c 65 64 20 22 54 68 65 20 52 43 20 33 39 20 0a 53 65 6c 66 74 65 ┆manual called "The RC 39 Selfte┆
0x0cc0…0ce0 73 74 20 43 6f 6e 63 65 70 74 22 2e 20 54 68 65 20 43 4f 4d 20 36 30 31 20 73 65 6c 66 74 65 73 ┆st Concept". The COM 601 selftes┆
0x0ce0…0d00 74 20 69 6e 63 6c 75 64 65 73 20 38 20 64 69 66 66 65 72 65 6e 74 20 0a 74 65 73 74 73 20 77 68 ┆t includes 8 different tests wh┆
0x0d00…0d20 69 63 68 20 6d 61 79 20 62 65 20 72 75 6e 20 69 6e 20 73 65 76 65 72 61 6c 20 6d 6f 64 65 73 2e ┆ich may be run in several modes.┆
0x0d20…0d40 20 46 69 76 65 20 6f 66 20 74 68 65 73 65 20 74 65 73 74 73 20 0a 61 72 65 20 b0 64 65 66 61 75 ┆ Five of these tests are defau┆
0x0d40…0d60 6c 74 f0 20 74 65 73 74 73 20 77 68 69 63 68 20 61 6c 6c 77 61 79 73 20 65 78 65 63 75 74 65 20 ┆lt tests which allways execute ┆
0x0d60…0d80 61 66 74 65 72 20 61 20 70 6f 77 65 72 20 6f 6e 2e 20 54 68 65 20 0a 19 80 81 80 6c 61 73 74 20 ┆after a power on. The last ┆
0x0d80…0da0 74 68 72 65 65 20 74 65 73 74 73 20 61 72 65 20 b0 65 78 74 65 6e 64 65 64 b0 f0 20 74 65 73 74 ┆three tests are extended test┆
0x0da0…0dc0 73 20 77 68 69 63 68 20 69 73 20 72 75 6e 20 6f 6e 6c 79 20 77 68 65 6e 20 0a 19 80 83 80 72 65 ┆s which is run only when re┆
0x0dc0…0de0 71 75 65 73 74 65 64 20 65 78 70 6c 69 63 69 74 20 62 79 20 61 6e 20 6f 70 65 72 61 74 6f 72 2e ┆quested explicit by an operator.┆
0x0de0…0e00 20 54 68 69 73 20 76 65 72 73 69 6f 6e 20 6f 66 20 74 68 65 20 43 4f 4d 20 0a 19 80 83 80 36 31 ┆ This version of the COM 61┆
0x0e00…0e20 (7,) 30 20 53 42 43 20 73 65 6c 66 74 65 73 74 20 69 6e 63 6c 75 64 65 73 20 6e 6f 20 b0 73 65 70 65 ┆0 SBC selftest includes no sepe┆
0x0e20…0e40 72 61 74 65 6c 79 f0 20 72 75 6e 20 f0 74 65 73 74 73 2e 0d 0a 0d 0a 0d 0a a1 b0 31 2e 32 20 53 ┆rately run tests. 1.2 S┆
0x0e40…0e60 65 6c 66 74 65 73 74 20 45 71 75 69 70 6d 65 6e 74 2e 0d 0a 0d 0a 54 68 65 20 64 65 66 61 75 6c ┆elftest Equipment. The defaul┆
0x0e60…0e80 74 20 70 6f 77 65 72 20 6f 6e 20 74 65 73 74 2c 20 77 68 69 63 68 20 69 73 20 61 6e 20 69 6e 74 ┆t power on test, which is an int┆
0x0e80…0ea0 65 67 72 61 74 65 64 20 70 61 72 74 20 6f 66 20 74 68 65 20 0a 73 79 73 74 65 6d 2c 20 64 6f 65 ┆egrated part of the system, doe┆
0x0ea0…0ec0 73 20 6e 61 74 75 72 61 6c 6c 79 20 6e 6f 74 20 72 65 71 75 69 72 65 20 61 6e 79 20 73 70 65 63 ┆s naturally not require any spec┆
0x0ec0…0ee0 69 61 6c 20 74 65 73 74 20 65 71 75 69 70 6d 65 6e 74 20 0a 69 6e 73 74 61 6c 6c 65 64 2e 0d 0a ┆ial test equipment installed. ┆
0x0ee0…0f00 0d 0a 54 68 65 20 b0 65 78 74 65 6e 64 65 64 20 70 61 72 74 20 f0 6f 66 20 74 68 65 20 73 65 6c ┆ The extended part of the sel┆
0x0f00…0f20 66 74 65 73 74 20 69 6e 20 63 6f 6e 74 72 61 73 74 20 72 65 71 75 69 72 65 73 20 61 20 0a 19 80 ┆ftest in contrast requires a ┆
0x0f20…0f40 81 80 73 70 65 63 69 61 6c 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 20 63 6f 6e 6e 65 63 ┆ special loop back cable connec┆
0x0f40…0f60 74 65 64 20 28 73 65 65 20 61 70 70 65 6e 64 69 78 20 41 29 2e 20 54 68 69 73 20 6c 6f 6f 70 20 ┆ted (see appendix A). This loop ┆
0x0f60…0f80 0a 19 80 81 80 62 61 63 6b 20 63 61 62 6c 65 20 69 73 20 75 73 65 64 20 62 79 20 74 68 65 20 38 ┆ back cable is used by the 8┆
0x0f80…0fa0 32 37 33 20 53 44 4c 43 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 74 65 73 74 20 61 6e 64 20 62 79 20 ┆273 SDLC controller test and by ┆
0x0fa0…0fc0 0a 19 80 81 80 74 68 65 20 38 32 37 34 20 4d 50 53 43 2f 48 44 4c 43 20 63 6f 6e 74 72 6f 6c 6c ┆ the 8274 MPSC/HDLC controll┆
0x0fc0…0fe0 65 72 20 63 68 61 6e 6e 65 6c 20 42 20 74 65 73 74 2e 20 54 68 65 20 65 78 74 65 6e 64 65 64 20 ┆er channel B test. The extended ┆
0x0fe0…1000 0a 19 80 81 80 70 61 72 74 20 6f 66 20 74 68 65 20 74 65 73 74 20 69 73 20 6f 6e 6c 79 20 72 75 ┆ part of the test is only ru┆
0x1000…1020 (8,) 6e 20 61 73 20 61 20 72 65 73 75 6c 74 20 6f 66 20 63 6f 6d 6d 61 6e 64 73 20 67 69 76 65 6e 20 ┆n as a result of commands given ┆
0x1020…1040 74 6f 20 0a 19 80 81 80 74 68 65 20 22 74 65 73 74 2d 68 6f 73 74 22 20 76 69 61 20 61 20 63 6f ┆to the "test-host" via a co┆
0x1040…1060 6e 6e 65 63 74 65 64 20 63 6f 6e 73 6f 6c 65 2e 54 68 65 73 65 20 74 65 73 74 73 20 61 72 65 20 ┆nnected console.These tests are ┆
0x1060…1080 75 73 65 64 20 0a 19 80 81 80 69 6e 20 74 68 65 20 a1 b0 e1 62 75 72 6e 20 69 6e 20 f0 70 68 61 ┆used in the burn in pha┆
0x1080…10a0 73 65 20 62 79 20 74 68 65 20 6d 61 6e 75 66 61 63 74 75 72 69 6e 67 20 64 65 70 61 72 74 6d 65 ┆se by the manufacturing departme┆
0x10a0…10c0 6e 74 20 6f 72 20 62 79 20 0a 19 80 82 80 74 65 63 68 6e 69 63 69 61 6e 73 20 61 73 20 70 61 72 ┆nt or by technicians as par┆
0x10c0…10dc 74 20 6f 66 20 74 68 65 69 72 20 64 65 62 75 67 67 69 6e 67 20 74 6f 6f 6c 2e 0d 0a ┆t of their debugging tool. ┆
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0x10e0…1100 a1 a1 b0 b0 32 2e 20 54 48 45 20 44 55 41 4c 20 43 48 41 4e 4e 45 4c 20 43 4f 4d 4d 55 4e 49 43 ┆ 2. THE DUAL CHANNEL COMMUNIC┆
0x1100…1120 41 54 49 4f 4e 20 41 50 50 52 4f 41 43 48 0d 0a 0d 0a 54 68 65 20 43 4f 4d 20 36 30 31 20 53 42 ┆ATION APPROACH The COM 601 SB┆
0x1120…1140 43 20 73 65 6c 66 74 65 73 74 20 b0 64 6f 65 73 20 6e 6f 74 f0 20 73 75 70 70 6f 72 74 73 20 74 ┆C selftest does not supports t┆
0x1140…1160 68 65 20 44 75 61 6c 20 43 68 61 6e 6e 65 6c 20 0a 19 80 81 80 43 6f 6d 6d 75 6e 69 63 61 74 69 ┆he Dual Channel Communicati┆
0x1160…1180 6f 6e 20 66 61 63 69 6c 69 74 79 20 61 73 20 64 65 73 63 72 69 62 65 64 20 69 6e 20 74 68 65 20 ┆on facility as described in the ┆
0x1180…11a0 22 52 43 20 33 39 20 53 65 6c 66 74 65 73 74 20 0a 19 80 81 80 43 6f 6e 63 65 70 74 22 2e 20 54 ┆"RC 39 Selftest Concept". T┆
0x11a0…11c0 68 65 20 72 65 61 73 6f 6e 20 74 6f 20 74 68 69 73 20 69 73 20 74 68 61 74 20 74 68 65 20 43 4f ┆he reason to this is that the CO┆
0x11c0…11e0 4d 20 36 30 31 20 69 73 20 61 6e 20 6f 6c 64 20 0a 19 80 81 80 62 6f 61 72 64 20 64 65 73 69 67 ┆M 601 is an old board desig┆
0x11e0…1200 6e 65 64 20 77 69 74 68 6f 75 74 20 61 6e 20 61 73 79 6e 63 68 72 6f 6e 6f 75 73 20 56 2e 32 34 ┆ned without an asynchronous V.24┆
0x1200…120d (9,) 20 69 6e 74 65 72 66 61 63 65 2e 0d 0a ┆ interface. ┆
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0x1210…1220 0a a1 b0 a1 33 2e 20 49 4e 54 45 52 52 55 50 54 ┆ 3. INTERRUPT┆
0x1220…1240 20 48 41 4e 44 4c 49 4e 47 0d 0a 0d 0a 57 68 65 6e 20 74 68 65 20 52 43 20 33 39 2c 20 43 4f 4d ┆ HANDLING When the RC 39, COM┆
0x1240…1260 20 36 30 31 2c 20 53 42 43 20 73 65 6c 66 74 65 73 74 20 68 61 73 20 66 69 6e 69 73 68 65 64 20 ┆ 601, SBC selftest has finished ┆
0x1260…1280 74 68 65 20 6d 65 6d 6f 72 79 20 0a 74 65 73 74 2c 20 61 20 73 65 74 20 6f 66 20 64 65 66 61 75 ┆the memory test, a set of defau┆
0x1280…12a0 6c 74 20 69 6e 74 65 72 72 75 70 74 20 76 65 63 74 6f 72 73 20 61 72 65 20 70 6c 61 63 65 64 20 ┆lt interrupt vectors are placed ┆
0x12a0…12c0 69 6e 20 74 68 65 20 0a 6d 65 6d 6f 72 79 2e 20 54 68 65 73 65 20 76 65 63 74 6f 72 73 20 61 72 ┆in the memory. These vectors ar┆
0x12c0…12e0 65 20 75 73 65 64 20 74 6f 20 68 61 6e 64 6c 65 20 62 6f 74 68 20 65 78 70 65 63 74 65 64 20 61 ┆e used to handle both expected a┆
0x12e0…1300 6e 64 20 0a 75 6e 65 78 70 65 63 74 65 64 20 69 6e 74 65 72 72 75 70 74 73 2e 20 54 68 65 72 65 ┆nd unexpected interrupts. There┆
0x1300…1320 20 61 72 65 20 74 77 6f 20 6b 69 6e 64 20 6f 66 20 75 6e 65 78 70 65 63 74 65 64 20 0a 69 6e 74 ┆ are two kind of unexpected int┆
0x1320…1340 65 72 72 75 70 74 73 2e 20 4f 6e 65 20 69 73 20 68 61 6e 64 6c 65 64 20 62 79 20 74 68 65 20 69 ┆errupts. One is handled by the i┆
0x1340…1360 6e 74 65 72 72 75 70 74 20 70 72 6f 63 65 64 75 72 65 20 66 6f 72 20 0a 69 6e 74 65 72 6e 61 6c ┆nterrupt procedure for internal┆
0x1360…1380 20 69 41 50 58 20 38 30 38 38 20 69 6e 73 74 72 75 63 74 69 6f 6e 20 69 6e 74 65 72 72 75 70 74 ┆ iAPX 8088 instruction interrupt┆
0x1380…13a0 73 2c 20 61 6e 64 20 74 68 65 20 6f 74 68 65 72 20 69 73 20 0a 68 61 6e 64 6c 65 64 20 62 79 20 ┆s, and the other is handled by ┆
0x13a0…13c0 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 70 72 6f 63 65 64 75 72 65 20 66 6f 72 20 69 6c 6c 65 ┆the interrupt procedure for ille┆
0x13c0…13e0 67 61 6c 20 64 65 76 69 63 65 20 0a 69 6e 74 65 72 72 75 70 74 73 2e 0d 0a 0d 0a 0d 0a b0 a1 33 ┆gal device interrupts. 3┆
0x13e0…1400 2e 31 20 49 6e 73 74 72 75 63 74 69 6f 6e 20 45 78 63 65 70 74 69 6f 6e 2e 0d 0a 0d 0a 49 66 20 ┆.1 Instruction Exception. If ┆
0x1400…1420 (10,) 61 6e 20 49 6e 73 74 72 75 63 74 69 6f 6e 20 45 78 63 65 70 74 69 6f 6e 20 69 6e 74 65 72 72 75 ┆an Instruction Exception interru┆
0x1420…1440 70 74 20 6f 63 63 75 72 73 2c 20 69 74 20 69 73 20 6c 69 6b 65 6c 79 20 74 6f 20 0a 62 65 6c 69 ┆pt occurs, it is likely to beli┆
0x1440…1460 65 76 65 20 74 68 61 74 20 74 68 69 73 20 77 61 73 20 63 61 75 73 65 64 20 62 79 20 61 20 6d 61 ┆eve that this was caused by a ma┆
0x1460…1480 6c 66 75 6e 63 74 69 6f 6e 20 6f 66 20 74 68 65 20 69 41 50 58 20 0a 38 30 38 38 2c 20 62 65 63 ┆lfunction of the iAPX 8088, bec┆
0x1480…14a0 61 75 73 65 20 74 68 69 73 20 69 6e 74 65 72 72 75 70 74 20 69 73 20 72 65 6c 61 74 65 64 20 74 ┆ause this interrupt is related t┆
0x14a0…14c0 6f 20 73 6f 6d 65 20 43 50 55 20 0a 69 6e 73 74 72 75 63 74 69 6f 6e 2e 20 49 66 20 74 68 69 73 ┆o some CPU instruction. If this┆
0x14c0…14e0 20 65 72 72 6f 72 20 68 61 70 70 65 6e 73 20 74 68 65 20 74 65 73 74 20 70 72 6f 67 72 61 6d 20 ┆ error happens the test program ┆
0x14e0…1500 77 72 69 74 65 73 20 0a 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 6d 65 73 73 61 67 65 20 74 6f ┆writes the following message to┆
0x1500…1520 20 74 68 65 20 62 75 66 66 65 72 20 3a 0d 0a 0d 0a b0 45 58 43 45 50 54 49 4f 4e 20 3a 20 69 6e ┆ the buffer : EXCEPTION : in┆
0x1520…1540 73 74 72 75 63 74 69 6f 6e 20 69 6e 74 65 72 72 75 70 74 0d 0a 0d 0a 0d 0a a1 b0 33 2e 32 20 49 ┆struction interrupt 3.2 I┆
0x1540…1560 6c 6c 65 67 61 6c 20 49 6e 74 65 72 72 75 70 74 73 2e 0d 0a 0d 0a 4f 6e 63 65 20 75 70 6f 6e 20 ┆llegal Interrupts. Once upon ┆
0x1560…1580 63 6f 6d 70 6c 65 74 69 6f 6e 20 6f 66 20 65 61 63 68 20 74 65 73 74 20 70 72 6f 67 72 61 6d 20 ┆completion of each test program ┆
0x1580…15a0 74 68 65 20 72 65 63 65 70 74 69 6f 6e 20 6f 66 20 0a 69 6e 74 65 72 72 75 70 74 73 20 61 72 65 ┆the reception of interrupts are┆
0x15a0…15c0 20 65 6e 61 62 65 6c 65 64 2e 20 4f 6e 6c 79 20 74 77 6f 20 6f 66 20 74 68 65 20 69 6e 74 65 72 ┆ enabeled. Only two of the inter┆
0x15c0…15e0 72 75 70 74 20 72 65 71 75 65 73 74 20 0a 6c 69 6e 65 73 20 77 69 6c 6c 20 62 65 20 75 73 65 64 ┆rupt request lines will be used┆
0x15e0…1600 20 69 6e 20 74 68 65 20 73 65 6c 66 74 65 73 74 20 61 73 20 6c 65 67 61 6c 20 69 6e 74 65 72 72 ┆ in the selftest as legal interr┆
0x1600…1620 (11,) 75 70 74 73 2e 20 54 68 69 73 20 0a 69 73 20 74 68 65 20 74 69 6d 65 72 30 20 61 6e 64 20 74 68 ┆upts. This is the timer0 and th┆
0x1620…1640 65 20 74 69 6d 65 72 31 20 69 6e 74 65 72 72 75 70 74 73 2c 20 74 68 65 79 20 61 72 65 20 62 6f ┆e timer1 interrupts, they are bo┆
0x1640…1660 74 68 20 72 65 61 6c 20 0a 74 69 6d 65 20 63 6c 6f 63 6b 73 20 67 65 6e 65 72 61 74 65 64 20 62 ┆th real time clocks generated b┆
0x1660…1680 79 20 74 68 65 20 38 32 35 34 20 70 72 6f 67 61 6d 6d 61 62 6c 65 20 69 6e 74 65 72 76 61 6c 20 ┆y the 8254 progammable interval ┆
0x1680…16a0 0a 74 69 6d 65 72 2e 54 69 6d 65 72 20 30 20 69 73 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 69 ┆ timer.Timer 0 is connected to i┆
0x16a0…16c0 6e 74 65 72 72 75 70 74 20 72 65 71 75 65 73 74 20 49 52 30 20 61 6d 64 20 0a 74 69 6d 65 72 31 ┆nterrupt request IR0 amd timer1┆
0x16c0…16e0 20 74 6f 20 49 52 34 2e 20 41 6c 6c 20 74 68 65 20 6f 74 68 65 72 20 69 6e 74 65 72 72 75 70 74 ┆ to IR4. All the other interrupt┆
0x16e0…1700 73 20 77 69 6c 6c 20 62 65 20 64 65 63 6f 64 65 64 20 61 73 20 0a 69 6c 6c 65 67 61 6c 2c 20 61 ┆s will be decoded as illegal, a┆
0x1700…1720 6e 64 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 6d 65 73 73 61 67 65 20 61 72 65 20 63 6f 70 ┆nd the following message are cop┆
0x1720…1740 69 65 64 20 74 6f 20 74 68 65 20 62 75 66 66 65 72 20 3a 0d 0a 0d 0a b0 45 58 43 45 50 54 49 4f ┆ied to the buffer : EXCEPTIO┆
0x1740…1760 4e 20 3a 20 69 6c 6c 65 67 61 6c 20 69 6e 74 65 72 72 75 70 74 20 20 20 20 6c 65 76 65 6c 20 49 ┆N : illegal interrupt level I┆
0x1760…1780 52 53 52 0d 0a 0d 0a 8c 83 b0 0a 54 68 65 20 6c 65 76 65 6c 20 69 6e 66 6f 72 6d 61 74 69 6f 6e ┆RSR The level information┆
0x1780…17a0 20 69 73 20 b0 6e 6f 74 f0 20 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 74 6f 20 74 68 65 20 69 ┆ is not corresponding to the i┆
0x17a0…17c0 6e 74 65 72 72 75 70 74 20 0a 19 80 81 80 72 65 71 75 65 73 74 20 6c 65 76 65 6c 2e 20 49 6e 73 ┆nterrupt request level. Ins┆
0x17c0…17e0 74 65 61 64 20 22 53 52 22 20 69 73 20 74 68 65 20 68 65 78 61 64 65 63 69 6d 61 6c 20 63 6f 6e ┆tead "SR" is the hexadecimal con┆
0x17e0…1800 74 65 6e 74 20 6f 66 20 74 68 65 20 0a 19 80 81 80 38 32 35 39 41 20 69 6e 74 65 72 72 75 70 74 ┆tent of the 8259A interrupt┆
0x1800…1820 (12,) 20 63 6f 6e 74 72 6f 6c 6c 65 72 73 20 69 6e 74 65 72 72 75 70 74 20 49 6e 20 53 65 72 76 69 63 ┆ controllers interrupt In Servic┆
0x1820…1840 65 20 52 65 67 69 73 74 65 72 20 0a 19 80 81 80 28 49 53 52 29 2c 20 61 6e 64 20 22 49 52 22 20 ┆e Register (ISR), and "IR" ┆
0x1840…1860 69 73 20 74 68 65 20 68 65 78 61 64 65 63 69 6d 61 6c 20 63 6f 6e 74 65 6e 74 20 6f 66 20 74 68 ┆is the hexadecimal content of th┆
0x1860…1880 65 20 49 6e 74 65 72 72 75 70 74 20 0a 19 80 81 80 52 65 71 75 65 73 74 20 52 65 67 69 73 74 65 ┆e Interrupt Request Registe┆
0x1880…18a0 72 20 28 49 52 52 29 2e 20 49 6e 20 62 6f 74 68 20 49 53 52 20 61 6e 64 20 49 52 52 20 69 6e 74 ┆r (IRR). In both ISR and IRR int┆
0x18a0…18c0 65 72 72 75 70 74 20 72 65 71 75 65 73 74 20 0a 19 80 81 80 30 20 63 6f 72 72 65 73 70 6f 6e 64 ┆errupt request 0 correspond┆
0x18c0…18e0 73 20 74 6f 20 62 69 74 20 30 20 28 6c 65 61 73 74 20 73 69 67 6e 69 66 69 63 61 6e 74 20 62 69 ┆s to bit 0 (least significant bi┆
0x18e0…1900 74 29 2c 20 49 52 37 20 74 6f 20 62 69 74 20 37 20 0a 19 80 81 80 61 6e 64 20 73 6f 20 6f 6e 2e ┆t), IR7 to bit 7 and so on.┆
0x1900…1920 20 57 68 65 6e 20 61 6e 20 69 6e 74 65 72 72 75 70 74 20 69 73 20 73 65 72 76 69 63 65 64 20 74 ┆ When an interrupt is serviced t┆
0x1920…1940 68 65 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 62 69 74 20 0a 19 80 81 80 69 6e 20 74 68 65 20 ┆hecorresponding bit in the ┆
0x1940…1960 49 53 52 20 72 65 67 69 73 74 65 72 20 73 68 6f 75 6c 64 20 62 65 20 73 65 74 2c 20 61 6e 64 20 ┆ISR register should be set, and ┆
0x1960…1980 77 68 65 6e 20 61 6e 20 69 6e 74 65 72 72 75 70 74 20 69 73 20 0a 19 80 81 80 72 65 71 75 65 73 ┆when an interrupt is reques┆
0x1980…19a0 74 65 64 20 74 68 65 20 63 6f 72 72 65 73 70 6f 6e 64 69 6e 67 20 62 69 74 20 69 6e 20 74 68 65 ┆ted the corresponding bit in the┆
0x19a0…19c0 20 49 52 52 20 72 65 67 69 73 74 65 72 73 20 73 68 6f 75 6c 64 20 0a 19 80 81 80 62 65 20 73 65 ┆ IRR registers should be se┆
0x19c0…19e0 74 2e 20 49 66 20 61 6e 20 69 6c 6c 65 67 61 6c 20 69 6e 74 65 72 72 75 70 74 20 69 73 20 73 72 ┆t. If an illegal interrupt is sr┆
0x19e0…1a00 76 69 63 65 64 20 61 6e 64 20 74 68 65 20 63 6f 6e 74 65 6e 74 20 6f 66 20 0a 19 80 81 80 74 68 ┆viced and the content of th┆
0x1a00…1a20 (13,) 65 20 49 53 52 20 72 65 67 69 73 74 65 72 20 69 73 20 30 30 2c 20 69 6e 64 69 63 61 74 69 6e 67 ┆e ISR register is 00, indicating┆
0x1a20…1a40 20 6e 6f 20 69 6e 74 65 72 72 75 70 74 20 69 6e 20 73 65 72 76 69 63 65 2c 20 0a 19 80 81 80 74 ┆ no interrupt in service, t┆
0x1a40…1a60 68 65 6e 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 69 73 20 61 20 72 65 73 75 6c 74 20 6f 66 ┆hen the interrupt is a result of┆
0x1a60…1a80 20 61 20 73 70 69 6b 65 20 6f 6e 20 6f 6e 65 20 6f 66 20 74 68 65 20 38 20 0a 19 80 81 80 69 6e ┆ a spike on one of the 8 in┆
0x1a80…1a9c 74 65 72 72 75 70 74 20 72 65 71 75 65 73 74 20 6c 69 6e 65 73 2c 20 61 6e 64 20 0a ┆terrupt request lines, and ┆
0x1a9c…1a9f FormFeed {
0x1a9c…1a9f 0c 81 9c ┆ ┆
0x1a9c…1a9f }
0x1a9f…1aa0 0a ┆ ┆
0x1aa0…1ad9 Params {
0x1aa0…1ad9 04 00 27 4e 0c 00 08 00 00 00 00 03 01 48 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N H1` ┆
0x1aa0…1ad9 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x1aa0…1ad9 }
0x1ad9…1b12 Params {
0x1ad9…1b12 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x1ad9…1b12 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x1ad9…1b12 }
0x1b12…1b20 0a a1 52 65 71 75 65 73 74 20 6c 69 6e 65 ┆ Request line┆
0x1b20…1b40 20 20 20 49 6e 74 65 72 72 75 70 74 20 6e 61 6d 65 20 20 20 20 56 65 63 74 6f 72 20 74 79 70 65 ┆ Interrupt name Vector type┆
0x1b40…1b60 20 20 20 20 52 65 6c 61 74 65 64 20 69 6e 73 74 72 75 63 74 69 6f 6e 73 20 20 20 20 0d 0a 0d 0a ┆ Related instructions ┆
0x1b60…1b80 20 20 69 6e 74 65 72 6e 61 6c 20 20 20 20 20 44 69 76 69 64 65 20 65 72 72 6f 72 09 09 20 20 20 ┆ internal Divide error ┆
0x1b80…1ba0 30 20 09 09 09 44 49 56 2c 20 49 44 49 56 0d 0a 0d 0a 20 20 69 6e 74 65 72 6e 61 6c 20 20 20 20 ┆0 DIV, IDIV internal ┆
0x1ba0…1bc0 20 53 69 6e 67 6c 65 20 73 74 65 70 09 09 20 20 20 31 20 09 09 09 41 4c 4c 0d 0a 0d 0a 20 20 69 ┆ Single step 1 ALL i┆
0x1bc0…1be0 6e 74 65 72 6e 61 6c 20 20 20 20 20 4e 4d 49 09 09 09 20 20 20 20 20 20 20 20 32 09 20 20 20 20 ┆nternal NMI 2 ┆
0x1be0…1c00 20 09 09 41 4c 4c 0d 0a 0d 0a 20 20 69 6e 74 65 72 6e 61 6c 20 20 20 20 20 42 72 65 61 6b 70 6f ┆ ALL internal Breakpo┆
0x1c00…1c20 (14,) 69 6e 74 09 20 20 20 20 20 20 20 20 33 20 09 09 09 49 4e 54 20 33 0d 0a 0d 0a 20 20 69 6e 74 65 ┆int 3 INT 3 inte┆
0x1c20…1c40 72 6e 61 6c 20 20 20 20 20 4f 77 65 72 66 6c 6f 77 07 09 20 20 20 20 20 20 20 20 34 20 09 09 09 ┆rnal Owerflow 4 ┆
0x1c40…1c60 49 4e 54 30 0d 0a 0d 0a 20 20 69 6e 74 65 72 6e 61 6c 20 20 20 20 20 6e 6f 74 20 75 73 65 64 09 ┆INT0 internal not used ┆
0x1c60…1c80 09 09 20 20 20 35 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 6e 6f 74 20 75 73 65 ┆ 5 not use┆
0x1c80…1ca0 64 09 09 20 20 20 20 20 20 20 20 36 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 6e ┆d 6 n┆
0x1ca0…1cc0 6f 74 20 75 73 65 64 09 09 20 20 20 20 20 20 20 20 37 0d 0a a1 20 20 20 20 20 20 20 20 20 20 20 ┆ot used 7 ┆
0x1cc0…1ce0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x1ce0…1d00 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 0d 0a ┆ ┆
0x1d00…1d20 0d 0a 0d 0a 0d 0a 52 a1 65 71 75 65 73 74 20 6c 69 6e 65 20 20 20 49 6e 74 65 72 72 75 70 74 20 ┆ R equest line Interrupt ┆
0x1d20…1d40 6e 61 6d 65 20 20 20 20 56 65 63 74 6f 72 20 74 79 70 65 20 20 20 20 52 65 6c 61 74 65 64 20 69 ┆name Vector type Related i┆
0x1d40…1d60 6e 74 65 72 72 75 70 74 20 6c 65 76 65 6c 20 20 20 20 20 20 20 20 20 20 20 0d 0a 0d 0a 20 20 49 ┆nterrupt level I┆
0x1d60…1d80 52 30 20 20 20 20 20 20 20 20 20 20 74 69 6d 65 72 30 09 09 09 20 20 20 33 32 20 20 20 20 20 20 ┆R0 timer0 32 ┆
0x1d80…1da0 20 20 20 20 20 20 20 20 09 33 32 0d 0a 0d 0a 20 20 49 52 31 20 20 20 20 20 20 20 20 20 20 38 32 ┆ 32 IR1 82┆
0x1da0…1dc0 37 34 69 6e 74 09 09 09 20 20 20 33 33 09 09 09 33 33 0d 0a 0d 0a 20 20 49 52 32 20 20 20 20 20 ┆74int 33 33 IR2 ┆
0x1dc0…1de0 20 20 20 20 20 38 32 37 33 52 58 69 6e 74 20 20 20 20 20 20 20 20 20 20 20 20 20 33 34 09 09 09 ┆ 8273RXint 34 ┆
0x1de0…1e00 33 34 0d 0a 0d 0a 20 20 49 52 33 20 20 20 20 20 20 20 20 20 20 38 32 37 33 54 58 69 6e 74 09 09 ┆34 IR3 8273TXint ┆
0x1e00…1e20 (15,) 20 20 20 33 35 09 09 09 33 35 0d 0a 0d 0a 20 20 49 52 34 20 20 20 20 20 20 20 20 20 20 74 69 6d ┆ 35 35 IR4 tim┆
0x1e20…1e40 65 72 31 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 33 36 20 20 20 20 20 20 20 20 20 20 20 ┆er1 36 ┆
0x1e40…1e60 20 20 20 20 33 36 0d 0a 0d 0a 20 20 49 52 35 20 20 20 20 20 20 20 20 20 20 4f 42 20 66 6c 61 67 ┆ 36 IR5 OB flag┆
0x1e60…1e80 20 69 6e 74 09 20 20 20 20 20 20 20 20 33 37 09 09 09 33 37 0d 0a 0d 0a 20 20 49 52 36 20 20 20 ┆ int 37 37 IR6 ┆
0x1e80…1ea0 20 20 20 20 20 20 20 53 42 58 20 69 6e 74 30 20 6f 72 20 53 42 58 20 69 6e 74 31 20 20 33 38 09 ┆ SBX int0 or SBX int1 38 ┆
0x1ea0…1ec0 09 09 33 38 0d 0a 0d 0a 20 20 49 52 37 20 20 20 20 20 20 20 20 20 20 45 4f 50 20 69 6e 74 20 20 ┆ 38 IR7 EOP int ┆
0x1ec0…1ee0 20 20 20 20 20 20 20 20 20 20 20 20 20 33 39 09 09 09 33 39 0d 0a a1 20 20 20 20 20 20 20 20 20 ┆ 39 39 ┆
0x1ee0…1f00 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
[…0x1…]
0x1f20…1f40 20 0d 0a 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 a1 e1 09 09 a1 49 6e 74 ┆ Int┆
0x1f40…1f55 65 72 72 75 70 74 20 4c 65 76 65 6c 20 54 61 62 6c 65 2e 0d 0a ┆errupt Level Table. ┆
0x1f55…1f8e Params {
0x1f55…1f8e 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x1f55…1f8e 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x1f55…1f8e }
0x1f8e…1fc7 Params {
0x1f8e…1fc7 04 00 27 4e 0c 00 08 00 00 00 00 03 01 48 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N H1` ┆
0x1f8e…1fc7 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x1f8e…1fc7 }
0x1fc7…1fc8 0a ┆ ┆
0x1fc8…1fcb FormFeed {
0x1fc8…1fcb 0c 82 fa ┆ ┆
0x1fc8…1fcb }
0x1fcb…1fe0 0a a1 b0 34 20 42 55 53 54 45 53 54 2e 0d 0a 0d 0a 41 73 20 61 ┆ 4 BUSTEST. As a┆
0x1fe0…2000 20 70 61 72 74 20 6f 66 20 74 68 65 20 69 6e 69 74 69 61 6c 69 7a 61 74 69 6f 6e 20 61 20 73 69 ┆ part of the initialization a si┆
0x2000…2020 (16,) 6d 70 6c 65 20 43 50 55 20 74 6f 20 6d 65 6d 6f 72 79 20 0a 62 75 73 74 65 73 74 20 69 73 20 6d ┆mple CPU to memory bustest is m┆
0x2020…2040 61 64 65 2e 0d 0a 0d 0a 54 68 65 20 62 75 73 74 65 73 74 20 75 73 65 73 20 6f 6e 65 20 77 6f 72 ┆ade. The bustest uses one wor┆
0x2040…2060 64 20 69 6e 20 52 41 4d 2d 6d 65 6d 6f 72 79 2e 20 54 68 69 73 20 77 6f 72 64 20 69 73 20 0a 69 ┆d in RAM-memory. This word is i┆
0x2060…2080 6e 69 74 69 61 6c 69 7a 65 64 20 77 69 74 68 20 61 20 7a 65 72 6f 2c 20 77 68 65 72 65 61 66 74 ┆nitialized with a zero, whereaft┆
0x2080…20a0 65 72 20 61 20 6f 6e 65 2d 62 69 74 20 69 73 20 73 68 69 66 74 65 64 20 0a 66 72 6f 6d 20 74 68 ┆er a one-bit is shifted from th┆
0x20a0…20c0 65 20 4c 53 42 20 74 6f 77 61 72 64 73 20 74 68 65 20 4d 53 42 2e 20 46 6f 72 20 65 76 65 72 79 ┆e LSB towards the MSB. For every┆
0x20c0…20e0 20 73 68 69 66 74 2c 20 74 68 65 20 70 61 74 74 65 72 6e 20 0a 69 73 20 72 65 61 64 20 62 61 63 ┆ shift, the pattern is read bac┆
0x20e0…2100 6b 20 61 6e 64 20 63 68 65 63 6b 65 64 2e 20 53 68 6f 75 6c 64 20 69 74 20 68 61 70 70 65 6e 2c ┆k and checked. Should it happen,┆
0x2100…2120 20 74 68 61 74 20 74 68 65 20 70 61 74 74 65 72 6e 20 0a 77 61 73 20 6e 6f 74 20 77 72 69 74 74 ┆ that the pattern was not writt┆
0x2120…2140 65 6e 2c 20 74 68 65 20 70 72 6f 67 72 61 6d 20 77 69 6c 6c 20 6c 6f 6f 70 20 63 6f 75 6e 74 69 ┆en, the program will loop counti┆
0x2140…2160 6e 75 6f 73 6c 79 20 74 72 79 69 6e 67 20 0a 74 6f 20 72 65 61 64 20 74 68 65 20 63 6f 72 72 65 ┆nuosly trying to read the corre┆
0x2160…2180 63 74 20 70 61 74 74 65 72 6e 2e 20 54 68 69 73 20 6d 65 61 6e 73 20 74 68 61 74 20 69 66 20 74 ┆ct pattern. This means that if t┆
0x2180…21a0 68 65 20 0a 62 75 73 73 69 67 6e 61 6c 73 20 61 72 65 20 63 68 65 63 6b 65 64 20 62 79 20 61 6e ┆he bussignals are checked by an┆
0x21a0…21c0 20 6f 73 63 69 6c 6c 6f 73 63 6f 70 65 20 61 6e 64 20 74 68 65 20 77 6f 72 64 20 72 65 61 64 20 ┆ oscilloscope and the word read ┆
0x21c0…21e0 0a 69 73 20 66 6f 75 6e 64 20 74 6f 20 68 61 76 65 20 62 69 74 73 20 30 20 61 6e 64 20 31 20 74 ┆ is found to have bits 0 and 1 t┆
0x21e0…2200 6f 20 74 68 65 20 6f 6e 65 20 6c 65 76 65 6c 20 61 6e 64 20 74 68 65 20 72 65 73 74 20 0a 74 6f ┆o the one level and the rest to┆
0x2200…2220 (17,) 20 74 68 65 20 7a 65 72 6f 20 6c 65 76 65 6c 2c 20 69 74 20 6d 75 73 74 20 62 65 20 62 69 74 20 ┆ the zero level, it must be bit ┆
0x2220…2240 32 2c 20 74 68 61 74 20 63 6f 6e 74 61 69 6e 73 20 74 68 65 20 0a 65 72 72 6f 72 2e 0d 0a 0d 0a ┆2, that contains the error. ┆
0x2240…2260 57 68 65 6e 20 74 68 65 20 6f 6e 65 20 62 69 74 20 68 61 73 20 62 65 65 6e 20 73 68 69 66 74 65 ┆When the one bit has been shifte┆
0x2260…2280 64 20 74 72 6f 75 67 68 20 74 68 65 20 65 6e 74 69 72 65 20 77 6f 72 64 2c 20 0a 74 68 69 73 20 ┆d trough the entire word, this ┆
0x2280…22a0 77 6f 72 64 20 69 73 20 72 65 69 6e 69 74 69 61 6c 69 7a 65 64 20 74 6f 20 61 6c 6c 20 6f 6e 65 ┆word is reinitialized to all one┆
0x22a0…22c0 73 20 61 6e 64 20 61 20 7a 65 72 6f 2d 62 69 74 20 69 73 20 0a 73 68 69 66 74 65 64 20 74 72 6f ┆s and a zero-bit is shifted tro┆
0x22c0…22e0 75 67 68 20 69 74 2e 20 0d 0a 0d 0a 54 68 69 73 20 74 65 73 74 20 69 73 20 75 6e 61 62 6c 65 20 ┆ugh it. This test is unable ┆
0x22e0…2300 74 6f 20 70 72 6f 64 75 63 65 20 61 6e 79 20 65 72 72 6f 72 2d 6d 65 73 73 61 67 65 2c 20 61 6e ┆to produce any error-message, an┆
0x2300…2320 64 20 69 73 20 0a 6f 6e 6c 79 20 72 75 6e 20 61 73 20 61 20 72 65 73 75 6c 74 20 6f 66 20 70 6f ┆d is only run as a result of po┆
0x2320…233b 77 65 72 20 6f 6e 20 6f 72 20 65 78 74 65 72 6e 61 6c 20 72 65 73 65 74 2e 0d 0a ┆wer on or external reset. ┆
0x233b…233e FormFeed {
0x233b…233e 0c 82 88 ┆ ┆
0x233b…233e }
0x233e…2340 0a a1 ┆ ┆
0x2340…2360 b0 35 2e 20 b0 54 65 73 74 20 30 20 3d 20 f0 b0 4d 45 4d 4f 52 59 20 54 45 53 54 2e 0d 0a 0d 0a ┆ 5. Test 0 = MEMORY TEST. ┆
0x2360…2380 54 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 6f 66 20 74 68 65 20 52 43 20 33 39 2c 20 43 4f ┆The memory test of the RC 39, CO┆
0x2380…23a0 4d 20 36 30 31 20 53 42 43 20 73 65 6c 66 74 65 73 74 20 63 6f 6e 73 69 73 74 73 20 0a 6f 66 20 ┆M 601 SBC selftest consists of ┆
0x23a0…23c0 74 77 6f 20 70 61 72 74 73 2c 20 61 20 50 52 4f 4d 20 63 68 65 63 6b 73 75 6d 20 74 65 73 74 20 ┆two parts, a PROM checksum test ┆
0x23c0…23e0 61 6e 64 20 61 20 52 41 4d 20 6d 65 6d 6f 72 79 20 74 65 73 74 2e 20 0a 54 68 65 20 50 52 4f 4d ┆and a RAM memory test. The PROM┆
0x23e0…2400 20 63 68 65 63 6b 73 75 6d 20 74 65 73 74 20 69 73 20 6f 6e 6c 79 20 72 75 6e 20 6f 6e 63 65 20 ┆ checksum test is only run once ┆
0x2400…2420 (18,) 61 74 20 70 6f 77 65 72 20 75 70 20 6f 72 20 0a 65 78 74 65 72 6e 61 6c 20 72 65 73 65 74 2c 20 ┆at power up or external reset, ┆
0x2420…2440 77 68 65 72 65 61 73 20 74 68 65 20 52 41 4d 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 6d 61 79 20 ┆whereas the RAM memory test may ┆
0x2440…2460 62 65 20 72 75 6e 20 0a 73 65 76 65 72 61 6c 20 74 69 6d 65 73 2c 20 69 66 20 72 65 71 75 65 73 ┆be run several times, if reques┆
0x2460…2480 74 65 64 20 62 79 20 74 68 65 20 6f 70 65 72 61 74 6f 72 2e 0d 0a 0d 0a 0d 0a b0 a1 35 2e 31 20 ┆ted by the operator. 5.1 ┆
0x2480…24a0 50 52 4f 4d 20 43 68 65 63 6b 73 75 6d 20 54 65 73 74 2e 0d 0a 0d 0a 54 68 65 20 63 6f 6e 74 65 ┆PROM Checksum Test. The conte┆
0x24a0…24c0 6e 74 20 6f 66 20 74 68 65 20 50 52 4f 4d 20 61 72 65 20 73 75 6d 6d 61 72 69 7a 65 64 20 62 79 ┆nt of the PROM are summarized by┆
0x24c0…24e0 74 65 77 69 73 65 20 61 6e 64 20 74 68 65 20 0a 72 65 73 75 6c 74 20 6d 75 73 74 20 62 65 20 61 ┆tewise and the result must be a┆
0x24e0…2500 20 7a 65 72 6f 2e 20 46 6f 72 20 74 68 61 74 20 72 65 61 73 6f 6e 20 74 68 65 20 50 52 4f 4d 20 ┆ zero. For that reason the PROM ┆
0x2500…2520 63 6f 6e 74 61 69 6e 73 20 61 20 0a 63 6f 6d 70 65 6e 73 61 74 69 6f 6e 20 62 79 74 65 20 69 6e ┆contains a compensation byte in┆
0x2520…2540 20 74 68 65 20 73 65 63 6f 6e 64 20 62 79 74 65 20 6f 66 20 74 68 65 20 50 52 4f 4d 2e 20 42 65 ┆ the second byte of the PROM. Be┆
0x2540…2560 6c 6f 77 20 69 73 20 0a 73 68 6f 77 6e 20 74 68 65 20 65 72 72 6f 72 20 64 65 73 63 72 69 70 74 ┆low is shown the error descript┆
0x2560…2580 69 6f 6e 20 74 68 61 74 20 6d 61 79 20 62 65 20 67 65 6e 65 72 61 74 65 64 20 62 79 20 74 68 65 ┆ion that may be generated by the┆
0x2580…2594 20 0a 63 68 65 63 6b 73 75 6d 20 74 65 73 74 2e 0d 0a 0d 0a ┆ checksum test. ┆
0x2594…25cd Params {
0x2594…25cd 04 00 27 4e 0c 00 08 00 00 00 00 03 01 50 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N P1` ┆
0x2594…25cd 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x2594…25cd }
0x25cd…2606 Params {
0x25cd…2606 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x25cd…2606 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x25cd…2606 }
0x2606…2620 0a 0d 0a a1 a1 e1 a2 a1 e1 a2 e2 a1 84 2d 20 20 20 20 20 20 20 20 20 20 20 20 ┆ - ┆
0x2620…2640 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
[…0x1…]
0x2660…2680 20 2d 0d 0a 21 20 45 52 52 2e 21 20 4c 45 44 20 21 20 20 20 49 4e 54 52 4f 44 55 43 54 49 4f 4e ┆ - ! ERR.! LED ! INTRODUCTION┆
0x2680…26a0 20 20 20 21 20 20 20 20 20 20 20 45 52 52 4f 52 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 ┆ ! ERROR ! ┆
0x26a0…26c0 41 55 58 49 4c 4c 41 52 59 20 20 20 20 20 20 20 20 20 21 0d 0a a1 e1 a2 e2 a1 21 20 4e 4f 2e 20 ┆AUXILLARY ! ! NO. ┆
0x26c0…26e0 21 20 4e 4f 2e 20 21 20 20 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 20 20 20 ┆! NO. ! TEXT ! ┆
0x26e0…2700 20 20 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 54 45 58 54 20 20 20 ┆ TEXT ! TEXT ┆
0x2700…2720 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 ┆ ! ! ! ! ┆
0x2720…2740 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 ┆ ! ! ┆
0x2740…2760 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a1 21 20 20 ┆ ! ! ┆
0x2760…2780 31 20 20 21 20 20 31 20 20 21 20 52 41 4d 2f 52 4f 4d 20 74 65 73 74 20 3a 20 20 20 21 20 63 68 ┆1 ! 1 ! RAM/ROM test : ! ch┆
0x2780…27a0 65 63 6b 73 75 6d 20 65 72 72 6f 72 20 20 20 20 21 20 65 78 70 2e 3d 30 30 30 30 20 72 65 63 2e ┆ecksum error ! exp.=0000 rec.┆
0x27a0…27ae 3d 30 30 58 58 20 20 20 20 20 20 21 0d 0a ┆=00XX ! ┆
0x27ae…27e7 Params {
0x27ae…27e7 04 00 27 4e 0c 00 06 00 00 00 00 03 01 48 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N H1` ┆
0x27ae…27e7 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x27ae…27e7 }
0x27e7…2820 Params {
0x27e7…2820 04 00 27 4e 0c 00 08 00 00 00 00 03 01 50 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N P1` ┆
0x27e7…2820 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x27e7…2820 }
0x2820…2825 0a 0d 0a 0d 0a ┆ ┆
0x2825…285e Params {
0x2825…285e 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x2825…285e 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x2825…285e }
0x285e…2897 Params {
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0x285e…2897 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x285e…2897 }
0x2897…28a0 0a 45 72 72 6f 72 20 31 2c ┆ Error 1,┆
0x28a0…28c0 20 63 68 65 63 6b 73 75 6d 20 65 72 72 6f 72 2c 20 75 73 75 61 6c 6c 79 20 6d 65 61 6e 73 20 74 ┆ checksum error, usually means t┆
0x28c0…28e0 68 61 74 20 74 68 65 20 63 6f 6e 74 65 6e 74 20 6f 66 20 0a 74 68 65 20 50 52 4f 4d 20 68 61 73 ┆hat the content of the PROM has┆
0x28e0…2900 20 6e 6f 74 20 62 65 65 6e 20 6d 61 69 6e 74 61 69 6e 65 64 20 61 6e 64 20 74 68 61 74 20 74 68 ┆ not been maintained and that th┆
0x2900…291e 65 20 50 52 4f 4d 20 6d 75 73 74 20 62 65 20 0a 63 68 61 6e 67 65 64 2e 0d 0a 0d 0a 0d 0a ┆e PROM must be changed. ┆
0x291e…2921 FormFeed {
0x291e…2921 0c 82 d6 ┆ ┆
0x291e…2921 }
0x2921…2940 0a a1 b0 35 2e 32 20 52 41 4d 20 4d 65 6d 6f 72 79 20 54 65 73 74 2e 0d 0a 0d 0a 54 68 65 20 ┆ 5.2 RAM Memory Test. The ┆
0x2940…2960 52 41 4d 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 6f 66 20 74 68 65 20 52 43 20 33 39 2c 20 43 4f ┆RAM memory test of the RC 39, CO┆
0x2960…2980 4d 20 36 30 31 20 53 42 43 20 73 65 6c 66 74 65 73 74 20 0a 76 65 72 69 66 69 65 73 20 74 68 65 ┆M 601 SBC selftest verifies the┆
0x2980…29a0 20 6f 6e 20 62 6f 61 72 64 20 6d 65 6d 6f 72 79 2e 0d 0a 0d 0a 54 68 65 20 52 41 4d 20 6d 65 6d ┆ on board memory. The RAM mem┆
0x29a0…29c0 6f 72 79 20 73 69 7a 65 20 69 73 20 66 69 78 65 64 20 61 6e 64 20 69 73 20 36 34 20 4b 2d 62 79 ┆ory size is fixed and is 64 K-by┆
0x29c0…29e0 74 65 73 2e 0d 0a 0d 0a 54 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 69 73 20 61 20 72 65 67 ┆tes. The memory test is a reg┆
0x29e0…2a00 69 73 74 65 72 20 62 61 73 65 64 20 74 65 73 74 20 61 6e 64 20 75 73 65 73 20 6e 6f 20 6d 65 6d ┆ister based test and uses no mem┆
0x2a00…2a20 (21,) 6f 72 79 20 0a 73 70 61 63 65 20 61 74 20 61 6c 6c 2c 20 6e 65 69 74 68 65 72 20 66 6f 72 20 76 ┆ory space at all, neither for v┆
0x2a20…2a40 61 72 69 61 62 6c 65 73 20 6e 6f 72 20 73 74 61 63 6b 2e 20 54 68 65 20 74 65 73 74 20 0a 76 65 ┆ariables nor stack. The test ve┆
0x2a40…2a60 72 69 66 69 65 73 20 65 76 65 72 79 20 73 69 6e 67 6c 65 20 62 79 74 65 20 6f 66 20 74 68 65 20 ┆rifies every single byte of the ┆
0x2a60…2a80 6f 6e 2d 62 6f 61 72 64 20 6d 65 6d 6f 72 79 2e 0d 0a 0d 0a 54 68 69 73 20 66 61 63 74 20 6c 65 ┆on-board memory. This fact le┆
0x2a80…2aa0 74 73 20 6f 6e 6c 79 20 6f 6e 65 20 72 65 67 69 73 74 65 72 20 66 6f 72 20 74 65 73 74 20 76 61 ┆ts only one register for test va┆
0x2aa0…2ac0 72 69 61 62 6c 65 73 20 73 75 72 76 69 76 65 20 0a 74 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 ┆riables survive the memory test┆
0x2ac0…2ae0 2e 20 54 68 61 74 20 76 61 72 69 61 62 6c 65 20 63 6f 6e 74 61 69 6e 73 20 61 6c 6c 20 74 68 65 ┆. That variable contains all the┆
0x2ae0…2b00 20 74 65 73 74 20 0a 73 77 69 74 63 68 65 73 20 61 6e 64 20 74 68 65 20 74 65 73 74 20 6e 75 6d ┆ test switches and the test num┆
0x2b00…2b20 62 65 72 2e 20 20 0d 0a 0d 0a 0d 0a a1 b0 35 2e 32 2e 31 20 4d 65 6d 6f 72 79 20 54 65 73 74 20 ┆ber. 5.2.1 Memory Test ┆
0x2b20…2b40 50 61 74 74 65 72 6e 2e 0d 0a 0d 0a 54 68 65 20 6f 6e 20 62 6f 61 72 64 20 44 75 61 6c 20 50 6f ┆Pattern. The on board Dual Po┆
0x2b40…2b60 72 74 65 64 20 52 41 4d 20 6d 65 6d 6f 72 79 20 63 6f 6e 73 69 73 74 73 20 6f 66 20 6d 65 6d 6f ┆rted RAM memory consists of memo┆
0x2b60…2b80 72 79 20 63 68 69 70 73 20 0a 6f 66 20 31 20 62 69 74 20 2a 20 36 34 20 4b 2e 20 54 68 65 20 6d ┆ry chips of 1 bit * 64 K. The m┆
0x2b80…2ba0 65 6d 6f 72 79 20 74 65 73 74 20 65 78 65 63 75 74 65 73 20 34 20 70 61 73 73 65 73 20 74 72 6f ┆emory test executes 4 passes tro┆
0x2ba0…2bc0 75 67 68 20 0a 74 68 65 20 65 6e 74 69 72 65 20 6d 65 6d 6f 72 79 2c 20 74 77 6f 20 74 69 6d 65 ┆ugh the entire memory, two time┆
0x2bc0…2be0 73 20 77 72 69 74 69 6e 67 20 61 6e 64 20 74 77 6f 20 74 69 6d 65 73 20 72 65 61 64 69 6e 67 2e ┆s writing and two times reading.┆
0x2be0…2c00 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 70 61 74 74 65 72 6e 20 69 73 20 74 68 65 20 63 6f 6e 76 ┆ The test pattern is the conv┆
0x2c00…2c20 (22,) 65 6e 69 65 6e 74 20 6d 6f 64 75 6c 75 73 20 33 20 70 61 74 74 65 72 6e 20 0a 63 6f 6e 73 69 73 ┆enient modulus 3 pattern consis┆
0x2c20…2c40 74 69 6e 67 20 6f 66 20 74 68 72 65 65 20 74 69 6d 65 73 20 30 30 30 30 20 66 6f 6c 6c 6f 77 65 ┆ting of three times 0000 followe┆
0x2c40…2c60 64 20 62 79 20 74 68 72 65 65 20 74 69 6d 65 73 20 46 46 46 46 20 0a 28 68 65 78 61 64 65 63 69 ┆d by three times FFFF (hexadeci┆
0x2c60…2c80 6d 61 6c 29 2e 0d 0a 0d 0a 0d 0a b0 a1 35 2e 32 2e 32 20 4d 65 6d 6f 72 79 20 54 65 73 74 20 46 ┆mal). 5.2.2 Memory Test F┆
0x2c80…2ca0 6c 6f 77 2e 0d 0a 0d 0a 54 68 65 20 74 65 73 74 20 73 74 61 72 74 73 20 69 6e 20 74 68 65 20 68 ┆low. The test starts in the h┆
0x2ca0…2cc0 69 67 68 65 73 74 20 52 41 4d 20 61 64 64 72 65 73 73 65 73 20 61 6e 64 20 69 6e 73 65 72 74 73 ┆ighest RAM addresses and inserts┆
0x2cc0…2ce0 20 74 68 65 20 0a 70 61 74 74 65 72 6e 20 74 6f 77 61 72 64 73 20 6c 6f 77 65 72 20 61 64 64 72 ┆ the pattern towards lower addr┆
0x2ce0…2d00 65 73 73 65 73 2e 0d 0a 0d 0a 57 68 65 6e 20 61 6c 6c 20 6d 65 6d 6f 72 79 20 77 6f 72 64 73 20 ┆esses. When all memory words ┆
0x2d00…2d20 68 61 76 65 20 62 65 65 6e 20 77 72 69 74 74 65 6e 20 61 6e 64 20 76 65 72 69 66 69 65 64 2c 20 ┆have been written and verified, ┆
0x2d20…2d40 74 68 65 79 20 0a 61 72 65 20 74 65 73 74 65 64 20 61 67 61 69 6e 20 77 69 74 68 20 74 68 65 20 ┆they are tested again with the ┆
0x2d40…2d60 69 6e 76 65 72 73 65 64 20 70 61 74 74 65 72 6e 2c 20 74 68 69 73 20 6d 65 61 6e 73 2c 20 74 68 ┆inversed pattern, this means, th┆
0x2d60…2d80 61 74 20 0a 61 6c 6c 20 62 69 74 73 20 61 72 65 20 74 65 73 74 65 64 20 66 6f 72 20 22 7a 65 72 ┆at all bits are tested for "zer┆
0x2d80…2da0 6f 22 20 61 6e 64 20 22 6f 6e 65 22 20 69 6e 73 65 72 74 69 6f 6e 2e 20 49 66 20 61 6e 20 0a 65 ┆o" and "one" insertion. If an e┆
0x2da0…2dc0 72 72 6f 72 20 6f 63 63 75 72 20 61 6e 20 61 74 74 65 6d 70 74 20 74 6f 20 73 65 6e 64 20 74 68 ┆rror occur an attempt to send th┆
0x2dc0…2de0 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 6d 65 73 73 61 67 65 2c 20 74 6f 20 74 68 65 20 0a 22 74 65 ┆e following message, to the "te┆
0x2de0…2df9 73 74 2d 6d 61 73 74 65 72 22 2c 20 69 73 20 6d 61 64 65 20 3a 0d 0a 0d 0a ┆st-master", is made : ┆
0x2df9…2e32 Params {
0x2df9…2e32 04 00 27 4e 0c 00 08 00 00 00 00 03 01 50 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N P1` ┆
0x2df9…2e32 00 00 00 00 00 00 00 00 01 06 0b 10 15 1a 1f 24 29 2e 33 38 3d 42 47 ff 04 ┆ $).38=BG ┆
0x2df9…2e32 }
0x2e32…2e6b Params {
0x2e32…2e6b 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x2e32…2e6b 00 00 00 00 00 00 00 00 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 4b ff 04 ┆ #(-27<AFK ┆
0x2e32…2e6b }
0x2e6b…2e80 0a 8c 83 c8 0a 84 a1 e1 a2 e2 a1 2d 20 20 20 20 20 20 20 20 20 ┆ - ┆
0x2e80…2ea0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
[…0x1…]
0x2ec0…2ee0 20 20 20 20 2d 0d 0a 21 20 45 52 52 2e 21 20 4c 45 44 20 21 20 20 20 49 4e 54 52 4f 44 55 43 54 ┆ - ! ERR.! LED ! INTRODUCT┆
0x2ee0…2f00 49 4f 4e 20 20 20 21 20 20 20 20 20 20 20 45 52 52 4f 52 20 20 20 20 20 20 20 21 20 20 20 20 20 ┆ION ! ERROR ! ┆
0x2f00…2f20 20 20 20 53 45 43 4f 4e 44 41 52 59 20 20 20 20 20 20 20 20 20 21 0d 0a a1 e1 a2 e2 a1 21 20 4e ┆ SECONDARY ! ! N┆
0x2f20…2f40 4f 2e 20 21 20 4e 4f 2e 20 21 20 20 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 ┆O. ! NO. ! TEXT ! ┆
0x2f40…2f60 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 54 45 58 54 ┆ TEXT ! TEXT┆
0x2f60…2f80 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 ┆ ! ! ! ! ┆
0x2f80…2fa0 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x2fa0…2fc0 20 21 20 73 65 67 6d 2e 3a 3c 73 73 73 73 3e 2c 61 64 72 2e 3a 3c 61 61 61 61 3e 07 21 0d 0a a1 ┆ ! segm.:<ssss>,adr.:<aaaa> ! ┆
0x2fc0…2fe0 21 20 20 32 20 20 21 20 20 32 20 20 21 20 52 41 4d 2f 52 4f 4d 20 74 65 73 74 20 3a 20 20 20 21 ┆! 2 ! 2 ! RAM/ROM test : !┆
0x2fe0…3000 20 52 41 4d 20 65 72 72 6f 72 20 20 20 20 20 20 20 20 20 21 20 65 78 70 2e 3a 3c 65 65 65 65 3e ┆ RAM error ! exp.:<eeee>┆
0x3000…3011 (24,) 2c 20 72 65 63 2e 3a 3c 72 72 72 72 3e 20 21 0d 0a ┆, rec.:<rrrr> ! ┆
0x3011…304a Params {
0x3011…304a 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x3011…304a 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x3011…304a }
0x304a…3083 Params {
0x304a…3083 04 00 27 4e 0c 00 08 00 00 00 00 03 01 50 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N P1` ┆
0x304a…3083 00 00 00 00 00 00 00 00 01 06 0b 10 15 1a 1f 24 29 2e 33 38 3d 42 47 ff 04 ┆ $).38=BG ┆
0x304a…3083 }
0x3083…30a0 0a 0d 0a 54 68 65 20 73 65 63 6f 6e 64 61 72 79 20 74 65 78 74 20 69 73 20 69 6e 74 65 ┆ The secondary text is inte┆
0x30a0…30c0 72 70 72 65 74 65 64 20 6c 69 6b 65 20 74 68 69 73 20 3a 0d 0a 0d 0a 3c 73 73 73 73 3e 20 69 73 ┆rpreted like this : <ssss> is┆
0x30c0…30e0 20 74 68 65 20 73 65 67 6d 65 6e 74 20 61 64 64 72 65 73 73 0d 0a 3c 61 61 61 61 3e 20 69 73 20 ┆ the segment address <aaaa> is ┆
0x30e0…3100 74 68 65 20 6f 66 66 73 65 74 20 61 64 64 72 65 73 73 0d 0a 3c 65 65 65 65 3e 20 84 69 73 20 74 ┆the offset address <eeee> is t┆
0x3100…3120 68 65 20 65 78 70 65 63 74 65 64 20 70 61 74 74 65 72 6e 2c 20 73 68 6f 75 6c 64 20 61 6c 6c 77 ┆he expected pattern, should allw┆
0x3120…3140 61 79 73 20 62 65 20 30 30 30 30 20 6f 72 20 0a 19 87 80 80 46 46 46 46 2e 0d 0a 3c 72 72 72 72 ┆ays be 0000 or FFFF. <rrrr┆
0x3140…3160 3e 20 69 73 20 74 68 65 20 72 65 63 65 69 76 65 64 20 70 61 74 74 65 72 6e 2e 0d 0a 0d 0a 54 68 ┆> is the received pattern. Th┆
0x3160…3180 65 20 61 62 6f 76 65 20 6d 65 6e 74 69 6f 6e 65 64 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 20 6d 61 ┆e above mentioned information ma┆
0x3180…31a0 79 20 62 65 20 75 73 65 64 20 74 6f 20 66 69 6e 64 20 61 20 0a 64 65 66 65 63 74 69 76 65 20 52 ┆y be used to find a defective R┆
0x31a0…31c0 41 4d 20 6d 65 6d 6f 72 79 20 63 68 69 70 20 66 72 6f 6d 20 74 68 65 20 6b 6e 6f 77 6c 65 64 67 ┆AM memory chip from the knowledg┆
0x31c0…31e0 65 20 6f 66 20 74 68 65 20 52 41 4d 2d 0a 6c 61 79 6f 75 74 2e 20 53 61 79 20 74 68 65 20 65 72 ┆e of the RAM- layout. Say the er┆
0x31e0…3200 72 6f 72 20 6d 65 73 73 61 67 65 20 67 6f 65 73 20 6c 69 6b 65 20 74 68 69 73 20 3a 0d 0a 0d 0a ┆ror message goes like this : ┆
0x3200…3239 (25,) Params {
0x3200…3239 04 00 27 4e 0c 00 06 00 00 00 00 03 01 4b 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N K1` ┆
0x3200…3239 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x3200…3239 }
0x3239…3272 Params {
0x3239…3272 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x3239…3272 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x3239…3272 }
0x3272…3280 0a b0 52 41 4d 2f 52 4f 4d 20 20 74 65 73 ┆ RAM/ROM tes┆
0x3280…32a0 74 20 3a 20 52 41 4d 20 65 72 72 6f 72 20 20 20 73 65 67 6d 2e 3a 30 30 30 30 2c 20 61 64 64 72 ┆t : RAM error segm.:0000, addr┆
0x32a0…32c0 2e 3a 30 30 30 32 2c 20 65 78 70 2e 3a 30 30 30 30 2c 20 72 65 63 2e 3a 30 31 30 31 0d 0a 0d 0a ┆.:0002, exp.:0000, rec.:0101 ┆
0x32c0…32f9 Params {
0x32c0…32f9 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x32c0…32f9 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x32c0…32f9 }
0x32f9…3332 Params {
0x32f9…3332 04 00 27 4e 0c 00 06 00 00 00 00 03 01 4b 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N K1` ┆
0x32f9…3332 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x32f9…3332 }
0x3332…3340 0a 41 6c 6c 74 68 6f 75 67 68 20 74 68 65 ┆ Allthough the┆
0x3340…3360 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 69 73 20 62 61 73 65 64 20 6f 6e 20 31 36 20 62 69 74 20 ┆ memory test is based on 16 bit ┆
0x3360…3380 77 6f 72 64 20 0a 6d 61 6e 69 70 75 6c 61 74 69 6f 6e 2c 20 74 68 65 20 6d 65 6d 6f 72 79 20 69 ┆word manipulation, the memory i┆
0x3380…33a0 73 20 6f 72 67 61 6e 69 7a 65 64 20 62 79 74 65 77 69 73 65 2c 20 62 69 74 20 30 20 61 6e 64 20 ┆s organized bytewise, bit 0 and ┆
0x33a0…33c0 38 20 0a 69 73 20 73 74 6f 72 65 64 20 69 6e 20 63 68 69 70 20 55 20 32 30 30 2c 20 62 69 74 20 ┆8 is stored in chip U 200, bit ┆
0x33c0…33e0 31 20 61 6e 64 20 39 20 69 6e 20 55 32 30 31 20 61 6e 64 20 73 6f 20 6f 6e 2e 20 54 68 65 20 0a ┆1 and 9 in U201 and so on. The ┆
0x33e0…3400 61 62 6f 76 65 20 65 72 72 6f 72 20 6d 69 67 68 74 20 69 6e 64 69 63 61 74 65 20 74 68 61 74 20 ┆above error might indicate that ┆
0x3400…3420 (26,) 63 68 69 70 20 55 20 32 30 30 20 69 73 20 64 65 66 65 63 74 2e 0d 0a 0d 0a 4e 4f 54 45 20 74 68 ┆chip U 200 is defect. NOTE th┆
0x3420…3440 61 74 20 74 68 65 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 72 6f 75 74 69 6e 65 73 20 61 72 ┆at the error message routines ar┆
0x3440…3460 65 20 62 61 73 65 64 20 6f 6e 20 52 41 4d 20 6d 65 6d 6f 72 79 20 0a 62 75 66 66 65 72 73 2c 20 ┆e based on RAM memory buffers, ┆
0x3460…3480 74 68 65 72 65 66 6f 72 65 20 73 6f 6d 65 20 70 65 63 75 6c 69 61 72 20 73 69 74 75 61 74 69 6f ┆therefore some peculiar situatio┆
0x3480…34a0 6e 20 6d 61 79 20 6f 63 63 75 72 20 64 75 72 69 6e 67 20 0a 52 41 4d 20 66 61 75 6c 74 73 2e 20 ┆n may occur during RAM faults. ┆
0x34a0…34c0 0d 0a 0d 0a 54 68 65 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 69 73 20 61 6c 77 61 79 73 20 ┆ The error message is always ┆
0x34c0…34e0 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 6c 69 67 68 74 20 65 6d 69 74 74 69 6e 67 20 0a 64 ┆written to the light emitting d┆
0x34e0…3500 69 6f 64 65 73 2c 20 74 68 69 73 20 6d 65 61 6e 73 20 74 68 61 74 20 69 66 20 74 68 65 20 6d 65 ┆iodes, this means that if the me┆
0x3500…3520 73 73 61 67 65 20 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 66 61 69 6c 73 2c 20 0a 74 68 65 72 ┆ssage communication fails, ther┆
0x3520…3540 65 20 69 73 20 73 74 69 6c 6c 20 77 72 69 74 74 65 6e 20 61 20 6c 65 64 20 65 72 72 6f 72 20 63 ┆e is still written a led error c┆
0x3540…3560 6f 64 65 20 3d 20 32 20 74 6f 20 74 68 65 20 6c 65 64 73 2e 20 0a 54 68 69 73 20 6d 65 61 6e 73 ┆ode = 2 to the leds. This means┆
0x3560…3580 20 74 68 61 74 20 6c 65 64 20 6e 75 6d 62 65 72 20 32 20 66 72 6f 6d 20 74 68 65 20 72 69 67 68 ┆ that led number 2 from the righ┆
0x3580…35a0 74 20 77 69 6c 6c 20 62 65 20 6c 69 74 2c 20 61 6e 64 20 0a 74 68 65 20 33 20 6f 74 68 65 72 73 ┆t will be lit, and the 3 others┆
0x35a0…35c0 20 62 6c 61 6e 6b 20 77 68 65 6e 20 61 20 52 41 4d 20 65 72 72 6f 72 20 6f 63 63 75 72 2e 0d 0a ┆ blank when a RAM error occur. ┆
0x35c0…35c2 0d 0a ┆ ┆
0x35c2…35c5 FormFeed {
0x35c2…35c5 0c 83 95 ┆ ┆
0x35c2…35c5 }
0x35c5…35e0 0a 57 68 65 6e 20 74 68 65 20 52 41 4d 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 ┆ When the RAM error message┆
0x35e0…3600 20 70 61 73 73 69 6e 67 20 67 6f 65 73 20 77 72 6f 6e 67 2c 20 74 68 65 72 65 20 69 73 20 61 20 ┆ passing goes wrong, there is a ┆
0x3600…3620 (27,) 0a 70 6f 73 73 69 62 69 6c 69 74 79 20 74 6f 20 66 6f 72 63 65 20 74 68 65 20 52 41 4d 20 74 65 ┆ possibility to force the RAM te┆
0x3620…3640 73 74 20 74 6f 20 6c 6f 6f 70 20 6f 6e 20 65 72 72 6f 72 2e 20 54 68 69 73 20 69 73 20 0a 64 6f ┆st to loop on error. This is do┆
0x3640…3660 6e 65 20 62 79 20 73 74 72 61 70 70 69 6e 67 20 57 31 31 20 6c 6f 77 2e 20 54 68 65 6e 20 74 68 ┆ne by strapping W11 low. Then th┆
0x3660…3680 65 20 52 41 4d 20 74 65 73 74 20 77 69 6c 6c 20 74 72 79 20 61 67 61 69 6e 20 0a 61 6e 64 20 61 ┆e RAM test will try again and a┆
0x3680…36a0 67 61 69 6e 20 74 6f 20 72 65 61 64 20 66 72 6f 6d 20 74 68 65 20 66 69 72 73 74 20 65 72 72 6f ┆gain to read from the first erro┆
0x36a0…36c0 6e 6f 75 73 20 63 65 6c 6c 20 69 73 20 66 69 6e 64 73 2e 20 49 66 20 0a 74 68 65 20 70 61 74 74 ┆nous cell is finds. If the patt┆
0x36c0…36e0 65 72 6e 20 73 6f 6d 65 74 69 6d 65 20 68 61 70 70 65 6e 73 20 74 6f 20 62 65 20 63 6f 72 72 65 ┆ern sometime happens to be corre┆
0x36e0…3700 63 74 20 74 68 65 20 74 65 73 74 20 77 69 6c 6c 20 0a 70 72 6f 63 65 65 64 20 66 75 72 74 68 65 ┆ct the test will proceed furthe┆
0x3700…3720 72 20 74 72 6f 75 67 68 20 74 68 65 20 74 65 73 74 2c 20 61 6e 64 20 69 66 20 74 68 65 20 52 41 ┆r trough the test, and if the RA┆
0x3720…3740 4d 20 69 73 20 4f 4b 2c 20 74 68 65 20 0a 74 65 73 74 20 77 69 6c 6c 20 65 6e 74 65 72 20 74 68 ┆M is OK, the test will enter th┆
0x3740…3760 65 20 74 65 73 74 61 64 6d 69 6e 69 73 74 72 61 74 6f 72 20 77 68 65 6e 20 69 74 20 74 65 72 6d ┆e testadministrator when it term┆
0x3760…3780 69 6e 61 74 65 73 2e 20 0d 0a 0d 0a 55 70 6f 6e 20 73 75 63 63 65 73 66 75 6c 20 63 6f 6d 70 6c ┆inates. Upon succesful compl┆
0x3780…37a0 65 74 69 6f 6e 20 6f 66 20 74 68 65 20 52 41 4d 20 74 65 73 74 2c 20 74 68 65 20 0a 74 65 73 74 ┆etion of the RAM test, the test┆
0x37a0…37c0 61 64 6d 69 6e 69 73 74 72 61 74 6f 72 20 61 6c 77 61 79 73 20 74 61 6b 65 73 20 6f 76 65 72 20 ┆administrator always takes over ┆
0x37c0…37e0 61 6e 64 20 63 6f 6e 74 72 6f 6c 73 20 74 68 65 20 66 6c 6f 77 20 6f 66 20 0a 74 68 65 20 72 65 ┆and controls the flow of the re┆
0x37e0…37f1 73 74 20 6f 66 20 74 68 65 20 74 65 73 74 2e 0d 0a ┆st of the test. ┆
0x37f1…37f4 FormFeed {
0x37f1…37f4 0c 81 84 ┆ ┆
0x37f1…37f4 }
0x37f4…3800 0a a1 b0 36 2e 20 b0 54 45 53 54 20 ┆ 6. TEST ┆
0x3800…3820 (28,) 31 20 3d 20 f0 b0 43 48 49 50 20 53 45 4c 45 43 54 20 54 45 53 54 0d 0a 0d 0a 54 6f 20 65 61 73 ┆1 = CHIP SELECT TEST To eas┆
0x3820…3840 65 20 63 6f 6d 70 6c 65 78 20 64 65 62 75 67 67 69 6e 67 2c 20 61 20 73 69 6d 70 6c 65 20 63 68 ┆e complex debugging, a simple ch┆
0x3840…3860 69 70 20 73 65 6c 65 63 74 20 6c 6f 6f 70 2c 20 0a 63 6f 6d 62 69 6e 65 64 20 77 69 74 68 20 61 ┆ip select loop, combined with a┆
0x3860…3880 20 52 41 4d 20 77 72 69 74 65 2f 72 65 61 64 2c 20 69 73 20 73 75 70 70 6c 69 65 64 2e 20 0d 0a ┆ RAM write/read, is supplied. ┆
0x3880…38a0 0d 0a 54 68 69 73 20 74 65 73 74 20 67 65 6e 65 72 61 74 65 73 20 63 68 69 70 20 73 65 6c 65 63 ┆ This test generates chip selec┆
0x38a0…38c0 74 73 20 74 6f 20 61 6c 6c 20 70 65 72 69 70 68 65 72 61 6c 20 64 65 76 69 63 65 73 20 0a 62 79 ┆ts to all peripheral devices by┆
0x38c0…38e0 20 65 78 65 63 75 74 69 6e 67 20 69 6e 70 75 74 20 69 6e 73 74 72 75 63 74 69 6f 6e 73 20 74 6f ┆ executing input instructions to┆
0x38e0…3900 20 61 6c 6c 20 72 65 6c 65 76 61 6e 74 20 49 2f 4f 2d 64 65 76 69 63 65 73 2e 20 0a 54 68 65 73 ┆ all relevant I/O-devices. Thes┆
0x3900…3920 65 20 61 72 65 20 3a 0d 0a 0d 0a 50 6f 72 74 20 41 30 48 2c 20 45 31 48 2c 20 39 30 48 2c 20 38 ┆e are : Port A0H, E1H, 90H, 8┆
0x3920…3940 30 48 2c 20 44 30 48 2c 20 46 30 48 2c 20 43 30 48 20 2c 20 42 30 48 0d 0a 0d 0a 57 68 65 6e 20 ┆0H, D0H, F0H, C0H , B0H When ┆
0x3940…3960 61 6c 6c 20 74 68 65 20 63 68 69 70 20 73 65 6c 65 63 74 73 20 61 72 65 20 6d 61 64 65 2c 20 61 ┆all the chip selects are made, a┆
0x3960…3980 20 70 61 74 74 65 72 6e 20 41 41 35 35 20 68 65 78 2e 20 69 73 20 0a 77 72 69 74 74 65 6e 20 74 ┆ pattern AA55 hex. is written t┆
0x3980…39a0 6f 20 61 20 52 41 4d 20 63 65 6c 6c 20 61 6e 64 20 69 6d 6d 65 64 69 61 74 65 6c 79 20 72 65 61 ┆o a RAM cell and immediately rea┆
0x39a0…39c0 64 20 62 61 63 6b 2e 0d 0a 0d 0a 54 68 69 73 20 74 65 73 74 20 69 73 20 75 6e 61 62 6c 65 20 74 ┆d back. This test is unable t┆
0x39c0…39e0 6f 20 67 65 6e 65 72 61 74 65 20 61 6e 79 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 73 2e 20 49 ┆o generate any error messages. I┆
0x39e0…3a00 74 20 69 73 20 0a 6d 65 61 6e 74 20 6f 6e 6c 79 20 61 73 20 61 20 73 70 65 63 69 61 6c 20 66 61 ┆t is meant only as a special fa┆
0x3a00…3a20 (29,) 73 74 20 73 63 6f 70 65 20 6c 6f 6f 70 20 74 65 73 74 2e 0d 0a 0d 0a 54 68 65 72 65 20 61 72 65 ┆st scope loop test. There are┆
0x3a20…3a40 20 73 65 76 65 72 61 6c 20 77 61 79 73 20 74 6f 20 6d 61 6b 65 20 74 68 69 73 20 74 65 73 74 20 ┆ several ways to make this test ┆
0x3a40…3a60 6c 6f 6f 70 2e 20 4f 6e 65 20 69 73 20 74 6f 20 73 65 74 20 0a 74 68 65 20 6c 6f 6f 70 2d 62 69 ┆loop. One is to set the loop-bi┆
0x3a60…3a80 74 20 3d 20 22 59 22 20 61 6e 64 20 74 68 65 20 74 65 73 74 20 6e 75 6d 62 65 72 20 74 6f 20 31 ┆t = "Y" and the test number to 1┆
0x3a80…3aa0 2c 20 74 68 65 6e 20 74 68 65 20 74 65 73 74 20 0a 77 69 6c 6c 20 6c 6f 6f 70 20 61 6e 64 20 77 ┆, then the test will loop and w┆
0x3aa0…3ac0 72 69 74 65 20 4f 4b 20 74 6f 20 74 68 65 20 63 6f 6e 73 6f 6c 65 20 77 68 65 6e 65 76 65 72 20 ┆rite OK to the console whenever ┆
0x3ac0…3ae0 74 68 65 20 74 65 73 74 20 68 61 73 20 0a 66 69 6e 69 73 68 65 64 2e 20 49 6e 20 74 68 69 73 20 ┆the test has finished. In this ┆
0x3ae0…3b00 63 61 73 65 20 74 68 65 20 63 6f 6e 73 6f 6c 65 20 6f 75 74 70 75 74 20 69 6e 63 72 65 61 73 65 ┆case the console output increase┆
0x3b00…3b20 73 20 74 68 65 20 6c 6f 6f 70 20 0a 74 69 6d 65 20 73 69 67 6e 69 66 69 63 61 6e 74 6c 79 2e 20 ┆s the loop time significantly. ┆
0x3b20…3b40 54 68 65 20 63 6f 6e 73 6f 6c 65 20 6f 75 74 70 75 74 20 72 6f 75 74 69 6e 65 20 6d 61 79 20 62 ┆The console output routine may b┆
0x3b40…3b60 65 20 0a 73 75 70 70 72 65 73 73 65 64 20 62 79 20 73 65 74 74 69 6e 67 20 74 68 65 20 73 75 70 ┆e suppressed by setting the sup┆
0x3b60…3b80 70 72 65 73 73 20 64 61 74 61 20 63 68 65 63 6b 20 3d 20 22 59 22 20 61 6e 64 20 74 68 65 20 0a ┆press data check = "Y" and the ┆
0x3b80…3ba0 73 75 70 70 72 65 73 73 20 73 74 61 74 75 73 20 63 68 65 63 6b 20 3d 20 22 59 22 2e 20 4e 6f 74 ┆suppress status check = "Y". Not┆
0x3ba0…3bc0 65 20 74 68 61 74 20 6e 6f 77 20 74 68 65 72 65 20 69 73 20 6f 6e 6c 79 20 6f 6e 65 20 0a 77 61 ┆e that now there is only one wa┆
0x3bc0…3be0 79 20 62 61 63 6b 20 74 6f 20 74 68 65 20 63 6f 6e 73 6f 6c 65 20 6f 75 74 70 75 74 2c 20 74 6f ┆y back to the console output, to┆
0x3be0…3c00 20 70 72 65 73 73 20 52 45 53 45 54 2e 20 54 68 69 73 20 6c 6f 6f 70 20 0a 72 75 6e 73 20 65 76 ┆ press RESET. This loop runs ev┆
0x3c00…3c20 (30,) 65 6e 20 66 61 73 74 65 72 20 69 66 20 79 6f 75 20 73 74 72 61 70 20 57 31 31 20 6c 6f 77 2e 20 ┆en faster if you strap W11 low. ┆
0x3c20…3c40 4e 6f 74 65 20 74 68 61 74 20 74 68 69 73 20 69 73 20 74 68 65 20 0a 73 61 6d 65 20 73 74 72 61 ┆Note that this is the same stra┆
0x3c40…3c60 70 20 74 68 61 74 20 63 61 75 73 65 73 20 74 68 65 20 52 41 4d 20 74 65 73 74 20 74 6f 20 6c 6f ┆p that causes the RAM test to lo┆
0x3c60…3c6e 6f 70 20 6f 6e 20 65 72 72 6f 72 2e 0d 0a ┆op on error. ┆
0x3c6e…3c71 FormFeed {
0x3c6e…3c71 0c 82 c4 ┆ ┆
0x3c6e…3c71 }
0x3c71…3c80 0a a2 e2 a1 b0 37 2e b0 20 54 45 53 54 20 32 ┆ 7. TEST 2┆
0x3c80…3ca0 20 3d f0 20 b0 38 32 35 35 41 20 50 41 52 41 4c 4c 45 4c 20 50 4f 52 54 20 54 45 53 54 0d 0a 0d ┆ = 8255A PARALLEL PORT TEST ┆
0x3ca0…3cc0 0a 54 68 65 20 38 32 35 35 41 20 50 50 49 20 74 65 73 74 20 77 72 69 74 65 73 20 61 20 70 61 74 ┆ The 8255A PPI test writes a pat┆
0x3cc0…3ce0 74 65 72 6e 20 31 30 31 30 30 30 30 30 20 62 69 6e 61 72 79 20 74 6f 20 74 68 65 20 0a 6f 75 74 ┆tern 10100000 binary to the out┆
0x3ce0…3d00 70 75 74 20 70 6f 72 74 20 42 20 28 20 69 6f 61 64 72 2e 20 41 31 48 20 29 2e 20 54 68 65 6e 20 ┆put port B ( ioadr. A1H ). Then ┆
0x3d00…3d20 69 74 20 72 65 61 64 73 20 74 68 65 20 70 61 74 74 65 72 6e 20 62 61 63 6b 20 0a 61 6e 64 20 76 ┆it reads the pattern back and v┆
0x3d20…3d40 65 72 69 66 69 65 73 20 69 74 2e 20 49 66 20 6e 6f 20 65 72 72 6f 72 20 69 73 20 64 65 74 65 63 ┆erifies it. If no error is detec┆
0x3d40…3d60 74 65 64 20 74 68 65 20 70 61 74 74 65 72 6e 20 69 73 20 0a 73 68 69 66 74 65 64 20 6f 6e 65 20 ┆ted the pattern is shifted one ┆
0x3d60…3d80 62 69 74 20 74 6f 20 74 68 65 20 72 69 67 68 74 2c 20 61 6e 64 20 74 68 65 20 77 72 69 74 65 2f ┆bit to the right, and the write/┆
0x3d80…3da0 72 65 61 64 20 76 65 72 69 66 79 20 0a 70 72 6f 63 65 64 75 72 65 20 69 73 20 72 65 70 65 61 74 ┆read verify procedure is repeat┆
0x3da0…3dc0 65 64 20 75 6e 74 69 6c 20 74 68 65 20 70 61 74 74 65 72 6e 20 62 65 63 6f 6d 65 73 20 7a 65 72 ┆ed until the pattern becomes zer┆
0x3dc0…3de0 6f 2e 20 49 66 20 61 6e 20 0a 65 72 72 6f 72 20 69 73 20 64 65 74 65 63 74 65 64 20 74 68 69 73 ┆o. If an error is detected this┆
0x3de0…3e00 20 6d 65 73 73 61 67 65 20 69 73 20 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 0a 63 6f 6d 6d ┆ message is written to the comm┆
0x3e00…3e16 (31,) 75 6e 69 63 61 74 69 6f 6e 20 62 75 66 66 65 72 20 3a 0d 0a 0d 0a ┆unication buffer : ┆
0x3e16…3e4f Params {
0x3e16…3e4f 04 00 27 4e 0c 00 08 00 00 00 00 03 01 50 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N P1` ┆
0x3e16…3e4f 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x3e16…3e4f }
0x3e4f…3e88 Params {
0x3e4f…3e88 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x3e4f…3e88 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x3e4f…3e88 }
0x3e88…3ea0 0a e1 a2 b0 e2 b0 84 a2 e2 a1 f0 2d 20 20 20 20 20 20 20 20 20 20 20 20 ┆ - ┆
0x3ea0…3ec0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
[…0x1…]
0x3ee0…3f00 20 2d 0d 0a 21 20 45 52 52 2e 21 20 4c 45 44 20 21 20 20 20 49 4e 54 52 4f 44 55 43 54 49 4f 4e ┆ - ! ERR.! LED ! INTRODUCTION┆
0x3f00…3f20 20 20 20 21 20 20 20 20 20 20 20 45 52 52 4f 52 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 ┆ ! ERROR ! ┆
0x3f20…3f40 53 45 43 4f 4e 44 41 52 59 20 20 20 20 20 20 20 20 20 21 0d 0a a1 e1 a2 e2 a1 21 20 4e 4f 2e 20 ┆SECONDARY ! ! NO. ┆
0x3f40…3f60 21 20 4e 4f 2e 20 21 20 20 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 20 20 20 ┆! NO. ! TEXT ! ┆
0x3f60…3f80 20 20 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 54 45 58 54 20 20 20 ┆ TEXT ! TEXT ┆
0x3f80…3fa0 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 ┆ ! ! ! ! ┆
0x3fa0…3fc0 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 ┆ ! ! ┆
0x3fc0…3fe0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a1 21 20 20 ┆ ! ! ┆
0x3fe0…4000 33 20 20 21 20 20 33 20 20 21 20 50 50 49 20 74 65 73 74 20 3a 20 20 20 20 20 20 20 21 20 70 6f ┆3 ! 3 ! PPI test : ! po┆
0x4000…4020 (32,) 72 74 20 65 72 72 6f 72 20 20 20 20 20 20 20 20 21 20 65 78 70 2e 3a 30 30 65 65 2c 20 72 65 63 ┆rt error ! exp.:00ee, rec┆
0x4020…402e 2e 3a 30 30 72 72 20 20 20 20 20 21 0d 0a ┆.:00rr ! ┆
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0x402e…4067 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
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0x4067…40a0 Params {
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0x4067…40a0 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
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0x40a0…40c0 0a 0d 0a 45 78 70 65 63 74 65 64 20 61 6e 64 20 72 65 63 65 69 76 65 64 20 70 61 74 74 65 72 6e ┆ Expected and received pattern┆
0x40c0…40e0 20 74 65 6c 6c 73 20 79 6f 75 20 77 68 61 74 20 62 69 74 73 20 77 65 6e 74 20 77 72 6f 6e 67 20 ┆ tells you what bits went wrong ┆
0x40e0…4100 0a 77 69 74 68 20 74 68 65 20 74 65 73 74 2e 0d 0a 0d 0a 54 68 69 73 20 65 72 72 6f 72 20 6d 69 ┆ with the test. This error mi┆
0x4100…4120 67 68 74 20 62 65 20 63 61 75 73 65 64 20 62 79 20 6d 61 6c 66 75 6e 63 74 69 6f 6e 20 6f 66 20 ┆ght be caused by malfunction of ┆
0x4120…4140 74 68 65 20 38 32 35 35 41 20 63 68 69 70 2c 20 0a 62 79 20 61 6e 20 69 6e 69 74 69 61 6c 69 7a ┆the 8255A chip, by an initializ┆
0x4140…4160 61 74 69 6f 6e 20 66 61 75 6c 74 20 28 49 2f 4f 20 73 70 61 63 65 20 65 72 72 6f 72 20 29 2c 20 ┆ation fault (I/O space error ), ┆
0x4160…4178 6f 72 20 62 79 20 0a 73 6f 6d 65 74 68 69 6e 67 20 65 6c 73 65 2e 20 0a ┆or by something else. ┆
0x4178…417b FormFeed {
0x4178…417b 0c 81 f9 ┆ ┆
0x4178…417b }
0x417b…4180 0a a1 b0 38 2e ┆ 8.┆
0x4180…41a0 20 b0 54 45 53 54 20 33 20 3d f0 20 b0 38 32 35 34 20 50 52 4f 47 52 41 4d 4d 41 42 4c 45 20 49 ┆ TEST 3 = 8254 PROGRAMMABLE I┆
0x41a0…41c0 4e 54 45 52 56 41 4c 20 54 49 4d 45 52 20 54 45 53 54 0d 0a 0d 0a 54 68 65 20 38 32 35 34 20 74 ┆NTERVAL TIMER TEST The 8254 t┆
0x41c0…41e0 69 6d 65 72 20 74 65 73 74 20 76 65 72 69 66 69 65 73 20 74 68 61 74 20 62 6f 74 68 20 74 68 65 ┆imer test verifies that both the┆
0x41e0…4200 20 72 65 61 6c 20 74 69 6d 65 20 74 69 6d 65 72 73 20 0a 67 65 6e 65 72 61 74 65 64 20 69 6e 74 ┆ real time timers generated int┆
0x4200…4220 (33,) 65 72 72 75 70 74 73 2e 20 54 68 69 73 20 6d 65 61 6e 73 20 74 68 61 74 20 62 6f 74 68 20 74 68 ┆errupts. This means that both th┆
0x4220…4240 65 20 38 32 35 34 20 74 69 6d 65 72 20 0a 63 68 69 70 20 61 6e 64 20 74 68 65 20 74 69 6d 65 72 ┆e 8254 timer chip and the timer┆
0x4240…4260 20 69 6e 74 65 72 72 75 70 74 20 72 65 71 75 65 73 74 20 49 52 30 20 61 6e 64 20 49 52 34 20 6f ┆ interrupt request IR0 and IR4 o┆
0x4260…4280 6e 20 74 68 65 20 0a 38 32 35 39 41 20 69 6e 74 65 72 72 75 70 74 20 63 6f 6e 74 72 6f 6c 6c 65 ┆n the 8259A interrupt controlle┆
0x4280…42a0 72 20 69 73 20 63 68 65 63 6b 65 64 2e 20 54 68 65 20 74 65 73 74 20 6d 61 79 20 70 72 6f 64 75 ┆r is checked. The test may produ┆
0x42a0…42bf 63 65 20 0a 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 65 72 72 6f 72 20 74 65 78 74 2e 0d 0a ┆ce the following error text. ┆
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0x42bf…42f8 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x42bf…42f8 }
0x42f8…4331 Params {
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0x42f8…4331 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x42f8…4331 }
0x4331…4340 0a 0d 0a 84 a1 e1 a2 e2 a1 2d 20 20 20 20 20 ┆ - ┆
0x4340…4360 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
[…0x1…]
0x4380…43a0 20 20 20 20 20 20 20 20 2d 0d 0a 21 20 45 52 52 2e 21 20 4c 45 44 20 21 20 20 20 49 4e 54 52 4f ┆ - ! ERR.! LED ! INTRO┆
0x43a0…43c0 44 55 43 54 49 4f 4e 20 20 20 21 20 20 20 20 20 20 20 45 52 52 4f 52 20 20 20 20 20 20 20 21 20 ┆DUCTION ! ERROR ! ┆
0x43c0…43e0 20 20 20 20 20 20 20 41 55 58 49 4c 4c 41 52 59 20 20 20 20 20 20 20 20 20 21 0d 0a a1 e1 a2 e2 ┆ AUXILLARY ! ┆
0x43e0…4400 a1 21 20 4e 4f 2e 20 21 20 4e 4f 2e 20 21 20 20 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 ┆ ! NO. ! NO. ! TEXT ┆
0x4400…4420 (34,) 21 20 20 20 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 ┆! TEXT ! ┆
0x4420…4440 54 45 58 54 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 ┆TEXT ! ! ! ! ┆
0x4440…4460 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 62 6f 74 68 20 69 6e 74 65 72 72 75 70 ┆ ! both interrup┆
0x4460…4480 74 73 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ts ! ┆
0x4480…44a0 21 0d 0a a1 21 20 20 34 20 20 21 20 20 34 20 20 21 20 50 49 54 20 74 65 73 74 3a 20 20 20 20 20 ┆! ! 4 ! 4 ! PIT test: ┆
0x44a0…44c0 20 20 20 21 20 6d 69 73 73 69 6e 67 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 ┆ ! missing ! ┆
0x44c0…44e0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 ┆ ! ! ! ┆
0x44e0…4500 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 6f 6e 65 20 69 6e 74 65 72 72 ┆ ! ! one interr┆
0x4500…4520 75 70 74 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆upt ! ┆
0x4520…4540 20 20 20 21 0d 0a a2 e2 a1 21 20 20 35 20 20 21 20 20 35 20 20 21 20 50 49 54 20 74 65 73 74 3a ┆ ! ! 5 ! 5 ! PIT test:┆
0x4540…4560 20 20 20 20 20 20 20 20 21 20 6d 69 73 73 69 6e 67 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 ┆ ! missing ! ┆
0x4560…457a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a ┆ ! ┆
0x457a…45b3 Params {
0x457a…45b3 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x457a…45b3 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x457a…45b3 }
0x45b3…45ec Params {
0x45b3…45ec 04 00 27 4e 0c 00 08 00 00 00 00 03 01 50 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N P1` ┆
0x45b3…45ec 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x45b3…45ec }
0x45ec…45ed 0a ┆ ┆
0x45ed…45f0 FormFeed {
0x45ed…45f0 0c 81 9c ┆ ┆
0x45ed…45f0 }
0x45f0…4600 0a a1 b0 39 2e 20 b0 54 45 53 54 20 34 20 3d f0 ┆ 9. TEST 4 = ┆
0x4600…4620 (35,) b0 20 38 32 33 37 41 20 44 49 52 45 43 54 20 4d 45 4d 4f 52 59 20 41 43 43 45 53 53 20 43 4f 4e ┆ 8237A DIRECT MEMORY ACCESS CON┆
0x4620…4640 54 52 4f 4c 4c 45 52 20 54 45 53 54 0d 0a 0d 0a 54 68 65 20 38 32 33 37 41 20 44 4d 41 20 74 65 ┆TROLLER TEST The 8237A DMA te┆
0x4640…4660 73 74 20 69 73 20 74 68 65 20 6c 61 73 74 20 74 65 73 74 20 74 68 61 74 20 69 73 20 72 75 6e 20 ┆st is the last test that is run ┆
0x4660…4680 62 79 20 64 65 66 61 75 6c 74 2c 20 0a 74 68 65 20 72 65 73 74 20 6f 66 20 74 68 65 20 74 65 73 ┆by default, the rest of the tes┆
0x4680…46a0 74 73 20 61 72 65 20 b0 65 78 74 65 6e 64 65 64 20 74 65 73 74 73 20 f0 61 6e 64 20 61 72 65 20 ┆ts are extended tests and are ┆
0x46a0…46c0 6f 6e 6c 79 20 72 75 6e 20 0a 19 80 81 80 77 68 65 6e 20 72 65 71 75 65 73 74 65 64 20 65 78 70 ┆only run when requested exp┆
0x46c0…46e0 6c 69 63 69 74 20 62 79 20 61 20 74 65 73 74 20 70 65 72 73 6f 6e 2e 20 0d 0a 0d 0a 54 68 65 20 ┆licit by a test person. The ┆
0x46e0…4700 44 4d 41 20 74 65 73 74 20 70 65 72 66 6f 72 6d 73 20 61 20 6d 65 6d 6f 72 79 20 74 6f 20 6d 65 ┆DMA test performs a memory to me┆
0x4700…4720 6d 6f 72 79 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 0a 62 65 74 77 65 65 6e 20 63 68 61 ┆mory data transport between cha┆
0x4720…4740 6e 6e 65 6c 20 30 20 61 6e 64 20 63 68 61 6e 6e 65 6c 20 31 2e 20 41 6e 20 38 20 4b 2d 62 79 74 ┆nnel 0 and channel 1. An 8 K-byt┆
0x4740…4760 65 20 62 75 66 66 65 72 20 0a 69 6e 69 74 69 61 6c 69 7a 65 64 20 77 69 74 68 20 61 20 63 6f 75 ┆e buffer initialized with a cou┆
0x4760…4780 6e 74 69 6e 67 20 70 61 74 74 65 72 6e 20 69 73 20 74 72 61 6e 73 66 65 72 72 65 64 20 74 6f 20 ┆nting pattern is transferred to ┆
0x4780…47a0 0a 61 6e 6f 74 68 65 72 20 62 75 66 66 65 72 2c 20 77 68 69 63 68 20 69 73 20 63 6c 65 61 72 65 ┆ another buffer, which is cleare┆
0x47a0…47c0 64 20 62 65 66 6f 72 65 20 74 68 65 20 74 72 61 6e 73 66 65 72 20 62 65 67 69 6e 73 2e 20 0a 54 ┆d before the transfer begins. T┆
0x47c0…47e0 68 65 20 74 65 73 74 20 61 6c 73 6f 20 76 65 72 69 66 69 65 73 20 74 68 65 20 44 4d 41 20 74 65 ┆he test also verifies the DMA te┆
0x47e0…4800 72 6d 69 6e 61 6c 20 63 6f 75 6e 74 20 69 6e 74 65 72 72 75 70 74 2c 20 0a 77 68 69 63 68 20 6d ┆rminal count interrupt, which m┆
0x4800…4820 (36,) 75 73 74 20 6f 63 63 75 72 20 6f 6e 20 74 68 65 20 38 32 35 39 41 20 69 6e 74 65 72 72 75 70 74 ┆ust occur on the 8259A interrupt┆
0x4820…4840 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 49 52 37 2e 20 49 66 20 0a 74 68 65 20 44 4d 41 20 74 72 61 ┆ controller IR7. If the DMA tra┆
0x4840…4860 6e 73 70 6f 72 74 2c 20 77 68 65 6e 20 73 74 61 72 74 65 64 2c 20 64 6f 6e 74 20 73 65 74 73 20 ┆nsport, when started, dont sets ┆
0x4860…4880 74 68 65 20 74 65 72 6d 69 6e 61 6c 20 0a 63 6f 75 6e 74 20 62 69 74 20 68 69 67 68 20 77 69 74 ┆the terminal count bit high wit┆
0x4880…48a0 68 69 6e 20 31 30 30 20 6d 69 6c 6c 69 73 65 63 6f 6e 64 73 2c 20 74 68 65 20 72 6f 75 74 69 6e ┆hin 100 milliseconds, the routin┆
0x48a0…48c0 65 20 20 0a 67 65 6e 65 72 61 74 65 73 20 61 20 74 69 6d 65 6f 75 74 20 6d 65 73 73 61 67 65 2e ┆e generates a timeout message.┆
0x48c0…48e0 20 54 68 65 20 74 65 72 6d 69 6e 61 6c 20 63 6f 75 6e 74 20 62 69 74 20 69 73 20 61 6c 73 6f 20 ┆ The terminal count bit is also ┆
0x48e0…4900 0a 63 68 65 63 6b 65 64 20 6e 6f 74 20 74 6f 20 62 65 20 73 65 74 20 68 69 67 68 20 62 65 66 6f ┆ checked not to be set high befo┆
0x4900…4920 72 65 20 74 68 65 20 74 72 61 6e 73 70 6f 72 74 20 69 73 20 73 74 61 72 74 65 64 2e 20 0d 0a 0d ┆re the transport is started. ┆
0x4920…4940 0a 49 66 20 74 68 65 20 44 4d 41 20 74 72 61 6e 73 70 6f 72 74 20 74 75 72 6e 73 20 6f 75 74 20 ┆ If the DMA transport turns out ┆
0x4940…4960 74 6f 20 62 65 20 73 75 63 63 65 73 73 66 75 6c 2c 20 61 6e 64 20 74 68 65 20 0a 74 65 72 6d 69 ┆to be successful, and the termi┆
0x4960…4980 6e 61 6c 20 63 6f 75 6e 74 20 69 6e 74 65 72 72 75 70 74 20 68 61 73 20 62 65 65 6e 20 73 65 72 ┆nal count interrupt has been ser┆
0x4980…49a0 76 69 63 65 64 2c 20 74 68 65 6e 20 74 68 65 20 72 65 63 65 69 76 65 20 0a 62 75 66 66 65 72 20 ┆viced, then the receive buffer ┆
0x49a0…49c0 69 73 20 63 6f 6d 70 61 72 65 64 20 77 69 74 68 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 62 75 ┆is compared with the transmit bu┆
0x49c0…49e0 66 66 65 72 2c 20 61 6e 64 20 69 66 20 6e 6f 74 20 0a 65 71 75 61 6c 20 61 6e 20 65 72 72 6f 72 ┆ffer, and if not equal an error┆
0x49e0…4a00 20 6d 65 73 73 61 67 65 20 69 73 20 69 73 73 75 65 64 2c 20 6f 74 68 65 72 77 69 73 65 20 74 68 ┆ message is issued, otherwise th┆
0x4a00…4a20 (37,) 65 20 44 4d 41 20 63 68 69 70 20 69 73 20 0a 73 61 69 64 20 74 6f 20 62 65 20 4f 4b 2e 0d 0a 0d ┆e DMA chip is said to be OK. ┆
0x4a20…4a40 0a 49 66 20 74 68 65 20 6d 65 6d 6f 72 79 20 73 69 7a 65 20 69 73 20 31 39 32 20 4b 2d 62 79 74 ┆ If the memory size is 192 K-byt┆
0x4a40…4a60 65 73 2c 20 74 68 65 20 44 4d 41 20 74 72 61 6e 73 66 65 72 20 69 73 20 6d 61 64 65 20 0a 69 6e ┆es, the DMA transfer is made in┆
0x4a60…4a80 20 33 20 70 61 73 73 65 73 2e 20 4f 6e 65 20 69 6e 20 65 61 63 68 20 36 34 20 4b 2d 62 79 74 65 ┆ 3 passes. One in each 64 K-byte┆
0x4a80…4aa0 20 73 65 67 6d 65 6e 74 2e 20 4e 6f 74 65 20 74 68 61 74 20 38 32 35 35 41 20 0a 70 6f 72 74 63 ┆ segment. Note that 8255A portc┆
0x4aa0…4ac0 20 62 69 74 20 34 20 61 6e 64 20 35 20 69 73 20 75 73 65 64 20 74 6f 20 73 65 6c 65 63 74 20 74 ┆ bit 4 and 5 is used to select t┆
0x4ac0…4ae0 68 65 20 44 4d 41 20 74 72 61 6e 73 66 65 72 20 70 61 67 65 2e 20 0a 54 68 65 20 44 4d 41 20 74 ┆he DMA transfer page. The DMA t┆
0x4ae0…4b00 65 73 74 20 6d 61 79 20 70 72 6f 64 75 63 65 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 65 72 ┆est may produce the following er┆
0x4b00…4b11 72 6f 72 20 6d 65 73 73 61 67 65 73 2e 0d 0a 0d 0a ┆ror messages. ┆
0x4b11…4b14 FormFeed {
0x4b11…4b14 0c 82 d0 ┆ ┆
0x4b11…4b14 }
0x4b14…4b15 0a ┆ ┆
0x4b15…4b4e Params {
0x4b15…4b4e 04 00 27 4e 0c 00 08 00 00 00 00 03 01 50 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N P1` ┆
0x4b15…4b4e 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x4b15…4b4e }
0x4b4e…4b87 Params {
0x4b4e…4b87 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x4b4e…4b87 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x4b4e…4b87 }
0x4b87…4ba0 0a 84 e2 e2 e2 a1 e1 a2 a1 f0 e1 e2 e2 a1 2d 20 20 20 20 20 20 20 20 20 20 ┆ - ┆
0x4ba0…4bc0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
[…0x1…]
0x4be0…4c00 20 20 20 2d 0d 0a 21 20 45 52 52 2e 21 20 4c 45 44 20 21 20 20 20 49 4e 54 52 4f 44 55 43 54 49 ┆ - ! ERR.! LED ! INTRODUCTI┆
0x4c00…4c20 (38,) 4f 4e 20 20 20 21 20 20 20 20 20 20 20 45 52 52 4f 52 20 20 20 20 20 20 20 21 20 20 20 20 20 20 ┆ON ! ERROR ! ┆
0x4c20…4c40 20 20 41 55 58 49 4c 4c 41 52 59 20 20 20 20 20 20 20 20 20 21 0d 0a e2 a1 e1 a2 e2 a1 21 20 4e ┆ AUXILLARY ! ! N┆
0x4c40…4c60 4f 2e 20 21 20 4e 4f 2e 20 21 20 20 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 ┆O. ! NO. ! TEXT ! ┆
0x4c60…4c80 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 54 45 58 54 ┆ TEXT ! TEXT┆
0x4c80…4ca0 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 ┆ ! ! ! ! ┆
0x4ca0…4cc0 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x4cc0…4ce0 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a1 ┆ ! ! ┆
0x4ce0…4d00 21 20 20 38 20 20 21 20 20 38 20 20 21 20 44 4d 41 20 74 65 73 74 3a 20 20 20 20 20 20 20 20 21 ┆! 8 ! 8 ! DMA test: !┆
0x4d00…4d20 20 54 43 20 62 65 66 6f 72 65 20 73 74 61 72 74 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 ┆ TC before start ! ┆
0x4d20…4d40 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 ┆ ! ! ! ! ┆
0x4d40…4d60 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x4d60…4d80 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 ┆ ! !┆
0x4d80…4da0 0d 0a a2 e2 a1 21 20 20 39 20 20 21 20 20 39 20 20 21 20 44 4d 41 20 74 65 73 74 3a 20 20 20 20 ┆ ! 9 ! 9 ! DMA test: ┆
0x4da0…4dc0 20 20 20 20 21 20 74 69 6d 65 6f 75 74 20 20 20 20 20 20 20 20 20 20 20 21 20 65 78 70 2e 3a 3c ┆ ! timeout ! exp.:<┆
0x4dc0…4de0 30 30 30 30 3e 2c 20 72 65 63 2e 3a 3c 72 72 72 72 3e 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 ┆0000>, rec.:<rrrr> ! ! ! ┆
0x4de0…4e00 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 ┆ ! ! ┆
0x4e00…4e20 (39,) 20 20 20 20 20 20 20 20 20 21 20 73 65 67 6d 2e 3a 3c 73 73 73 73 3e 2c 20 61 64 72 2e 3a 3c 61 ┆ ! segm.:<ssss>, adr.:<a┆
0x4e20…4e40 61 61 61 3e 21 0d 0a a1 21 20 31 30 20 20 21 20 31 30 20 20 21 20 44 4d 41 20 74 65 73 74 3a 20 ┆aaa>! ! 10 ! 10 ! DMA test: ┆
0x4e40…4e60 20 20 20 20 20 20 20 21 20 64 61 74 61 20 65 72 72 6f 72 20 20 20 20 20 20 20 20 21 20 65 78 70 ┆ ! data error ! exp┆
0x4e60…4e80 2e 3a 3c 65 65 65 65 3e 2c 20 72 65 63 2e 3a 3c 72 72 72 72 3e 20 21 0d 0a 21 20 20 20 20 20 21 ┆.:<eeee>, rec.:<rrrr> ! ! !┆
0x4e80…4ea0 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 ┆ ! ! ┆
0x4ea0…4ec0 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x4ec0…4ee0 20 20 20 20 20 20 20 21 0d 0a a1 21 20 31 31 20 20 21 20 31 31 20 20 21 20 44 4d 41 20 74 65 73 ┆ ! ! 11 ! 11 ! DMA tes┆
0x4ee0…4f00 74 3a 20 20 20 20 20 20 20 20 21 20 6d 69 73 73 69 6e 67 20 69 6e 74 65 72 72 75 70 74 20 21 20 ┆t: ! missing interrupt ! ┆
0x4f00…4f1c 6c 65 76 65 6c 2e 3a 30 30 30 37 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a ┆level.:0007 ! ┆
0x4f1c…4f55 Params {
0x4f1c…4f55 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x4f1c…4f55 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x4f1c…4f55 }
0x4f55…4f8e Params {
0x4f55…4f8e 04 00 27 4e 0c 00 08 00 00 00 00 03 01 50 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N P1` ┆
0x4f55…4f8e 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x4f55…4f8e }
0x4f8e…4fa0 0a 0d 0a 45 72 72 6f 72 20 6d 65 73 73 61 67 65 20 39 ┆ Error message 9┆
0x4fa0…4fc0 2c 20 74 69 6d 65 6f 75 74 2c 20 77 72 69 74 65 73 20 74 68 65 20 44 4d 41 20 63 6f 75 6e 74 20 ┆, timeout, writes the DMA count ┆
0x4fc0…4fe0 76 61 6c 75 65 20 61 73 20 0a 61 75 78 69 6c 6c 61 72 79 20 64 61 74 61 2e 20 54 68 65 20 69 6e ┆value as auxillary data. The in┆
0x4fe0…5000 69 74 69 61 6c 20 63 6f 75 6e 74 20 76 61 6c 75 65 20 69 73 20 31 46 42 41 20 68 65 78 2e 20 28 ┆itial count value is 1FBA hex. (┆
0x5000…5020 (40,) 38 20 4b 2d 0a 62 79 74 65 73 29 2c 20 61 6e 64 20 74 68 65 20 65 78 70 65 63 74 65 64 20 63 6f ┆8 K- bytes), and the expected co┆
0x5020…5040 75 6e 74 20 69 73 20 7a 65 72 6f 2c 20 77 68 65 6e 20 61 6c 6c 20 74 72 61 6e 73 66 65 72 73 20 ┆unt is zero, when all transfers ┆
0x5040…5060 0a 68 61 76 65 20 62 65 65 6e 20 6d 61 64 65 2e 20 20 20 0d 0a 0d 0a 4e 6f 74 65 20 74 68 61 74 ┆ have been made. Note that┆
0x5060…5080 20 74 68 65 20 6f 74 68 65 72 20 44 4d 41 20 63 68 61 6e 6e 65 6c 73 20 61 72 65 20 6e 6f 74 20 ┆ the other DMA channels are not ┆
0x5080…50a0 74 65 73 74 65 64 20 62 79 20 74 68 69 73 20 0a 72 6f 75 74 69 6e 65 2c 20 74 68 65 20 61 72 65 ┆tested by this routine, the are┆
0x50a0…50c0 20 74 65 73 74 65 64 20 62 79 20 74 68 65 20 63 6f 6e 74 72 6f 6c 6c 65 72 73 2c 20 74 6f 20 77 ┆ tested by the controllers, to w┆
0x50c0…50da 68 6f 6d 20 74 68 65 79 20 61 72 65 20 0a 64 65 64 69 63 61 74 65 64 2e 0d 0a ┆hom they are dedicated. ┆
0x50da…50dd FormFeed {
0x50da…50dd 0c 81 cf ┆ ┆
0x50da…50dd }
0x50dd…50e0 0a a1 b0 ┆ ┆
0x50e0…5100 31 30 2e 20 b0 54 45 53 54 20 35 20 3d f0 20 f0 b0 38 32 37 34 20 43 48 41 4e 4e 45 4c 20 41 20 ┆10. TEST 5 = 8274 CHANNEL A ┆
0x5100…5120 54 45 53 54 0d 0a 0d 0a 54 68 65 20 72 65 73 74 20 6f 66 20 74 68 65 20 74 65 73 74 73 20 61 72 ┆TEST The rest of the tests ar┆
0x5120…5140 65 20 b0 65 78 74 65 6e 64 65 64 20 74 65 73 74 73 20 f0 61 6e 64 20 61 72 65 20 6f 6e 6c 79 20 ┆e extended tests and are only ┆
0x5140…5160 72 75 6e 20 0a 19 80 81 80 77 68 65 6e 20 72 65 71 75 65 73 74 65 64 20 65 78 70 6c 69 63 69 74 ┆run when requested explicit┆
0x5160…5180 20 62 79 20 61 20 74 65 73 74 20 70 65 72 73 6f 6e 2e 20 4e 4f 54 45 20 74 68 61 74 20 69 74 20 ┆ by a test person. NOTE that it ┆
0x5180…51a0 6d 61 79 20 0a 19 80 81 80 64 69 73 74 75 72 62 20 73 65 72 69 65 6c 20 6c 69 6e 65 73 20 73 65 ┆may disturb seriel lines se┆
0x51a0…51c0 72 69 6f 75 73 6c 79 20 69 66 20 74 68 65 20 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 6c 69 6e ┆riously if the communication lin┆
0x51c0…51e0 65 20 0a 19 80 81 80 74 65 73 74 73 20 61 72 65 20 73 74 61 72 74 65 64 20 77 68 65 6e 20 74 68 ┆e tests are started when th┆
0x51e0…5200 65 20 6c 69 6e 65 73 20 61 72 65 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 4d 4f 44 45 4d 53 2e ┆e lines are connected to MODEMS.┆
0x5200…5220 (41,) 20 0a 19 80 81 80 54 68 65 20 63 69 72 63 75 69 74 20 6c 69 6e 65 20 6d 75 73 74 20 62 65 20 6f ┆ The circuit line must be o┆
0x5220…5240 70 65 6e 2c 20 61 6e 64 20 61 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 20 6d 75 73 74 20 ┆pen, and a loop back cable must ┆
0x5240…5260 62 65 20 0a 19 80 81 80 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 4a 33 20 61 6e 64 20 4a 34 2e 20 ┆be connected to J3 and J4. ┆
0x5260…5280 53 65 65 20 61 70 70 65 6e 64 69 78 20 41 2e 0d 0a 0d 0a 54 68 65 20 38 32 37 34 20 63 68 41 20 ┆See appendix A. The 8274 chA ┆
0x5280…52a0 69 6d 70 6c 65 6d 65 6e 74 73 20 74 68 65 20 52 43 2d 63 69 72 63 75 69 74 20 63 6f 6d 6d 75 6e ┆implements the RC-circuit commun┆
0x52a0…52c0 69 63 61 74 69 6f 6e 20 6c 69 6e 65 2e 20 0a 54 68 69 73 20 74 65 73 74 20 6d 75 73 74 20 62 65 ┆ication line. This test must be┆
0x52c0…52e0 20 65 78 65 63 75 74 65 64 20 77 69 74 68 20 61 6e 20 6f 70 65 6e 20 4a 32 20 63 6f 6e 6e 65 63 ┆ executed with an open J2 connec┆
0x52e0…5300 74 6f 72 2c 20 6f 72 20 0a 77 69 74 68 20 74 68 65 20 63 6f 6e 6e 65 63 74 65 64 20 74 65 72 6d ┆tor, or with the connected term┆
0x5300…5320 69 6e 61 6c 73 20 73 68 75 74 20 6f 66 66 2c 20 6f 74 68 65 72 77 69 73 65 20 73 6f 6d 65 20 0a ┆inals shut off, otherwise some ┆
0x5320…5340 74 65 72 6d 69 6e 61 6c 20 6d 69 67 74 68 20 64 69 73 74 75 72 62 20 74 68 65 20 6c 69 6e 65 2e ┆terminal migth disturb the line.┆
0x5340…5360 0d 0a 0d 0a 54 68 65 20 38 32 37 34 20 63 68 41 20 52 43 2d 63 69 72 63 75 69 74 20 74 65 73 74 ┆ The 8274 chA RC-circuit test┆
0x5360…5380 20 70 65 72 66 6f 72 6d 20 61 20 73 65 72 69 61 6c 20 74 72 61 6e 73 70 6f 72 74 20 6f 66 20 0a ┆ perform a serial transport of ┆
0x5380…53a0 61 6e 20 38 20 4b 2d 62 79 74 65 20 62 75 66 66 65 72 20 77 69 74 68 20 61 20 63 6f 75 6e 74 69 ┆an 8 K-byte buffer with a counti┆
0x53a0…53c0 6e 67 20 70 61 74 74 65 72 6e 20 74 6f 20 61 20 72 65 63 65 69 76 65 20 0a 62 75 66 66 65 72 2c ┆ng pattern to a receive buffer,┆
0x53c0…53e0 20 77 68 69 63 68 20 69 73 20 63 6c 65 61 72 65 64 20 62 65 66 6f 72 65 20 74 68 65 20 74 72 61 ┆ which is cleared before the tra┆
0x53e0…5400 6e 73 70 6f 72 74 20 74 61 6b 65 73 20 70 6c 61 63 65 2e 0d 0a 0d 0a 54 68 65 20 38 32 37 34 20 ┆nsport takes place. The 8274 ┆
0x5400…5420 (42,) 63 68 41 20 69 73 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 74 6f 20 53 44 4c 43 20 6d 6f 64 65 2c ┆chA is initialized to SDLC mode,┆
0x5420…5440 20 77 69 74 68 20 44 4d 41 20 72 65 63 65 69 76 65 2c 20 0a 61 6e 64 20 70 6f 6c 6c 65 64 20 64 ┆ with DMA receive, and polled d┆
0x5440…5460 61 74 61 20 74 72 61 6e 73 6d 69 74 2e 20 57 68 65 6e 20 74 68 65 20 63 68 69 70 20 68 61 73 20 ┆ata transmit. When the chip has ┆
0x5460…5480 63 6f 6d 70 6c 65 74 65 64 20 61 20 0a 74 72 61 6e 73 66 65 72 20 69 74 20 61 6c 73 6f 20 67 65 ┆completed a transfer it also ge┆
0x5480…54a0 6e 65 72 61 74 65 73 20 61 6e 20 65 6e 64 20 6f 66 20 6d 65 73 73 61 67 65 20 69 6e 74 65 72 72 ┆nerates an end of message interr┆
0x54a0…54c0 75 70 74 2e 20 54 68 65 20 0a 74 65 73 74 20 6e 61 74 75 72 61 6c 6c 79 20 76 65 72 69 66 69 65 ┆upt. The test naturally verifie┆
0x54c0…54e0 73 20 69 66 20 74 68 69 73 20 69 6e 74 65 72 72 75 70 74 20 72 65 61 6c 6c 79 20 69 73 20 73 65 ┆s if this interrupt really is se┆
0x54e0…5500 72 76 69 63 65 64 20 0a 6f 72 20 6e 6f 74 2e 0d 0a 0d 0a 41 20 74 69 6d 65 6f 75 74 20 6d 65 73 ┆rviced or not. A timeout mes┆
0x5500…5520 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 20 69 66 20 74 68 65 20 74 72 61 6e 73 6d 69 ┆sage is generated if the transmi┆
0x5520…5540 74 20 62 75 66 66 65 72 20 6e 65 76 65 72 20 0a 67 65 74 73 20 65 6d 70 74 79 20 64 75 72 69 6e ┆t buffer never gets empty durin┆
0x5540…5560 67 20 74 68 65 20 70 6f 6c 6c 65 64 20 74 72 61 6e 73 6d 69 73 73 69 6f 6e 2e 20 0d 0a 0d 0a 57 ┆g the polled transmission. W┆
0x5560…5580 68 65 6e 20 61 6c 6c 20 63 68 61 72 61 63 74 65 72 73 20 68 61 76 65 20 62 65 65 6e 20 73 65 6e ┆hen all characters have been sen┆
0x5580…55a0 64 2c 20 61 6e 64 20 74 68 65 20 69 6e 74 65 72 72 75 70 74 20 61 6c 73 6f 20 0a 68 61 73 20 62 ┆d, and the interrupt also has b┆
0x55a0…55c0 65 65 6e 20 73 65 72 76 69 63 65 64 2c 20 74 68 65 6e 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 ┆een serviced, then the transmit ┆
0x55c0…55e0 61 6e 64 20 72 65 63 65 69 76 65 20 62 75 66 66 65 72 73 20 61 72 65 20 0a 63 6f 6d 70 61 72 65 ┆and receive buffers are compare┆
0x55e0…5600 64 2e 20 49 66 20 61 6e 20 65 72 72 6f 72 20 69 73 20 64 65 74 65 63 74 65 64 2c 20 61 6e 20 65 ┆d. If an error is detected, an e┆
0x5600…5620 (43,) 72 72 6f 72 20 6d 65 73 73 61 67 65 20 69 73 20 0a 77 72 69 74 74 65 6e 20 74 6f 20 74 68 65 20 ┆rror message is written to the ┆
0x5620…5640 22 74 65 73 74 2d 6d 61 73 74 65 72 22 2c 20 6f 74 68 65 72 77 69 73 65 20 74 68 65 20 52 43 2d ┆"test-master", otherwise the RC-┆
0x5640…5660 63 69 72 63 75 69 74 20 0a 63 68 61 6e 6e 65 6c 20 69 73 20 73 61 69 64 20 74 6f 20 62 65 20 4f ┆circuit channel is said to be O┆
0x5660…5680 4b 2e 20 42 65 6c 6f 77 20 69 73 20 61 20 6c 69 73 74 20 6f 66 20 61 6c 6c 20 70 6f 73 73 69 62 ┆K. Below is a list of all possib┆
0x5680…56a0 6c 65 20 0a 65 72 72 6f 72 20 6d 65 73 73 61 67 65 73 20 67 65 6e 65 72 61 74 65 64 20 62 79 20 ┆le error messages generated by ┆
0x56a0…56af 74 68 69 73 20 74 65 73 74 20 3a 0d 0a 0d 0a ┆this test : ┆
0x56af…56b2 FormFeed {
0x56af…56b2 0c 83 98 ┆ ┆
0x56af…56b2 }
0x56b2…56b3 0a ┆ ┆
0x56b3…56ec Params {
0x56b3…56ec 04 00 27 4e 0c 00 08 00 00 00 00 03 01 50 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N P1` ┆
0x56b3…56ec 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x56b3…56ec }
0x56ec…5725 Params {
0x56ec…5725 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x56ec…5725 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x56ec…5725 }
0x5725…5740 0a e2 e1 f0 e2 a1 e1 a2 e2 a1 84 2d 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ - ┆
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0x5760…5780 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2d 0d ┆ - ┆
0x5780…57a0 0a 21 20 45 52 52 2e 21 20 4c 45 44 20 21 20 20 20 49 4e 54 52 4f 44 55 43 54 49 4f 4e 20 20 20 ┆ ! ERR.! LED ! INTRODUCTION ┆
0x57a0…57c0 21 20 20 20 20 20 20 20 45 52 52 4f 52 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 53 45 43 ┆! ERROR ! SEC┆
0x57c0…57e0 4f 4e 44 41 52 59 20 20 20 20 20 20 20 20 20 21 0d 0a a1 e1 a2 e2 a1 21 20 4e 4f 2e 20 21 20 4e ┆ONDARY ! ! NO. ! N┆
0x57e0…5800 4f 2e 20 21 20 20 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 54 ┆O. ! TEXT ! T┆
0x5800…5820 (44,) 45 58 54 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 ┆EXT ! TEXT ┆
0x5820…5840 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ! ! ! ┆
0x5840…5860 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 73 65 67 ┆ ! ! seg┆
0x5860…5880 6d 2e 3a 3c 73 73 73 73 3e 2c 20 61 64 72 2e 3a 3c 61 61 61 61 3e 21 0d 0a a1 21 20 32 30 20 20 ┆m.:<ssss>, adr.:<aaaa>! ! 20 ┆
0x5880…58a0 21 20 32 30 20 20 21 20 38 32 37 34 20 63 68 41 20 74 65 73 74 3a 20 20 20 21 20 64 61 74 61 20 ┆! 20 ! 8274 chA test: ! data ┆
0x58a0…58c0 65 72 72 6f 72 20 20 20 20 20 20 20 20 21 20 65 78 70 2e 3a 3c 65 65 65 65 3e 2c 20 72 65 63 2e ┆error ! exp.:<eeee>, rec.┆
0x58c0…58e0 3a 3c 72 72 72 72 3e 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 ┆:<rrrr> ! ! ! ! ┆
0x58e0…5900 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 ┆ ! ! ┆
0x5900…5920 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a2 e2 a1 21 ┆ ! !┆
0x5920…5940 20 32 31 20 20 21 20 32 31 20 20 21 20 38 32 37 34 20 63 68 41 20 74 65 73 74 3a 20 20 20 21 20 ┆ 21 ! 21 ! 8274 chA test: ! ┆
0x5940…5960 74 69 6d 65 6f 75 74 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆timeout ! ┆
0x5960…5980 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 ┆ ! ! ! ! ┆
0x5980…59a0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x59a0…59c0 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d ┆ ! ! ┆
0x59c0…59e0 0a a1 21 20 32 32 20 20 21 20 32 32 20 20 21 20 38 32 37 34 20 63 68 41 20 74 65 73 74 3a 20 20 ┆ ! 22 ! 22 ! 8274 chA test: ┆
0x59e0…5a00 20 21 20 74 72 61 6e 73 66 65 72 20 65 72 72 6f 72 20 20 20 20 21 20 72 65 63 2e 3a 3c 72 72 72 ┆ ! transfer error ! rec.:<rrr┆
0x5a00…5a20 (45,) 72 3e 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 ┆r> ! ! ! !┆
0x5a20…5a40 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x5a40…5a60 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x5a60…5a80 20 21 0d 0a a1 21 20 32 33 20 20 21 20 32 33 20 20 21 20 38 32 37 34 20 63 68 41 20 74 65 73 74 ┆ ! ! 23 ! 23 ! 8274 chA test┆
0x5a80…5aa0 3a 20 20 20 21 20 6d 69 73 73 69 6e 67 20 69 6e 74 65 72 72 75 70 74 20 21 20 20 20 20 20 20 20 ┆: ! missing interrupt ! ┆
0x5aa0…5ab6 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a ┆ ! ┆
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0x5b28…5b40 0a 0d 0a 54 68 65 20 74 65 73 74 20 69 73 20 72 75 6e 20 61 74 20 66 75 ┆ The test is run at fu┆
0x5b40…5b56 6c 6c 20 73 70 65 65 64 2c 20 32 35 30 20 4b 20 62 61 75 64 2e 0a ┆ll speed, 250 K baud. ┆
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0x5b59…5b60 0a a1 b0 31 31 2e 20 ┆ 11. ┆
0x5b60…5b80 b0 54 45 53 54 20 36 20 3d f0 20 b0 38 32 37 34 20 43 48 41 4e 4e 45 4c 20 42 20 54 45 53 54 0d ┆ TEST 6 = 8274 CHANNEL B TEST ┆
0x5b80…5ba0 0a 0d 0a 54 68 65 20 38 32 37 34 20 63 68 42 20 69 6d 70 6c 65 6d 65 6e 74 73 20 74 68 65 20 42 ┆ The 8274 chB implements the B┆
0x5ba0…5bc0 53 43 20 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 6c 69 6e 65 2e 20 54 68 69 73 20 0a 74 65 73 ┆SC communication line. This tes┆
0x5bc0…5be0 74 20 6d 75 73 74 20 62 65 20 65 78 65 63 75 74 65 64 20 77 69 74 68 20 61 20 6c 6f 6f 70 62 61 ┆t must be executed with a loopba┆
0x5be0…5c00 63 6b 20 63 61 62 6c 65 20 63 6f 6e 6e 65 63 74 65 64 2e 20 53 65 65 20 0a 61 70 70 65 6e 64 69 ┆ck cable connected. See appendi┆
0x5c00…5c20 (46,) 78 20 41 2e 0d 0a 0d 0a 0d 0a b0 a1 31 31 2e 31 20 53 74 61 74 75 73 20 53 69 67 6e 61 6c 73 20 ┆x A. 11.1 Status Signals ┆
0x5c20…5c40 43 68 65 63 6b 2e 0d 0a 0d 0a 42 65 66 6f 72 65 20 61 6e 79 20 73 65 72 69 61 6c 20 64 61 74 61 ┆Check. Before any serial data┆
0x5c40…5c60 20 74 72 61 6e 73 70 6f 72 74 20 69 73 20 73 74 61 72 74 65 64 2c 20 74 68 65 20 56 2e 32 34 20 ┆ transport is started, the V.24 ┆
0x5c60…5c80 0a 69 6e 74 65 72 66 61 63 65 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 73 20 61 73 20 77 65 6c ┆ interface status signals as wel┆
0x5c80…5ca0 6c 20 61 73 20 74 68 65 20 58 2e 32 31 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 73 20 0a 61 72 ┆l as the X.21 status signals ar┆
0x5ca0…5cc0 65 20 63 68 65 63 6b 65 64 2e 20 54 68 65 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 73 20 61 72 ┆e checked. The status signals ar┆
0x5cc0…5ce0 65 20 63 6f 6e 6e 65 63 74 65 64 20 6c 69 6b 65 20 74 68 69 73 20 3a 20 0d 0a 82 82 0d 0a 20 20 ┆e connected like this : ┆
0x5ce0…5d00 a1 b0 56 2e 32 34 20 53 74 61 74 75 73 20 53 69 67 6e 61 6c 73 2e 0d 0a 0d 0a 20 20 52 65 71 75 ┆ V.24 Status Signals. Requ┆
0x5d00…5d20 65 73 74 20 54 6f 20 53 65 6e 64 2c 20 20 20 20 20 52 54 53 62 20 2d 2d 2d 3e 84 84 2d 84 0a 81 ┆est To Send, RTSb ---> - ┆
0x5d20…5d40 0d 0a 20 20 43 6c 65 61 72 20 54 6f 20 53 65 6e 64 2c 20 20 20 20 20 20 20 43 54 53 62 20 2d 2d ┆ Clear To Send, CTSb --┆
0x5d40…5d60 2d 3c 2d 0a 0d 0a 20 20 44 61 74 61 20 53 65 74 20 52 65 61 64 79 2c 20 20 20 20 20 20 44 53 52 ┆-<- Data Set Ready, DSR┆
0x5d60…5d80 62 20 2d 2d 2d 3c 2d 0a 0d 0a 0d 0a 20 20 44 61 74 61 20 54 65 72 6d 69 6e 61 6c 20 52 65 61 64 ┆b ---<- Data Terminal Read┆
0x5d80…5da0 79 2c 20 44 54 52 42 20 2d 2d 2d 3e 2d 0a 0d 0a 20 20 44 61 74 61 20 43 61 72 72 69 65 72 20 44 ┆y, DTRB --->- Data Carrier D┆
0x5da0…5dc0 65 74 65 63 74 2c 20 44 43 44 42 20 2d 2d 2d 3c 2d 0a 0d 0a 20 20 43 61 6c 6c 69 6e 67 20 49 6e ┆etect, DCDB ---<- Calling In┆
0x5dc0…5dda 64 69 63 61 74 6f 72 2c 20 20 20 43 49 42 20 20 2d 2d 2d 3c 2d 0a 0d 0a 0d 0a ┆dicator, CIB ---<- ┆
0x5dda…5ddd FormFeed {
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0x5ddd…5de0 0a 81 20 ┆ ┆
0x5de0…5e00 20 a1 b0 58 2e 32 31 20 53 74 61 74 75 73 20 53 69 67 6e 61 6c 73 2e 0d 0a 0d 0a 20 20 43 6f 6e ┆ X.21 Status Signals. Con┆
0x5e00…5e20 (47,) 74 72 6f 6c 20 28 41 29 2c 20 20 20 20 20 20 20 20 20 43 28 41 29 42 20 2d 2d 3e 2d 0a 0d 0a 20 ┆trol (A), C(A)B -->- ┆
0x5e20…5e40 20 49 6e 64 69 63 61 74 69 6f 6e 20 28 41 29 2c 20 20 20 20 20 20 49 28 41 29 42 20 2d 2d 3c 2d ┆ Indication (A), I(A)B --<-┆
0x5e40…5e60 20 20 20 0a 0d 0a 20 20 43 6f 6e 74 72 6f 6c 20 28 42 29 2c 20 20 20 20 20 20 20 20 20 43 28 42 ┆ Control (B), C(B┆
0x5e60…5e80 29 42 20 2d 2d 3e 2d 20 0a 0d 0a 20 20 49 6e 64 69 63 61 74 69 6f 6e 20 28 42 29 2c 20 20 20 20 ┆)B -->- Indication (B), ┆
0x5e80…5ea0 20 20 49 28 42 29 42 20 2d 2d 3c 2d 0a 0d 0a 41 20 73 74 61 74 75 73 20 65 72 72 6f 72 20 64 75 ┆ I(B)B --<- A status error du┆
0x5ea0…5ec0 72 69 6e 67 20 56 2e 32 34 20 74 65 73 74 20 6d 69 67 68 74 20 6c 6f 6f 6b 20 6c 69 6b 65 20 74 ┆ring V.24 test might look like t┆
0x5ec0…5ee0 68 69 73 20 3a 0d 0a 0d 0a b0 38 32 37 34 20 63 68 42 20 74 65 73 74 3a 20 56 32 34 20 73 74 61 ┆his : 8274 chB test: V24 sta┆
0x5ee0…5f00 74 75 73 20 65 72 72 6f 72 20 20 20 72 65 63 2e 3a 20 30 30 30 31 20 20 20 65 78 70 2e 3a 20 30 ┆tus error rec.: 0001 exp.: 0┆
0x5f00…5f20 30 30 30 0d 0a 0d 0a 4f 6e 6c 79 20 74 68 65 20 74 68 72 65 65 20 6c 65 61 73 74 20 73 69 67 6e ┆000 Only the three least sign┆
0x5f20…5f40 69 66 69 63 61 6e 74 20 62 69 74 73 20 61 72 65 20 75 73 65 64 2c 20 61 6e 64 20 6d 75 73 74 20 ┆ificant bits are used, and must ┆
0x5f40…5f60 62 65 20 0a 69 6e 74 65 72 70 72 65 74 65 64 20 6c 69 6b 65 20 74 68 69 73 20 3a 0d 0a 0d 0a 42 ┆be interpreted like this : B┆
0x5f60…5f80 69 74 20 30 20 3d 20 2d 2c 44 53 52 42 20 3b 20 42 69 74 20 31 20 3d 20 2d 2c 43 49 42 20 3b 20 ┆it 0 = -,DSRB ; Bit 1 = -,CIB ; ┆
0x5f80…5fa0 42 69 74 20 32 20 3d 20 2d 2c 43 54 53 42 0d 0a 0d 0a 54 68 65 20 6d 65 73 73 61 67 65 20 61 62 ┆Bit 2 = -,CTSB The message ab┆
0x5fa0…5fc0 6f 76 65 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 73 6f 6d 65 74 68 69 6e 67 20 69 73 20 ┆ove indicates that something is ┆
0x5fc0…5fe0 77 72 6f 6e 67 20 77 69 74 68 20 74 68 65 20 0a 56 2e 32 34 20 44 61 74 61 20 53 65 74 20 52 65 ┆wrong with the V.24 Data Set Re┆
0x5fe0…6000 61 64 79 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 2c 20 77 68 69 63 68 20 69 73 20 74 6f 67 67 ┆ady status signal, which is togg┆
0x6000…6020 (48,) 6c 65 64 20 62 79 20 74 68 65 20 0a 52 65 71 75 65 73 74 20 54 6f 20 53 65 6e 64 20 73 69 67 6e ┆led by the Request To Send sign┆
0x6020…6040 61 6c 20 62 79 20 74 68 65 20 74 65 73 74 20 70 72 6f 67 72 61 6d 2e 0d 0a 0d 0a 41 20 73 74 61 ┆al by the test program. A sta┆
0x6040…6060 74 75 73 20 65 72 72 6f 72 20 64 75 72 69 6e 67 20 74 68 65 20 58 2e 32 31 20 74 65 73 74 20 61 ┆tus error during the X.21 test a┆
0x6060…6080 6c 6c 77 61 79 73 20 6c 6f 6f 6b 73 20 6c 69 6b 65 20 74 68 69 73 3a 0d 0a 0d 0a b0 38 32 37 34 ┆llways looks like this: 8274┆
0x6080…60a0 20 63 68 42 20 74 65 73 74 3a 20 58 32 31 20 43 6f 6e 74 72 6f 6c 2d 49 6e 64 69 63 61 74 69 6f ┆ chB test: X21 Control-Indicatio┆
0x60a0…60c0 6e 20 65 72 72 6f 72 0d 0a 0d 0a 54 68 69 73 20 6d 65 73 73 61 67 65 20 69 6e 64 69 63 61 74 65 ┆n error This message indicate┆
0x60c0…60e0 73 20 74 68 61 74 20 73 6f 6d 65 74 68 69 6e 67 20 69 73 20 77 72 6f 6e 67 20 77 69 74 68 20 74 ┆s that something is wrong with t┆
0x60e0…6100 68 65 20 58 2e 32 31 20 0a 73 74 61 74 75 73 20 73 69 67 6e 61 6c 20 49 20 3d 20 43 6c 65 61 72 ┆he X.21 status signal I = Clear┆
0x6100…6120 20 54 6f 20 53 65 6e 64 2c 20 77 68 69 63 68 20 69 73 20 63 6f 6e 74 72 6f 6c 6c 65 64 20 62 79 ┆ To Send, which is controlled by┆
0x6120…6140 20 74 68 65 20 0a 73 69 67 6e 61 6c 20 63 61 6c 6c 65 64 20 43 20 3d 20 44 61 74 61 20 54 65 72 ┆ the signal called C = Data Ter┆
0x6140…6152 6d 69 6e 61 6c 20 52 65 61 64 79 2e 0d 0a 0d 0a 0d 0a ┆minal Ready. ┆
0x6152…6155 FormFeed {
0x6152…6155 0c 83 80 ┆ ┆
0x6152…6155 }
0x6155…6160 0a b0 a1 31 31 2e 32 20 56 2e 32 ┆ 11.2 V.2┆
0x6160…6180 34 2f 58 2e 32 31 20 53 65 6c 65 63 74 2e 0d 0a 0d 0a 53 65 6c 65 63 74 69 6f 6e 20 6f 66 20 56 ┆4/X.21 Select. Selection of V┆
0x6180…61a0 2e 32 34 2f 2d 2c 58 2e 32 31 20 6d 6f 64 65 20 69 73 20 64 6f 6e 65 20 66 72 6f 6d 20 74 68 65 ┆.24/-,X.21 mode is done from the┆
0x61a0…61c0 20 38 32 37 33 20 53 44 4c 43 20 0a 63 6f 6e 74 72 6f 6c 6c 65 72 20 76 69 61 20 74 68 65 20 6c ┆ 8273 SDLC controller via the l┆
0x61c0…61e0 6f 6f 70 62 61 63 6b 20 63 61 62 6c 65 2c 20 73 65 65 20 62 65 6c 6f 77 2e 0d 0a 0d 0a a1 20 20 ┆oopback cable, see below. ┆
0x61e0…6200 20 4a 33 2e 20 20 20 e1 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ J3. ┆
0x6200…6220 (49,) 20 20 20 20 20 20 20 20 20 84 a1 20 20 20 20 4a 34 2e 20 20 20 20 0d 0a 0d 0a 2d 2c 58 2e 32 31 ┆ J4. -,X.21┆
0x6220…6240 42 20 20 2d 2d 2d 3c 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆B ---<----------- ┆
0x6240…6260 20 20 20 20 20 2d 2d 2d 3c 2d 20 52 54 53 43 0d 0a 0d 0a 54 68 65 20 64 69 6f 64 65 20 61 6e 64 ┆ ---<- RTSC The diode and┆
0x6260…6280 20 74 68 65 20 72 65 73 69 73 74 6f 72 20 70 72 65 76 65 6e 74 73 20 6e 65 67 61 74 69 76 65 20 ┆ the resistor prevents negative ┆
0x6280…62a0 76 6f 6c 74 61 67 65 20 6f 6e 20 74 68 65 20 0a 2d 2c 58 2e 32 31 20 70 69 6e 2e 0d 0a 0d 0a 4e ┆voltage on the -,X.21 pin. N┆
0x62a0…62c0 4f 54 45 20 74 68 61 74 20 74 68 65 20 38 32 37 33 20 63 68 69 70 20 6d 61 79 20 64 65 73 74 75 ┆OTE that the 8273 chip may destu┆
0x62c0…62e0 72 62 20 74 68 65 20 38 32 37 34 20 63 68 42 20 74 65 73 74 20 0a 73 65 72 69 6f 75 73 6c 79 20 ┆rb the 8274 chB test seriously ┆
0x62e0…6300 69 66 20 74 68 65 20 56 2e 32 34 2f 58 2e 32 31 20 73 65 6c 65 63 74 69 6f 6e 20 6c 6f 67 69 63 ┆if the V.24/X.21 selection logic┆
0x6300…6320 20 66 61 69 6c 73 2e 0d 0a 0d 0a 0d 0a a1 b0 31 31 2e 33 20 4c 6f 6f 70 20 42 61 63 6b 20 54 65 ┆ fails. 11.3 Loop Back Te┆
0x6320…6340 73 74 2e 0d 0a 0d 0a 54 68 65 20 38 32 37 34 20 63 68 42 20 42 53 43 20 74 65 73 74 20 70 65 72 ┆st. The 8274 chB BSC test per┆
0x6340…6360 66 6f 72 6d 20 61 20 73 65 72 69 61 6c 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 6f 66 20 ┆form a serial data transport of ┆
0x6360…6380 61 6e 20 0a 38 20 4b 2d 62 79 74 65 20 62 75 66 66 65 72 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 ┆an 8 K-byte buffer initialized ┆
0x6380…63a0 77 69 74 68 20 61 20 63 6f 75 6e 74 69 6e 67 20 70 61 74 74 65 72 6e 20 74 6f 20 61 20 0a 72 65 ┆with a counting pattern to a re┆
0x63a0…63c0 63 65 69 76 65 20 62 75 66 66 65 72 2c 20 77 68 69 63 68 20 69 73 20 63 6c 65 61 72 65 64 20 62 ┆ceive buffer, which is cleared b┆
0x63c0…63e0 65 66 6f 72 65 20 74 68 65 20 74 72 61 6e 73 70 6f 72 74 20 74 61 6b 65 73 20 0a 70 6c 61 63 65 ┆efore the transport takes place┆
0x63e0…6400 2e 20 46 69 72 73 74 20 74 68 65 20 74 72 61 6e 73 70 6f 72 74 20 69 73 20 6d 61 64 65 20 74 72 ┆. First the transport is made tr┆
0x6400…6420 (50,) 6f 75 67 68 20 74 68 65 20 56 2e 32 34 20 0a 69 6e 74 65 72 66 61 63 65 2c 20 61 6e 64 20 74 68 ┆ough the V.24 interface, and th┆
0x6420…6440 65 6e 20 72 65 70 65 61 74 65 64 20 74 72 6f 75 67 68 20 74 68 65 20 58 2e 32 31 20 69 6e 74 65 ┆en repeated trough the X.21 inte┆
0x6440…6460 72 66 61 63 65 20 0a 63 69 72 63 75 69 74 73 2e 0d 0a 0d 0a 54 68 65 20 38 32 37 34 20 63 68 42 ┆rface circuits. The 8274 chB┆
0x6460…6480 20 69 73 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 74 6f 20 53 44 4c 43 20 6d 6f 64 65 2c 20 77 69 ┆ is initialized to SDLC mode, wi┆
0x6480…64a0 74 68 20 70 6f 6c 6c 65 64 20 64 61 74 61 20 0a 74 72 61 6e 73 6d 69 74 2c 20 61 6e 64 20 69 6e ┆th polled data transmit, and in┆
0x64a0…64c0 74 65 72 72 75 70 74 20 63 6f 6e 74 72 6f 6c 6c 65 64 20 64 61 74 61 20 72 65 63 65 69 76 65 2e ┆terrupt controlled data receive.┆
0x64c0…64e0 20 0d 0a 0d 0a 49 66 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 62 75 66 66 65 72 20 69 6e 74 65 ┆ If the transmit buffer inte┆
0x64e0…6500 72 6e 61 6c 20 74 6f 20 74 68 65 20 38 32 37 34 20 63 68 69 70 20 6e 65 76 65 72 20 67 65 74 73 ┆rnal to the 8274 chip never gets┆
0x6500…6520 20 0a 65 6d 70 74 79 20 64 75 72 69 6e 67 20 70 6f 6c 6c 65 64 20 74 72 61 6e 73 6d 69 74 2c 20 ┆ empty during polled transmit, ┆
0x6520…6540 61 20 74 69 6d 65 6f 75 74 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 69 73 20 0a 67 65 6e 65 ┆a timeout error message is gene┆
0x6540…6560 72 61 74 65 64 2e 0d 0a 0d 0a 49 66 20 6e 6f 6e 65 20 69 6e 74 65 72 72 75 70 74 73 20 66 72 6f ┆rated. If none interrupts fro┆
0x6560…6580 6d 20 74 68 65 20 38 32 37 34 20 63 68 69 70 20 69 73 20 73 65 72 76 69 63 65 64 2c 20 61 20 6d ┆m the 8274 chip is serviced, a m┆
0x6580…65a0 69 73 73 69 6e 67 20 0a 69 6e 74 65 72 72 75 70 74 20 6d 65 73 73 61 67 65 20 69 73 20 67 65 6e ┆issing interrupt message is gen┆
0x65a0…65ab 65 72 61 74 65 64 2e 0d 0a 0d 0a ┆erated. ┆
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0x65ab…65ae 0c 83 a4 ┆ ┆
0x65ab…65ae }
0x65ae…65c0 0a 57 68 65 6e 20 61 6c 6c 20 64 61 74 61 20 68 61 73 ┆ When all data has┆
0x65c0…65e0 20 62 65 65 6e 20 73 65 6e 74 2c 20 61 6e 64 20 61 6c 73 6f 20 74 68 65 20 69 6e 74 65 72 72 75 ┆ been sent, and also the interru┆
0x65e0…6600 70 74 73 20 68 61 73 20 0a 62 65 65 6e 20 73 65 72 76 69 63 65 64 2c 20 74 68 65 20 74 65 73 74 ┆pts has been serviced, the test┆
0x6600…6620 (51,) 20 70 72 6f 67 72 61 6d 20 63 6f 6d 70 61 72 65 73 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 61 ┆ program compares the transmit a┆
0x6620…6640 6e 64 20 0a 74 68 65 20 72 65 63 65 69 76 65 20 62 75 66 66 65 72 2e 20 49 66 20 61 6e 20 65 72 ┆nd the receive buffer. If an er┆
0x6640…6660 72 6f 72 20 69 73 20 64 65 74 65 63 74 65 64 20 61 20 64 61 74 61 20 65 72 72 6f 72 20 0a 6d 65 ┆ror is detected a data error me┆
0x6660…6680 73 73 61 67 65 20 69 73 20 72 65 70 6f 72 74 65 64 20 74 6f 20 74 68 65 20 22 74 65 73 74 2d 6d ┆ssage is reported to the "test-m┆
0x6680…66a0 61 73 74 65 72 22 2c 20 6f 74 68 65 72 77 69 73 65 20 74 68 65 20 42 53 43 20 0a 63 68 61 6e 6e ┆aster", otherwise the BSC chann┆
0x66a0…66c0 65 6c 20 69 73 20 73 61 69 64 20 74 6f 20 62 65 20 4f 4b 2e 0d 0a 0d 0a 42 65 6c 6f 77 20 69 73 ┆el is said to be OK. Below is┆
0x66c0…66e0 20 61 20 63 6f 6d 70 6c 65 74 65 20 6c 69 73 74 20 6f 66 20 70 6f 73 73 69 62 6c 65 20 65 72 72 ┆ a complete list of possible err┆
0x66e0…6700 6f 72 20 6d 65 73 73 61 67 65 73 20 0a 67 65 6e 65 72 61 74 65 64 20 62 79 20 74 68 69 73 20 74 ┆or messages generated by this t┆
0x6700…6708 65 73 74 2e 0d 0a 0d 0a ┆est. ┆
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0x6741…677a 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x6741…677a 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x6741…677a }
0x677a…6780 0a a1 2d e2 e1 f0 ┆ - ┆
0x6780…67a0 e2 a1 e1 a2 e2 a1 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x67a0…67c0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x67c0…67e0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2d 0d 0a 21 20 45 52 52 2e 21 20 4c 45 ┆ - ! ERR.! LE┆
0x67e0…6800 44 20 21 20 20 20 49 4e 54 52 4f 44 55 43 54 49 4f 4e 20 20 20 21 20 20 20 20 20 20 20 45 52 52 ┆D ! INTRODUCTION ! ERR┆
0x6800…6820 (52,) 4f 52 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 53 45 43 4f 4e 44 41 52 59 20 20 20 20 20 ┆OR ! SECONDARY ┆
0x6820…6840 20 20 20 20 21 0d 0a a1 e1 a2 e2 a1 21 20 4e 4f 2e 20 21 20 4e 4f 2e 20 21 20 20 20 20 20 20 20 ┆ ! ! NO. ! NO. ! ┆
0x6840…6860 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 21 ┆TEXT ! TEXT !┆
0x6860…6880 20 20 20 20 20 20 20 20 20 20 20 54 45 58 54 09 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 ┆ TEXT ! ! ┆
0x6880…68a0 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 ┆ ! ! ! ┆
0x68a0…68c0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 73 65 67 6d 2e 3a 3c 73 73 73 73 3e 2c 20 61 ┆ ! segm.:<ssss>, a┆
0x68c0…68e0 64 72 2e 3a 3c 61 61 61 61 3e 21 0d 0a a1 21 20 32 34 20 20 21 20 32 34 20 20 21 20 38 32 37 34 ┆dr.:<aaaa>! ! 24 ! 24 ! 8274┆
0x68e0…6900 20 63 68 42 20 74 65 73 74 3a 20 20 20 21 20 64 61 74 61 20 65 72 72 6f 72 20 20 20 20 20 20 20 ┆ chB test: ! data error ┆
0x6900…6920 20 21 20 65 78 70 2e 3a 3c 65 65 65 65 3e 2c 20 72 65 63 2e 3a 3c 72 72 72 72 3e 20 21 0d 0a 21 ┆ ! exp.:<eeee>, rec.:<rrrr> ! !┆
0x6920…6940 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 ┆ ! ! ! ┆
0x6940…6960 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x6960…6980 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a2 e2 a1 21 20 32 35 20 20 21 20 32 35 20 20 21 ┆ ! ! 25 ! 25 !┆
0x6980…69a0 20 38 32 37 34 20 63 68 42 20 74 65 73 74 3a 20 20 20 21 20 74 69 6d 65 6f 75 74 20 20 20 20 20 ┆ 8274 chB test: ! timeout ┆
0x69a0…69c0 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x69c0…69e0 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ! ! ! ┆
0x69e0…6a00 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 ┆ ! ! ┆
0x6a00…6a20 (53,) 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a1 21 20 32 36 20 20 21 20 32 36 ┆ ! ! 26 ! 26┆
0x6a20…6a40 20 20 21 20 38 32 37 34 20 63 68 42 20 74 65 73 74 3a 20 20 20 21 20 74 72 61 6e 73 66 65 72 20 ┆ ! 8274 chB test: ! transfer ┆
0x6a40…6a60 65 72 72 6f 72 20 20 20 20 21 20 72 65 63 2e 3a 3c 72 72 72 72 3e 20 20 20 20 20 20 20 20 20 20 ┆error ! rec.:<rrrr> ┆
0x6a60…6a80 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ! ! ! ┆
0x6a80…6aa0 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 ┆ ! ! ┆
0x6aa0…6ac0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a1 21 20 32 37 20 20 21 ┆ ! ! 27 !┆
0x6ac0…6ae0 20 32 37 20 20 21 20 38 32 37 34 20 63 68 42 20 74 65 73 74 3a 20 20 20 21 20 6d 69 73 73 69 6e ┆ 27 ! 8274 chB test: ! missin┆
0x6ae0…6b00 67 20 69 6e 74 65 72 72 75 70 74 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆g interrupt ! ┆
0x6b00…6b20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 ┆ ! ! ! ! ┆
0x6b20…6b40 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 ┆ ! ! ┆
0x6b40…6b60 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a1 21 20 32 38 ┆ ! ! 28┆
0x6b60…6b80 20 20 21 20 32 38 20 20 21 20 38 32 37 34 20 63 68 42 20 74 65 73 74 3a 20 20 20 21 20 56 2e 32 ┆ ! 28 ! 8274 chB test: ! V.2┆
0x6b80…6ba0 34 20 73 74 61 74 75 73 20 65 72 72 6f 72 20 21 20 65 78 70 2e 3a 3c 30 30 30 65 3e 2c 20 72 65 ┆4 status error ! exp.:<000e>, re┆
0x6ba0…6bc0 63 2e 3a 3c 30 30 30 72 3e 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 ┆c.:<000r> ! ! ! ! ┆
0x6bc0…6be0 20 20 20 20 20 20 20 20 20 20 20 20 21 20 58 2e 32 31 20 43 6f 6e 74 72 6f 6c 2d 20 20 20 20 20 ┆ ! X.21 Control- ┆
0x6be0…6c00 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a1 21 ┆! ! !┆
0x6c00…6c20 (54,) 20 32 39 20 20 21 20 32 39 20 20 21 20 38 32 37 34 20 63 68 42 20 74 65 73 74 3a 20 20 20 21 20 ┆ 29 ! 29 ! 8274 chB test: ! ┆
0x6c20…6c40 49 6e 64 69 63 61 74 69 6f 6e 2d 65 72 72 6f 72 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆Indication-error ! ┆
0x6c40…6c60 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 ┆ ! ! ! ! ┆
0x6c60…6c80 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 58 2e 32 31 20 64 69 61 6c 20 65 72 72 6f 72 ┆ ! X.21 dial error┆
0x6c80…6ca0 20 20 20 21 09 09 09 09 09 09 09 20 20 20 20 20 20 21 0d 0a a1 21 20 33 30 20 20 21 20 33 30 20 ┆ ! ! ! 30 ! 30 ┆
0x6ca0…6cc0 20 21 20 38 32 37 34 20 63 68 42 20 74 65 73 74 3a 20 20 20 21 20 63 69 72 63 75 69 74 20 66 61 ┆ ! 8274 chB test: ! circuit fa┆
0x6cc0…6ce0 69 6c 75 72 65 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ilure ! ┆
0x6ce0…6ce6 20 20 20 21 0d 0a ┆ ! ┆
0x6ce6…6d1f Params {
0x6ce6…6d1f 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x6ce6…6d1f 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x6ce6…6d1f }
0x6d1f…6d58 Params {
0x6d1f…6d58 04 00 27 4e 0c 00 08 00 00 00 00 03 01 50 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N P1` ┆
0x6d1f…6d58 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x6d1f…6d58 }
0x6d58…6d60 0a 0d 0a 54 68 65 20 74 ┆ The t┆
0x6d60…6d80 65 73 74 20 69 73 20 72 75 6e 20 61 74 20 61 20 62 61 75 64 20 72 61 74 65 20 6f 66 20 36 34 20 ┆est is run at a baud rate of 64 ┆
0x6d80…6d87 4b 62 2f 73 2e 0d 0a ┆Kb/s. ┆
0x6d87…6d8a FormFeed {
0x6d87…6d8a 0c 82 9d ┆ ┆
0x6d87…6d8a }
0x6d8a…6da0 0a a1 b0 31 32 2e 20 b0 54 45 53 54 20 37 20 3d f0 b0 20 38 32 37 ┆ 12. TEST 7 = 827┆
0x6da0…6dc0 33 20 43 48 41 4e 4e 45 4c 20 43 20 54 45 53 54 0d 0a 0d 0a 54 68 65 20 38 32 37 33 20 63 68 43 ┆3 CHANNEL C TEST The 8273 chC┆
0x6dc0…6de0 20 69 6d 70 6c 65 6d 65 6e 74 73 20 74 68 65 20 53 44 4c 43 20 63 6f 6d 6d 75 6e 69 63 61 74 69 ┆ implements the SDLC communicati┆
0x6de0…6e00 6f 6e 20 6c 69 6e 65 2e 20 54 68 69 73 20 0a 74 65 73 74 20 6d 75 73 74 20 62 65 20 65 78 65 63 ┆on line. This test must be exec┆
0x6e00…6e20 (55,) 75 74 65 64 20 77 69 74 68 20 61 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 20 63 6f 6e 6e ┆uted with a loop back cable conn┆
0x6e20…6e40 65 63 74 65 64 2e 20 53 65 65 20 0a 61 70 70 65 6e 64 69 78 20 41 2e 0d 0a 0d 0a 0d 0a a1 b0 31 ┆ected. See appendix A. 1┆
0x6e40…6e60 32 2e 31 20 53 74 61 74 75 73 20 53 69 67 6e 61 6c 20 43 68 65 63 6b 2e 0d 0a 0d 0a 42 65 66 6f ┆2.1 Status Signal Check. Befo┆
0x6e60…6e80 72 65 20 61 6e 79 20 73 65 72 69 61 6c 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 69 73 20 ┆re any serial data transport is ┆
0x6e80…6ea0 73 74 61 72 74 65 64 2c 20 74 68 65 20 56 2e 32 34 20 0a 69 6e 74 65 72 66 61 63 65 20 73 74 61 ┆started, the V.24 interface sta┆
0x6ea0…6ec0 74 75 73 20 73 69 67 6e 61 6c 73 20 61 73 20 77 65 6c 6c 20 61 73 20 74 68 65 20 58 2e 32 31 20 ┆tus signals as well as the X.21 ┆
0x6ec0…6ee0 73 74 61 74 75 73 20 73 69 67 6e 61 6c 73 20 0a 61 72 65 20 63 68 65 63 6b 65 64 2e 20 54 68 65 ┆status signals are checked. The┆
0x6ee0…6f00 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 73 20 61 72 65 20 63 6f 6e 6e 65 63 74 65 64 20 6c 69 ┆ status signals are connected li┆
0x6f00…6f20 6b 65 20 74 68 69 73 20 3a 20 0d 0a 82 82 0d 0a 20 20 a1 b0 56 2e 32 34 20 53 74 61 74 75 73 20 ┆ke this : V.24 Status ┆
0x6f20…6f40 53 69 67 6e 61 6c 73 2e 0d 0a 0d 0a 20 20 52 65 71 75 65 73 74 20 54 6f 20 53 65 6e 64 2c 20 20 ┆Signals. Request To Send, ┆
0x6f40…6f60 20 20 20 52 54 53 43 20 2d 2d 2d 3e 84 84 2d 84 81 0d 0a 20 20 43 6c 65 61 72 20 54 6f 20 53 65 ┆ RTSC ---> - Clear To Se┆
0x6f60…6f80 6e 64 2c 20 20 20 20 20 20 20 43 54 53 43 20 2d 2d 2d 3c 2d 0d 0a 20 20 44 61 74 61 20 53 65 74 ┆nd, CTSC ---<- Data Set┆
0x6f80…6fa0 20 52 65 61 64 79 2c 20 20 20 20 20 20 44 53 52 43 20 2d 2d 2d 3c 2d 0d 0a 0d 0a 20 20 44 61 74 ┆ Ready, DSRC ---<- Dat┆
0x6fa0…6fc0 61 20 54 65 72 6d 69 6e 61 6c 20 52 65 61 64 79 2c 20 44 54 52 43 20 2d 2d 2d 3e 2d 0d 0a 20 20 ┆a Terminal Ready, DTRC --->- ┆
0x6fc0…6fe0 43 61 6c 6c 69 6e 67 20 49 6e 64 69 63 61 74 6f 72 2c 20 20 20 43 49 43 20 20 2d 2d 2d 3c 2d 0d ┆Calling Indicator, CIC ---<- ┆
0x6fe0…6fe3 0a 0d 0a ┆ ┆
0x6fe3…701c Params {
0x6fe3…701c 04 00 27 4e 0c 00 06 00 00 00 00 03 01 4e 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N N1` ┆
0x6fe3…701c 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x6fe3…701c }
0x701c…7055 Params {
0x701c…7055 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x701c…7055 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x701c…7055 }
0x7055…7060 0a 81 20 20 44 61 74 61 20 43 61 ┆ Data Ca┆
0x7060…7080 72 72 69 65 72 20 44 65 74 65 63 74 2c 20 44 43 44 43 20 2d 2d 2d 3c 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆rrier Detect, DCDC ---<---------┆
0x7080…70a0 3c 2d 2d 2d 20 44 54 52 42 2c 20 44 61 74 61 20 54 65 72 6d 69 6e 61 6c 20 52 65 61 64 79 0d 0a ┆<--- DTRB, Data Terminal Ready ┆
0x70a0…70a2 0d 0a ┆ ┆
0x70a2…70db Params {
0x70a2…70db 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3d 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N =1` ┆
0x70a2…70db 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x70a2…70db }
0x70db…7114 Params {
0x70db…7114 04 00 27 4e 0c 00 06 00 00 00 00 03 01 4e 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N N1` ┆
0x70db…7114 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x70db…7114 }
0x7114…7120 0a 4e 4f 54 45 20 74 68 61 74 20 74 ┆ NOTE that t┆
0x7120…7140 68 65 20 44 43 44 43 20 73 69 67 6e 61 6c 20 69 73 20 74 6f 67 67 6c 65 64 20 66 72 6f 6d 20 74 ┆he DCDC signal is toggled from t┆
0x7140…7160 68 65 20 38 32 37 34 20 63 68 69 70 20 76 69 61 20 0a 74 68 65 20 6c 6f 6f 70 62 61 63 6b 20 63 ┆he 8274 chip via the loopback c┆
0x7160…7180 61 62 6c 65 2e 0d 0a 0d 0a 20 20 a1 b0 58 2e 32 31 20 53 74 61 74 75 73 20 53 69 67 6e 61 6c 73 ┆able. X.21 Status Signals┆
0x7180…71a0 2e 0d 0a 0d 0a 20 20 43 6f 6e 74 72 6f 6c 20 28 41 29 2c 20 20 20 20 20 20 20 20 20 43 28 41 29 ┆. Control (A), C(A)┆
0x71a0…71c0 42 20 2d 2d 3e 2d 0d 0a 20 20 49 6e 64 69 63 61 74 69 6f 6e 20 28 41 29 2c 20 20 20 20 20 20 49 ┆B -->- Indication (A), I┆
0x71c0…71e0 28 41 29 42 20 2d 2d 3c 2d 20 20 20 0d 0a 0d 0a 8c 83 80 0a 20 20 43 6f 6e 74 72 6f 6c 20 28 42 ┆(A)B --<- Control (B┆
0x71e0…7200 29 2c 20 20 20 20 20 20 20 20 20 43 28 42 29 42 20 2d 2d 3e 2d 20 0d 0a 20 20 49 6e 64 69 63 61 ┆), C(B)B -->- Indica┆
0x7200…7220 (57,) 74 69 6f 6e 20 28 42 29 2c 20 20 20 20 20 20 49 28 42 29 42 20 2d 2d 3c 2d 0d 0a 0d 0a 41 20 73 ┆tion (B), I(B)B --<- A s┆
0x7220…7240 74 61 74 75 73 20 65 72 72 6f 72 20 64 75 72 69 6e 67 20 56 2e 32 34 20 74 65 73 74 20 6d 69 67 ┆tatus error during V.24 test mig┆
0x7240…7260 68 74 20 6c 6f 6f 6b 20 6c 69 6b 65 20 74 68 69 73 20 3a 0d 0a 0d 0a b0 38 32 37 33 20 63 68 43 ┆ht look like this : 8273 chC┆
0x7260…7280 20 74 65 73 74 3a 20 56 2e 32 34 20 73 74 61 74 75 73 20 65 72 72 6f 72 20 20 72 65 63 2e 3a 30 ┆ test: V.24 status error rec.:0┆
0x7280…72a0 30 30 38 20 20 65 78 70 2e 3a 20 30 30 30 30 0d 0a 0d 0a 4f 6e 6c 79 20 74 68 65 20 66 6f 75 72 ┆008 exp.: 0000 Only the four┆
0x72a0…72c0 20 6c 65 61 73 74 20 73 69 67 6e 69 66 69 63 61 6e 74 20 62 69 74 73 20 61 72 65 20 75 73 65 64 ┆ least significant bits are used┆
0x72c0…72e0 2c 20 61 6e 64 20 6d 75 73 74 20 62 65 20 0a 69 6e 74 65 72 70 72 65 74 65 64 20 6c 69 6b 65 20 ┆, and must be interpreted like ┆
0x72e0…7300 74 68 69 73 20 3a 0d 0a 0d 0a 42 69 74 20 30 20 3d 20 2d 2c 43 54 53 43 20 3b 20 42 69 74 20 31 ┆this : Bit 0 = -,CTSC ; Bit 1┆
0x7300…7320 20 3d 20 2d 3b 43 44 43 20 3b 20 42 69 74 20 32 20 3d 20 2d 2c 43 49 43 43 20 3b 20 0d 0a 42 69 ┆ = -;CDC ; Bit 2 = -,CICC ; Bi┆
0x7320…7340 74 20 33 20 3d 20 2d 2c 44 53 52 43 0d 0a 0d 0a 54 68 65 20 6d 65 73 73 61 67 65 20 61 62 6f 76 ┆t 3 = -,DSRC The message abov┆
0x7340…7360 65 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 73 6f 6d 65 74 68 69 6e 67 20 69 73 20 77 72 ┆e indicates that something is wr┆
0x7360…7380 6f 6e 67 20 77 69 74 68 20 74 68 65 20 0a 56 2e 32 34 20 44 61 74 61 20 53 65 74 20 52 65 61 64 ┆ong with the V.24 Data Set Read┆
0x7380…73a0 79 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 2c 20 77 68 69 63 68 20 69 73 20 74 6f 67 67 6c 65 ┆y status signal, which is toggle┆
0x73a0…73c0 64 20 66 72 6f 6d 20 74 68 65 20 0a 52 65 71 75 65 73 74 20 54 6f 20 53 65 6e 64 20 73 69 67 6e ┆d from the Request To Send sign┆
0x73c0…73e0 61 6c 20 62 79 20 74 68 65 20 74 65 73 74 20 70 72 6f 67 72 61 6d 2e 0d 0a 0d 0a 41 6e 20 58 2e ┆al by the test program. An X.┆
0x73e0…7400 32 31 20 73 74 61 74 75 73 20 65 72 72 6f 72 20 6d 61 79 20 6c 6f 6f 6b 20 6c 69 6b 65 20 74 68 ┆21 status error may look like th┆
0x7400…7420 (58,) 69 73 20 3a 0d 0a 0d 0a b0 38 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 58 2e 32 31 20 73 74 61 ┆is : 8273 chC test: X.21 sta┆
0x7420…7440 74 75 73 20 65 72 72 6f 72 20 20 72 65 63 2e 3a 20 30 30 30 33 20 20 65 78 70 2e 3a 20 30 30 30 ┆tus error rec.: 0003 exp.: 000┆
0x7440…7460 32 0d 0a 0d 0a 4f 6e 6c 79 20 74 68 65 20 74 77 6f 20 6c 65 61 73 74 20 73 69 67 6e 69 66 69 63 ┆2 Only the two least signific┆
0x7460…7480 61 6e 74 20 62 69 74 73 20 61 72 65 20 75 73 65 64 20 61 6e 64 20 6d 75 73 74 20 62 65 20 0a 69 ┆ant bits are used and must be i┆
0x7480…74a0 6e 74 65 72 70 72 65 74 65 64 20 6c 69 6b 65 20 74 68 69 73 20 3a 0d 0a 0d 0a 42 69 74 20 30 20 ┆nterpreted like this : Bit 0 ┆
0x74a0…74c0 3d 20 2d 2c 43 54 53 43 20 3b 20 42 69 74 20 31 20 3d 20 2d 2c 43 44 43 0d 0a 0d 0a 54 68 65 20 ┆= -,CTSC ; Bit 1 = -,CDC The ┆
0x74c0…74e0 6d 65 73 73 61 67 65 20 61 62 6f 76 65 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 73 6f 6d ┆message above indicates that som┆
0x74e0…7500 65 74 68 69 6e 67 20 69 73 20 77 72 6f 6e 67 20 77 69 74 68 20 74 68 65 20 0a 58 2e 32 31 20 73 ┆ething is wrong with the X.21 s┆
0x7500…7520 74 61 74 75 73 20 73 69 67 6e 61 6c 20 49 20 3d 20 43 6c 65 61 72 20 54 6f 20 53 65 6e 64 2c 20 ┆tatus signal I = Clear To Send, ┆
0x7520…7540 77 68 69 63 68 20 69 73 20 74 6f 67 67 6c 65 64 20 66 72 6f 6d 20 0a 74 68 65 20 44 61 74 61 20 ┆which is toggled from the Data ┆
0x7540…7560 54 65 72 6d 69 6e 61 6c 20 52 65 61 64 79 20 73 69 67 6e 61 6c 20 62 79 20 74 68 65 20 74 65 73 ┆Terminal Ready signal by the tes┆
0x7560…7580 74 20 70 72 6f 67 72 61 6d 2e 0d 0a 0d 0a 0d 0a 8c 82 f4 0a a1 b0 31 32 2e 32 20 56 2e 32 34 2f ┆t program. 12.2 V.24/┆
0x7580…75a0 58 2e 32 31 20 53 65 6c 65 63 74 2e 0d 0a 0d 0a 4e 4f 54 45 20 74 68 61 74 20 74 68 65 20 56 2e ┆X.21 Select. NOTE that the V.┆
0x75a0…75c0 32 34 2f 2d 2c 58 2e 32 31 20 74 65 73 74 20 73 65 6c 65 63 74 20 69 73 20 64 6f 6e 65 20 66 72 ┆24/-,X.21 test select is done fr┆
0x75c0…75e0 6f 6d 20 74 68 65 20 38 32 37 34 20 0a 4d 50 53 43 20 63 6f 6e 74 72 6f 6c 6c 65 72 2c 20 73 65 ┆om the 8274 MPSC controller, se┆
0x75e0…7600 65 20 62 65 6c 6f 77 2e 0d 0a 0d 0a a1 20 20 4a 34 2e 20 20 e1 20 20 20 20 20 20 20 20 20 20 20 ┆e below. J4. ┆
0x7600…7620 (59,) 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 e1 a1 84 20 20 20 4a 33 2e ┆ J3.┆
0x7620…7640 20 20 0d 0a 0d 0a 2d 2c 58 2e 32 31 43 20 2d 2d 2d 3c 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 20 20 20 20 ┆ -,X.21C ---<---------- ┆
0x7640…7660 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2d 2d 2d 2d 3c 2d 20 52 54 53 42 0d 0a 0d 0a 54 68 65 ┆ ----<- RTSB The┆
0x7660…7680 20 64 69 6f 64 65 20 61 6e 64 20 74 68 65 20 72 65 73 69 73 74 6f 72 20 70 72 65 76 65 6e 74 73 ┆ diode and the resistor prevents┆
0x7680…76a0 20 6e 65 67 61 74 69 76 65 20 76 6f 6c 74 61 67 65 20 6f 6e 20 74 68 65 20 2d 0a 2c 58 2e 32 31 ┆ negative voltage on the - ,X.21┆
0x76a0…76c0 20 70 69 6e 2e 20 4e 4f 54 45 20 74 68 61 74 20 74 68 65 20 38 32 37 34 20 63 68 69 70 20 6d 61 ┆ pin. NOTE that the 8274 chip ma┆
0x76c0…76e0 79 20 64 65 73 74 75 72 62 20 74 68 65 20 38 32 37 33 20 63 68 43 20 0a 74 65 73 74 20 73 65 72 ┆y desturb the 8273 chC test ser┆
0x76e0…7700 69 6f 75 73 6c 79 20 69 66 20 74 68 65 20 56 2e 32 34 2f 2d 2c 58 2e 32 31 20 73 65 6c 65 63 74 ┆iously if the V.24/-,X.21 select┆
0x7700…7720 69 6f 6e 20 6c 6f 67 69 63 20 66 61 69 6c 73 2e 0d 0a 0d 0a 54 68 65 20 38 32 37 33 20 63 68 43 ┆ion logic fails. The 8273 chC┆
0x7720…7740 20 69 73 20 69 6e 69 74 69 61 6c 69 7a 65 64 20 74 6f 20 53 44 4c 43 20 6d 6f 64 65 2c 20 77 69 ┆ is initialized to SDLC mode, wi┆
0x7740…7760 74 68 20 62 6f 74 68 20 44 4d 41 20 0a 63 6f 6e 74 72 6f 6c 6c 65 64 20 64 61 74 61 20 74 72 61 ┆th both DMA controlled data tra┆
0x7760…7780 6e 73 6d 69 74 20 61 6e 64 20 72 65 63 65 69 76 65 2e 20 54 68 65 20 44 4d 41 20 63 68 61 6e 6e ┆nsmit and receive. The DMA chann┆
0x7780…77a0 65 6c 20 31 20 69 73 20 0a 64 65 64 69 63 61 74 65 64 20 61 73 20 72 65 63 65 69 76 65 20 63 68 ┆el 1 is dedicated as receive ch┆
0x77a0…77c0 61 6e 6e 65 6c 2c 20 61 6e 64 20 44 4d 41 20 63 68 61 6e 6e 65 6c 20 32 20 61 73 20 74 72 61 6e ┆annel, and DMA channel 2 as tran┆
0x77c0…77e0 73 6d 69 74 20 0a 63 68 61 6e 6e 65 6c 2e 0d 0a 0d 0a 0d 0a a2 a1 e2 b0 31 32 2e 33 20 4c 6f 6f ┆smit channel. 12.3 Loo┆
0x77e0…7800 70 20 42 61 63 6b 20 54 65 73 74 2e 0d 0a 0d 0a 54 68 65 20 38 32 37 33 20 63 68 43 20 53 44 4c ┆p Back Test. The 8273 chC SDL┆
0x7800…7820 (60,) 43 20 74 65 73 74 20 70 65 72 66 6f 72 6d 20 61 20 73 65 72 69 61 6c 20 64 61 74 61 20 74 72 61 ┆C test perform a serial data tra┆
0x7820…7840 6e 73 70 6f 72 74 20 6f 66 20 61 6e 20 0a 38 20 4b 2d 62 79 74 65 20 62 75 66 66 65 72 20 69 6e ┆nsport of an 8 K-byte buffer in┆
0x7840…7860 69 74 69 61 6c 69 7a 65 64 20 77 69 74 68 20 61 20 63 6f 75 6e 74 69 6e 67 20 70 61 74 74 65 72 ┆itialized with a counting patter┆
0x7860…7880 6e 20 74 6f 20 61 20 0a 72 65 63 65 69 76 65 20 62 75 66 66 65 72 2c 20 77 68 69 63 68 20 69 73 ┆n to a receive buffer, which is┆
0x7880…78a0 20 63 6c 65 61 72 65 64 20 62 65 66 6f 72 65 20 74 68 65 20 74 72 61 6e 73 70 6f 72 74 20 74 61 ┆ cleared before the transport ta┆
0x78a0…78c0 6b 65 73 20 0a 70 6c 61 63 65 2e 20 46 69 72 73 74 20 74 68 65 20 74 72 61 6e 73 70 6f 72 74 20 ┆kes place. First the transport ┆
0x78c0…78e0 69 73 20 6d 61 64 65 20 74 72 6f 75 67 68 20 74 68 65 20 56 2e 32 34 20 69 6e 74 65 72 66 61 63 ┆is made trough the V.24 interfac┆
0x78e0…7900 65 2c 20 0a 61 6e 64 20 74 68 65 6e 20 72 65 70 65 61 74 65 64 20 74 72 6f 75 67 68 20 74 68 65 ┆e, and then repeated trough the┆
0x7900…7920 20 58 2e 32 31 20 69 6e 74 65 72 66 61 63 65 20 63 69 72 63 75 69 74 73 2e 0d 0a 0d 0a 54 68 65 ┆ X.21 interface circuits. The┆
0x7920…7940 20 38 32 37 33 20 53 44 4c 43 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 61 6c 73 6f 20 67 65 6e 65 72 ┆ 8273 SDLC controller also gener┆
0x7940…7960 61 74 65 73 20 62 6f 74 68 20 61 6e 20 52 58 2d 20 61 6e 64 20 61 20 54 58 2d 0a 69 6e 74 65 72 ┆ates both an RX- and a TX- inter┆
0x7960…7980 72 75 70 74 20 72 65 73 75 6c 74 2c 20 77 68 65 6e 20 69 74 20 68 61 73 20 66 69 6e 69 73 68 65 ┆rupt result, when it has finishe┆
0x7980…79a0 64 20 61 20 63 6f 6d 6d 61 6e 64 2c 20 6f 72 20 65 78 70 69 72 65 64 20 0a 73 6f 6d 65 20 75 6e ┆d a command, or expired some un┆
0x79a0…79b4 75 73 75 61 6c 20 63 6f 6e 64 69 74 69 6f 6e 2e 0d 0a 0d 0a ┆usual condition. ┆
0x79b4…79b7 FormFeed {
0x79b4…79b7 0c 82 f4 ┆ ┆
0x79b4…79b7 }
0x79b7…79c0 0a 54 68 65 20 6f 6e 6c 79 ┆ The only┆
0x79c0…79e0 20 76 61 6c 69 64 20 52 58 2d 69 6e 74 65 72 72 75 70 74 20 72 65 73 75 6c 74 20 69 73 20 74 68 ┆ valid RX-interrupt result is th┆
0x79e0…7a00 65 20 67 65 6e 65 72 65 6c 20 72 65 63 65 69 76 65 20 0a 72 65 73 75 6c 74 2c 20 77 68 69 63 68 ┆e generel receive result, which┆
0x7a00…7a20 (61,) 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 61 20 76 61 6c 69 64 20 53 44 4c 43 20 66 72 61 ┆ indicates that a valid SDLC fra┆
0x7a20…7a40 6d 65 20 68 61 73 20 62 65 65 6e 20 0a 64 65 74 65 63 74 65 64 2c 20 61 6e 64 20 74 72 61 6e 73 ┆me has been detected, and trans┆
0x7a40…7a60 66 65 72 72 65 64 20 74 6f 20 6d 65 6d 6f 72 79 20 62 79 20 74 68 65 20 44 4d 41 20 63 68 61 6e ┆ferred to memory by the DMA chan┆
0x7a60…7a80 6e 65 6c 2c 20 0a 68 6f 70 65 66 75 6c 6c 79 2e 0d 0a 0d 0a 49 66 20 61 6e 20 52 58 2d 69 6e 74 ┆nel, hopefully. If an RX-int┆
0x7a80…7aa0 65 72 72 75 70 74 20 72 65 73 75 6c 74 20 69 73 20 72 65 61 64 2c 20 61 6e 64 20 69 66 20 69 74 ┆errupt result is read, and if it┆
0x7aa0…7ac0 20 64 6f 6e 74 20 69 6e 64 69 63 61 74 65 20 0a 74 72 61 6e 73 66 65 72 20 63 6f 6d 70 6c 65 74 ┆ dont indicate transfer complet┆
0x7ac0…7ae0 65 2c 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 20 69 ┆e, the following error message i┆
0x7ae0…7b00 73 20 67 65 6e 65 72 61 74 65 64 20 3a 0d 0a 0d 0a b0 b0 38 32 37 33 20 63 68 43 20 74 65 73 74 ┆s generated : 8273 chC test┆
0x7b00…7b20 3a 20 52 58 20 65 72 72 6f 72 20 20 20 72 65 63 2e 3a 20 30 30 72 72 0d 0a 0d 0a 54 68 65 20 52 ┆: RX error rec.: 00rr The R┆
0x7b20…7b40 58 2d 69 6e 74 65 72 72 75 70 74 20 72 65 73 75 6c 74 20 6d 75 73 74 20 62 65 20 69 6e 74 65 72 ┆X-interrupt result must be inter┆
0x7b40…7b60 70 72 65 74 65 64 20 74 68 69 73 20 77 61 79 20 3a 0d 0a 0d 0a 52 65 73 75 6c 74 20 3d 20 42 37 ┆preted this way : Result = B7┆
0x7b60…7b80 2c 42 36 2c 42 35 2c 42 34 2c 42 33 2c 42 32 2c 42 31 2c 42 30 20 62 69 6e 61 72 79 20 3d 20 72 ┆,B6,B5,B4,B3,B2,B1,B0 binary = r┆
0x7b80…7b87 72 20 68 65 78 0d 0a ┆r hex ┆
0x7b87…7bc0 Params {
0x7b87…7bc0 04 00 27 4e 0c 00 06 00 00 00 00 03 01 4d 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N M1` ┆
0x7b87…7bc0 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x7b87…7bc0 }
0x7bc0…7bf9 Params {
0x7bc0…7bf9 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3d 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N =1` ┆
0x7bc0…7bf9 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x7bc0…7bf9 }
0x7bf9…7c00 0a 0d 0a a2 e2 a1 2d ┆ -┆
0x7c00…7c20 (62,) 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
[…0x1…]
0x7c40…7c60 20 20 20 20 20 20 2d 0d 0a a1 42 37 20 2c 20 42 36 20 2c 20 42 35 20 2c 20 42 34 20 2c 20 42 33 ┆ - B7 , B6 , B5 , B4 , B3┆
0x7c60…7c80 20 2c 20 42 32 20 2c 20 42 31 20 2c 20 42 30 20 20 20 21 20 52 58 2d 69 6e 74 65 72 72 75 70 74 ┆ , B2 , B1 , B0 ! RX-interrupt┆
0x7c80…7ca0 20 72 65 73 75 6c 74 20 63 6f 64 65 20 20 20 20 20 21 0d 0a 44 37 20 2c 20 44 36 20 2c 20 44 35 ┆ result code ! D7 , D6 , D5┆
0x7ca0…7cc0 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 20 20 21 20 41 31 ┆ , 0 , 0 , 0 , 0 , 0 ! A1┆
0x7cc0…7ce0 20 6d 61 74 63 68 20 6f 72 20 67 65 6e 65 72 65 6c 20 72 65 63 65 69 76 65 0d 0a 44 37 20 2c 20 ┆ match or generel receive D7 , ┆
0x7ce0…7d00 44 36 20 2c 20 44 35 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 31 20 ┆D6 , D5 , 0 , 0 , 0 , 0 , 1 ┆
0x7d00…7d20 20 20 20 21 20 41 32 20 6d 61 74 63 68 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 ┆ ! A2 match 0 , 0 , 0 , 0 ┆
0x7d20…7d40 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 31 20 20 2c 20 31 20 20 20 20 21 20 43 52 43 20 65 72 72 ┆ , 0 , 0 , 1 , 1 ! CRC err┆
0x7d40…7d60 6f 72 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 31 20 20 ┆or 0 , 0 , 0 , 0 , 0 , 1 ┆
0x7d60…7d80 2c 20 30 20 20 2c 20 30 20 20 20 20 21 20 41 62 6f 72 74 20 64 65 74 65 63 74 65 64 0d 0a 30 20 ┆, 0 , 0 ! Abort detected 0 ┆
0x7d80…7da0 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 31 20 20 2c 20 30 20 20 2c ┆ , 0 , 0 , 0 , 0 , 1 , 0 ,┆
0x7da0…7dc0 20 31 20 20 20 20 21 20 49 64 6c 65 20 64 65 74 65 63 74 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 ┆ 1 ! Idle detect 0 , 0 , 0┆
0x7dc0…7de0 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 31 20 20 2c 20 31 20 20 2c 20 30 20 20 20 20 21 20 45 ┆ , 0 , 0 , 1 , 1 , 0 ! E┆
0x7de0…7e00 4f 50 20 64 65 74 65 63 74 65 64 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c ┆OP detected 0 , 0 , 0 , 0 ,┆
0x7e00…7e20 (63,) 20 30 20 20 2c 20 31 20 20 2c 20 31 20 20 2c 20 31 20 20 20 20 21 20 46 72 61 6d 65 20 6c 65 73 ┆ 0 , 1 , 1 , 1 ! Frame les┆
0x7e20…7e40 73 20 74 68 61 6e 20 33 32 20 62 69 74 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 ┆s than 32 bit 0 , 0 , 0 , 0 ┆
0x7e40…7e60 20 2c 20 31 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 20 20 21 20 44 4d 41 20 6f 76 65 ┆ , 1 , 0 , 0 , 0 ! DMA ove┆
0x7e60…7e80 72 72 75 6e 20 64 65 74 65 63 74 65 64 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 ┆rrun detected 0 , 0 , 0 , 0 ┆
0x7e80…7ea0 20 2c 20 31 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 31 20 20 20 20 21 20 4d 65 6d 6f 72 79 20 ┆ , 1 , 0 , 0 , 1 ! Memory ┆
0x7ea0…7ec0 62 75 66 66 65 72 20 6f 76 65 72 66 6c 6f 77 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 ┆buffer overflow 0 , 0 , 0 , ┆
0x7ec0…7ee0 30 20 20 2c 20 31 20 20 2c 20 30 20 20 2c 20 31 20 20 2c 20 30 20 20 20 20 21 20 43 61 72 72 69 ┆0 , 1 , 0 , 1 , 0 ! Carri┆
0x7ee0…7f00 65 72 20 44 65 74 65 63 74 20 66 61 69 6c 75 72 65 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 ┆er Detect failure 0 , 0 , 0 ┆
0x7f00…7f20 2c 20 30 20 20 2c 20 31 20 20 2c 20 30 20 20 2c 20 31 20 20 2c 20 31 20 20 20 20 21 20 52 65 63 ┆, 0 , 1 , 0 , 1 , 1 ! Rec┆
0x7f20…7f3a 65 69 76 65 20 49 6e 74 65 72 72 75 70 74 20 6f 76 65 72 72 75 6e 0d 0a 0d 0a ┆eive Interrupt overrun ┆
0x7f3a…7f73 Params {
0x7f3a…7f73 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x7f3a…7f73 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x7f3a…7f73 }
0x7f73…7fac Params {
0x7f73…7fac 04 00 27 4e 0c 00 06 00 00 00 00 03 01 4d 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N M1` ┆
0x7f73…7fac 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x7f73…7fac }
0x7fac…7fad 0a ┆ ┆
0x7fad…7fb0 FormFeed {
0x7fad…7fb0 0c 82 d0 ┆ ┆
0x7fad…7fb0 }
0x7fb0…7fc0 0a 44 37 2c 44 36 20 61 6e 64 20 44 35 20 6d 75 ┆ D7,D6 and D5 mu┆
0x7fc0…7fe0 73 74 20 62 65 20 74 61 6b 65 6e 20 66 72 6f 6d 20 74 68 65 20 74 61 62 6c 65 20 62 65 6c 6f 77 ┆st be taken from the table below┆
0x7fe0…8000 2e 0d 0a 0d 0a a1 2d 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆. - ┆
0x8000…8020 (64,) 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x8020…8040 2d 0d 0a a1 44 37 20 2c 20 44 36 20 2c 20 44 35 20 20 20 21 20 20 42 69 74 73 20 72 65 63 65 69 ┆- D7 , D6 , D5 ! Bits recei┆
0x8040…8060 76 65 64 20 69 6e 20 6c 61 73 74 20 62 79 74 65 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 0d ┆ved in last byte ┆
0x8060…8080 0a 31 20 20 2c 20 31 20 20 2c 20 31 20 20 20 20 21 20 41 6c 6c 20 38 20 62 69 74 73 20 72 65 63 ┆ 1 , 1 , 1 ! All 8 bits rec┆
0x8080…80a0 65 69 76 65 64 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 20 20 21 20 44 30 20 72 65 63 65 69 ┆eived 0 , 0 , 0 ! D0 recei┆
0x80a0…80c0 76 65 64 0d 0a 31 20 20 2c 20 30 20 20 2c 20 30 20 20 20 20 21 20 44 31 2d 44 30 20 72 65 63 65 ┆ved 1 , 0 , 0 ! D1-D0 rece┆
0x80c0…80e0 69 76 65 64 0d 0a 30 20 20 2c 20 31 20 20 2c 20 30 20 20 20 20 21 20 44 32 2d 44 30 20 72 65 63 ┆ived 0 , 1 , 0 ! D2-D0 rec┆
0x80e0…8100 65 69 76 65 64 0d 0a 31 20 20 2c 20 31 20 20 2c 20 30 20 20 20 20 21 20 44 33 2d 44 30 20 72 65 ┆eived 1 , 1 , 0 ! D3-D0 re┆
0x8100…8120 63 65 69 76 65 64 0d 0a 30 20 20 2c 20 30 20 20 2c 20 31 20 20 20 20 21 20 44 34 2d 44 30 20 72 ┆ceived 0 , 0 , 1 ! D4-D0 r┆
0x8120…8140 65 63 65 69 76 65 64 0d 0a 31 20 20 2c 20 30 20 20 2c 20 31 20 20 20 20 21 20 44 35 2d 44 30 20 ┆eceived 1 , 0 , 1 ! D5-D0 ┆
0x8140…8160 72 65 63 65 69 76 65 64 0d 0a 30 20 20 2c 20 31 20 20 2c 20 31 20 20 20 20 21 20 44 36 2d 44 30 ┆received 0 , 1 , 1 ! D6-D0┆
0x8160…8180 20 72 65 63 65 69 76 65 64 0d 0a 0d 0a 54 68 65 20 6f 6e 6c 79 20 61 6c 6c 6f 77 65 64 20 52 58 ┆ received The only allowed RX┆
0x8180…81a0 2d 69 6e 74 65 72 72 75 70 74 20 72 65 73 75 6c 74 20 69 6e 20 74 68 69 73 20 74 65 73 74 20 69 ┆-interrupt result in this test i┆
0x81a0…81c0 73 20 74 68 65 20 45 30 20 0a 68 65 78 2e 20 72 65 73 75 6c 74 2c 20 77 68 69 63 68 20 6d 65 61 ┆s the E0 hex. result, which mea┆
0x81c0…81e0 6e 73 20 38 20 62 69 74 73 20 69 6e 20 6c 61 73 74 20 62 79 74 65 20 72 65 63 65 69 76 65 64 20 ┆ns 8 bits in last byte received ┆
0x81e0…8200 61 6e 64 20 0a 66 72 61 6d 65 20 4f 4b 2e 20 0d 0a 0d 0a 54 68 65 20 6f 6e 6c 79 20 76 61 6c 69 ┆and frame OK. The only vali┆
0x8200…8220 (65,) 64 20 54 58 2d 69 6e 74 65 72 72 75 70 74 20 72 65 73 75 6c 74 20 69 73 20 74 68 65 20 46 72 61 ┆d TX-interrupt result is the Fra┆
0x8220…8240 6d 65 20 54 72 61 6e 73 6d 69 74 20 0a 43 6f 6d 70 6c 65 74 65 20 72 65 73 75 6c 74 2c 20 77 68 ┆me Transmit Complete result, wh┆
0x8240…8260 69 63 68 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 74 72 61 6e 73 6d 69 74 20 66 72 61 6d ┆ich indicates that transmit fram┆
0x8260…8280 65 20 69 73 20 0a 63 6f 6d 70 6c 65 74 65 2e 20 49 66 20 61 6e 6f 74 68 65 72 20 72 65 73 75 6c ┆e is complete. If another resul┆
0x8280…82a0 74 20 69 73 20 72 65 61 64 20 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 65 72 72 6f 72 20 0a 6d ┆t is read the following error m┆
0x82a0…82c0 65 73 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 2e 0d 0a 0d 0a b0 38 32 37 33 20 63 68 ┆essage is generated. 8273 ch┆
0x82c0…82e0 43 20 74 65 73 74 3a 20 54 58 20 65 72 72 6f 72 20 20 20 20 72 65 63 2e 3a 20 30 30 72 72 0d 0a ┆C test: TX error rec.: 00rr ┆
0x82e0…8300 0d 0a 54 68 65 20 6c 6f 77 20 6f 72 64 65 72 20 62 79 74 65 20 6f 66 20 74 68 65 20 72 65 63 65 ┆ The low order byte of the rece┆
0x8300…8320 69 76 65 64 20 64 61 74 61 20 69 73 20 73 69 67 6e 69 66 69 63 61 6e 74 2c 20 61 6e 64 20 0a 6d ┆ived data is significant, and m┆
0x8320…8340 75 73 74 20 62 65 20 69 6e 74 65 72 70 72 65 74 65 64 20 6c 69 6b 65 20 74 68 69 73 20 3a 0d 0a ┆ust be interpreted like this : ┆
0x8340…8360 0d 0a 52 65 73 75 6c 74 20 3d 20 42 37 2c 42 36 2c 42 35 2c 42 34 2c 42 33 2c 42 32 2c 42 31 2c ┆ Result = B7,B6,B5,B4,B3,B2,B1,┆
0x8360…8375 42 30 20 62 69 6e 61 72 79 20 3d 20 72 72 20 68 65 78 2e 0d 0a ┆B0 binary = rr hex. ┆
0x8375…83ae Params {
0x8375…83ae 04 00 27 4e 0c 00 06 00 00 00 00 03 01 4b 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N K1` ┆
0x8375…83ae 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x8375…83ae }
0x83ae…83e7 Params {
0x83ae…83e7 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x83ae…83e7 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x83ae…83e7 }
0x83e7…8400 0a 0d 0a a2 e2 a1 a1 2d 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ - ┆
0x8400…8420 (66,) 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x8420…8440 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2d 0d 0a a1 42 37 20 2c 20 42 36 20 ┆ - B7 , B6 ┆
0x8440…8460 2c 20 42 35 20 2c 20 42 34 20 2c 20 42 33 20 2c 20 42 32 20 2c 20 42 31 20 2c 20 42 30 20 20 20 ┆, B5 , B4 , B3 , B2 , B1 , B0 ┆
0x8460…8480 21 20 54 58 2d 69 6e 74 65 72 72 75 70 74 20 72 65 73 75 6c 74 20 63 6f 64 65 20 20 20 20 21 0d ┆! TX-interrupt result code ! ┆
0x8480…84a0 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 31 20 20 2c 20 31 20 20 2c 20 30 ┆ 0 , 0 , 0 , 0 , 1 , 1 , 0┆
0x84a0…84c0 20 20 2c 20 30 20 20 20 20 21 20 45 61 72 6c 79 20 74 72 61 6e 73 6d 69 74 20 69 6e 74 65 72 72 ┆ , 0 ! Early transmit interr┆
0x84c0…84e0 75 70 74 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 31 20 20 2c 20 31 20 ┆upt 0 , 0 , 0 , 0 , 1 , 1 ┆
0x84e0…8500 20 2c 20 30 20 20 2c 20 31 20 20 20 20 21 20 46 72 61 6d 65 20 74 72 61 6e 73 6d 69 74 20 63 6f ┆ , 0 , 1 ! Frame transmit co┆
0x8500…8520 6d 70 6c 65 74 65 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 31 20 20 2c ┆mplete 0 , 0 , 0 , 0 , 1 ,┆
0x8520…8540 20 31 20 20 2c 20 31 20 20 2c 20 30 20 20 20 20 21 20 44 4d 41 20 75 6e 64 65 72 72 75 6e 0d 0a ┆ 1 , 1 , 0 ! DMA underrun ┆
0x8540…8560 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 31 20 20 2c 20 31 20 20 2c 20 31 20 ┆0 , 0 , 0 , 0 , 1 , 1 , 1 ┆
0x8560…8580 20 2c 20 31 20 20 20 20 21 20 43 6c 65 61 72 20 54 6f 20 53 65 6e 64 20 28 43 54 53 29 20 65 72 ┆ , 1 ! Clear To Send (CTS) er┆
0x8580…85a0 72 6f 72 0d 0a 30 20 20 2c 20 30 20 20 2c 20 30 20 20 2c 20 31 20 20 2c 20 30 20 20 2c 20 30 20 ┆ror 0 , 0 , 0 , 1 , 0 , 0 ┆
0x85a0…85c0 20 2c 20 30 20 20 2c 20 30 20 20 20 20 21 20 41 62 6f 72 74 20 63 6f 6d 70 6c 65 74 65 0d 0a 0d ┆ , 0 , 0 ! Abort complete ┆
0x85c0…85c1 0a ┆ ┆
0x85c1…85c4 FormFeed {
0x85c1…85c4 0c 83 bc ┆ ┆
0x85c1…85c4 }
0x85c4…85c5 0a ┆ ┆
0x85c5…85fe Params {
0x85c5…85fe 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x85c5…85fe 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x85c5…85fe }
0x85fe…8637 Params {
0x85fe…8637 04 00 27 4e 0c 00 06 00 00 00 00 03 01 4b 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N K1` ┆
0x85fe…8637 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
0x85fe…8637 }
0x8637…8640 0a 54 68 65 20 6f 6e 6c 79 ┆ The only┆
0x8640…8660 20 76 61 6c 69 64 20 54 58 2d 69 6e 74 65 72 72 75 70 74 20 72 65 73 75 6c 74 20 69 6e 20 74 68 ┆ valid TX-interrupt result in th┆
0x8660…8680 69 73 20 70 72 6f 67 72 61 6d 20 69 73 20 44 30 20 0a 68 65 78 2e 2c 20 74 68 65 20 72 65 73 74 ┆is program is D0 hex., the rest┆
0x8680…86a0 20 61 72 65 20 74 72 65 61 74 65 64 20 6c 69 6b 65 20 65 72 72 6f 72 73 2e 0d 0a 0d 0a 49 66 20 ┆ are treated like errors. If ┆
0x86a0…86c0 6e 6f 6e 65 20 69 6e 74 65 72 72 75 70 74 73 20 66 72 6f 6d 20 74 68 65 20 38 32 37 33 20 63 6f ┆none interrupts from the 8273 co┆
0x86c0…86e0 6e 74 72 6f 6c 6c 65 72 20 69 73 20 73 65 72 76 69 63 65 64 2c 20 61 20 0a 6d 69 73 73 69 6e 67 ┆ntroller is serviced, a missing┆
0x86e0…8700 20 69 6e 74 65 72 72 75 70 74 20 6d 65 73 73 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 2e ┆ interrupt message is generated.┆
0x8700…8720 0d 0a 0d 0a 57 68 65 6e 20 63 6f 6d 6d 61 6e 64 73 20 61 72 65 20 77 72 69 74 74 65 6e 20 74 6f ┆ When commands are written to┆
0x8720…8740 2c 20 6f 72 20 70 61 72 61 6d 65 74 65 72 73 20 72 65 61 64 20 66 72 6f 6d 20 74 68 65 20 0a 38 ┆, or parameters read from the 8┆
0x8740…8760 32 37 33 20 53 44 4c 43 20 63 6f 6e 74 72 6f 6c 6c 65 72 2c 20 74 68 65 20 70 72 6f 67 72 61 6d ┆273 SDLC controller, the program┆
0x8760…8780 20 6d 75 73 74 20 77 61 69 74 20 75 6e 74 69 6c 20 70 61 72 61 6d 65 74 65 72 73 20 0a 61 72 65 ┆ must wait until parameters are┆
0x8780…87a0 20 76 61 6c 69 64 2c 20 6f 72 20 75 6e 74 69 6c 20 74 68 65 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 ┆ valid, or until the controller ┆
0x87a0…87c0 69 73 20 72 65 61 64 79 20 74 6f 20 61 63 63 65 70 74 20 0a 63 6f 6d 6d 61 6e 64 73 2e 20 49 66 ┆is ready to accept commands. If┆
0x87c0…87e0 20 74 68 65 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 64 6f 6e 74 20 67 65 74 20 72 65 61 64 79 20 74 ┆ the controller dont get ready t┆
0x87e0…8800 6f 20 61 63 63 65 70 74 20 61 20 0a 63 6f 6d 6d 61 6e 64 2c 20 6f 72 20 64 65 6c 69 76 65 72 20 ┆o accept a command, or deliver ┆
0x8800…8820 (68,) 73 6f 6d 65 20 70 61 72 61 6d 65 74 65 72 73 2c 20 69 6e 20 61 20 72 65 61 73 6f 6e 61 62 6c 65 ┆some parameters, in a reasonable┆
0x8820…8840 20 74 69 6d 65 2c 20 0a 74 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 20 65 72 72 6f 72 20 6d 61 73 73 ┆ time, the following error mass┆
0x8840…8860 61 67 65 20 69 73 20 67 65 6e 65 72 61 74 65 64 20 3a 0d 0a 0d 0a b0 38 32 37 33 20 63 68 43 20 ┆age is generated : 8273 chC ┆
0x8860…8880 74 65 73 74 3a 20 63 6f 6d 6d 61 6e 64 20 74 69 6d 65 6f 75 74 0d 0a 0d 0a 57 68 65 6e 20 61 6c ┆test: command timeout When al┆
0x8880…88a0 6c 20 64 61 74 61 20 68 61 73 20 62 65 65 6e 20 73 65 6e 74 2c 20 61 6e 64 20 61 6c 73 6f 20 74 ┆l data has been sent, and also t┆
0x88a0…88c0 68 65 20 69 6e 74 65 72 72 75 70 74 73 20 68 61 73 20 0a 62 65 65 6e 20 73 65 72 76 69 63 65 64 ┆he interrupts has been serviced┆
0x88c0…88e0 2c 20 74 68 65 6e 20 74 68 65 20 74 65 73 74 20 70 72 6f 67 72 61 6d 20 63 6f 6d 70 61 72 65 73 ┆, then the test program compares┆
0x88e0…8900 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 0a 61 6e 64 20 74 68 65 20 72 65 63 65 69 76 65 20 62 ┆ the transmit and the receive b┆
0x8900…8920 75 66 66 65 72 2e 20 49 66 20 61 6e 20 65 72 72 6f 72 20 69 73 20 64 65 74 65 63 74 65 64 20 61 ┆uffer. If an error is detected a┆
0x8920…8940 20 64 61 74 61 20 65 72 72 6f 72 20 0a 6d 65 73 73 61 67 65 20 69 73 20 72 65 70 6f 72 74 65 64 ┆ data error message is reported┆
0x8940…8960 20 74 6f 20 74 68 65 20 22 74 65 73 74 2d 6d 61 73 74 65 72 22 2c 20 6f 74 68 65 72 77 69 73 65 ┆ to the "test-master", otherwise┆
0x8960…8980 20 74 68 65 20 53 44 4c 43 20 0a 63 68 61 6e 6e 65 6c 20 69 73 20 73 61 69 64 20 74 6f 20 62 65 ┆ the SDLC channel is said to be┆
0x8980…89a0 20 4f 4b 2e 0d 0a 0d 0a 42 65 6c 6f 77 20 69 73 20 61 20 63 6f 6d 70 6c 65 74 65 20 6c 69 73 74 ┆ OK. Below is a complete list┆
0x89a0…89c0 20 6f 66 20 70 6f 73 73 69 62 6c 65 20 65 72 72 6f 72 20 6d 65 73 73 61 67 65 73 20 0a 67 65 6e ┆ of possible error messages gen┆
0x89c0…89d8 65 72 61 74 65 64 20 62 79 20 74 68 69 73 20 74 65 73 74 2e 0d 0a 0d 0a ┆erated by this test. ┆
0x89d8…89db FormFeed {
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0x89db…89dc 0a ┆ ┆
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0x89dc…8a15 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
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0x8a15…8a4e 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
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0x8a4e…8a60 0a e2 e2 e1 f0 e2 a1 e1 a2 e2 a1 2d 20 20 20 20 20 20 ┆ - ┆
0x8a60…8a80 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
[…0x1…]
0x8aa0…8ac0 20 20 20 20 20 20 20 2d 0d 0a 21 20 45 52 52 2e 21 20 4c 45 44 20 21 20 20 20 49 4e 54 52 4f 44 ┆ - ! ERR.! LED ! INTROD┆
0x8ac0…8ae0 55 43 54 49 4f 4e 20 20 20 21 20 20 20 20 20 20 20 45 52 52 4f 52 20 20 20 20 20 20 20 21 20 20 ┆UCTION ! ERROR ! ┆
0x8ae0…8b00 20 20 20 20 20 20 53 45 43 4f 4e 44 41 52 59 20 20 20 20 20 20 20 20 20 21 0d 0a a1 e1 a2 e2 a1 ┆ SECONDARY ! ┆
0x8b00…8b20 21 20 4e 4f 2e 20 21 20 4e 4f 2e 20 21 20 20 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 21 ┆! NO. ! NO. ! TEXT !┆
0x8b20…8b40 20 20 20 20 20 20 20 20 54 45 58 54 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 54 ┆ TEXT ! T┆
0x8b40…8b60 45 58 54 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 ┆EXT ! ! ! ! ┆
0x8b60…8b80 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x8b80…8ba0 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 ┆ ! !┆
0x8ba0…8bc0 0d 0a a1 21 20 31 32 20 20 21 20 31 32 20 20 21 20 38 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 ┆ ! 12 ! 12 ! 8273 chC test: ┆
0x8bc0…8be0 20 20 21 20 63 6f 6d 6d 61 6e 64 20 74 69 6d 65 6f 75 74 20 20 20 21 20 20 20 20 20 20 20 20 20 ┆ ! command timeout ! ┆
0x8be0…8c00 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 ┆ ! ! ! ┆
0x8c00…8c20 (70,) 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 ┆! ! ┆
0x8c20…8c40 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x8c40…8c60 20 20 21 0d 0a a2 e2 a1 21 20 31 33 20 20 21 20 31 33 20 20 21 20 38 32 37 33 20 63 68 43 20 74 ┆ ! ! 13 ! 13 ! 8273 chC t┆
0x8c60…8c80 65 73 74 3a 20 20 20 21 20 74 72 61 6e 73 66 65 72 20 74 69 6d 65 6f 75 74 20 20 21 20 20 20 20 ┆est: ! transfer timeout ! ┆
0x8c80…8ca0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 ┆ ! ! !┆
0x8ca0…8cc0 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 ┆ ! ! ┆
0x8cc0…8ce0 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x8ce0…8d00 20 20 20 20 20 20 20 21 0d 0a a1 21 20 31 34 20 20 21 20 31 34 20 20 21 20 38 32 37 33 20 63 68 ┆ ! ! 14 ! 14 ! 8273 ch┆
0x8d00…8d20 43 20 74 65 73 74 3a 20 20 20 21 20 52 58 20 65 72 72 6f 72 20 20 20 20 20 20 20 20 20 20 21 20 ┆C test: ! RX error ! ┆
0x8d20…8d40 72 65 63 2e 3a 3c 30 30 72 72 3e 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 ┆rec.:<00rr> ! ! ┆
0x8d40…8d60 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 ┆ ! ! ! ┆
0x8d60…8d80 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x8d80…8da0 20 20 20 20 20 20 20 20 20 20 21 0d 0a a1 21 20 31 35 20 20 21 20 31 35 20 20 21 20 38 32 37 33 ┆ ! ! 15 ! 15 ! 8273┆
0x8da0…8dc0 20 63 68 43 20 74 65 73 74 3a 20 20 20 21 20 54 58 20 65 72 72 6f 72 20 20 20 20 20 20 20 20 20 ┆ chC test: ! TX error ┆
0x8dc0…8de0 20 21 20 72 65 63 2e 3a 3c 30 30 72 72 3e 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 ┆ ! rec.:<00rr> ! !┆
0x8de0…8e00 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 ┆ ! ! ! ┆
0x8e00…8e20 (71,) 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ┆
0x8e20…8e40 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a1 21 20 31 36 20 20 21 20 31 36 20 20 21 20 38 ┆ ! ! 16 ! 16 ! 8┆
0x8e40…8e60 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 20 20 21 20 56 2e 32 34 20 73 74 61 74 75 73 20 65 72 ┆273 chC test: ! V.24 status er┆
0x8e60…8e80 72 6f 72 20 21 20 65 78 70 2e 3a 3c 30 30 30 65 3e 2c 20 72 65 63 2e 3a 3c 30 30 30 72 3e 20 21 ┆ror ! exp.:<000e>, rec.:<000r> !┆
0x8e80…8ea0 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ! ! ┆
0x8ea0…8ec0 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 ┆ ! ! ┆
0x8ec0…8ee0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a1 21 20 31 37 20 20 21 20 31 37 20 20 ┆ ! ! 17 ! 17 ┆
0x8ee0…8f00 21 20 38 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 20 20 21 20 58 2e 32 31 20 73 74 61 74 75 73 ┆! 8273 chC test: ! X.21 status┆
0x8f00…8f20 20 65 72 72 6f 72 20 21 20 65 78 70 2e 3a 3c 30 30 30 65 3e 2c 20 72 65 63 2e 3a 3c 30 30 30 72 ┆ error ! exp.:<000e>, rec.:<000r┆
0x8f20…8f40 3e 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆> ! ! ! ! ┆
0x8f40…8f60 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 ┆ ! ! ┆
0x8f60…8f80 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a2 e2 a1 21 20 31 38 20 20 21 ┆ ! ! 18 !┆
0x8f80…8fa0 20 31 38 20 20 21 20 38 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 20 20 21 20 6d 69 73 73 69 6e ┆ 18 ! 8273 chC test: ! missin┆
0x8fa0…8fc0 67 20 69 6e 74 65 72 72 75 70 74 20 21 20 72 65 63 2e 3a 3c 30 30 72 72 3e 20 20 20 20 20 20 20 ┆g interrupt ! rec.:<00rr> ┆
0x8fc0…8fe0 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 ┆ ! ! ! ! ┆
0x8fe0…9000 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 61 ┆ ! ! a┆
0x9000…9020 (72,) 64 72 2e 3a 3c 61 61 61 61 3e 2c 20 72 65 63 2e 3a 3c 72 72 72 72 3e 20 21 0d 0a a1 21 20 31 39 ┆dr.:<aaaa>, rec.:<rrrr> ! ! 19┆
0x9020…9040 20 20 21 20 31 39 20 20 21 20 38 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 20 20 21 20 64 61 74 ┆ ! 19 ! 8273 chC test: ! dat┆
0x9040…9060 61 20 65 72 72 6f 72 20 20 20 20 20 20 20 20 21 20 65 78 70 2e 3a 3c 65 65 65 65 3e 20 20 20 20 ┆a error ! exp.:<eeee> ┆
0x9060…9080 20 20 20 20 20 20 20 20 20 20 21 0d 0a 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 20 ┆ ! ! ! ! ┆
0x9080…90a0 20 20 20 20 20 20 20 20 20 20 20 20 21 20 58 2e 32 31 20 64 69 61 6c 20 65 72 72 6f 72 20 20 20 ┆ ! X.21 dial error ┆
0x90a0…90c0 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a a1 21 ┆! ! !┆
0x90c0…90e0 20 33 31 20 20 21 20 33 31 20 20 21 20 38 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 20 20 21 20 ┆ 31 ! 31 ! 8273 chC test: ! ┆
0x90e0…9100 63 69 72 63 75 69 74 20 66 61 69 6c 75 72 65 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆circuit failure ! ┆
0x9100…9110 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a ┆ ! ┆
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0x9110…9149 04 00 27 4e 0a 00 06 00 00 00 00 03 01 3c 31 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ 'N <1` ┆
0x9110…9149 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
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0x9149…9182 Params {
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0x9149…9182 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
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0x9182…91a0 0a 0d 0a 54 68 65 20 74 65 73 74 20 69 73 20 72 75 6e 20 61 74 20 61 20 62 61 75 64 20 72 ┆ The test is run at a baud r┆
0x91a0…91b1 61 74 65 20 6f 66 20 36 34 20 4b 62 2f 73 2e 0d 0a ┆ate of 64 Kb/s. ┆
0x91b1…91b4 FormFeed {
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0x91cc…9205 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
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0x9205…923e Params {
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0x9205…923e 00 00 00 00 00 00 00 00 01 05 0a 0f 14 19 1e 23 28 2d 32 37 3c 41 46 ff 04 ┆ #(-27<AF ┆
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0x923e…9240 0a 52 ┆ R┆
0x9240…9260 43 53 4c 2e 20 39 39 31 20 31 30 30 39 32 0d 0a 52 43 20 33 39 20 53 65 6c 66 74 65 73 74 20 43 ┆CSL. 991 10092 RC 39 Selftest C┆
0x9260…9280 6f 6e 63 65 70 74 2c 20 0d 0a 55 73 65 72 27 73 20 6d 61 6e 75 61 6c 20 09 20 20 20 20 20 09 0d ┆oncept, User's manual ┆
0x9280…92a0 0a 0d 0a 52 43 53 4c 2e 20 39 39 31 20 31 30 30 39 36 0d 0a 52 43 20 33 39 33 31 20 45 54 43 36 ┆ RCSL. 991 10096 RC 3931 ETC6┆
0x92a0…92c0 31 31 20 68 61 72 64 77 61 72 65 20 73 65 6c 66 74 65 73 74 2c 20 0d 0a 55 73 65 72 27 73 20 6d ┆11 hardware selftest, User's m┆
0x92c0…92e0 61 6e 75 61 6c 20 20 0d 0a 0d 0a 52 43 53 4c 2e 20 39 39 31 20 31 30 30 39 35 0d 0a 49 54 43 20 ┆anual RCSL. 991 10095 ITC ┆
0x92e0…9300 36 30 32 20 68 61 72 64 77 61 72 65 20 73 65 6c 66 74 65 73 74 2c 20 0d 0a 55 73 65 72 27 73 20 ┆602 hardware selftest, User's ┆
0x9300…9320 6d 61 6e 75 61 6c 20 20 20 20 09 0d 0a 0d 0a 52 43 53 4c 2e 20 39 39 31 20 31 30 30 39 34 0d 0a ┆manual RCSL. 991 10094 ┆
0x9320…9340 52 43 33 39 30 32 20 43 50 55 20 36 39 31 20 68 61 72 64 77 61 72 65 20 73 65 6c 66 74 65 73 74 ┆RC3902 CPU 691 hardware selftest┆
0x9340…9360 2c 20 0d 0a 55 73 65 72 27 73 20 6d 61 6e 75 61 6c 20 20 0d 0a 0d 0a 52 43 53 4c 2e 20 39 39 31 ┆, User's manual RCSL. 991┆
0x9360…9380 20 31 30 31 33 34 0d 0a 52 43 33 39 20 6d 6f 6e 69 74 6f 72 20 38 30 38 36 20 76 65 72 73 69 6f ┆ 10134 RC39 monitor 8086 versio┆
0x9380…93a0 6e 2c 20 0d 0a 52 65 66 65 72 65 6e 63 65 20 6d 61 6e 75 61 6c 09 20 20 20 20 20 0d 0a 0d 0a 52 ┆n, Reference manual R┆
0x93a0…93c0 43 53 4c 2e 20 39 39 31 20 31 30 30 39 33 0d 0a 52 43 33 39 20 6d 6f 6e 69 74 6f 72 20 38 30 32 ┆CSL. 991 10093 RC39 monitor 802┆
0x93c0…93e0 38 36 20 76 65 72 73 69 6f 6e 2c 20 0d 0a 52 65 66 65 72 65 6e 63 65 20 6d 61 6e 75 61 6c 20 20 ┆86 version, Reference manual ┆
0x93e0…93e5 20 20 20 0d 0a ┆ ┆
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0x93e8…9400 0a a1 b0 42 2e 20 b0 4c 4f 4f 50 20 42 41 43 4b 20 43 41 42 4c 45 0d 0a ┆ B. LOOP BACK CABLE ┆
0x9400…9420 (74,) 0d 0a 42 6f 74 68 20 74 68 65 20 38 32 37 34 20 63 68 61 6e 6e 65 6c 20 42 20 61 6e 64 20 74 68 ┆ Both the 8274 channel B and th┆
0x9420…9440 65 20 38 32 37 33 20 74 65 73 74 20 72 65 6c 69 65 73 20 6f 6e 20 74 68 65 20 66 61 63 74 20 0a ┆e 8273 test relies on the fact ┆
0x9440…9460 74 68 61 74 20 61 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 20 69 73 20 63 6f 6e 6e 65 63 ┆that a loop back cable is connec┆
0x9460…9480 74 65 64 20 74 6f 20 74 68 65 20 43 4f 4d 20 36 30 31 20 65 64 67 65 20 0a 63 6f 6e 6e 65 63 74 ┆ted to the COM 601 edge connect┆
0x9480…94a0 6f 72 73 20 4a 33 20 61 6e 64 20 4a 34 2e 20 4f 6e 20 74 68 65 20 6e 65 78 74 20 70 61 67 65 20 ┆ors J3 and J4. On the next page ┆
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0x94c0…94e0 6e 75 6d 62 65 72 20 6f 66 20 74 68 65 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 2e 0d 0a ┆number of the loop back cable. ┆
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0x9552…9553 0a ┆ ┆
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0x9556…9560 0a a1 20 20 4a 33 20 20 20 20 ┆ J3 ┆
0x9560…9580 20 20 20 20 20 20 20 20 20 20 70 69 6e 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ pin ┆
0x9580…95a0 20 20 20 20 20 20 20 20 20 20 20 20 20 70 69 6e 20 4a 34 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ pin J4 ┆
0x95a0…95c0 0d 0a 0d 0a 52 54 53 42 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 37 20 2d 09 09 09 09 09 ┆ RTSB 7 - ┆
0x95c0…95e0 09 20 20 20 2d 09 20 37 20 52 54 53 43 0d 0a 43 54 53 42 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ - 7 RTSC CTSB ┆
0x95e0…9600 20 20 20 39 20 2d 09 09 09 09 09 09 20 20 20 2d 09 20 39 20 43 54 53 43 0d 0a 44 53 52 42 20 20 ┆ 9 - - 9 CTSC DSRB ┆
0x9600…9620 (75,) 20 20 20 20 20 20 20 20 20 20 20 20 20 31 31 20 2d 09 09 09 09 09 09 20 20 20 2d 09 31 31 20 44 ┆ 11 - - 11 D┆
0x9620…9640 53 52 43 0d 0a 0d 0a 54 58 44 42 09 09 09 20 33 20 2d 09 09 09 09 09 09 20 20 20 2d 09 20 33 20 ┆SRC TXDB 3 - - 3 ┆
0x9640…9660 54 58 44 43 0d 0a 52 58 44 42 09 09 09 20 35 20 2d 09 09 09 09 09 20 09 20 20 20 2d 09 20 35 20 ┆TXDC RXDB 5 - - 5 ┆
0x9660…9680 52 58 44 43 0d 0a 0d 0a 44 54 52 42 09 09 09 31 34 20 2d 09 09 09 09 09 09 20 20 20 2d 09 31 34 ┆RXDC DTRB 14 - - 14┆
0x9680…96a0 20 44 54 52 43 0d 0a 44 43 44 42 09 09 09 31 35 20 2d 09 09 09 09 09 09 20 20 20 2d 09 31 35 20 ┆ DTRC DCDB 15 - - 15 ┆
0x96a0…96c0 44 43 44 43 0d 0a 43 49 42 09 09 09 09 31 38 20 2d 09 09 09 09 09 09 20 20 20 2d 09 31 38 20 43 ┆DCDC CIB 18 - - 18 C┆
0x96c0…96e0 49 43 0d 0a 0d 0a 47 4e 44 09 09 09 09 31 33 20 2d 09 09 09 09 09 09 20 20 20 2d 09 31 33 20 47 ┆IC GND 13 - - 13 G┆
0x96e0…9700 4e 44 0d 0a 0d 0a 52 28 41 29 42 20 09 09 09 31 36 20 2d 09 09 09 09 09 09 20 20 20 2d 09 31 36 ┆ND R(A)B 16 - - 16┆
0x9700…9720 20 52 28 41 29 43 0d 0a 54 28 41 29 42 09 09 09 31 37 20 2d 09 09 09 09 09 09 20 20 20 2d 09 31 ┆ R(A)C T(A)B 17 - - 1┆
0x9720…9740 37 20 54 28 41 29 43 0d 0a 0d 0a 52 28 42 29 42 09 09 09 31 32 20 2d 09 09 09 09 09 09 20 20 20 ┆7 T(A)C R(B)B 12 - ┆
0x9740…9760 2d 09 31 32 20 52 28 42 29 43 0d 0a 54 28 42 29 42 20 09 09 09 32 33 20 2d 09 09 09 09 09 09 20 ┆- 12 R(B)C T(B)B 23 - ┆
0x9760…9780 20 20 2d 09 32 33 20 54 28 42 29 43 0d 0a 0d 0a 43 28 41 29 42 09 09 09 32 34 20 2d 09 09 09 09 ┆ - 23 T(B)C C(A)B 24 - ┆
0x9780…97a0 09 09 20 20 20 2d 09 32 34 20 43 28 41 29 43 0d 0a 49 28 41 29 42 09 09 09 31 39 20 2d 09 09 09 ┆ - 24 C(A)C I(A)B 19 - ┆
0x97a0…97c0 09 09 09 20 20 20 2d 09 31 39 20 49 28 41 29 43 0d 0a 0d 0a 43 28 42 29 42 09 09 09 20 32 20 2d ┆ - 19 I(A)C C(B)B 2 -┆
0x97c0…97e0 09 09 09 09 09 09 20 20 20 2d 20 20 32 20 43 28 42 29 43 0d 0a 49 28 42 29 42 09 09 09 32 32 20 ┆ - 2 C(B)C I(B)B 22 ┆
0x97e0…9800 2d 09 09 09 09 09 09 20 20 20 2d 20 32 32 20 49 28 42 29 43 0d 0a 0d 0a 53 28 41 29 42 09 09 09 ┆- - 22 I(B)C S(A)B ┆
0x9800…9820 (76,) 31 30 20 2d 09 09 09 09 09 09 20 20 20 2d 20 31 30 20 53 28 41 29 43 0d 0a 53 28 42 29 42 09 09 ┆10 - - 10 S(A)C S(B)B ┆
0x9820…9840 09 20 36 20 2d 09 09 09 09 09 09 20 20 20 2d 20 20 36 20 53 28 42 29 43 0d 0a 58 2e 32 31 20 54 ┆ 6 - - 6 S(B)C X.21 T┆
0x9840…9860 45 53 54 20 43 4c 4b 2e 20 42 09 32 30 20 2d 09 09 09 09 09 09 20 20 20 2d 20 32 30 20 58 2e 32 ┆EST CLK. B 20 - - 20 X.2┆
0x9860…9880 31 20 54 45 53 54 20 43 4c 4b 2e 20 43 0d 0a 0d 0a 56 2e 32 34 20 54 45 53 54 20 43 4c 4b 2e 20 ┆1 TEST CLK. C V.24 TEST CLK. ┆
0x9880…98a0 42 09 32 35 20 2d 09 09 09 09 09 09 20 20 20 2d 20 32 35 20 56 2e 32 34 20 54 45 53 54 20 43 4c ┆B 25 - - 25 V.24 TEST CL┆
0x98a0…98c0 4b 2e 20 43 0d 0a 52 45 43 2e 20 43 4c 4b 2e 20 42 09 09 20 38 20 2d 09 09 09 09 09 09 20 20 20 ┆K. C REC. CLK. B 8 - ┆
0x98c0…98e0 2d 20 20 38 20 52 45 43 2e 20 43 4c 4b 2e 20 43 20 0d 0a 54 52 41 4e 53 2e 20 43 4c 4b 2e 20 42 ┆- 8 REC. CLK. C TRANS. CLK. B┆
0x98e0…9900 09 09 20 34 20 2d 09 09 09 09 09 09 20 20 20 2d 20 20 34 20 54 52 41 4e 53 2e 20 43 4c 4b 2e 20 ┆ 4 - - 4 TRANS. CLK. ┆
0x9900…9920 43 0d 0a 0d 0a 58 2e 32 31 20 53 45 4c 2e 20 42 20 20 20 20 20 20 20 20 32 31 20 2d 09 09 09 09 ┆C X.21 SEL. B 21 - ┆
0x9920…9940 09 09 20 20 20 2d 20 32 31 20 58 2e 32 31 20 53 45 4c 2e 20 43 0d 0a 0d 0a b0 70 61 72 74 20 6e ┆ - 21 X.21 SEL. C part n┆
0x9940…9960 75 6d 62 65 72 20 3a 20 4b 42 4c 20 36 30 39 0d 0a 0d 0a 09 09 09 09 a1 43 4f 4d 20 36 30 31 20 ┆umber : KBL 609 COM 601 ┆
0x9960…997d 43 61 72 64 20 65 64 67 65 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 2e 20 0d 0a ┆Card edge loop back cable. ┆
0x997d…9980 FormFeed {
0x997d…9980 0c 83 90 ┆ ┆
0x997d…9980 }
0x9980…99a0 0a a1 a1 a1 b0 43 2e 20 43 4f 4d 50 4c 45 54 45 20 45 52 52 4f 52 20 4c 49 53 54 0d 0a 0d 0a 21 ┆ C. COMPLETE ERROR LIST !┆
0x99a0…99c0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x99e0…9a00 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 45 72 72 2e 20 4e 6f 20 21 09 09 09 09 20 ┆-------------! ! Err. No ! ┆
0x9a00…9a20 (77,) 20 20 45 72 72 6f 72 20 54 65 78 74 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d ┆ Error Text ! !-----┆
0x9a20…9a40 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x9a60…9a80 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 30 20 20 20 20 21 20 4f 4b 09 09 09 09 09 09 09 ┆--------! ! 0 ! OK ┆
0x9a80…9aa0 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !-------------------┆
0x9aa0…9ac0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x9ac0…9ae0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 4e ┆--------------------------! N┆
0x9ae0…9b00 6f 20 65 72 72 6f 72 20 64 65 74 65 63 74 65 64 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆o error detected. !----------┆
0x9b00…9b20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x9b40…9b60 2d 2d 2d 21 0d 0a 21 20 20 20 20 31 20 20 20 20 21 20 52 41 4d 2f 52 4f 4d 20 74 65 73 74 20 3a ┆---! ! 1 ! RAM/ROM test :┆
0x9b60…9b80 20 63 68 65 63 6b 73 75 6d 20 65 72 72 6f 72 09 09 09 09 09 09 09 09 09 09 20 21 0d 0a 21 2d 2d ┆ checksum error ! !--┆
0x9b80…9ba0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x9bc0…9be0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 54 68 65 20 63 61 6c 63 75 6c 61 74 65 64 20 45 ┆-----------! The calculated E┆
0x9be0…9c00 50 52 4f 4d 20 63 68 65 63 6b 73 75 6d 20 77 61 73 20 6e 6f 74 20 7a 65 72 6f 2e 0d 0a 0d 0a 21 ┆PROM checksum was not zero. !┆
0x9c00…9c20 (78,) 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x9c40…9c60 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 32 09 20 21 20 52 41 4d 2f 52 4f ┆-------------! ! 2 ! RAM/RO┆
0x9c60…9c80 4d 20 74 65 73 74 20 3a 20 52 41 4d 20 65 72 72 6f 72 09 09 09 09 09 09 09 09 20 20 20 20 21 0d ┆M test : RAM error ! ┆
0x9c80…9ca0 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ !------------------------------┆
0x9ca0…9cc0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x9cc0…9ce0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 54 68 65 20 52 41 4d 2d 74 65 73 74 ┆---------------! The RAM-test┆
0x9ce0…9d00 20 64 69 64 20 6e 6f 74 20 72 65 61 64 20 62 61 63 6b 20 74 68 65 20 73 61 6d 65 20 70 61 74 74 ┆ did not read back the same patt┆
0x9d00…9d20 65 72 6e 20 61 73 20 77 72 69 74 74 65 6e 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ern as written. !------------┆
0x9d20…9d40 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x9d60…9d80 2d 21 0d 0a 21 20 20 20 20 33 20 20 20 20 21 20 50 50 49 20 74 65 73 74 3a 20 70 6f 72 74 20 65 ┆-! ! 3 ! PPI test: port e┆
0x9d80…9da0 72 72 6f 72 09 09 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆rror ! !-----------┆
0x9da0…9dc0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x9de0…9e00 2d 2d 21 0d 0a 0d 0a 54 68 65 20 70 61 72 61 6c 6c 65 6c 20 70 6f 72 74 20 74 65 73 74 20 64 69 ┆--! The parallel port test di┆
0x9e00…9e20 (79,) 64 20 6e 6f 74 20 72 65 61 64 20 62 61 63 6b 20 74 68 65 20 73 61 6d 65 20 70 61 74 74 65 72 6e ┆d not read back the same pattern┆
0x9e20…9e40 20 61 73 20 77 72 69 74 74 65 6e 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ as written. !---------------┆
0x9e40…9e60 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x9e60…9e80 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d ┆------------------------------! ┆
0x9e80…9ea0 0a 21 20 20 20 20 34 20 20 20 20 21 20 50 49 54 20 74 65 73 74 3a 20 62 6f 74 68 20 69 6e 74 65 ┆ ! 4 ! PIT test: both inte┆
0x9ea0…9ec0 72 72 75 70 74 73 20 6d 69 73 73 69 6e 67 20 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d ┆rrupts missing ! !---┆
0x9ec0…9ee0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x9f00…9f20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 42 6f 74 68 20 38 32 35 34 20 74 69 6d 65 72 20 69 ┆----------! Both 8254 timer i┆
0x9f20…9f40 6e 74 65 72 72 75 70 74 73 20 77 65 72 65 20 65 69 74 68 65 72 20 6e 6f 74 20 67 65 6e 65 72 61 ┆nterrupts were either not genera┆
0x9f40…9f60 74 65 64 20 6f 72 20 73 65 72 76 69 63 65 64 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ted or serviced. !-----------┆
0x9f60…9f80 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0x9fa0…9fc0 2d 2d 21 0d 0a 21 20 20 20 20 35 20 20 20 20 21 20 50 49 54 20 74 65 73 74 3a 20 6f 6e 65 20 69 ┆--! ! 5 ! PIT test: one i┆
0x9fc0…9fe0 6e 74 65 72 72 75 70 74 20 6d 69 73 73 69 6e 67 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d ┆nterrupt missing ! !-┆
0x9fe0…a000 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xa020…a040 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 4f 6e 65 20 6f 66 20 74 68 65 20 38 32 35 34 ┆------------! One of the 8254┆
0xa040…a060 20 74 69 6d 65 72 20 69 6e 74 65 72 72 75 70 74 73 20 77 61 73 20 6e 6f 74 20 67 65 6e 65 72 61 ┆ timer interrupts was not genera┆
0xa060…a074 74 65 64 20 6f 72 20 73 65 72 76 69 63 65 64 2e 0d 0a 0d 0a ┆ted or serviced. ┆
0xa074…a077 FormFeed {
0xa074…a077 0c 83 90 ┆ ┆
0xa074…a077 }
0xa077…a080 0a 21 2d 2d 2d 2d 2d 2d 2d ┆ !-------┆
0xa080…a0a0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xa0c0…a0e0 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 38 20 20 20 20 21 20 44 4d 41 20 74 65 73 74 3a 20 54 ┆------! ! 8 ! DMA test: T┆
0xa0e0…a100 43 20 62 65 66 6f 72 65 20 73 74 61 72 74 09 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d ┆C before start ! !--┆
0xa100…a120 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xa140…a160 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 54 68 65 20 38 32 33 37 41 20 44 4d 41 20 63 68 ┆-----------! The 8237A DMA ch┆
0xa160…a180 69 70 20 69 6e 64 69 63 61 74 65 73 20 54 65 72 6d 69 6e 61 6c 20 43 6f 75 6e 74 20 72 65 61 63 ┆ip indicates Terminal Count reac┆
0xa180…a1a0 68 65 64 20 62 65 66 6f 72 65 20 61 6e 79 20 74 72 61 6e 73 70 6f 72 74 20 69 73 20 0d 0a 73 74 ┆hed before any transport is st┆
0xa1a0…a1c0 61 72 74 65 64 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆arted. !---------------------┆
0xa1c0…a1e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xa1e0…a200 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 ┆------------------------! ! ┆
0xa200…a220 (81,) 39 20 20 20 20 21 20 44 4d 41 20 74 65 73 74 3a 20 74 69 6d 65 6f 75 74 09 09 09 09 09 09 09 09 ┆9 ! DMA test: timeout ┆
0xa220…a240 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !-----------------------┆
0xa240…a260 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xa260…a280 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 54 68 65 20 44 ┆----------------------! The D┆
0xa280…a2a0 4d 41 20 74 72 61 6e 73 70 6f 72 74 20 68 61 73 20 6e 6f 74 20 66 69 6e 69 73 68 65 64 20 77 69 ┆MA transport has not finished wi┆
0xa2a0…a2c0 74 68 69 6e 20 61 70 70 2e 20 31 30 30 20 6d 69 6c 6c 69 73 65 63 6f 6e 64 73 2e 0d 0a 0d 0a 21 ┆thin app. 100 milliseconds. !┆
0xa2c0…a2e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xa300…a320 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 3b 0d 0a 21 20 20 20 20 31 30 20 20 20 21 20 44 4d 41 20 ┆-------------; ! 10 ! DMA ┆
0xa320…a340 74 65 73 74 3a 20 64 61 74 61 20 65 72 72 6f 72 09 09 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a ┆test: data error ! ┆
0xa340…a360 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆!-------------------------------┆
0xa360…a380 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xa380…a3a0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 54 68 65 20 44 4d 41 20 64 61 74 61 20 ┆--------------! The DMA data ┆
0xa3a0…a3c0 74 72 61 6e 73 70 6f 72 74 20 68 61 73 20 66 69 6e 69 73 68 65 64 2c 20 62 75 74 20 74 68 65 20 ┆transport has finished, but the ┆
0xa3c0…a3e0 72 65 63 65 69 76 65 64 20 64 61 74 61 20 69 73 20 64 69 66 66 65 72 65 6e 74 20 66 72 6f 6d 20 ┆received data is different from ┆
0xa3e0…a400 0d 0a 74 68 65 20 64 61 74 61 20 73 65 6e 74 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ the data sent. !-----------┆
0xa400…a420 (82,) 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xa440…a460 2d 2d 21 0d 0a 21 20 20 20 20 31 31 20 20 20 21 20 44 4d 41 20 74 65 73 74 3a 20 6d 69 73 73 69 ┆--! ! 11 ! DMA test: missi┆
0xa460…a480 6e 67 20 69 6e 74 65 72 72 75 70 74 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d ┆ng interrupt ! !-----┆
0xa480…a4a0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xa4c0…a4e0 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 4e 6f 20 44 4d 41 20 54 65 72 6d 69 6e 61 6c 20 43 6f 75 ┆--------! No DMA Terminal Cou┆
0xa4e0…a500 6e 74 20 69 6e 74 65 72 72 75 70 74 20 67 65 6e 65 72 61 74 65 64 20 6f 72 20 73 65 72 76 69 63 ┆nt interrupt generated or servic┆
0xa500…a520 65 64 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ed. !------------------------┆
0xa520…a540 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xa540…a560 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 31 32 20 ┆---------------------! ! 12 ┆
0xa560…a580 20 20 21 20 38 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 63 6f 6d 6d 61 6e 64 20 74 69 6d 65 6f ┆ ! 8273 chC test: command timeo┆
0xa580…a5a0 75 74 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ut ! !---------------┆
0xa5a0…a5c0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xa5c0…a5e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d ┆------------------------------! ┆
0xa5e0…a600 0a 0d 0a 54 68 65 20 38 32 37 33 20 53 44 4c 43 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 63 68 69 70 ┆ The 8273 SDLC controller chip┆
0xa600…a620 (83,) 20 64 69 64 20 6e 6f 74 20 61 63 63 65 70 74 20 74 68 65 20 63 6f 6d 6d 61 6e 64 20 69 73 73 75 ┆ did not accept the command issu┆
0xa620…a640 65 64 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ed. !------------------------┆
0xa640…a660 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xa660…a680 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 31 33 20 ┆---------------------! ! 13 ┆
0xa680…a6a0 20 20 21 20 38 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 74 72 61 6e 73 66 65 72 20 74 69 6d 65 ┆ ! 8273 chC test: transfer time┆
0xa6a0…a6c0 6f 75 74 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆out ! !--------------┆
0xa6c0…a6e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xa6e0…a700 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 ┆-------------------------------!┆
0xa700…a720 0d 0a 0d 0a 54 68 65 20 73 65 72 69 61 6c 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 20 28 44 ┆ The serial data transport (D┆
0xa720…a740 4d 41 20 63 6f 6e 74 72 6f 6c 6c 65 64 29 20 64 69 64 20 6e 6f 74 20 63 6f 6d 70 6c 65 74 65 20 ┆MA controlled) did not complete ┆
0xa740…a760 77 69 74 68 69 6e 20 32 2e 35 20 73 65 63 6f 6e 64 73 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d ┆within 2.5 seconds. !--------┆
0xa760…a780 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xa7a0…a7c0 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 31 34 20 20 20 21 20 38 32 37 33 20 63 68 43 20 74 65 73 ┆-----! ! 14 ! 8273 chC tes┆
0xa7c0…a7e0 74 3a 20 52 58 20 65 72 72 6f 72 09 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d ┆t: RX error ! !-----┆
0xa7e0…a800 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xa820…a840 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 54 68 65 20 52 58 2d 69 6e 74 65 72 72 75 70 74 20 72 65 ┆--------! The RX-interrupt re┆
0xa840…a860 73 75 6c 74 20 77 61 73 20 6e 6f 74 20 61 20 67 65 6e 65 72 61 6c 20 66 72 61 6d 65 20 72 65 63 ┆sult was not a general frame rec┆
0xa860…a880 65 69 76 65 64 20 72 65 73 75 6c 74 20 61 73 20 65 78 70 65 63 74 65 64 2e 0d 0a 0d 0a 21 2d 2d ┆eived result as expected. !--┆
0xa880…a8a0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xa8c0…a8e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 8c 83 c2 0a 21 20 20 20 20 31 35 20 20 20 21 20 38 32 ┆-----------! ! 15 ! 82┆
0xa8e0…a900 37 33 20 63 68 43 20 74 65 73 74 3a 20 54 58 20 65 72 72 6f 72 09 09 09 09 09 09 09 09 20 20 20 ┆73 chC test: TX error ┆
0xa900…a920 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !---------------------------┆
0xa920…a940 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xa940…a960 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 54 68 65 20 54 58 2d 69 6e ┆------------------! The TX-in┆
0xa960…a980 74 65 72 72 75 70 74 20 72 65 73 75 6c 74 20 77 61 73 20 6e 6f 74 20 61 20 66 72 61 6d 65 20 74 ┆terrupt result was not a frame t┆
0xa980…a9a0 72 61 6e 73 6d 69 74 20 63 6f 6d 70 6c 65 74 65 64 20 72 65 73 75 6c 74 20 61 73 20 65 78 70 65 ┆ransmit completed result as expe┆
0xa9a0…a9c0 63 74 65 64 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆cted. !----------------------┆
0xa9c0…a9e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xa9e0…aa00 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 31 ┆-----------------------! ! 1┆
0xaa00…aa20 (85,) 36 20 20 20 21 20 38 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 56 2e 32 34 20 73 74 61 74 75 73 ┆6 ! 8273 chC test: V.24 status┆
0xaa20…aa40 20 65 72 72 6f 72 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ error ! !------------┆
0xaa40…aa60 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xaa80…aaa0 2d 21 0d 0a 0d 0a 54 68 65 20 56 2e 32 34 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 73 2c 20 77 ┆-! The V.24 status signals, w┆
0xaaa0…aac0 68 69 63 68 20 69 73 20 74 6f 67 67 6c 65 64 20 76 69 61 20 74 68 65 20 6c 6f 6f 70 20 62 61 63 ┆hich is toggled via the loop bac┆
0xaac0…aae0 6b 20 63 61 62 6c 65 2c 20 66 61 69 6c 73 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆k cable, fails. !------------┆
0xaae0…ab00 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xab20…ab40 2d 21 0d 0a 21 20 20 20 20 31 37 20 20 20 21 20 38 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 58 ┆-! ! 17 ! 8273 chC test: X┆
0xab40…ab60 2e 32 31 20 73 74 61 74 75 73 20 65 72 72 6f 72 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d ┆.21 status error ! !--┆
0xab60…ab80 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xaba0…abc0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 54 68 65 20 58 2e 32 31 20 73 74 61 74 75 73 20 ┆-----------! The X.21 status ┆
0xabc0…abe0 73 69 67 6e 61 6c 73 2c 20 77 68 69 63 68 20 69 73 20 74 6f 67 67 6c 65 64 20 76 69 61 20 74 68 ┆signals, which is toggled via th┆
0xabe0…ac00 65 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 2c 20 66 61 69 6c 73 2e 0d 0a 0d 0a 21 2d 2d ┆e loop back cable, fails. !--┆
0xac00…ac20 (86,) 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xac40…ac60 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 31 38 20 20 20 21 20 38 32 37 33 20 63 ┆-----------! ! 18 ! 8273 c┆
0xac60…ac80 68 43 20 74 65 73 74 3a 20 6d 69 73 73 69 6e 67 20 69 6e 74 65 72 72 75 70 74 09 09 09 09 09 09 ┆hC test: missing interrupt ┆
0xac80…aca0 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !------------------------┆
0xaca0…acc0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xacc0…ace0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 52 58 2d 69 6e 74 ┆---------------------! RX-int┆
0xace0…ad00 65 72 72 75 70 74 20 6f 72 20 54 58 2d 69 6e 74 65 72 72 75 70 74 20 6f 72 20 62 6f 74 68 20 61 ┆errupt or TX-interrupt or both a┆
0xad00…ad20 72 65 20 6d 69 73 73 69 6e 67 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆re missing. !----------------┆
0xad20…ad40 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xad40…ad60 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a ┆-----------------------------! ┆
0xad60…ad80 21 20 20 20 20 31 39 20 20 20 21 20 38 32 37 33 20 63 68 43 20 74 65 73 74 3a 20 64 61 74 61 20 ┆! 19 ! 8273 chC test: data ┆
0xad80…ada0 65 72 72 6f 72 09 09 09 09 09 09 09 09 09 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆error ! !-----------┆
0xada0…adc0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xade0…ae00 2d 2d 21 0d 0a 0d 0a 54 68 65 20 64 61 74 61 20 74 72 61 6e 73 6d 69 74 74 65 64 20 76 69 61 20 ┆--! The data transmitted via ┆
0xae00…ae20 (87,) 74 68 65 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 20 69 6e 20 66 75 6c 6c 20 64 75 70 6c ┆the loop back cable in full dupl┆
0xae20…ae40 65 78 20 6d 6f 64 65 20 77 61 73 20 6e 6f 74 20 72 65 63 65 69 2d 0d 0a 76 65 64 20 70 72 6f 70 ┆ex mode was not recei- ved prop┆
0xae40…ae60 65 72 6c 79 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆erly. !----------------------┆
0xae60…ae80 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xae80…aea0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 32 ┆-----------------------! ! 2┆
0xaea0…aec0 30 20 20 20 21 20 38 32 37 34 20 63 68 41 20 74 65 73 74 3a 20 64 61 74 61 20 65 72 72 6f 72 09 ┆0 ! 8274 chA test: data error ┆
0xaec0…aee0 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !-----------------┆
0xaee0…af00 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xaf00…af20 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d ┆----------------------------! ┆
0xaf20…af40 0a 54 68 65 20 64 61 74 61 20 74 72 61 6e 73 6d 69 74 74 65 64 20 69 6e 20 66 75 6c 6c 20 64 75 ┆ The data transmitted in full du┆
0xaf40…af60 70 6c 65 78 20 6d 6f 64 65 20 77 61 73 20 6e 6f 74 20 72 65 63 65 69 76 65 64 20 70 72 6f 70 65 ┆plex mode was not received prope┆
0xaf60…af80 72 6c 79 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆rly. !-----------------------┆
0xaf80…afa0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xafa0…afc0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 32 31 ┆----------------------! ! 21┆
0xafc0…afe0 20 20 20 21 20 38 32 37 34 20 63 68 41 20 74 65 73 74 3a 20 74 69 6d 65 6f 75 74 09 09 09 09 09 ┆ ! 8274 chA test: timeout ┆
0xafe0…b000 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !---------------------┆
0xb000…b020 (88,) 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xb020…b03b 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a ┆------------------------! ┆
0xb03b…b03e FormFeed {
0xb03b…b03e 0c 83 86 ┆ ┆
0xb03b…b03e }
0xb03e…b040 0a 54 ┆ T┆
0xb040…b060 68 65 20 38 32 37 34 20 48 44 4c 43 2f 4d 50 53 43 20 63 68 69 70 20 64 69 64 20 6e 6f 74 20 67 ┆he 8274 HDLC/MPSC chip did not g┆
0xb060…b080 65 74 20 72 65 61 64 79 20 66 6f 72 20 64 61 74 61 20 77 69 74 68 69 6e 20 61 70 70 2e 20 35 20 ┆et ready for data within app. 5 ┆
0xb080…b0a0 6d 69 6c 6c 69 73 65 63 6f 6e 64 73 20 28 0d 0a 70 6f 6c 6c 65 64 20 74 72 61 6e 73 6d 69 74 29 ┆milliseconds ( polled transmit)┆
0xb0a0…b0c0 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆. !--------------------------┆
0xb0c0…b0e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xb0e0…b100 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 32 32 20 20 20 ┆-------------------! ! 22 ┆
0xb100…b120 21 20 38 32 37 34 20 63 68 41 20 74 65 73 74 3a 20 74 72 61 6e 73 66 65 72 20 65 72 72 6f 72 20 ┆! 8274 chA test: transfer error ┆
0xb120…b140 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !-----------------┆
0xb140…b160 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xb160…b180 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d ┆----------------------------! ┆
0xb180…b1a0 0a 49 6c 6c 65 67 61 6c 20 69 6e 74 65 72 72 75 70 74 20 63 6f 6e 64 69 74 69 6f 6e 20 68 61 73 ┆ Illegal interrupt condition has┆
0xb1a0…b1c0 20 61 72 69 73 65 64 20 64 75 72 69 6e 67 20 74 68 65 20 64 61 74 61 20 74 72 61 6e 73 66 65 72 ┆ arised during the data transfer┆
0xb1c0…b1e0 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆. !--------------------------┆
0xb1e0…b200 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xb200…b220 (89,) 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 32 33 20 20 20 ┆-------------------! ! 23 ┆
0xb220…b240 21 20 38 32 37 34 20 63 68 41 20 74 65 73 74 3a 20 6d 69 73 73 69 6e 67 20 69 6e 74 65 72 72 75 ┆! 8274 chA test: missing interru┆
0xb240…b260 70 74 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆pt ! !----------------┆
0xb260…b280 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xb280…b2a0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a ┆-----------------------------! ┆
0xb2a0…b2c0 0d 0a 4e 6f 20 38 32 37 34 20 48 44 4c 43 2f 4d 50 53 43 20 63 68 69 70 20 69 6e 74 65 72 72 75 ┆ No 8274 HDLC/MPSC chip interru┆
0xb2c0…b2e0 70 74 20 77 61 73 20 67 65 6e 65 72 61 74 65 64 20 6f 72 20 73 65 72 76 69 63 65 64 2e 0d 0a 0d ┆pt was generated or serviced. ┆
0xb2e0…b300 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ !------------------------------┆
0xb300…b320 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xb320…b340 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 32 34 20 20 20 21 20 38 32 ┆---------------! ! 24 ! 82┆
0xb340…b360 37 34 20 63 68 42 20 74 65 73 74 3a 20 64 61 74 61 20 65 72 72 6f 72 09 09 09 09 09 09 09 09 20 ┆74 chB test: data error ┆
0xb360…b380 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! !-------------------------┆
0xb380…b3a0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xb3a0…b3c0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 54 68 65 20 64 61 74 ┆--------------------! The dat┆
0xb3c0…b3e0 61 20 74 72 61 6e 73 6d 69 74 74 65 64 20 76 69 61 20 74 68 65 20 6c 6f 6f 70 20 62 61 63 6b 20 ┆a transmitted via the loop back ┆
0xb3e0…b400 63 61 62 6c 65 20 69 6e 20 66 75 6c 6c 20 64 75 70 6c 65 78 20 6d 6f 64 65 20 77 61 73 20 6e 6f ┆cable in full duplex mode was no┆
0xb400…b420 (90,) 74 20 0a 72 65 63 65 69 76 65 64 20 70 72 6f 70 65 72 6c 79 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d ┆t received properly. !------┆
0xb420…b440 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xb460…b480 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 32 35 20 20 20 21 20 38 32 37 34 20 63 68 42 20 74 ┆-------! ! 25 ! 8274 chB t┆
0xb480…b4a0 65 73 74 3a 20 74 69 6d 65 6f 75 74 09 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d ┆est: timeout ! !----┆
0xb4a0…b4c0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xb4e0…b500 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 54 68 65 20 38 32 37 34 20 48 44 4c 43 2f 4d 50 53 43 ┆---------! The 8274 HDLC/MPSC┆
0xb500…b520 20 63 68 69 70 20 64 69 64 20 6e 6f 74 20 67 65 74 20 72 65 61 64 79 20 66 6f 72 20 64 61 74 61 ┆ chip did not get ready for data┆
0xb520…b540 20 77 69 74 68 69 6e 20 61 70 70 2e 20 35 20 6d 69 6c 6c 69 73 65 63 6f 6e 64 73 20 28 0d 0a 70 ┆ within app. 5 milliseconds ( p┆
0xb540…b560 6f 6c 6c 65 64 20 74 72 61 6e 73 6d 69 74 29 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆olled transmit). !-----------┆
0xb560…b580 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xb5a0…b5c0 2d 2d 21 0d 0a 21 20 20 20 20 32 36 20 20 20 21 20 38 32 37 34 20 63 68 42 20 74 65 73 74 3a 20 ┆--! ! 26 ! 8274 chB test: ┆
0xb5c0…b5e0 74 72 61 6e 73 66 65 72 20 65 72 72 6f 72 09 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d ┆transfer error ! !---┆
0xb5e0…b600 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xb620…b640 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 49 6c 6c 65 67 61 6c 20 69 6e 74 65 72 72 75 70 74 ┆----------! Illegal interrupt┆
0xb640…b660 20 63 6f 6e 64 69 74 69 6f 6e 20 68 61 73 20 61 72 69 73 65 64 20 64 75 72 69 6e 67 20 74 68 65 ┆ condition has arised during the┆
0xb660…b680 20 64 61 74 61 20 74 72 61 6e 73 66 65 72 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ data transfer. !------------┆
0xb680…b6a0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xb6c0…b6e0 2d 21 0d 0a 21 20 20 20 20 32 37 20 20 20 21 20 38 32 37 34 20 63 68 42 20 74 65 73 74 3a 20 6d ┆-! ! 27 ! 8274 chB test: m┆
0xb6e0…b700 69 73 73 69 6e 67 20 69 6e 74 65 72 72 75 70 74 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d ┆issing interrupt ! !--┆
0xb700…b720 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xb740…b760 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 0d 0a 4e 6f 20 38 32 37 34 20 48 44 4c 43 2f 4d 50 53 ┆-----------! No 8274 HDLC/MPS┆
0xb760…b780 43 20 63 68 69 70 20 69 6e 74 65 72 72 75 70 74 20 77 61 73 20 67 65 6e 65 72 61 74 65 64 20 6f ┆C chip interrupt was generated o┆
0xb780…b7a0 72 20 73 65 72 76 69 63 65 64 2e 0d 0a 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆r serviced. !----------------┆
0xb7a0…b7c0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xb7c0…b7e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a ┆-----------------------------! ┆
0xb7e0…b800 21 20 20 20 20 32 38 20 20 20 21 20 38 32 37 34 20 63 68 42 20 74 65 73 74 3a 20 56 2e 32 34 20 ┆! 28 ! 8274 chB test: V.24 ┆
0xb800…b820 (92,) 73 74 61 74 75 73 20 65 72 72 6f 72 09 09 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d ┆status error ! !------┆
0xb820…b840 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xb860…b86a 2d 2d 2d 2d 2d 2d 2d 21 0d 0a ┆-------! ┆
0xb86a…b86d FormFeed {
0xb86a…b86d 0c 83 b8 ┆ ┆
0xb86a…b86d }
0xb86d…b880 0a 54 68 65 20 56 2e 32 34 20 73 74 61 74 75 73 20 73 69 ┆ The V.24 status si┆
0xb880…b8a0 67 6e 61 6c 73 2c 20 77 68 69 63 68 20 69 73 20 74 6f 67 67 6c 65 64 20 76 69 61 20 74 68 65 20 ┆gnals, which is toggled via the ┆
0xb8a0…b8c0 6c 6f 6f 70 20 62 61 63 6b 20 63 61 62 6c 65 2c 20 66 61 69 6c 73 2e 0d 0a 0d 0a 21 2d 2d 2d 2d ┆loop back cable, fails. !----┆
0xb8c0…b8e0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
[…0x1…]
0xb900…b920 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 32 39 20 20 20 21 20 38 32 37 34 20 63 68 42 ┆---------! ! 29 ! 8274 chB┆
0xb920…b940 20 74 65 73 74 3a 20 58 2e 32 31 20 43 6f 6e 74 72 6f 6c 2d 49 6e 64 69 63 61 74 69 6f 6e 20 65 ┆ test: X.21 Control-Indication e┆
0xb940…b960 72 72 6f 72 09 09 09 09 20 20 20 20 21 0d 0a 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆rror ! !----------------┆
0xb960…b980 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0xb980…b9a0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a ┆-----------------------------! ┆
0xb9a0…b9c0 0d 0a 54 68 65 20 58 2e 32 31 20 73 74 61 74 75 73 20 73 69 67 6e 61 6c 73 2c 20 77 68 69 63 68 ┆ The X.21 status signals, which┆
0xb9c0…b9e0 20 69 73 20 74 6f 67 67 6c 65 64 20 76 69 61 20 74 68 65 20 6c 6f 6f 70 20 62 61 63 6b 20 63 61 ┆ is toggled via the loop back ca┆
0xb9e0…ba00 62 6c 65 2c 20 66 61 69 6c 73 2e 0d 0a 1a 1a 2d 2d 2d 2d 2d 2d 2d 2d 2d 21 0d 0a 21 20 20 20 20 ┆ble, fails. ---------! ! ┆