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DataMuseum.dkPresents historical artifacts from the history of: CP/M |
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Length: 11008 (0x2b00)
Types: RcTekst
Names: »44RT2156.WP«
└─⟦481be0aa0⟧ Bits:30008870 Diskette med 42-I og 44-RT dokumenter
└─⟦this⟧ »44RT2156.WP«
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┆b0┆┆a2┆┆e2┆┆a1┆TABLE OF CONTENTS ┆05┆PAGE↲
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┆b0┆1. GENERAL DESCRIPTION ┆f0┆.................................... 1↲
1.1 Functional Description ............................ 1↲
1.2 CIRC┆f0┆UIT-II Interface ................................ 1↲
1.3 DUAL-CIRCUIT Interface Connector ................... 1↲
2.2 Data Character ..................................... 3↲
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┆b0┆↲
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┆14┆┆b3┆ ┆0b┆↲
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┆b0┆┆a1┆1. GENERAL DESCRIPTION↲
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┆84┆CTA501 is an adapter which makes it possible to upgrade ↓
┆19┆┆89┆┄┄an RC855 with a DUAL-CIRCUIT interface for the purpose ↓
┆19┆┆89┆┄┄of communication with an RC3900 in a character by ↓
┆19┆┆89┆┄┄character protocol.↲
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┆b0┆┆a1┆1.1 Functional Description↲
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┆84┆The CTA501 makes it possible to choose between the LINE ↓
┆19┆┆89┆┄┄1 and CIRCUIT-II. The selection is done by means of the ↓
┆19┆┆89┆┄┄DTRA and RTSA.↲
↲
┆84┆LINE 1 is selected by activating the DTRA for at least ↓
┆19┆┆89┆┄┄25 nsec. before the RTSA, CIRCUIT-II is selected by ↓
┆19┆┆89┆┄┄activating the RTSA at least 20 nsec. before the DTRA.↲
↲
┆84┆Every time the DTRA is activated the selection circuit ↓
┆19┆┆89┆┄┄is triggered. Changes in the RTSA have no triggering ↓
┆19┆┆89┆┄┄effect.↲
↲
┆84┆Every time the CIRCUIT-II is selected an address has to ↓
┆19┆┆89┆┄┄be sent to the CTA501. This is done by sending a ↓
┆19┆┆89┆┄┄character from the MIC-board containing the address bits ↓
┆19┆┆89┆┄┄in the 5 lower bits, but with odd parity. The address is ↓
┆19┆┆89┆┄┄normally the secondary address in the RC855 and can be ↓
┆19┆┆89┆┄┄changed in CONFI.↲
↲
┆84┆Normal communication between the MIC-board and the ↓
┆19┆┆89┆┄┄CTA501 is in even parity, in 9600 baud, with 8 bit data, ↓
┆19┆┆89┆┄┄with 1 parity, and 1 stopbit.↲
↲
┆84┆An internal transformer creates an interface to CIRCUIT ↓
┆19┆┆89┆┄┄II, hereby a polarity check is not required and galvanic ↓
┆19┆┆89┆┄┄isolation is secured.↲
↲
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┆b0┆┆a1┆1.2 CIRCUIT-II Interface↲
↲
┆84┆The CIRCUIT-II is an internal transformer coupled ↓
┆19┆┆89┆┄┄multidrop connection for local data transmission up to a ↓
┆19┆┆89┆┄┄maximum of 1500 meters on a twisted pair, and with a ↓
┆19┆┆89┆┄┄transmission speed of 250 Kbit per second. The CIRCUIT-↓
┆19┆┆89┆┄┄II is one pair of the DUAL-CIRCUIT connection. The other ↓
┆19┆┆89┆┄┄pair is the CIRCUIT-I.↲
↲
┆b0┆┆a1┆↲
┆b0┆┆a1┆1.3 DUAL-CIRCUIT Interface Connector↲
↲
┆84┆Connector: 5 pin round connector, Binder type 680 with ↓
┆19┆┆89┆┄┄screw connection↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆PIN Name↲
1 LINE 0 CIRCUIT-I↲
2 NC↲
3 LINE 1 CIRCUIT-I↲
4 LINE 0 CIRCUIT-II↲
5 LINE 1 CIRCUIT-II↲
↲
┆84┆CTA501 is assembled on a single circuitboard which is ↓
┆19┆┆89┆┄┄mounted on top of the COI503 and electrically connected ↓
┆19┆┆89┆┄┄to it by J7 on the CTA501 and J5 on the COI503. J6 on ↓
┆19┆┆89┆┄┄the CTA501provides the common connection to the MIC ↓
┆19┆┆89┆┄┄board.↲
↲
Power needs : +5V, +12V and -12V↲
Typical power consumption: ????↲
↲
┆84┆The CIRCUIT-II driver is controlled by 7 transmit ↓
┆19┆┆89┆┄┄enable. A logic 1 will force the output in three state, ↓
┆19┆┆89┆┄┄while a logic 0 enables the output. The peak voltage on ↓
┆19┆┆89┆┄┄CRICUIT-II can be adjusted by a single resistor on the ↓
┆19┆┆89┆┄┄CTA501.↲
↲
┆84┆The receiver comprises a comparator with positive feed ↓
┆19┆┆89┆┄┄back and a hystereses of 250 mV symmetric around 2.5 V.↲
↲
┆84┆The characters from CIRCUI-II are demodulated (RXDB) and ↓
┆19┆┆89┆┄┄read into a serial in - parallel out circuit. When a ↓
┆19┆┆89┆┄┄correct address and data are received, the data is ↓
┆19┆┆89┆┄┄loaded into the UART and from there to the MIC-board.↲
↲
┆84┆From the MIC-board the data is received by the UART, ↓
┆19┆┆89┆┄┄then loaded into a parallel in - serial out circuit. ↓
┆19┆┆89┆┄┄When a poll has been received the data is sent via ↓
┆19┆┆89┆┄┄CIRCUIT-II.↲
↲
┆84┆The three PALs PAT050, PAT051, PAT052 together form the ↓
┆19┆┆89┆┄┄controlling circuit in the CTA501. Base on input from ↓
┆19┆┆89┆┄┄CIRCUIT-II and the UART they start transmission via ↓
┆19┆┆89┆┄┄CIRCUIT-II or to the MIC board.↲
↲
┆84┆Timing diagrams are shown in fig. 1, 2, 3 and 4.↲
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Figure 1: ┆84┆Receiving a correct address without a ↓
┆19┆┆93┆┄┄succeeding character.↲
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Figure 2: ┆84┆Receiving a correct address, which will be ↓
┆19┆┆93┆┄┄followed by a character.↲
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Figure 3: ┆84┆Receiving a character after having received a ↓
┆19┆┆93┆┄┄correct address.↲
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Figure 4: Transmitting a character.↲
↲
┆84┆The CTA501 is controlled by a poll from the RC3900. A poll ↓
┆19┆┆89┆┄┄can have two different forms:↲
↲
A) a poll without data from the host.↲
B) a poll followed by data from the host.↲
↲
┆84┆In both cases the CTA501 has to answer the poll. This ↓
┆19┆┆89┆┄┄again can be in two different forms:↲
↲
A) an answer with data from the terminal.↲
B) an answer without data from the terminal.↲
↲
┆84┆A character from the host on the CIRCUIT-II consists of ↓
┆19┆┆89┆┄┄12 bits:↲
↲
┆84┆A start sequence of two 6 usec. logic ones, 8 databits, ↓
┆19┆┆89┆┄┄a paritybit, and a stopbit.↲
↲
┆84┆A poll is always started by an address character which ↓
┆19┆┆89┆┄┄after demodulation in the CTA501, will have the ↓
┆19┆┆89┆┄┄following form:↲
↲
bit ┆a1┆┆e1┆ ┆a1┆1 2 3 4 5 6 7 8 9 10 11↲
↲
value 0 A A A A A X C X P 1↲
↲
┆84┆The 5 A's are the 5 address bits which can address a ↓
┆19┆┆89┆┄┄maximum of 32 terminals.↲
↲
┆84┆A x is a don't care↲
The C is the bit that tells if data is following:↲
┆84┆A logic 1 indicates that data is following. A logic 0 ↓
┆19┆┆89┆┄┄that no data is following.↲
P is the paritybit.↲
↲
════════════════════════════════════════════════════════════════════════
↓
PAL16R4A↲
PAT050.TXT↲
RXCK AND RESET CIRCUIT↲
↲
PALCLK QA QB QC QD QB1 QD1 RXDB OBINIT GND↲
/0E RXCB RXC1 /Q14 /Q3 /Q2 /Q1 Q4 RXC2 VCC↲
↲
/RXC2= /Q14*/RXC1↲
↲
/Q4= QA↲
+QB↲
+QC↲
+QD↲
↲
Q1:= QA*QB*QD*/Q1*/Q2*/Q3↲
↲
Q2:= Q1↲
+OBINIT↲
↲
Q3:= Q2↲
+QB1*QD1*/Q4↲
+RXDB*Q3↲
↲
Q14:= QA*QD*RXC1↲
+Q14*/Q3↲
↲
/RXC1= /RXCB*/Q3↲
↲
PAL16R4A↲
PAT051.TXT↲
↲
PALDLK /EQUAL /PE /Q2 RB6 /Q1 OBINIT /Q3 /Q18 GND↲
/OE Q30 /Q9 /CSC /Q13 /CHRTOR /OKADDR /DS /RTS VCC↲
↲
RTS= OKADDR*/CHRTOR*Q13↲
+OKADDR*CHRTOR*Q1↲
↲
DS= OKADDR*Q1*/PE↲
↲
OKADDR:= EQUAL*PE*Q2↲
+/Q9*OKADDR↲
↲
CHRTOR*= EQUAL*RB6*Q1*/PE↲
+/09*CHRTOR↲
↲
Q13:= Q2↲
↲
CSC:= Q18↲
+OBINIT↲
↲
Q9= CSC↲
+Q3*/EQUAL↲
↲
/Q30= /Q3↲
↲
════════════════════════════════════════════════════════════════════════
↓
PAL26RA8↲
PAT052.TXT↲
↲
PALCLK /RTS QD2 DAV /CSC OBINIT TXDATA PBIT NC GND↲
/OE QD4 PEUART /QD2SNC /DTRB /RTSB /Q10 TXDB /QRD VCC↲
↲
QRD= DAV*PEUART↲
+DTRB↲
↲
/TXDB= DTRB*/TXDATA*/PBIT*/OBINIT↲
+DTRB*/TXDATA*/QD4*/OBINIT↲
↲
Q10:= RTS*/OBINIT↲
+/QD2SNC*Q10*/OBINIT↲
↲
RTSB:= Q10*QD2SNC*/OBINIT↲
+RTSB*/CSC*/OBINIT↲
↲
DTRB:= RTS*DAV*/OBINIT↲
+DTRB*/CSC*/OBINIT↲
↲
QD2SNC:= QD2↲
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↓
↲
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↓
┆b0┆Signal Destination Description↲
↲
/TXCB 2 TX clock↲
↲
LINE 0 J2 Signal to CIRCUIT-II.↲
↲
LINE 1 J2 Signal to CIRCUIT-II.↲
↲
/RXDB 2 RX data from CIRCUIT-II.↲
↲
CLKRST 1 ┆84┆Pulse signal when a shift ↓
┆19┆┆a6┆┄┄occurs on line.↲
↲
/DCDB 1 ┆84┆Signal indicating that a ↓
┆19┆┆a6┆┄┄start sequence has been ↓
┆19┆┆a6┆┄┄detected.↲
↲
PALCK 3 PAL clock 4 MHz↲
↲
RXCB 3 Receiver clock for RXDB.↲
↲
/CTSA J6 V24 signal from COI.↲
↲
RXDA J6 V24 signal from COI.↲
↲
/DSRA J6 V24 signal from COI.↲
↲
/DCDA J6 V24 signal from COI.↲
↲
/CIA J6 V24 signal from COI.↲
↲
TXDA J7 V24 signal from COI.↲
↲
/RTSA J7 V24 signal from COI.↲
↲
/DTRA J7 V24 signal from COI.↲
↲
RXDC 2 ┆84┆Received data from MIC-↓
┆19┆┆a6┆┄┄board.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
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↓
┆b0┆Signal Destination Description↲
↲
TXDC 1 Data to MIC board.↲
↲
RD1 - 8 2 ┆84┆Received data from MIC-↓
┆19┆┆a6┆┄┄board.↲
↲
/RFS 3 ┆84┆A logic 0 indicates that ↓
┆19┆┆a6┆┄┄CTA is ready to receive ↓
┆19┆┆a6┆┄┄data from MIC-board. A ↓
┆19┆┆a6┆┄┄logic 1 indicates that a ↓
┆19┆┆a6┆┄┄chr. is available to be ↓
┆19┆┆a6┆┄┄sent via CIRCUIT-II.↲
↲
RB6 3 ┆84┆This bit is 1 if the ↓
┆19┆┆a6┆┄┄received address is ↓
┆19┆┆a6┆┄┄followed by data.↲
↲
/EQUAL 3 ┆84┆A logic 0 indicates that a ↓
┆19┆┆a6┆┄┄correct address has been ↓
┆19┆┆a6┆┄┄received.↲
↲
QD2 3 ┆84┆Signal used as 13 usec. ↓
┆19┆┆a6┆┄┄delay.↲
↲
PEUART 3 ┆84┆Parity error from MIC-↓
┆19┆┆a6┆┄┄board.↲
↲
TXDATA 3 ┆84┆Serial data from MIC-board.↲
↲
PBIT 3 ┆84┆Parity bit for data for ↓
┆19┆┆a6┆┄┄CIRCUIT-II.↲
↲
/CHR. SENT 3 ┆84┆A logic 0 indicates that a ↓
┆19┆┆a6┆┄┄chr has been sent at ↓
┆19┆┆a6┆┄┄CIRCUIT-II.↲
↲
OBINIT, /OBINIT RESET signals.↲
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┆b0┆Signal Destination Description↲
↲
RXC2 2 ┆84┆RX clock to serial in - ↓
┆19┆┆a6┆┄┄parallel out↲
↲
/Q1,/Q2 ↲
/Q3,/Q30 Clear and reset signals.↲
↲
RCX1 3 ┆84┆RX clock to parity ↓
┆19┆┆a6┆┄┄generation.↲
↲
/RXC1 3 ┆84┆Clock and reset for ↓
┆19┆┆a6┆┄┄counters.↲
↲
/RTS 3 ┆84┆Strobe to start transmis-↓
┆19┆┆a6┆┄┄sion when a correct address ↓
┆19┆┆a6┆┄┄is received and poll is ↓
┆19┆┆a6┆┄┄finished.↲
↲
/DS 3 ┆84┆Data strobe, loads chr. ↓
┆19┆┆a6┆┄┄from CIRCUIT-II into UART.↲
↲
/CSC 2 ┆84┆Chr. sent clear, clear ↓
┆19┆┆a6┆┄┄signal when a chr. has been ↓
┆19┆┆a6┆┄┄sent via CIRCUIT-II.↲
↲
/QRD 2 Reset signal to UART (RDAV)↲
↲
TXDB 1 Transmit data to CIRCUIT-II↲
↲
/Q10 2 ┆84┆Reset signal for 13 usec ↓
┆19┆┆a6┆┄┄timer.↲
↲
/RTSB 1 RTS signal to CIRCUIT-II.↲
↲
/DTRB 1 DTR signal to CIRCUIT-II.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆1a┆┆1a┆when a shift ↓
┆19┆┆a6┆┄┄occurs on line.↲
↲
ransmit ↓
┆19┆┆89┆┄┄enable. A logic 1 will force the output in thr