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DataMuseum.dkPresents historical artifacts from the history of: CP/M |
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Length: 11008 (0x2b00)
Types: RcTekst
Names: »44RT2156.WP«
└─⟦481be0aa0⟧ Bits:30008870 Diskette med 42-I og 44-RT dokumenter
└─⟦this⟧ »44RT2156.WP«
╱04002d4e0a0006000000000201413140000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
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┆b0┆┆a2┆┆e2┆┆a1┆TABLE OF CONTENTS ┆05┆PAGE↲
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┆b0┆1. GENERAL DESCRIPTION ┆f0┆.................................... 1↲
1.1 Functional Description ............................ 1↲
1.2 CIRC┆f0┆UIT-II Interface ................................ 1↲
1.3 DUAL-CIRCUIT Interface Connector ................... 1↲
2.2 Data Character ..................................... 3↲
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┆b0┆↲
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┆14┆┆b3┆ ┆0b┆↲
↲
┆b0┆┆a1┆1. GENERAL DESCRIPTION↲
↲
┆84┆CTA501 is an adapter which makes it possible to upgrade ↓
┆19┆┆89┆┄┄an RC855 with a DUAL-CIRCUIT interface for the purpose ↓
┆19┆┆89┆┄┄of communication with an RC3900 in a character by ↓
┆19┆┆89┆┄┄character protocol.↲
↲
↲
┆b0┆┆a1┆1.1 Functional Description↲
↲
┆84┆The CTA501 makes it possible to choose between the LINE ↓
┆19┆┆89┆┄┄1 and CIRCUIT-II. The selection is done by means of the ↓
┆19┆┆89┆┄┄DTRA and RTSA.↲
↲
┆84┆LINE 1 is selected by activating the DTRA for at least ↓
┆19┆┆89┆┄┄25 nsec. before the RTSA, CIRCUIT-II is selected by ↓
┆19┆┆89┆┄┄activating the RTSA at least 20 nsec. before the DTRA.↲
↲
┆84┆Every time the DTRA is activated the selection circuit ↓
┆19┆┆89┆┄┄is triggered. Changes in the RTSA have no triggering ↓
┆19┆┆89┆┄┄effect.↲
↲
┆84┆Every time the CIRCUIT-II is selected an address has to ↓
┆19┆┆89┆┄┄be sent to the CTA501. This is done by sending a ↓
┆19┆┆89┆┄┄character from the MIC-board containing the address bits ↓
┆19┆┆89┆┄┄in the 5 lower bits, but with odd parity. The address is ↓
┆19┆┆89┆┄┄normally the secondary address in the RC855 and can be ↓
┆19┆┆89┆┄┄changed in CONFI.↲
↲
┆84┆Normal communication between the MIC-board and the ↓
┆19┆┆89┆┄┄CTA501 is in even parity, in 9600 baud, with 8 bit data, ↓
┆19┆┆89┆┄┄with 1 parity, and 1 stopbit.↲
↲
┆84┆An internal transformer creates an interface to CIRCUIT ↓
┆19┆┆89┆┄┄II, hereby a polarity check is not required and galvanic ↓
┆19┆┆89┆┄┄isolation is secured.↲
↲
↲
┆b0┆┆a1┆1.2 CIRCUIT-II Interface↲
↲
┆84┆The CIRCUIT-II is an internal transformer coupled ↓
┆19┆┆89┆┄┄multidrop connection for local data transmission up to a ↓
┆19┆┆89┆┄┄maximum of 1500 meters on a twisted pair, and with a ↓
┆19┆┆89┆┄┄transmission speed of 250 Kbit per second. The CIRCUIT-↓
┆19┆┆89┆┄┄II is one pair of the DUAL-CIRCUIT connection. The other ↓
┆19┆┆89┆┄┄pair is the CIRCUIT-I.↲
↲
┆b0┆┆a1┆↲
┆b0┆┆a1┆1.3 DUAL-CIRCUIT Interface Connector↲
↲
┆84┆Connector: 5 pin round connector, Binder type 680 with ↓
┆19┆┆89┆┄┄screw connection↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆PIN Name↲
1 LINE 0 CIRCUIT-I↲
2 NC↲
3 LINE 1 CIRCUIT-I↲
4 LINE 0 CIRCUIT-II↲
5 LINE 1 CIRCUIT-II↲
↲
┆84┆CTA501 is assembled on a single circuitboard which is ↓
┆19┆┆89┆┄┄mounted on top of the COI503 and electrically connected ↓
┆19┆┆89┆┄┄to it by J7 on the CTA501 and J5 on the COI503. J6 on ↓
┆19┆┆89┆┄┄the CTA501provides the common connection to the MIC ↓
┆19┆┆89┆┄┄board.↲
↲
Power needs : +5V, +12V and -12V↲
Typical power consumption: ????↲
↲
┆84┆The CIRCUIT-II driver is controlled by 7 transmit ↓
┆19┆┆89┆┄┄enable. A logic 1 will force the output in three state, ↓
┆19┆┆89┆┄┄while a logic 0 enables the output. The peak voltage on ↓
┆19┆┆89┆┄┄CRICUIT-II can be adjusted by a single resistor on the ↓
┆19┆┆89┆┄┄CTA501.↲
↲
┆84┆The receiver comprises a comparator with positive feed ↓
┆19┆┆89┆┄┄back and a hystereses of 250 mV symmetric around 2.5 V.↲
↲
┆84┆The characters from CIRCUI-II are demodulated (RXDB) and ↓
┆19┆┆89┆┄┄read into a serial in - parallel out circuit. When a ↓
┆19┆┆89┆┄┄correct address and data are received, the data is ↓
┆19┆┆89┆┄┄loaded into the UART and from there to the MIC-board.↲
↲
┆84┆From the MIC-board the data is received by the UART, ↓
┆19┆┆89┆┄┄then loaded into a parallel in - serial out circuit. ↓
┆19┆┆89┆┄┄When a poll has been received the data is sent via ↓
┆19┆┆89┆┄┄CIRCUIT-II.↲
↲
┆84┆The three PALs PAT050, PAT051, PAT052 together form the ↓
┆19┆┆89┆┄┄controlling circuit in the CTA501. Base on input from ↓
┆19┆┆89┆┄┄CIRCUIT-II and the UART they start transmission via ↓
┆19┆┆89┆┄┄CIRCUIT-II or to the MIC board.↲
↲
┆84┆Timing diagrams are shown in fig. 1, 2, 3 and 4.↲
↲
↲
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↲
↲
Figure 1: ┆84┆Receiving a correct address without a ↓
┆19┆┆93┆┄┄succeeding character.↲
════════════════════════════════════════════════════════════════════════
↓
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↲
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↲
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↲
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Figure 2: ┆84┆Receiving a correct address, which will be ↓
┆19┆┆93┆┄┄followed by a character.↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
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↲
Figure 3: ┆84┆Receiving a character after having received a ↓
┆19┆┆93┆┄┄correct address.↲
════════════════════════════════════════════════════════════════════════
↓
↲
↲
↲
↲
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Figure 4: Transmitting a character.↲
↲
┆84┆The CTA501 is controlled by a poll from the RC3900. A poll ↓
┆19┆┆89┆┄┄can have two different forms:↲
↲
A) a poll without data from the host.↲
B) a poll followed by data from the host.↲
↲
┆84┆In both cases the CTA501 has to answer the poll. This ↓
┆19┆┆89┆┄┄again can be in two different forms:↲
↲
A) an answer with data from the terminal.↲
B) an answer without data from the terminal.↲
↲
┆84┆A character from the host on the CIRCUIT-II consists of ↓
┆19┆┆89┆┄┄12 bits:↲
↲
┆84┆A start sequence of two 6 usec. logic ones, 8 databits, ↓
┆19┆┆89┆┄┄a paritybit, and a stopbit.↲
↲
┆84┆A poll is always started by an address character which ↓
┆19┆┆89┆┄┄after demodulation in the CTA501, will have the ↓
┆19┆┆89┆┄┄following form:↲
↲
bit ┆a1┆┆e1┆ ┆a1┆1 2 3 4 5 6 7 8 9 10 11↲
↲
value 0 A A A A A X C X P 1↲
↲
┆84┆The 5 A's are the 5 address bits which can address a ↓
┆19┆┆89┆┄┄maximum of 32 terminals.↲
↲
┆84┆A x is a don't care↲
The C is the bit that tells if data is following:↲
┆84┆A logic 1 indicates that data is following. A logic 0 ↓
┆19┆┆89┆┄┄that no data is following.↲
P is the paritybit.↲
↲
════════════════════════════════════════════════════════════════════════
↓
PAL16R4A↲
PAT050.TXT↲
RXCK AND RESET CIRCUIT↲
↲
PALCLK QA QB QC QD QB1 QD1 RXDB OBINIT GND↲
/0E RXCB RXC1 /Q14 /Q3 /Q2 /Q1 Q4 RXC2 VCC↲
↲
/RXC2= /Q14*/RXC1↲
↲
/Q4= QA↲
+QB↲
+QC↲
+QD↲
↲
Q1:= QA*QB*QD*/Q1*/Q2*/Q3↲
↲
Q2:= Q1↲
+OBINIT↲
↲
Q3:= Q2↲
+QB1*QD1*/Q4↲
+RXDB*Q3↲
↲
Q14:= QA*QD*RXC1↲
+Q14*/Q3↲
↲
/RXC1= /RXCB*/Q3↲
↲
PAL16R4A↲
PAT051.TXT↲
↲
PALDLK /EQUAL /PE /Q2 RB6 /Q1 OBINIT /Q3 /Q18 GND↲
/OE Q30 /Q9 /CSC /Q13 /CHRTOR /OKADDR /DS /RTS VCC↲
↲
RTS= OKADDR*/CHRTOR*Q13↲
+OKADDR*CHRTOR*Q1↲
↲
DS= OKADDR*Q1*/PE↲
↲
OKADDR:= EQUAL*PE*Q2↲
+/Q9*OKADDR↲
↲
CHRTOR*= EQUAL*RB6*Q1*/PE↲
+/09*CHRTOR↲
↲
Q13:= Q2↲
↲
CSC:= Q18↲
+OBINIT↲
↲
Q9= CSC↲
+Q3*/EQUAL↲
↲
/Q30= /Q3↲
↲
════════════════════════════════════════════════════════════════════════
↓
PAL26RA8↲
PAT052.TXT↲
↲
PALCLK /RTS QD2 DAV /CSC OBINIT TXDATA PBIT NC GND↲
/OE QD4 PEUART /QD2SNC /DTRB /RTSB /Q10 TXDB /QRD VCC↲
↲
QRD= DAV*PEUART↲
+DTRB↲
↲
/TXDB= DTRB*/TXDATA*/PBIT*/OBINIT↲
+DTRB*/TXDATA*/QD4*/OBINIT↲
↲
Q10:= RTS*/OBINIT↲
+/QD2SNC*Q10*/OBINIT↲
↲
RTSB:= Q10*QD2SNC*/OBINIT↲
+RTSB*/CSC*/OBINIT↲
↲
DTRB:= RTS*DAV*/OBINIT↲
+DTRB*/CSC*/OBINIT↲
↲
QD2SNC:= QD2↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆Signal Destination Description↲
↲
/TXCB 2 TX clock↲
↲
LINE 0 J2 Signal to CIRCUIT-II.↲
↲
LINE 1 J2 Signal to CIRCUIT-II.↲
↲
/RXDB 2 RX data from CIRCUIT-II.↲
↲
CLKRST 1 ┆84┆Pulse signal when a shift ↓
┆19┆┆a6┆┄┄occurs on line.↲
↲
/DCDB 1 ┆84┆Signal indicating that a ↓
┆19┆┆a6┆┄┄start sequence has been ↓
┆19┆┆a6┆┄┄detected.↲
↲
PALCK 3 PAL clock 4 MHz↲
↲
RXCB 3 Receiver clock for RXDB.↲
↲
/CTSA J6 V24 signal from COI.↲
↲
RXDA J6 V24 signal from COI.↲
↲
/DSRA J6 V24 signal from COI.↲
↲
/DCDA J6 V24 signal from COI.↲
↲
/CIA J6 V24 signal from COI.↲
↲
TXDA J7 V24 signal from COI.↲
↲
/RTSA J7 V24 signal from COI.↲
↲
/DTRA J7 V24 signal from COI.↲
↲
RXDC 2 ┆84┆Received data from MIC-↓
┆19┆┆a6┆┄┄board.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆Signal Destination Description↲
↲
TXDC 1 Data to MIC board.↲
↲
RD1 - 8 2 ┆84┆Received data from MIC-↓
┆19┆┆a6┆┄┄board.↲
↲
/RFS 3 ┆84┆A logic 0 indicates that ↓
┆19┆┆a6┆┄┄CTA is ready to receive ↓
┆19┆┆a6┆┄┄data from MIC-board. A ↓
┆19┆┆a6┆┄┄logic 1 indicates that a ↓
┆19┆┆a6┆┄┄chr. is available to be ↓
┆19┆┆a6┆┄┄sent via CIRCUIT-II.↲
↲
RB6 3 ┆84┆This bit is 1 if the ↓
┆19┆┆a6┆┄┄received address is ↓
┆19┆┆a6┆┄┄followed by data.↲
↲
/EQUAL 3 ┆84┆A logic 0 indicates that a ↓
┆19┆┆a6┆┄┄correct address has been ↓
┆19┆┆a6┆┄┄received.↲
↲
QD2 3 ┆84┆Signal used as 13 usec. ↓
┆19┆┆a6┆┄┄delay.↲
↲
PEUART 3 ┆84┆Parity error from MIC-↓
┆19┆┆a6┆┄┄board.↲
↲
TXDATA 3 ┆84┆Serial data from MIC-board.↲
↲
PBIT 3 ┆84┆Parity bit for data for ↓
┆19┆┆a6┆┄┄CIRCUIT-II.↲
↲
/CHR. SENT 3 ┆84┆A logic 0 indicates that a ↓
┆19┆┆a6┆┄┄chr has been sent at ↓
┆19┆┆a6┆┄┄CIRCUIT-II.↲
↲
OBINIT, /OBINIT RESET signals.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆Signal Destination Description↲
↲
RXC2 2 ┆84┆RX clock to serial in - ↓
┆19┆┆a6┆┄┄parallel out↲
↲
/Q1,/Q2 ↲
/Q3,/Q30 Clear and reset signals.↲
↲
RCX1 3 ┆84┆RX clock to parity ↓
┆19┆┆a6┆┄┄generation.↲
↲
/RXC1 3 ┆84┆Clock and reset for ↓
┆19┆┆a6┆┄┄counters.↲
↲
/RTS 3 ┆84┆Strobe to start transmis-↓
┆19┆┆a6┆┄┄sion when a correct address ↓
┆19┆┆a6┆┄┄is received and poll is ↓
┆19┆┆a6┆┄┄finished.↲
↲
/DS 3 ┆84┆Data strobe, loads chr. ↓
┆19┆┆a6┆┄┄from CIRCUIT-II into UART.↲
↲
/CSC 2 ┆84┆Chr. sent clear, clear ↓
┆19┆┆a6┆┄┄signal when a chr. has been ↓
┆19┆┆a6┆┄┄sent via CIRCUIT-II.↲
↲
/QRD 2 Reset signal to UART (RDAV)↲
↲
TXDB 1 Transmit data to CIRCUIT-II↲
↲
/Q10 2 ┆84┆Reset signal for 13 usec ↓
┆19┆┆a6┆┄┄timer.↲
↲
/RTSB 1 RTS signal to CIRCUIT-II.↲
↲
/DTRB 1 DTR signal to CIRCUIT-II.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆1a┆┆1a┆when a shift ↓
┆19┆┆a6┆┄┄occurs on line.↲
↲
ransmit ↓
┆19┆┆89┆┄┄enable. A logic 1 will force the output in thr
0x0000…0020 (0,) 00 00 00 00 00 00 00 00 42 03 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4e 00 00 00 ┆ B N ┆
0x0020…0040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
0x0040…0047 00 00 00 00 00 00 00 ┆ ┆
0x0047…0080 Params {
0x0047…0080 04 00 2d 4e 0a 00 06 00 00 00 00 02 01 41 31 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N A1@ ┆
0x0047…0080 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x0047…0080 }
0x0080…00a0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x00a0…00c0 69 0d 0a 0d 0a b0 a2 e2 a1 54 41 42 4c 45 20 4f 46 20 43 4f 4e 54 45 4e 54 53 20 05 50 41 47 45 ┆i TABLE OF CONTENTS PAGE┆
0x00c0…00e0 0d 0a 0d 0a b0 31 2e 20 20 47 45 4e 45 52 41 4c 20 44 45 53 43 52 49 50 54 49 4f 4e 20 f0 2e 2e ┆ 1. GENERAL DESCRIPTION ..┆
0x00e0…0100 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0100…0120 2e 2e 20 20 20 20 31 0d 0a 20 20 20 20 31 2e 31 20 20 46 75 6e 63 74 69 6f 6e 61 6c 20 44 65 73 ┆.. 1 1.1 Functional Des┆
0x0120…0140 63 72 69 70 74 69 6f 6e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆cription .......................┆
0x0140…0160 2e 2e 2e 2e 2e 20 20 20 20 31 0d 0a 20 20 20 20 31 2e 32 20 20 43 49 52 43 f0 55 49 54 2d 49 49 ┆..... 1 1.2 CIRC UIT-II┆
0x0160…0180 20 49 6e 74 65 72 66 61 63 65 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ Interface .....................┆
0x0180…01a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 0d 0a 20 20 20 20 31 2e 33 20 20 44 55 41 4c 2d 43 49 ┆........... 1 1.3 DUAL-CI┆
0x01a0…01c0 52 43 55 49 54 20 49 6e 74 65 72 66 61 63 65 20 43 6f 6e 6e 65 63 74 6f 72 20 2e 2e 2e 2e 2e 2e ┆RCUIT Interface Connector ......┆
0x01c0…01e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 0d 0a 20 20 20 20 32 2e 32 20 20 44 61 74 61 ┆............. 1 2.2 Data┆
0x01e0…0200 20 43 68 61 72 61 63 74 65 72 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ Character .....................┆
0x0200…021b (1,) 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 33 0d 0a 0d 0a b0 0d 0a ┆................ 3 ┆
0x021b…021e FormFeed {
0x021b…021e 0c 80 d8 ┆ ┆
0x021b…021e }
0x021e…0220 0a 20 ┆ ┆
0x0220…0240 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 69 ┆ i┆
0x0240…0245 69 0d 0a 0d 0a ┆i ┆
0x0245…0248 FormFeed {
0x0245…0248 0c 80 90 ┆ ┆
0x0245…0248 }
0x0248…0260 0a 14 b3 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ┆
0x0260…0280 20 20 20 20 20 20 20 20 20 20 20 0b 0d 0a 0d 0a b0 a1 31 2e 20 20 20 20 20 20 20 47 45 4e 45 52 ┆ 1. GENER┆
0x0280…02a0 41 4c 20 44 45 53 43 52 49 50 54 49 4f 4e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 43 54 41 35 ┆AL DESCRIPTION CTA5┆
0x02a0…02c0 30 31 20 69 73 20 61 6e 20 61 64 61 70 74 65 72 20 77 68 69 63 68 20 6d 61 6b 65 73 20 69 74 20 ┆01 is an adapter which makes it ┆
0x02c0…02e0 70 6f 73 73 69 62 6c 65 20 74 6f 20 75 70 67 72 61 64 65 20 0a 19 89 80 80 61 6e 20 52 43 38 35 ┆possible to upgrade an RC85┆
0x02e0…0300 35 20 77 69 74 68 20 61 20 44 55 41 4c 2d 43 49 52 43 55 49 54 20 69 6e 74 65 72 66 61 63 65 20 ┆5 with a DUAL-CIRCUIT interface ┆
0x0300…0320 66 6f 72 20 74 68 65 20 70 75 72 70 6f 73 65 20 0a 19 89 80 80 6f 66 20 63 6f 6d 6d 75 6e 69 63 ┆for the purpose of communic┆
0x0320…0340 61 74 69 6f 6e 20 77 69 74 68 20 61 6e 20 52 43 33 39 30 30 20 69 6e 20 61 20 63 68 61 72 61 63 ┆ation with an RC3900 in a charac┆
0x0340…0360 74 65 72 20 62 79 20 0a 19 89 80 80 63 68 61 72 61 63 74 65 72 20 70 72 6f 74 6f 63 6f 6c 2e 0d ┆ter by character protocol. ┆
0x0360…0380 0a 0d 0a 0d 0a b0 a1 31 2e 31 20 20 20 20 20 20 46 75 6e 63 74 69 6f 6e 61 6c 20 44 65 73 63 72 ┆ 1.1 Functional Descr┆
0x0380…03a0 69 70 74 69 6f 6e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 54 68 65 20 43 54 41 35 30 31 20 6d ┆iption The CTA501 m┆
0x03a0…03c0 61 6b 65 73 20 69 74 20 70 6f 73 73 69 62 6c 65 20 74 6f 20 63 68 6f 6f 73 65 20 62 65 74 77 65 ┆akes it possible to choose betwe┆
0x03c0…03e0 65 6e 20 74 68 65 20 4c 49 4e 45 20 0a 19 89 80 80 31 20 61 6e 64 20 43 49 52 43 55 49 54 2d 49 ┆en the LINE 1 and CIRCUIT-I┆
0x03e0…0400 49 2e 20 54 68 65 20 73 65 6c 65 63 74 69 6f 6e 20 69 73 20 64 6f 6e 65 20 62 79 20 6d 65 61 6e ┆I. The selection is done by mean┆
0x0400…0420 (2,) 73 20 6f 66 20 74 68 65 20 0a 19 89 80 80 44 54 52 41 20 61 6e 64 20 52 54 53 41 2e 0d 0a 0d 0a ┆s of the DTRA and RTSA. ┆
0x0420…0440 20 20 20 20 20 20 20 20 20 84 4c 49 4e 45 20 31 20 69 73 20 73 65 6c 65 63 74 65 64 20 62 79 20 ┆ LINE 1 is selected by ┆
0x0440…0460 61 63 74 69 76 61 74 69 6e 67 20 74 68 65 20 44 54 52 41 20 66 6f 72 20 61 74 20 6c 65 61 73 74 ┆activating the DTRA for at least┆
0x0460…0480 20 0a 19 89 80 80 32 35 20 6e 73 65 63 2e 20 62 65 66 6f 72 65 20 74 68 65 20 52 54 53 41 2c 20 ┆ 25 nsec. before the RTSA, ┆
0x0480…04a0 43 49 52 43 55 49 54 2d 49 49 20 69 73 20 73 65 6c 65 63 74 65 64 20 62 79 20 0a 19 89 80 80 61 ┆CIRCUIT-II is selected by a┆
0x04a0…04c0 63 74 69 76 61 74 69 6e 67 20 74 68 65 20 52 54 53 41 20 61 74 20 6c 65 61 73 74 20 20 32 30 20 ┆ctivating the RTSA at least 20 ┆
0x04c0…04e0 6e 73 65 63 2e 20 62 65 66 6f 72 65 20 74 68 65 20 44 54 52 41 2e 0d 0a 0d 0a 20 20 20 20 20 20 ┆nsec. before the DTRA. ┆
0x04e0…0500 20 20 20 84 45 76 65 72 79 20 74 69 6d 65 20 74 68 65 20 44 54 52 41 20 69 73 20 61 63 74 69 76 ┆ Every time the DTRA is activ┆
0x0500…0520 61 74 65 64 20 74 68 65 20 73 65 6c 65 63 74 69 6f 6e 20 63 69 72 63 75 69 74 20 0a 19 89 80 80 ┆ated the selection circuit ┆
0x0520…0540 69 73 20 74 72 69 67 67 65 72 65 64 2e 20 43 68 61 6e 67 65 73 20 69 6e 20 74 68 65 20 52 54 53 ┆is triggered. Changes in the RTS┆
0x0540…0560 41 20 68 61 76 65 20 6e 6f 20 74 72 69 67 67 65 72 69 6e 67 20 0a 19 89 80 80 65 66 66 65 63 74 ┆A have no triggering effect┆
0x0560…0580 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 45 76 65 72 79 20 74 69 6d 65 20 74 68 65 20 43 49 ┆. Every time the CI┆
0x0580…05a0 52 43 55 49 54 2d 49 49 20 69 73 20 73 65 6c 65 63 74 65 64 20 61 6e 20 61 64 64 72 65 73 73 20 ┆RCUIT-II is selected an address ┆
0x05a0…05c0 68 61 73 20 74 6f 20 0a 19 89 80 80 62 65 20 73 65 6e 74 20 74 6f 20 74 68 65 20 43 54 41 35 30 ┆has to be sent to the CTA50┆
0x05c0…05e0 31 2e 20 54 68 69 73 20 69 73 20 64 6f 6e 65 20 62 79 20 73 65 6e 64 69 6e 67 20 61 20 0a 19 89 ┆1. This is done by sending a ┆
0x05e0…0600 80 80 63 68 61 72 61 63 74 65 72 20 66 72 6f 6d 20 74 68 65 20 4d 49 43 2d 62 6f 61 72 64 20 63 ┆ character from the MIC-board c┆
0x0600…0620 (3,) 6f 6e 74 61 69 6e 69 6e 67 20 74 68 65 20 61 64 64 72 65 73 73 20 62 69 74 73 20 0a 19 89 80 80 ┆ontaining the address bits ┆
0x0620…0640 69 6e 20 74 68 65 20 35 20 6c 6f 77 65 72 20 62 69 74 73 2c 20 62 75 74 20 77 69 74 68 20 6f 64 ┆in the 5 lower bits, but with od┆
0x0640…0660 64 20 70 61 72 69 74 79 2e 20 54 68 65 20 61 64 64 72 65 73 73 20 69 73 20 0a 19 89 80 80 6e 6f ┆d parity. The address is no┆
0x0660…0680 72 6d 61 6c 6c 79 20 74 68 65 20 73 65 63 6f 6e 64 61 72 79 20 61 64 64 72 65 73 73 20 69 6e 20 ┆rmally the secondary address in ┆
0x0680…06a0 74 68 65 20 52 43 38 35 35 20 61 6e 64 20 63 61 6e 20 62 65 20 0a 19 89 80 80 63 68 61 6e 67 65 ┆the RC855 and can be change┆
0x06a0…06c0 64 20 69 6e 20 43 4f 4e 46 49 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 4e 6f 72 6d 61 6c 20 ┆d in CONFI. Normal ┆
0x06c0…06e0 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 20 62 65 74 77 65 65 6e 20 74 68 65 20 4d 49 43 2d 62 6f ┆communication between the MIC-bo┆
0x06e0…0700 61 72 64 20 61 6e 64 20 74 68 65 20 0a 19 89 80 80 43 54 41 35 30 31 20 69 73 20 69 6e 20 65 76 ┆ard and the CTA501 is in ev┆
0x0700…0720 65 6e 20 70 61 72 69 74 79 2c 20 69 6e 20 39 36 30 30 20 62 61 75 64 2c 20 77 69 74 68 20 38 20 ┆en parity, in 9600 baud, with 8 ┆
0x0720…0740 62 69 74 20 64 61 74 61 2c 20 0a 19 89 80 80 77 69 74 68 20 31 20 70 61 72 69 74 79 2c 20 61 6e ┆bit data, with 1 parity, an┆
0x0740…0760 64 20 31 20 73 74 6f 70 62 69 74 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 41 6e 20 69 6e 74 ┆d 1 stopbit. An int┆
0x0760…0780 65 72 6e 61 6c 20 74 72 61 6e 73 66 6f 72 6d 65 72 20 63 72 65 61 74 65 73 20 61 6e 20 69 6e 74 ┆ernal transformer creates an int┆
0x0780…07a0 65 72 66 61 63 65 20 74 6f 20 43 49 52 43 55 49 54 20 0a 19 89 80 80 49 49 2c 20 68 65 72 65 62 ┆erface to CIRCUIT II, hereb┆
0x07a0…07c0 79 20 61 20 70 6f 6c 61 72 69 74 79 20 63 68 65 63 6b 20 69 73 20 6e 6f 74 20 72 65 71 75 69 72 ┆y a polarity check is not requir┆
0x07c0…07e0 65 64 20 61 6e 64 20 67 61 6c 76 61 6e 69 63 20 0a 19 89 80 80 69 73 6f 6c 61 74 69 6f 6e 20 69 ┆ed and galvanic isolation i┆
0x07e0…0800 73 20 73 65 63 75 72 65 64 2e 0d 0a 0d 0a 0d 0a b0 a1 31 2e 32 20 20 20 20 20 20 43 49 52 43 55 ┆s secured. 1.2 CIRCU┆
0x0800…0820 (4,) 49 54 2d 49 49 20 49 6e 74 65 72 66 61 63 65 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 54 68 65 ┆IT-II Interface The┆
0x0820…0840 20 43 49 52 43 55 49 54 2d 49 49 20 69 73 20 61 6e 20 69 6e 74 65 72 6e 61 6c 20 74 72 61 6e 73 ┆ CIRCUIT-II is an internal trans┆
0x0840…0860 66 6f 72 6d 65 72 20 63 6f 75 70 6c 65 64 20 0a 19 89 80 80 6d 75 6c 74 69 64 72 6f 70 20 63 6f ┆former coupled multidrop co┆
0x0860…0880 6e 6e 65 63 74 69 6f 6e 20 66 6f 72 20 6c 6f 63 61 6c 20 64 61 74 61 20 74 72 61 6e 73 6d 69 73 ┆nnection for local data transmis┆
0x0880…08a0 73 69 6f 6e 20 75 70 20 74 6f 20 61 20 0a 19 89 80 80 6d 61 78 69 6d 75 6d 20 6f 66 20 31 35 30 ┆sion up to a maximum of 150┆
0x08a0…08c0 30 20 6d 65 74 65 72 73 20 6f 6e 20 61 20 74 77 69 73 74 65 64 20 70 61 69 72 2c 20 61 6e 64 20 ┆0 meters on a twisted pair, and ┆
0x08c0…08e0 77 69 74 68 20 61 20 0a 19 89 80 80 74 72 61 6e 73 6d 69 73 73 69 6f 6e 20 73 70 65 65 64 20 6f ┆with a transmission speed o┆
0x08e0…0900 66 20 32 35 30 20 4b 62 69 74 20 70 65 72 20 73 65 63 6f 6e 64 2e 20 54 68 65 20 43 49 52 43 55 ┆f 250 Kbit per second. The CIRCU┆
0x0900…0920 49 54 2d 0a 19 89 80 80 49 49 20 69 73 20 6f 6e 65 20 70 61 69 72 20 6f 66 20 74 68 65 20 44 55 ┆IT- II is one pair of the DU┆
0x0920…0940 41 4c 2d 43 49 52 43 55 49 54 20 63 6f 6e 6e 65 63 74 69 6f 6e 2e 20 54 68 65 20 6f 74 68 65 72 ┆AL-CIRCUIT connection. The other┆
0x0940…0960 20 0a 19 89 80 80 70 61 69 72 20 69 73 20 74 68 65 20 43 49 52 43 55 49 54 2d 49 2e 0d 0a 0d 0a ┆ pair is the CIRCUIT-I. ┆
0x0960…0980 b0 a1 0d 0a b0 a1 31 2e 33 20 20 20 20 20 20 44 55 41 4c 2d 43 49 52 43 55 49 54 20 49 6e 74 65 ┆ 1.3 DUAL-CIRCUIT Inte┆
0x0980…09a0 72 66 61 63 65 20 43 6f 6e 6e 65 63 74 6f 72 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 43 6f 6e ┆rface Connector Con┆
0x09a0…09c0 6e 65 63 74 6f 72 3a 20 35 20 70 69 6e 20 72 6f 75 6e 64 20 63 6f 6e 6e 65 63 74 6f 72 2c 20 42 ┆nector: 5 pin round connector, B┆
0x09c0…09e0 69 6e 64 65 72 20 74 79 70 65 20 36 38 30 20 77 69 74 68 20 0a 19 89 80 80 73 63 72 65 77 20 63 ┆inder type 680 with screw c┆
0x09e0…09ed 6f 6e 6e 65 63 74 69 6f 6e 0d 0a 0d 0a ┆onnection ┆
0x09ed…09f0 FormFeed {
0x09ed…09f0 0c 83 b0 ┆ ┆
0x09ed…09f0 }
0x09f0…0a00 0a 20 20 20 20 20 20 20 20 20 b0 50 49 4e 20 20 ┆ PIN ┆
0x0a00…0a20 (5,) 20 20 20 20 20 4e 61 6d 65 0d 0a 20 20 20 20 20 20 20 20 20 20 31 20 20 20 20 20 20 20 20 4c 49 ┆ Name 1 LI┆
0x0a20…0a40 4e 45 20 30 20 43 49 52 43 55 49 54 2d 49 0d 0a 20 20 20 20 20 20 20 20 20 20 32 20 20 20 20 20 ┆NE 0 CIRCUIT-I 2 ┆
0x0a40…0a60 20 20 20 4e 43 0d 0a 20 20 20 20 20 20 20 20 20 20 33 20 20 20 20 20 20 20 20 4c 49 4e 45 20 31 ┆ NC 3 LINE 1┆
0x0a60…0a80 20 43 49 52 43 55 49 54 2d 49 0d 0a 20 20 20 20 20 20 20 20 20 20 34 20 20 20 20 20 20 20 20 4c ┆ CIRCUIT-I 4 L┆
0x0a80…0aa0 49 4e 45 20 30 20 43 49 52 43 55 49 54 2d 49 49 0d 0a 20 20 20 20 20 20 20 20 20 20 35 20 20 20 ┆INE 0 CIRCUIT-II 5 ┆
0x0aa0…0ac0 20 20 20 20 20 4c 49 4e 45 20 31 20 43 49 52 43 55 49 54 2d 49 49 0d 0a 0d 0a 20 20 20 20 20 20 ┆ LINE 1 CIRCUIT-II ┆
0x0ac0…0ae0 20 20 20 84 43 54 41 35 30 31 20 69 73 20 61 73 73 65 6d 62 6c 65 64 20 6f 6e 20 61 20 73 69 6e ┆ CTA501 is assembled on a sin┆
0x0ae0…0b00 67 6c 65 20 63 69 72 63 75 69 74 62 6f 61 72 64 20 77 68 69 63 68 20 69 73 20 0a 19 89 80 80 6d ┆gle circuitboard which is m┆
0x0b00…0b20 6f 75 6e 74 65 64 20 6f 6e 20 74 6f 70 20 6f 66 20 74 68 65 20 43 4f 49 35 30 33 20 61 6e 64 20 ┆ounted on top of the COI503 and ┆
0x0b20…0b40 65 6c 65 63 74 72 69 63 61 6c 6c 79 20 63 6f 6e 6e 65 63 74 65 64 20 0a 19 89 80 80 74 6f 20 69 ┆electrically connected to i┆
0x0b40…0b60 74 20 62 79 20 4a 37 20 6f 6e 20 74 68 65 20 43 54 41 35 30 31 20 61 6e 64 20 4a 35 20 6f 6e 20 ┆t by J7 on the CTA501 and J5 on ┆
0x0b60…0b80 74 68 65 20 43 4f 49 35 30 33 2e 20 4a 36 20 6f 6e 20 0a 19 89 80 80 74 68 65 20 43 54 41 35 30 ┆the COI503. J6 on the CTA50┆
0x0b80…0ba0 31 70 72 6f 76 69 64 65 73 20 74 68 65 20 63 6f 6d 6d 6f 6e 20 63 6f 6e 6e 65 63 74 69 6f 6e 20 ┆1provides the common connection ┆
0x0ba0…0bc0 74 6f 20 74 68 65 20 4d 49 43 20 0a 19 89 80 80 62 6f 61 72 64 2e 0d 0a 0d 0a 20 20 20 20 20 20 ┆to the MIC board. ┆
0x0bc0…0be0 20 20 20 50 6f 77 65 72 20 6e 65 65 64 73 20 3a 20 2b 35 56 2c 20 2b 31 32 56 20 61 6e 64 20 2d ┆ Power needs : +5V, +12V and -┆
0x0be0…0c00 31 32 56 0d 0a 20 20 20 20 20 20 20 20 20 54 79 70 69 63 61 6c 20 70 6f 77 65 72 20 63 6f 6e 73 ┆12V Typical power cons┆
0x0c00…0c20 (6,) 75 6d 70 74 69 6f 6e 3a 20 3f 3f 3f 3f 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 54 68 65 20 43 ┆umption: ???? The C┆
0x0c20…0c40 49 52 43 55 49 54 2d 49 49 20 64 72 69 76 65 72 20 69 73 20 63 6f 6e 74 72 6f 6c 6c 65 64 20 62 ┆IRCUIT-II driver is controlled b┆
0x0c40…0c60 79 20 37 20 74 72 61 6e 73 6d 69 74 20 0a 19 89 80 80 65 6e 61 62 6c 65 2e 20 41 20 6c 6f 67 69 ┆y 7 transmit enable. A logi┆
0x0c60…0c80 63 20 31 20 77 69 6c 6c 20 66 6f 72 63 65 20 74 68 65 20 6f 75 74 70 75 74 20 69 6e 20 74 68 72 ┆c 1 will force the output in thr┆
0x0c80…0ca0 65 65 20 73 74 61 74 65 2c 20 0a 19 89 80 80 77 68 69 6c 65 20 61 20 6c 6f 67 69 63 20 30 20 65 ┆ee state, while a logic 0 e┆
0x0ca0…0cc0 6e 61 62 6c 65 73 20 74 68 65 20 6f 75 74 70 75 74 2e 20 54 68 65 20 70 65 61 6b 20 76 6f 6c 74 ┆nables the output. The peak volt┆
0x0cc0…0ce0 61 67 65 20 6f 6e 20 0a 19 89 80 80 43 52 49 43 55 49 54 2d 49 49 20 63 61 6e 20 62 65 20 61 64 ┆age on CRICUIT-II can be ad┆
0x0ce0…0d00 6a 75 73 74 65 64 20 62 79 20 61 20 73 69 6e 67 6c 65 20 72 65 73 69 73 74 6f 72 20 6f 6e 20 74 ┆justed by a single resistor on t┆
0x0d00…0d20 68 65 20 0a 19 89 80 80 43 54 41 35 30 31 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 54 68 65 ┆he CTA501. The┆
0x0d20…0d40 20 72 65 63 65 69 76 65 72 20 63 6f 6d 70 72 69 73 65 73 20 61 20 63 6f 6d 70 61 72 61 74 6f 72 ┆ receiver comprises a comparator┆
0x0d40…0d60 20 77 69 74 68 20 70 6f 73 69 74 69 76 65 20 66 65 65 64 20 0a 19 89 80 80 62 61 63 6b 20 61 6e ┆ with positive feed back an┆
0x0d60…0d80 64 20 61 20 68 79 73 74 65 72 65 73 65 73 20 6f 66 20 32 35 30 20 6d 56 20 73 79 6d 6d 65 74 72 ┆d a hystereses of 250 mV symmetr┆
0x0d80…0da0 69 63 20 61 72 6f 75 6e 64 20 32 2e 35 20 56 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 54 68 ┆ic around 2.5 V. Th┆
0x0da0…0dc0 65 20 63 68 61 72 61 63 74 65 72 73 20 66 72 6f 6d 20 43 49 52 43 55 49 2d 49 49 20 61 72 65 20 ┆e characters from CIRCUI-II are ┆
0x0dc0…0de0 64 65 6d 6f 64 75 6c 61 74 65 64 20 28 52 58 44 42 29 20 61 6e 64 20 0a 19 89 80 80 72 65 61 64 ┆demodulated (RXDB) and read┆
0x0de0…0e00 20 69 6e 74 6f 20 61 20 73 65 72 69 61 6c 20 69 6e 20 2d 20 70 61 72 61 6c 6c 65 6c 20 6f 75 74 ┆ into a serial in - parallel out┆
0x0e00…0e20 (7,) 20 63 69 72 63 75 69 74 2e 20 57 68 65 6e 20 61 20 0a 19 89 80 80 63 6f 72 72 65 63 74 20 61 64 ┆ circuit. When a correct ad┆
0x0e20…0e40 64 72 65 73 73 20 61 6e 64 20 64 61 74 61 20 61 72 65 20 72 65 63 65 69 76 65 64 2c 20 74 68 65 ┆dress and data are received, the┆
0x0e40…0e60 20 64 61 74 61 20 69 73 20 0a 19 89 80 80 6c 6f 61 64 65 64 20 69 6e 74 6f 20 74 68 65 20 55 41 ┆ data is loaded into the UA┆
0x0e60…0e80 52 54 20 61 6e 64 20 66 72 6f 6d 20 74 68 65 72 65 20 74 6f 20 74 68 65 20 4d 49 43 2d 62 6f 61 ┆RT and from there to the MIC-boa┆
0x0e80…0ea0 72 64 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 46 72 6f 6d 20 74 68 65 20 4d 49 43 2d 62 6f ┆rd. From the MIC-bo┆
0x0ea0…0ec0 61 72 64 20 74 68 65 20 64 61 74 61 20 69 73 20 72 65 63 65 69 76 65 64 20 62 79 20 74 68 65 20 ┆ard the data is received by the ┆
0x0ec0…0ee0 55 41 52 54 2c 20 0a 19 89 80 80 74 68 65 6e 20 6c 6f 61 64 65 64 20 69 6e 74 6f 20 61 20 70 61 ┆UART, then loaded into a pa┆
0x0ee0…0f00 72 61 6c 6c 65 6c 20 69 6e 20 2d 20 73 65 72 69 61 6c 20 6f 75 74 20 63 69 72 63 75 69 74 2e 20 ┆rallel in - serial out circuit. ┆
0x0f00…0f20 0a 19 89 80 80 57 68 65 6e 20 61 20 70 6f 6c 6c 20 68 61 73 20 62 65 65 6e 20 72 65 63 65 69 76 ┆ When a poll has been receiv┆
0x0f20…0f40 65 64 20 74 68 65 20 64 61 74 61 20 69 73 20 73 65 6e 74 20 76 69 61 20 0a 19 89 80 80 43 49 52 ┆ed the data is sent via CIR┆
0x0f40…0f60 43 55 49 54 2d 49 49 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 54 68 65 20 74 68 72 65 65 20 ┆CUIT-II. The three ┆
0x0f60…0f80 50 41 4c 73 20 50 41 54 30 35 30 2c 20 50 41 54 30 35 31 2c 20 50 41 54 30 35 32 20 74 6f 67 65 ┆PALs PAT050, PAT051, PAT052 toge┆
0x0f80…0fa0 74 68 65 72 20 66 6f 72 6d 20 74 68 65 20 0a 19 89 80 80 63 6f 6e 74 72 6f 6c 6c 69 6e 67 20 63 ┆ther form the controlling c┆
0x0fa0…0fc0 69 72 63 75 69 74 20 69 6e 20 74 68 65 20 43 54 41 35 30 31 2e 20 42 61 73 65 20 6f 6e 20 69 6e ┆ircuit in the CTA501. Base on in┆
0x0fc0…0fe0 70 75 74 20 66 72 6f 6d 20 0a 19 89 80 80 43 49 52 43 55 49 54 2d 49 49 20 61 6e 64 20 74 68 65 ┆put from CIRCUIT-II and the┆
0x0fe0…1000 20 55 41 52 54 20 74 68 65 79 20 73 74 61 72 74 20 74 72 61 6e 73 6d 69 73 73 69 6f 6e 20 76 69 ┆ UART they start transmission vi┆
0x1000…1020 (8,) 61 20 0a 19 89 80 80 43 49 52 43 55 49 54 2d 49 49 20 6f 72 20 74 6f 20 74 68 65 20 4d 49 43 20 ┆a CIRCUIT-II or to the MIC ┆
0x1020…1040 62 6f 61 72 64 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 54 69 6d 69 6e 67 20 64 69 61 67 72 ┆board. Timing diagr┆
0x1040…1060 61 6d 73 20 61 72 65 20 73 68 6f 77 6e 20 69 6e 20 66 69 67 2e 20 31 2c 20 32 2c 20 33 20 61 6e ┆ams are shown in fig. 1, 2, 3 an┆
0x1060…1080 64 20 34 2e 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a ┆d 4. ┆
0x1080…10a0 0d 0a 0d 0a 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 46 69 67 75 72 65 20 31 3a 20 84 52 65 63 65 ┆ Figure 1: Rece┆
0x10a0…10c0 69 76 69 6e 67 20 61 20 63 6f 72 72 65 63 74 20 61 64 64 72 65 73 73 20 77 69 74 68 6f 75 74 20 ┆iving a correct address without ┆
0x10c0…10de 61 20 0a 19 93 80 80 73 75 63 63 65 65 64 69 6e 67 20 63 68 61 72 61 63 74 65 72 2e 0d 0a ┆a succeeding character. ┆
0x10de…10e1 FormFeed {
0x10de…10e1 0c 83 e0 ┆ ┆
0x10de…10e1 }
0x10e1…1100 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a ┆ ┆
0x1100…1120 0d 0a 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 46 69 67 75 72 65 20 32 3a 20 84 52 65 63 65 69 76 ┆ Figure 2: Receiv┆
0x1120…1140 69 6e 67 20 61 20 63 6f 72 72 65 63 74 20 61 64 64 72 65 73 73 2c 20 77 68 69 63 68 20 77 69 6c ┆ing a correct address, which wil┆
0x1140…1160 6c 20 62 65 20 0a 19 93 80 80 66 6f 6c 6c 6f 77 65 64 20 62 79 20 61 20 63 68 61 72 61 63 74 65 ┆l be followed by a characte┆
0x1160…1180 72 2e 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a ┆r. ┆
0x1180…11a0 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 46 69 67 75 72 65 20 33 3a 20 84 ┆ Figure 3: ┆
0x11a0…11c0 52 65 63 65 69 76 69 6e 67 20 61 20 63 68 61 72 61 63 74 65 72 20 61 66 74 65 72 20 68 61 76 69 ┆Receiving a character after havi┆
0x11c0…11e0 6e 67 20 72 65 63 65 69 76 65 64 20 61 20 0a 19 93 80 80 63 6f 72 72 65 63 74 20 61 64 64 72 65 ┆ng received a correct addre┆
0x11e0…11e5 73 73 2e 0d 0a ┆ss. ┆
0x11e5…11e8 FormFeed {
0x11e5…11e8 0c 82 d0 ┆ ┆
0x11e5…11e8 }
0x11e8…1200 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d ┆ ┆
0x1200…1220 (9,) 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 46 69 67 75 72 65 ┆ Figure┆
0x1220…1240 20 34 3a 20 54 72 61 6e 73 6d 69 74 74 69 6e 67 20 61 20 63 68 61 72 61 63 74 65 72 2e 0d 0a 0d ┆ 4: Transmitting a character. ┆
0x1240…1260 0a 20 20 20 20 20 20 20 20 20 84 54 68 65 20 43 54 41 35 30 31 20 69 73 20 63 6f 6e 74 72 6f 6c ┆ The CTA501 is control┆
0x1260…1280 6c 65 64 20 62 79 20 61 20 70 6f 6c 6c 20 66 72 6f 6d 20 74 68 65 20 52 43 33 39 30 30 2e 20 41 ┆led by a poll from the RC3900. A┆
0x1280…12a0 20 70 6f 6c 6c 20 0a 19 89 80 80 63 61 6e 20 68 61 76 65 20 74 77 6f 20 64 69 66 66 65 72 65 6e ┆ poll can have two differen┆
0x12a0…12c0 74 20 66 6f 72 6d 73 3a 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 41 29 20 61 20 70 6f 6c 6c 20 77 ┆t forms: A) a poll w┆
0x12c0…12e0 69 74 68 6f 75 74 20 64 61 74 61 20 66 72 6f 6d 20 74 68 65 20 68 6f 73 74 2e 0d 0a 20 20 20 20 ┆ithout data from the host. ┆
0x12e0…1300 20 20 20 20 20 42 29 20 61 20 70 6f 6c 6c 20 66 6f 6c 6c 6f 77 65 64 20 62 79 20 64 61 74 61 20 ┆ B) a poll followed by data ┆
0x1300…1320 66 72 6f 6d 20 74 68 65 20 68 6f 73 74 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 49 6e 20 62 ┆from the host. In b┆
0x1320…1340 6f 74 68 20 63 61 73 65 73 20 74 68 65 20 43 54 41 35 30 31 20 68 61 73 20 74 6f 20 61 6e 73 77 ┆oth cases the CTA501 has to answ┆
0x1340…1360 65 72 20 74 68 65 20 70 6f 6c 6c 2e 20 54 68 69 73 20 0a 19 89 80 80 61 67 61 69 6e 20 63 61 6e ┆er the poll. This again can┆
0x1360…1380 20 62 65 20 69 6e 20 74 77 6f 20 64 69 66 66 65 72 65 6e 74 20 66 6f 72 6d 73 3a 0d 0a 0d 0a 20 ┆ be in two different forms: ┆
0x1380…13a0 20 20 20 20 20 20 20 20 41 29 20 61 6e 20 61 6e 73 77 65 72 20 77 69 74 68 20 64 61 74 61 20 66 ┆ A) an answer with data f┆
0x13a0…13c0 72 6f 6d 20 74 68 65 20 74 65 72 6d 69 6e 61 6c 2e 0d 0a 20 20 20 20 20 20 20 20 20 42 29 20 61 ┆rom the terminal. B) a┆
0x13c0…13e0 6e 20 61 6e 73 77 65 72 20 77 69 74 68 6f 75 74 20 64 61 74 61 20 66 72 6f 6d 20 74 68 65 20 74 ┆n answer without data from the t┆
0x13e0…1400 65 72 6d 69 6e 61 6c 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 41 20 63 68 61 72 61 63 74 65 ┆erminal. A characte┆
0x1400…1420 (10,) 72 20 66 72 6f 6d 20 74 68 65 20 68 6f 73 74 20 6f 6e 20 74 68 65 20 43 49 52 43 55 49 54 2d 49 ┆r from the host on the CIRCUIT-I┆
0x1420…1440 49 20 63 6f 6e 73 69 73 74 73 20 6f 66 20 0a 19 89 80 80 31 32 20 62 69 74 73 3a 0d 0a 0d 0a 20 ┆I consists of 12 bits: ┆
0x1440…1460 20 20 20 20 20 20 20 20 84 41 20 73 74 61 72 74 20 73 65 71 75 65 6e 63 65 20 6f 66 20 74 77 6f ┆ A start sequence of two┆
0x1460…1480 20 36 20 75 73 65 63 2e 20 6c 6f 67 69 63 20 6f 6e 65 73 2c 20 38 20 64 61 74 61 62 69 74 73 2c ┆ 6 usec. logic ones, 8 databits,┆
0x1480…14a0 20 0a 19 89 80 80 61 20 70 61 72 69 74 79 62 69 74 2c 20 61 6e 64 20 61 20 73 74 6f 70 62 69 74 ┆ a paritybit, and a stopbit┆
0x14a0…14c0 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 84 41 20 70 6f 6c 6c 20 69 73 20 61 6c 77 61 79 73 20 ┆. A poll is always ┆
0x14c0…14e0 73 74 61 72 74 65 64 20 62 79 20 61 6e 20 61 64 64 72 65 73 73 20 63 68 61 72 61 63 74 65 72 20 ┆started by an address character ┆
0x14e0…1500 77 68 69 63 68 20 0a 19 89 80 80 61 66 74 65 72 20 64 65 6d 6f 64 75 6c 61 74 69 6f 6e 20 69 6e ┆which after demodulation in┆
0x1500…1520 20 74 68 65 20 43 54 41 35 30 31 2c 20 77 69 6c 6c 20 68 61 76 65 20 74 68 65 20 0a 19 89 80 80 ┆ the CTA501, will have the ┆
0x1520…1540 66 6f 6c 6c 6f 77 69 6e 67 20 66 6f 72 6d 3a 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 62 69 74 20 ┆following form: bit ┆
0x1540…1560 20 a1 e1 20 20 20 20 a1 31 20 20 20 32 20 20 20 33 20 20 20 34 20 20 20 35 20 20 20 36 20 20 20 ┆ 1 2 3 4 5 6 ┆
0x1560…1580 37 20 20 20 38 20 20 20 39 20 20 31 30 20 20 31 31 0d 0a 20 20 20 20 20 20 20 20 20 0d 0a 20 20 ┆7 8 9 10 11 ┆
0x1580…15a0 20 20 20 20 20 20 20 76 61 6c 75 65 20 20 20 20 30 20 20 20 41 20 20 20 41 20 20 20 41 20 20 20 ┆ value 0 A A A ┆
0x15a0…15c0 41 20 20 20 41 20 20 20 58 20 20 20 43 20 20 20 58 20 20 20 50 20 20 20 31 0d 0a 0d 0a 20 20 20 ┆A A X C X P 1 ┆
0x15c0…15e0 20 20 20 20 20 20 84 54 68 65 20 35 20 41 27 73 20 61 72 65 20 74 68 65 20 35 20 61 64 64 72 65 ┆ The 5 A's are the 5 addre┆
0x15e0…1600 73 73 20 62 69 74 73 20 77 68 69 63 68 20 63 61 6e 20 61 64 64 72 65 73 73 20 61 20 0a 19 89 80 ┆ss bits which can address a ┆
0x1600…1620 (11,) 80 6d 61 78 69 6d 75 6d 20 6f 66 20 33 32 20 74 65 72 6d 69 6e 61 6c 73 2e 0d 0a 0d 0a 20 20 20 ┆ maximum of 32 terminals. ┆
0x1620…1640 20 20 20 20 20 20 84 41 20 78 20 69 73 20 61 20 64 6f 6e 27 74 20 63 61 72 65 0d 0a 20 20 20 20 ┆ A x is a don't care ┆
0x1640…1660 20 20 20 20 20 54 68 65 20 43 20 69 73 20 74 68 65 20 62 69 74 20 74 68 61 74 20 74 65 6c 6c 73 ┆ The C is the bit that tells┆
0x1660…1680 20 69 66 20 64 61 74 61 20 69 73 20 66 6f 6c 6c 6f 77 69 6e 67 3a 0d 0a 20 20 20 20 20 20 20 20 ┆ if data is following: ┆
0x1680…16a0 20 84 41 20 6c 6f 67 69 63 20 31 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 64 61 74 61 20 ┆ A logic 1 indicates that data ┆
0x16a0…16c0 69 73 20 66 6f 6c 6c 6f 77 69 6e 67 2e 20 41 20 6c 6f 67 69 63 20 30 20 0a 19 89 80 80 74 68 61 ┆is following. A logic 0 tha┆
0x16c0…16e0 74 20 6e 6f 20 64 61 74 61 20 69 73 20 66 6f 6c 6c 6f 77 69 6e 67 2e 0d 0a 20 20 20 20 20 20 20 ┆t no data is following. ┆
0x16e0…16f9 20 20 50 20 69 73 20 74 68 65 20 70 61 72 69 74 79 62 69 74 2e 0d 0a 0d 0a ┆ P is the paritybit. ┆
0x16f9…16fc FormFeed {
0x16f9…16fc 0c 83 c8 ┆ ┆
0x16f9…16fc }
0x16fc…1700 0a 20 20 20 ┆ ┆
0x1700…1720 20 20 20 20 20 20 50 41 4c 31 36 52 34 41 0d 0a 20 20 20 20 20 20 20 20 20 50 41 54 30 35 30 2e ┆ PAL16R4A PAT050.┆
0x1720…1740 54 58 54 0d 0a 20 20 20 20 20 20 20 20 20 52 58 43 4b 20 41 4e 44 20 52 45 53 45 54 20 43 49 52 ┆TXT RXCK AND RESET CIR┆
0x1740…1760 43 55 49 54 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 50 41 4c 43 4c 4b 20 51 41 20 51 42 20 51 43 ┆CUIT PALCLK QA QB QC┆
0x1760…1780 20 51 44 20 51 42 31 20 51 44 31 20 52 58 44 42 20 4f 42 49 4e 49 54 20 47 4e 44 0d 0a 20 20 20 ┆ QD QB1 QD1 RXDB OBINIT GND ┆
0x1780…17a0 20 20 20 20 20 20 2f 30 45 20 52 58 43 42 20 52 58 43 31 20 2f 51 31 34 20 2f 51 33 20 2f 51 32 ┆ /0E RXCB RXC1 /Q14 /Q3 /Q2┆
0x17a0…17c0 20 2f 51 31 20 51 34 20 52 58 43 32 20 56 43 43 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 52 58 ┆ /Q1 Q4 RXC2 VCC /RX┆
0x17c0…17e0 43 32 3d 20 2f 51 31 34 2a 2f 52 58 43 31 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 51 34 3d 20 ┆C2= /Q14*/RXC1 /Q4= ┆
0x17e0…1800 51 41 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 2b 51 42 0d 0a 20 20 20 20 20 20 20 20 20 20 ┆QA +QB ┆
0x1800…1820 (12,) 20 20 20 2b 51 43 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 2b 51 44 0d 0a 0d 0a 20 20 20 20 ┆ +QC +QD ┆
0x1820…1840 20 20 20 20 20 51 31 3a 3d 20 51 41 2a 51 42 2a 51 44 2a 2f 51 31 2a 2f 51 32 2a 2f 51 33 0d 0a ┆ Q1:= QA*QB*QD*/Q1*/Q2*/Q3 ┆
0x1840…1860 0d 0a 20 20 20 20 20 20 20 20 20 51 32 3a 3d 20 51 31 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 ┆ Q2:= Q1 ┆
0x1860…1880 20 2b 4f 42 49 4e 49 54 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 51 33 3a 3d 20 51 32 0d 0a 20 20 ┆ +OBINIT Q3:= Q2 ┆
0x1880…18a0 20 20 20 20 20 20 20 20 20 20 20 2b 51 42 31 2a 51 44 31 2a 2f 51 34 0d 0a 20 20 20 20 20 20 20 ┆ +QB1*QD1*/Q4 ┆
0x18a0…18c0 20 20 20 20 20 20 2b 52 58 44 42 2a 51 33 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 51 31 34 3a 3d ┆ +RXDB*Q3 Q14:=┆
0x18c0…18e0 20 51 41 2a 51 44 2a 52 58 43 31 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2b 51 31 34 2a ┆ QA*QD*RXC1 +Q14*┆
0x18e0…1900 2f 51 33 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 52 58 43 31 3d 20 2f 52 58 43 42 2a 2f 51 33 ┆/Q3 /RXC1= /RXCB*/Q3┆
0x1900…1920 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 50 41 4c 31 36 52 34 41 0d 0a 20 20 20 20 20 20 20 20 20 ┆ PAL16R4A ┆
0x1920…1940 50 41 54 30 35 31 2e 54 58 54 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 50 41 4c 44 4c 4b 20 2f 45 ┆PAT051.TXT PALDLK /E┆
0x1940…1960 51 55 41 4c 20 2f 50 45 20 2f 51 32 20 52 42 36 20 2f 51 31 20 4f 42 49 4e 49 54 20 2f 51 33 20 ┆QUAL /PE /Q2 RB6 /Q1 OBINIT /Q3 ┆
0x1960…1980 2f 51 31 38 20 47 4e 44 0d 0a 20 20 20 20 20 20 20 20 20 2f 4f 45 20 51 33 30 20 2f 51 39 20 2f ┆/Q18 GND /OE Q30 /Q9 /┆
0x1980…19a0 43 53 43 20 2f 51 31 33 20 2f 43 48 52 54 4f 52 20 2f 4f 4b 41 44 44 52 20 2f 44 53 20 2f 52 54 ┆CSC /Q13 /CHRTOR /OKADDR /DS /RT┆
0x19a0…19c0 53 20 56 43 43 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 52 54 53 3d 20 4f 4b 41 44 44 52 2a 2f 43 ┆S VCC RTS= OKADDR*/C┆
0x19c0…19e0 48 52 54 4f 52 2a 51 31 33 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 2b 4f 4b 41 44 44 52 2a ┆HRTOR*Q13 +OKADDR*┆
0x19e0…1a00 43 48 52 54 4f 52 2a 51 31 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 44 53 3d 20 4f 4b 41 44 44 52 ┆CHRTOR*Q1 DS= OKADDR┆
0x1a00…1a20 (13,) 2a 51 31 2a 2f 50 45 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 4f 4b 41 44 44 52 3a 3d 20 45 51 55 ┆*Q1*/PE OKADDR:= EQU┆
0x1a20…1a40 41 4c 2a 50 45 2a 51 32 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2b 2f 51 39 2a ┆AL*PE*Q2 +/Q9*┆
0x1a40…1a60 4f 4b 41 44 44 52 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 43 48 52 54 4f 52 2a 3d 20 45 51 55 41 ┆OKADDR CHRTOR*= EQUA┆
0x1a60…1a80 4c 2a 52 42 36 2a 51 31 2a 2f 50 45 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2b ┆L*RB6*Q1*/PE +┆
0x1a80…1aa0 2f 30 39 2a 43 48 52 54 4f 52 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 51 31 33 3a 3d 20 51 32 0d ┆/09*CHRTOR Q13:= Q2 ┆
0x1aa0…1ac0 0a 0d 0a 20 20 20 20 20 20 20 20 20 43 53 43 3a 3d 20 51 31 38 0d 0a 20 20 20 20 20 20 20 20 20 ┆ CSC:= Q18 ┆
0x1ac0…1ae0 20 20 20 20 20 2b 4f 42 49 4e 49 54 0d 0a 20 20 0d 0a 20 20 20 20 20 20 20 20 20 51 39 3d 20 43 ┆ +OBINIT Q9= C┆
0x1ae0…1b00 53 43 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 2b 51 33 2a 2f 45 51 55 41 4c 0d 0a 0d 0a 20 20 ┆SC +Q3*/EQUAL ┆
0x1b00…1b14 20 20 20 20 20 20 20 2f 51 33 30 3d 20 2f 51 33 0d 0a 0d 0a ┆ /Q30= /Q3 ┆
0x1b14…1b17 FormFeed {
0x1b14…1b17 0c 83 b8 ┆ ┆
0x1b14…1b17 }
0x1b17…1b20 0a 20 20 20 20 20 20 20 20 ┆ ┆
0x1b20…1b40 20 50 41 4c 32 36 52 41 38 0d 0a 20 20 20 20 20 20 20 20 20 50 41 54 30 35 32 2e 54 58 54 0d 0a ┆ PAL26RA8 PAT052.TXT ┆
0x1b40…1b60 0d 0a 20 20 20 20 20 20 20 20 20 50 41 4c 43 4c 4b 20 2f 52 54 53 20 51 44 32 20 44 41 56 20 2f ┆ PALCLK /RTS QD2 DAV /┆
0x1b60…1b80 43 53 43 20 4f 42 49 4e 49 54 20 54 58 44 41 54 41 20 50 42 49 54 20 4e 43 20 47 4e 44 0d 0a 20 ┆CSC OBINIT TXDATA PBIT NC GND ┆
0x1b80…1ba0 20 20 20 20 20 20 20 20 2f 4f 45 20 51 44 34 20 50 45 55 41 52 54 20 2f 51 44 32 53 4e 43 20 2f ┆ /OE QD4 PEUART /QD2SNC /┆
0x1ba0…1bc0 44 54 52 42 20 2f 52 54 53 42 20 2f 51 31 30 20 54 58 44 42 20 2f 51 52 44 20 56 43 43 0d 0a 0d ┆DTRB /RTSB /Q10 TXDB /QRD VCC ┆
0x1bc0…1be0 0a 20 20 20 20 20 20 20 20 20 51 52 44 3d 20 44 41 56 2a 50 45 55 41 52 54 0d 0a 20 20 20 20 20 ┆ QRD= DAV*PEUART ┆
0x1be0…1c00 20 20 20 20 20 20 20 20 2b 44 54 52 42 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 54 58 44 42 3d ┆ +DTRB /TXDB=┆
0x1c00…1c20 (14,) 20 44 54 52 42 2a 2f 54 58 44 41 54 41 2a 2f 50 42 49 54 2a 2f 4f 42 49 4e 49 54 0d 0a 20 20 20 ┆ DTRB*/TXDATA*/PBIT*/OBINIT ┆
0x1c20…1c40 20 20 20 20 20 20 20 20 20 20 20 20 2b 44 54 52 42 2a 2f 54 58 44 41 54 41 2a 2f 51 44 34 2a 2f ┆ +DTRB*/TXDATA*/QD4*/┆
0x1c40…1c60 4f 42 49 4e 49 54 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 51 31 30 3a 3d 20 52 54 53 2a 2f 4f 42 ┆OBINIT Q10:= RTS*/OB┆
0x1c60…1c80 49 4e 49 54 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2b 2f 51 44 32 53 4e 43 2a 51 31 30 ┆INIT +/QD2SNC*Q10┆
0x1c80…1ca0 2a 2f 4f 42 49 4e 49 54 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 52 54 53 42 3a 3d 20 51 31 30 2a ┆*/OBINIT RTSB:= Q10*┆
0x1ca0…1cc0 51 44 32 53 4e 43 2a 2f 4f 42 49 4e 49 54 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 2b ┆QD2SNC*/OBINIT +┆
0x1cc0…1ce0 52 54 53 42 2a 2f 43 53 43 2a 2f 4f 42 49 4e 49 54 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 44 54 ┆RTSB*/CSC*/OBINIT DT┆
0x1ce0…1d00 52 42 3a 3d 20 52 54 53 2a 44 41 56 2a 2f 4f 42 49 4e 49 54 0d 0a 20 20 20 20 20 20 20 20 20 20 ┆RB:= RTS*DAV*/OBINIT ┆
0x1d00…1d20 20 20 20 20 20 2b 44 54 52 42 2a 2f 43 53 43 2a 2f 4f 42 49 4e 49 54 0d 0a 0d 0a 20 20 20 20 20 ┆ +DTRB*/CSC*/OBINIT ┆
0x1d20…1d32 20 20 20 20 51 44 32 53 4e 43 3a 3d 20 51 44 32 0d 0a ┆ QD2SNC:= QD2 ┆
0x1d32…1d35 FormFeed {
0x1d32…1d35 0c 81 b0 ┆ ┆
0x1d32…1d35 }
0x1d35…1d38 0a 0d 0a ┆ ┆
0x1d38…1d3b FormFeed {
0x1d38…1d3b 0c 80 88 ┆ ┆
0x1d38…1d3b }
0x1d3b…1d40 0a 20 20 20 20 ┆ ┆
0x1d40…1d60 20 20 20 20 20 b0 53 69 67 6e 61 6c 20 20 20 20 20 20 20 20 44 65 73 74 69 6e 61 74 69 6f 6e 20 ┆ Signal Destination ┆
0x1d60…1d80 20 20 20 44 65 73 63 72 69 70 74 69 6f 6e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 54 58 43 42 ┆ Description /TXCB┆
0x1d80…1da0 20 20 20 20 20 20 20 20 20 32 20 20 20 20 20 20 20 20 20 20 20 20 20 20 54 58 20 63 6c 6f 63 6b ┆ 2 TX clock┆
0x1da0…1dc0 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 4c 49 4e 45 20 30 20 20 20 20 20 20 20 20 4a 32 20 20 20 ┆ LINE 0 J2 ┆
0x1dc0…1de0 20 20 20 20 20 20 20 20 20 20 53 69 67 6e 61 6c 20 74 6f 20 43 49 52 43 55 49 54 2d 49 49 2e 0d ┆ Signal to CIRCUIT-II. ┆
0x1de0…1e00 0a 0d 0a 20 20 20 20 20 20 20 20 20 4c 49 4e 45 20 31 20 20 20 20 20 20 20 20 4a 32 20 20 20 20 ┆ LINE 1 J2 ┆
0x1e00…1e20 (15,) 20 20 20 20 20 20 20 20 20 53 69 67 6e 61 6c 20 74 6f 20 43 49 52 43 55 49 54 2d 49 49 2e 0d 0a ┆ Signal to CIRCUIT-II. ┆
0x1e20…1e40 0d 0a 20 20 20 20 20 20 20 20 20 2f 52 58 44 42 20 20 20 20 20 20 20 20 20 32 20 20 20 20 20 20 ┆ /RXDB 2 ┆
0x1e40…1e60 20 20 20 20 20 20 20 20 52 58 20 64 61 74 61 20 66 72 6f 6d 20 43 49 52 43 55 49 54 2d 49 49 2e ┆ RX data from CIRCUIT-II.┆
0x1e60…1e80 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 43 4c 4b 52 53 54 20 20 20 20 20 20 20 20 31 20 20 20 20 ┆ CLKRST 1 ┆
0x1e80…1ea0 20 20 20 20 20 20 20 20 20 20 84 50 75 6c 73 65 20 73 69 67 6e 61 6c 20 77 68 65 6e 20 61 20 73 ┆ Pulse signal when a s┆
0x1ea0…1ec0 68 69 66 74 20 0a 19 a6 80 80 6f 63 63 75 72 73 20 6f 6e 20 6c 69 6e 65 2e 0d 0a 0d 0a 20 20 20 ┆hift occurs on line. ┆
0x1ec0…1ee0 20 20 20 20 20 20 2f 44 43 44 42 20 20 20 20 20 20 20 20 20 31 20 20 20 20 20 20 20 20 20 20 20 ┆ /DCDB 1 ┆
0x1ee0…1f00 20 20 20 84 53 69 67 6e 61 6c 20 69 6e 64 69 63 61 74 69 6e 67 20 74 68 61 74 20 61 20 0a 19 a6 ┆ Signal indicating that a ┆
0x1f00…1f20 80 80 73 74 61 72 74 20 73 65 71 75 65 6e 63 65 20 68 61 73 20 62 65 65 6e 20 0a 19 a6 80 80 64 ┆ start sequence has been d┆
0x1f20…1f40 65 74 65 63 74 65 64 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 50 41 4c 43 4b 20 20 20 20 20 20 ┆etected. PALCK ┆
0x1f40…1f60 20 20 20 33 20 20 20 20 20 20 20 20 20 20 20 20 20 20 50 41 4c 20 63 6c 6f 63 6b 20 34 20 4d 48 ┆ 3 PAL clock 4 MH┆
0x1f60…1f80 7a 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 52 58 43 42 20 20 20 20 20 20 20 20 20 20 33 20 20 20 ┆z RXCB 3 ┆
0x1f80…1fa0 20 20 20 20 20 20 20 20 20 20 20 52 65 63 65 69 76 65 72 20 63 6c 6f 63 6b 20 66 6f 72 20 52 58 ┆ Receiver clock for RX┆
0x1fa0…1fc0 44 42 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 43 54 53 41 20 20 20 20 20 20 20 20 20 4a 36 ┆DB. /CTSA J6┆
0x1fc0…1fe0 20 20 20 20 20 20 20 20 20 20 20 20 20 56 32 34 20 73 69 67 6e 61 6c 20 66 72 6f 6d 20 43 4f 49 ┆ V24 signal from COI┆
0x1fe0…2000 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 52 58 44 41 20 20 20 20 20 20 20 20 20 20 4a 36 20 20 ┆. RXDA J6 ┆
0x2000…2020 (16,) 20 20 20 20 20 20 20 20 20 20 20 56 32 34 20 73 69 67 6e 61 6c 20 66 72 6f 6d 20 43 4f 49 2e 0d ┆ V24 signal from COI. ┆
0x2020…2040 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 44 53 52 41 20 20 20 20 20 20 20 20 20 4a 36 20 20 20 20 ┆ /DSRA J6 ┆
0x2040…2060 20 20 20 20 20 20 20 20 20 56 32 34 20 73 69 67 6e 61 6c 20 66 72 6f 6d 20 43 4f 49 2e 0d 0a 0d ┆ V24 signal from COI. ┆
0x2060…2080 0a 20 20 20 20 20 20 20 20 20 2f 44 43 44 41 20 20 20 20 20 20 20 20 20 4a 36 20 20 20 20 20 20 ┆ /DCDA J6 ┆
0x2080…20a0 20 20 20 20 20 20 20 56 32 34 20 73 69 67 6e 61 6c 20 66 72 6f 6d 20 43 4f 49 2e 0d 0a 0d 0a 20 ┆ V24 signal from COI. ┆
0x20a0…20c0 20 20 20 20 20 20 20 20 2f 43 49 41 20 20 20 20 20 20 20 20 20 20 4a 36 20 20 20 20 20 20 20 20 ┆ /CIA J6 ┆
0x20c0…20e0 20 20 20 20 20 56 32 34 20 73 69 67 6e 61 6c 20 66 72 6f 6d 20 43 4f 49 2e 0d 0a 0d 0a 20 20 20 ┆ V24 signal from COI. ┆
0x20e0…2100 20 20 20 20 20 20 54 58 44 41 20 20 20 20 20 20 20 20 20 20 4a 37 20 20 20 20 20 20 20 20 20 20 ┆ TXDA J7 ┆
0x2100…2120 20 20 20 56 32 34 20 73 69 67 6e 61 6c 20 66 72 6f 6d 20 43 4f 49 2e 0d 0a 0d 0a 20 20 20 20 20 ┆ V24 signal from COI. ┆
0x2120…2140 20 20 20 20 2f 52 54 53 41 20 20 20 20 20 20 20 20 20 4a 37 20 20 20 20 20 20 20 20 20 20 20 20 ┆ /RTSA J7 ┆
0x2140…2160 20 56 32 34 20 73 69 67 6e 61 6c 20 66 72 6f 6d 20 43 4f 49 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 ┆ V24 signal from COI. ┆
0x2160…2180 20 20 2f 44 54 52 41 20 20 20 20 20 20 20 20 20 4a 37 20 20 20 20 20 20 20 20 20 20 20 20 20 56 ┆ /DTRA J7 V┆
0x2180…21a0 32 34 20 73 69 67 6e 61 6c 20 66 72 6f 6d 20 43 4f 49 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 ┆24 signal from COI. ┆
0x21a0…21c0 52 58 44 43 20 20 20 20 20 20 20 20 20 20 32 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 52 65 ┆RXDC 2 Re┆
0x21c0…21e0 63 65 69 76 65 64 20 64 61 74 61 20 66 72 6f 6d 20 4d 49 43 2d 0a 19 a6 80 80 62 6f 61 72 64 2e ┆ceived data from MIC- board.┆
0x21e0…21e4 0d 0a 0d 0a ┆ ┆
0x21e4…21e7 FormFeed {
0x21e4…21e7 0c 82 c0 ┆ ┆
0x21e4…21e7 }
0x21e7…21ea 0a 0d 0a ┆ ┆
0x21ea…21ed FormFeed {
0x21ea…21ed 0c 80 88 ┆ ┆
0x21ea…21ed }
0x21ed…2200 0a 20 20 20 20 20 20 20 20 20 b0 53 69 67 6e 61 6c 20 20 ┆ Signal ┆
0x2200…2220 (17,) 20 20 20 20 20 20 44 65 73 74 69 6e 61 74 69 6f 6e 20 20 20 20 44 65 73 63 72 69 70 74 69 6f 6e ┆ Destination Description┆
0x2220…2240 0d 0a 20 0d 0a 20 20 20 20 20 20 20 20 20 54 58 44 43 20 20 20 20 20 20 20 20 20 20 31 20 20 20 ┆ TXDC 1 ┆
0x2240…2260 20 20 20 20 20 20 20 20 20 20 20 44 61 74 61 20 74 6f 20 4d 49 43 20 62 6f 61 72 64 2e 0d 0a 0d ┆ Data to MIC board. ┆
0x2260…2280 0a 20 20 20 20 20 20 20 20 20 52 44 31 20 2d 20 38 20 20 20 20 20 20 20 32 20 20 20 20 20 20 20 ┆ RD1 - 8 2 ┆
0x2280…22a0 20 20 20 20 20 20 20 84 52 65 63 65 69 76 65 64 20 64 61 74 61 20 66 72 6f 6d 20 4d 49 43 2d 0a ┆ Received data from MIC- ┆
0x22a0…22c0 19 a6 80 80 62 6f 61 72 64 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 52 46 53 20 20 20 20 20 ┆ board. /RFS ┆
0x22c0…22e0 20 20 20 20 20 33 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 41 20 6c 6f 67 69 63 20 30 20 69 ┆ 3 A logic 0 i┆
0x22e0…2300 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 0a 19 a6 80 80 43 54 41 20 69 73 20 72 65 61 64 79 20 ┆ndicates that CTA is ready ┆
0x2300…2320 74 6f 20 72 65 63 65 69 76 65 20 0a 19 a6 80 80 64 61 74 61 20 66 72 6f 6d 20 4d 49 43 2d 62 6f ┆to receive data from MIC-bo┆
0x2320…2340 61 72 64 2e 20 41 20 0a 19 a6 80 80 6c 6f 67 69 63 20 31 20 69 6e 64 69 63 61 74 65 73 20 74 68 ┆ard. A logic 1 indicates th┆
0x2340…2360 61 74 20 61 20 0a 19 a6 80 80 63 68 72 2e 20 69 73 20 61 76 61 69 6c 61 62 6c 65 20 74 6f 20 62 ┆at a chr. is available to b┆
0x2360…2380 65 20 0a 19 a6 80 80 73 65 6e 74 20 76 69 61 20 43 49 52 43 55 49 54 2d 49 49 2e 0d 0a 0d 0a 20 ┆e sent via CIRCUIT-II. ┆
0x2380…23a0 20 20 20 20 20 20 20 20 52 42 36 20 20 20 20 20 20 20 20 20 20 20 33 20 20 20 20 20 20 20 20 20 ┆ RB6 3 ┆
0x23a0…23c0 20 20 20 20 20 84 54 68 69 73 20 62 69 74 20 69 73 20 31 20 69 66 20 74 68 65 20 0a 19 a6 80 80 ┆ This bit is 1 if the ┆
0x23c0…23e0 72 65 63 65 69 76 65 64 20 61 64 64 72 65 73 73 20 69 73 20 0a 19 a6 80 80 66 6f 6c 6c 6f 77 65 ┆received address is followe┆
0x23e0…2400 64 20 62 79 20 64 61 74 61 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 45 51 55 41 4c 20 20 20 ┆d by data. /EQUAL ┆
0x2400…2420 (18,) 20 20 20 20 20 33 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 41 20 6c 6f 67 69 63 20 30 20 69 ┆ 3 A logic 0 i┆
0x2420…2440 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 61 20 0a 19 a6 80 80 63 6f 72 72 65 63 74 20 61 64 64 ┆ndicates that a correct add┆
0x2440…2460 72 65 73 73 20 68 61 73 20 62 65 65 6e 20 0a 19 a6 80 80 72 65 63 65 69 76 65 64 2e 0d 0a 0d 0a ┆ress has been received. ┆
0x2460…2480 20 20 20 20 20 20 20 20 20 51 44 32 20 20 20 20 20 20 20 20 20 20 20 33 20 20 20 20 20 20 20 20 ┆ QD2 3 ┆
0x2480…24a0 20 20 20 20 20 20 84 53 69 67 6e 61 6c 20 75 73 65 64 20 61 73 20 31 33 20 75 73 65 63 2e 20 0a ┆ Signal used as 13 usec. ┆
0x24a0…24c0 19 a6 80 80 64 65 6c 61 79 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 50 45 55 41 52 54 20 20 20 ┆ delay. PEUART ┆
0x24c0…24e0 20 20 20 20 20 33 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 50 61 72 69 74 79 20 65 72 72 6f ┆ 3 Parity erro┆
0x24e0…2500 72 20 66 72 6f 6d 20 4d 49 43 2d 0a 19 a6 80 80 62 6f 61 72 64 2e 0d 0a 0d 0a 20 20 20 20 20 20 ┆r from MIC- board. ┆
0x2500…2520 20 20 20 54 58 44 41 54 41 20 20 20 20 20 20 20 20 33 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ TXDATA 3 ┆
0x2520…2540 84 53 65 72 69 61 6c 20 64 61 74 61 20 66 72 6f 6d 20 4d 49 43 2d 62 6f 61 72 64 2e 0d 0a 0d 0a ┆ Serial data from MIC-board. ┆
0x2540…2560 20 20 20 20 20 20 20 20 20 50 42 49 54 20 20 20 20 20 20 20 20 20 20 33 20 20 20 20 20 20 20 20 ┆ PBIT 3 ┆
0x2560…2580 20 20 20 20 20 20 84 50 61 72 69 74 79 20 62 69 74 20 66 6f 72 20 64 61 74 61 20 66 6f 72 20 0a ┆ Parity bit for data for ┆
0x2580…25a0 19 a6 80 80 43 49 52 43 55 49 54 2d 49 49 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 43 48 52 ┆ CIRCUIT-II. /CHR┆
0x25a0…25c0 2e 20 53 45 4e 54 20 20 20 20 33 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 41 20 6c 6f 67 69 ┆. SENT 3 A logi┆
0x25c0…25e0 63 20 30 20 69 6e 64 69 63 61 74 65 73 20 74 68 61 74 20 61 20 0a 19 a6 80 80 63 68 72 20 68 61 ┆c 0 indicates that a chr ha┆
0x25e0…2600 73 20 62 65 65 6e 20 73 65 6e 74 20 61 74 20 0a 19 a6 80 80 43 49 52 43 55 49 54 2d 49 49 2e 0d ┆s been sent at CIRCUIT-II. ┆
0x2600…2620 (19,) 0a 0d 0a 20 20 20 20 20 20 20 20 20 4f 42 49 4e 49 54 2c 20 2f 4f 42 49 4e 49 54 20 20 20 20 20 ┆ OBINIT, /OBINIT ┆
0x2620…2639 20 20 20 20 20 20 20 20 20 52 45 53 45 54 20 73 69 67 6e 61 6c 73 2e 0d 0a ┆ RESET signals. ┆
0x2639…263c FormFeed {
0x2639…263c 0c 82 b0 ┆ ┆
0x2639…263c }
0x263c…263f 0a 0d 0a ┆ ┆
0x263f…2642 FormFeed {
0x263f…2642 0c 80 88 ┆ ┆
0x263f…2642 }
0x2642…2660 0a 20 20 20 20 20 20 20 20 20 b0 53 69 67 6e 61 6c 20 20 20 20 20 20 20 20 44 65 73 74 69 ┆ Signal Desti┆
0x2660…2680 6e 61 74 69 6f 6e 20 20 20 20 44 65 73 63 72 69 70 74 69 6f 6e 0d 0a 0d 0a 20 20 20 20 20 20 20 ┆nation Description ┆
0x2680…26a0 20 20 52 58 43 32 20 20 20 20 20 20 20 20 20 20 32 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 ┆ RXC2 2 ┆
0x26a0…26c0 52 58 20 63 6c 6f 63 6b 20 74 6f 20 73 65 72 69 61 6c 20 69 6e 20 2d 20 0a 19 a6 80 80 70 61 72 ┆RX clock to serial in - par┆
0x26c0…26e0 61 6c 6c 65 6c 20 6f 75 74 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 51 31 2c 2f 51 32 20 20 20 ┆allel out /Q1,/Q2 ┆
0x26e0…2700 20 20 20 20 0d 0a 20 20 20 20 20 20 20 20 20 2f 51 33 2c 2f 51 33 30 20 20 20 20 20 20 20 20 20 ┆ /Q3,/Q30 ┆
0x2700…2720 20 20 20 20 20 20 20 20 20 20 20 20 43 6c 65 61 72 20 61 6e 64 20 72 65 73 65 74 20 73 69 67 6e ┆ Clear and reset sign┆
0x2720…2740 61 6c 73 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 52 43 58 31 20 20 20 20 20 20 20 20 20 20 33 ┆als. RCX1 3┆
0x2740…2760 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 52 58 20 63 6c 6f 63 6b 20 74 6f 20 70 61 72 69 74 ┆ RX clock to parit┆
0x2760…2780 79 20 0a 19 a6 80 80 67 65 6e 65 72 61 74 69 6f 6e 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f ┆y generation. /┆
0x2780…27a0 52 58 43 31 20 20 20 20 20 20 20 20 20 33 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 43 6c 6f ┆RXC1 3 Clo┆
0x27a0…27c0 63 6b 20 61 6e 64 20 72 65 73 65 74 20 66 6f 72 20 0a 19 a6 80 80 63 6f 75 6e 74 65 72 73 2e 0d ┆ck and reset for counters. ┆
0x27c0…27e0 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 52 54 53 20 20 20 20 20 20 20 20 20 20 33 20 20 20 20 20 ┆ /RTS 3 ┆
0x27e0…2800 20 20 20 20 20 20 20 20 20 84 53 74 72 6f 62 65 20 74 6f 20 73 74 61 72 74 20 74 72 61 6e 73 6d ┆ Strobe to start transm┆
0x2800…2820 (20,) 69 73 2d 0a 19 a6 80 80 73 69 6f 6e 20 77 68 65 6e 20 61 20 63 6f 72 72 65 63 74 20 61 64 64 72 ┆is- sion when a correct addr┆
0x2820…2840 65 73 73 20 0a 19 a6 80 80 69 73 20 72 65 63 65 69 76 65 64 20 61 6e 64 20 70 6f 6c 6c 20 69 73 ┆ess is received and poll is┆
0x2840…2860 20 0a 19 a6 80 80 66 69 6e 69 73 68 65 64 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 44 53 20 ┆ finished. /DS ┆
0x2860…2880 20 20 20 20 20 20 20 20 20 20 33 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 44 61 74 61 20 73 ┆ 3 Data s┆
0x2880…28a0 74 72 6f 62 65 2c 20 6c 6f 61 64 73 20 63 68 72 2e 20 0a 19 a6 80 80 66 72 6f 6d 20 43 49 52 43 ┆trobe, loads chr. from CIRC┆
0x28a0…28c0 55 49 54 2d 49 49 20 69 6e 74 6f 20 55 41 52 54 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 43 ┆UIT-II into UART. /C┆
0x28c0…28e0 53 43 20 20 20 20 20 20 20 20 20 20 32 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 43 68 72 2e ┆SC 2 Chr.┆
0x28e0…2900 20 73 65 6e 74 20 63 6c 65 61 72 2c 20 63 6c 65 61 72 20 0a 19 a6 80 80 73 69 67 6e 61 6c 20 77 ┆ sent clear, clear signal w┆
0x2900…2920 68 65 6e 20 61 20 63 68 72 2e 20 68 61 73 20 62 65 65 6e 20 0a 19 a6 80 80 73 65 6e 74 20 76 69 ┆hen a chr. has been sent vi┆
0x2920…2940 61 20 43 49 52 43 55 49 54 2d 49 49 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 51 52 44 20 20 ┆a CIRCUIT-II. /QRD ┆
0x2940…2960 20 20 20 20 20 20 20 20 32 20 20 20 20 20 20 20 20 20 20 20 20 20 20 52 65 73 65 74 20 73 69 67 ┆ 2 Reset sig┆
0x2960…2980 6e 61 6c 20 74 6f 20 55 41 52 54 20 28 52 44 41 56 29 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 54 ┆nal to UART (RDAV) T┆
0x2980…29a0 58 44 42 20 20 20 20 20 20 20 20 20 20 31 20 20 20 20 20 20 20 20 20 20 20 20 20 20 54 72 61 6e ┆XDB 1 Tran┆
0x29a0…29c0 73 6d 69 74 20 64 61 74 61 20 74 6f 20 43 49 52 43 55 49 54 2d 49 49 0d 0a 0d 0a 20 20 20 20 20 ┆smit data to CIRCUIT-II ┆
0x29c0…29e0 20 20 20 20 2f 51 31 30 20 20 20 20 20 20 20 20 20 20 32 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ /Q10 2 ┆
0x29e0…2a00 20 84 52 65 73 65 74 20 73 69 67 6e 61 6c 20 66 6f 72 20 31 33 20 75 73 65 63 20 0a 19 a6 80 80 ┆ Reset signal for 13 usec ┆
0x2a00…2a20 (21,) 74 69 6d 65 72 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 52 54 53 42 20 20 20 20 20 20 20 20 ┆timer. /RTSB ┆
0x2a20…2a40 20 31 20 20 20 20 20 20 20 20 20 20 20 20 20 20 52 54 53 20 73 69 67 6e 61 6c 20 74 6f 20 43 49 ┆ 1 RTS signal to CI┆
0x2a40…2a60 52 43 55 49 54 2d 49 49 2e 0d 0a 0d 0a 20 20 20 20 20 20 20 20 20 2f 44 54 52 42 20 20 20 20 20 ┆RCUIT-II. /DTRB ┆
0x2a60…2a80 20 20 20 20 31 20 20 20 20 20 20 20 20 20 20 20 20 20 20 44 54 52 20 73 69 67 6e 61 6c 20 74 6f ┆ 1 DTR signal to┆
0x2a80…2a92 20 43 49 52 43 55 49 54 2d 49 49 2e 0d 0a 0d 0a 0d 0a ┆ CIRCUIT-II. ┆
0x2a92…2a95 FormFeed {
0x2a92…2a95 0c 82 b0 ┆ ┆
0x2a92…2a95 }
0x2a95…2aa0 0a 1a 1a 77 68 65 6e 20 61 20 73 ┆ when a s┆
0x2aa0…2ac0 68 69 66 74 20 0a 19 a6 80 80 6f 63 63 75 72 73 20 6f 6e 20 6c 69 6e 65 2e 0d 0a 0d 0a 20 20 20 ┆hift occurs on line. ┆
0x2ac0…2ae0 20 20 20 20 20 72 61 6e 73 6d 69 74 20 0a 19 89 80 80 65 6e 61 62 6c 65 2e 20 41 20 6c 6f 67 69 ┆ ransmit enable. A logi┆
0x2ae0…2b00 63 20 31 20 77 69 6c 6c 20 66 6f 72 63 65 20 74 68 65 20 6f 75 74 70 75 74 20 69 6e 20 74 68 72 ┆c 1 will force the output in thr┆