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Length: 74752 (0x12400)
Types: RcTekst
Names: »99109758.WP«
└─⟦dedaa6eab⟧ Bits:30005866/disk1.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99109758.WP«
╱04002d4e0a0006000000000201413140000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
┆b0┆┆a1┆┆e1┆ i↲
┆a1┆┆b0┆TABLE OF CONTENTS PAGE↲
↲
┆b0┆┆a1┆┆e1┆1. GENERAL INFOR┆f0┆┆b0┆MATION ┆f0┆................................... 1↲
1.1 Introduction ..................................... 1↲
1.2 Specifications ................................... 1↲
1.2.1 Power Requirements ........................ 1↲
1.2.2 Environmental Requirements ................ 1↲
1.2.3 Physical Charac┆f0┆teristics ................. 1↲
1.3 Jumper Configuration ............................. 1↲
1.4 Connector Pin Assignments ........................ 5↲
1.4.1 Multibus Connector P1 ..................... 5↲
1.4.2 Multibus Connector P2 ..................... 6↲
1.4.3 SBX Connector J1 .......................... 7↲
1.4.4 SBX Connector J2 .......................... 7↲
1.4.5 Communication Interface Connector J3 ...... 8↲
1.4.6 Internal Cable KBL551 ..................... 8↲
↲
┆b0┆2. PROGRAMMING INFORMATION ┆f0┆............................... 9↲
2.1 80186 Initialization ............................. 9↲
┆19┆┄┆81┆┄ 2.1.1 Relocation Register ....................... 9↲
2.1.2 Upper Memory Chip Select Register ......... 9↲
2.1.3 Lower Memory Chip Select Register ......... 11↲
2.1.4 Mid-Range Memory Chip Selects ............. 11↲
2.1.5 Peripheral Chip Selects ................... 11↲
2.1.6 Timer 1 ................................... 11↲
2.1.7 Interrupt Controller ...................... 12↲
2.2 CPU602 Address Space ............................. 12↲
2.2.1 EPROM Addressing .......................... 12↲
2.2.2 Dual-Port RAM Addressing .................. 12↲
2.2.3 On Board I/O Addressing ................... 13↲
2.2.4 Multibus Memory Addressing ................ 13↲
2.2.5 Multibus I/O Addressing ................... 13↲
2.2.6 I/O Port Addresses ........................ 13↲
2.3 8255A Parallel I/O Ports ......................... 14↲
2.3.1 8255A Port A .............................. 15↲
2.3.2 8255A Port B .............................. 15↲
2.3.3 8255A Port C .............................. 15↲
2.4 Multibus Interrupt Outputs ....................... 16↲
2.4.1 Set Multibus Interrupt Output ............. 16↲
2.4.2 Clear Multibus Interrupt Output ........... 16↲
↲
┆b0┆3. TECHNICAL DESCRIPTION┆f0┆ ................................. 17↲
3.1 Logic Diagrams and Signal Descriptions ........... 19↲
┆19┆┄┆81┆┄ 3.2 PAL Description .................................. 54↲
3.2.1 PAT007 .................................... 54↲
3.2.2 PAT008 .................................... 55↲
3.2.3 PAT009 .................................... 56↲
3.2.4 PAT010 .................................... 56↲
3.2.5 PAT011 .................................... 57↲
3.2.6 PAT012 .................................... 57↲
3.3 State Diagrams ................................... 58↲
3.3.1 Dual-Port RAM Access Control .............. 58↲
3.3.2 Dual-Port RAM Timing Control .............. 59↲
3.4 Timing Diagrams .................................. 60↲
3.5 Assembly Drawing ................................. 65↲
════════════════════════════════════════════════════════════════════════
↓
ii↲
┆a1┆┆b0┆↲
════════════════════════════════════════════════════════════════════════
↓
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆ ┆0b┆↲
↲
┆b0┆┆a1┆1. GENERAL INFORMATION↲
↲
┆b0┆┆a1┆1.1 Introduction↲
↲
┆84┆The CPU602 is a single board computer with the following ↓
┆19┆┆89┆┄┄major features:↲
↲
┆84┆Multibus board format and compatibility.↲
↲
80186 CPU.↲
↲
10 interrupt levels↲
↲
256 kB dual port RAM.↲
↲
Serial port with V.24 interface.↲
↲
2 SBX connectors for I/O expansion.↲
↲
↲
┆b0┆┆a1┆1.2 Specifications↲
↲
┆b0┆┆a1┆1.2.1 Power Requirements↲
↲
+ 5 VDC ┆a1┆+┆e1┆ 0.25V, 6.4 A max.↲
+12 VDC ┆a1┆+┆e1┆ 0.6 V, 0.05A max.↲
-12 VDC ┆a1┆+┆e1┆ 0.6 V, 0.05A max.↲
↲
↲
┆b0┆┆a1┆1.2.2 Environmental Requirements↲
↲
Operating temperature 0┆81┆o┆82┆C to 50┆81┆o┆82┆C↲
Relative humidity 20% to 80% without condensation.↲
↲
↲
┆b0┆┆a1┆1.2.3 Physical Characteristics↲
↲
Width 179,1 mm (7.05 inches)↲
Length 304,8 mm (12 inches)↲
Component height 10 mm (0.39 inch)↲
Weight 0,5 kg↲
↲
↲
┆b0┆┆a1┆1.3 Jumper Configuration↲
↲
┆84┆┆b0┆┆a1┆JUMPER DESCRIPTION ↲
W1 : 1-2 8289 ANYRQ inp. high↲
2-3 - - - low↲
↲
W2 : 1-2 Multibus CBRQ to 8289 CBRQ↲
2-3 - - - GND↲
↲
W3 : 1-2 8289 BPRO to Multibus BPRO↲
OPEN - - disconnected↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆┆b0┆┆a1┆JUMPER DESCRIPTION ↲
W4 : 1-4 CPU602 BCLK to Multibus BCLK↲
OPEN - - disconnected↲
↲
2-3 CPU602 CCLK to Multibus CCLK↲
OPEN - - disconnected↲
↲
W5 : 1-2 Must be connected↲
↲
W6 : 3-4 256 kB dual-port RAM↲
3-1 512 kB - - -↲
↲
W8 : 1-2 80186 HOLD inp. to GND↲
OPEN - - - open↲
↲
W9 : 1-2 80186 TEST inp. to GND↲
open - - - open↲
↲
W10: 1-2 80186 DRQ1 inp. to SBX J2 MDRQT↲
2-3 - - - - GND↲
↲
W11: 1-2 80186 NMI inp. to GND↲
OPEN - - - open↲
↲
W12: ┆84┆Allows up to 4 on board interrupt ↓
┆19┆┆9b┆┄┄outputs to be connected to any of the ↓
┆19┆┆9b┆┄┄8 Multibus intr. lines↲
↲
1 to 8 Multibus INT0 to INT7 intr. lines↲
↲
9 to 12 Intr. outputs MBINTOUT0 to MBINTOUT3↲
↲
W13: OPEN ┆84┆2764 or 27128 type EPROM's in pos. 55 ↓
┆19┆┆9b┆┄┄and 56↲
1-2 ┆84┆27256 type EPROM's in pos. 55 and 56↲
↲
W14: 1-2 80186 DRQ0 inp. to SBX J1 MDRQT↲
2-3 - - - - GND↲
↲
W15: 1-2 SBX connector J1 configured for 8 bit ↲
W18: 1-2 operation↲
↲
W15: 2-3 SBX connector J1 configured for 16-bit ↲
W18: 2-3 ┆84┆operation. MCS0 active for words and ↓
┆19┆┆9b┆┄┄even bytes. MCS1 active for words and ↓
┆19┆┆9b┆┄┄odd bytes.↲
↲
W16: 1-2 SBX connector J2 configured for 8-bit↲
W17: 1-2 operation↲
↲
W16: 2-3 SBX connector J2 configured for 16-bit↲
W17: 2-3 ┆84┆operation. MCS0 active for words and ↓
┆19┆┆9b┆┄┄even bytes. MCS1 active for words and ↓
┆19┆┆9b┆┄┄odd bytes↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆┆b0┆┆a1┆JUMPER DESCRIPTION ↲
W19: ┆84┆Interrupt jumper matrix. Allows any ↓
┆19┆┆9b┆┄┄interrupt source to be connected to ↓
┆19┆┆9b┆┄┄any interrupt input. Pins 1 to 15 are ↓
┆19┆┆9b┆┄┄interrupt sources, and pins 16 to 25 ↓
┆19┆┆9b┆┄┄are interrupt inputs.↲
↲
1 8251 receiver intr.↲
2 8251 transmitter intr.↲
3 SBX conn. J1 MINTR0 intr.↲
4 - - - MINTR1 -↲
5 - - J2 MINTR0 -↲
6 - - - MINTR1 -↲
7 Multibus INT3 intr.↲
8 - INT2 -↲
9 - INT1 -↲
10 - INT0 -↲
11 - INT4 -↲
12 - INT7 -↲
13 - INT6 -↲
14 - INT5 -↲
15 Slave select for RMX86 compatible↲
interrupt mode.↲
16 80186 INT1 inp.↲
17 - INT3 -↲
18 8259A IR7 inp.↲
19 - IR0 -↲
20 - IR1 -↲
21 - IR2 -↲
22 - IR3 -↲
23 - IR4 -↲
24 - IR5 -↲
25 - IR6 -↲
↲
26 GND↲
↲
┆84┆The W20 and W25 jumper fields defines ↓
┆19┆┆9b┆┄┄the CPU602 Multibus I/O slave address, ↓
┆19┆┆9b┆┄┄used to reset the Multibus intr. ↓
┆19┆┆9b┆┄┄outputs. ↲
A jumper corresponds to addr. bit = 1↲
No jumper corresponds to addr. bit = 0↲
↲
W20: 1-16 Multibus ADRF↲
3-14 - E↲
5-12 - D↲
7-10 - C↲
8-9 - B↲
6-11 - A↲
4-13 - 9↲
2-15 - 8↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆┆b0┆┆a1┆JUMPER DESCRIPTION ↲
W25: 4-5 Multibus ADR7↲
3-6 - 6↲
2-7 - 5↲
1-8 - 4↲
↲
┆84┆The jumpers W21, W22, W23 and W24 are ↓
┆19┆┆9b┆┄┄used to configure the SBX option ↓
┆19┆┆9b┆┄┄signals OPT0 and OPT1 as outputs. With ↓
┆19┆┆9b┆┄┄a jumper inserted the OPT signal is ↓
┆19┆┆9b┆┄┄connected to one of the 8255A port C ↓
┆19┆┆9b┆┄┄outputs.↲
↲
W21: 1-2 SBX conn. J2, OPT1 to 8255A PC3↲
↲
W22: 1-2 - - J2, OPT0 - - PC2↲
↲
W23: 1-2 - - J1, OPT1 - - PC1↲
↲
W24: 1-2 - - J1, OPT0 - - PC0↲
↲
┆84┆The W26 jumper field generates an 8-↓
┆19┆┆9b┆┄┄bit input to the 8255A port A.↲
A jumper = 0↲
No jumper = 1↲
↲
W26: 4-13 PA0↲
3-14 PA1↲
2-15 PA2↲
1-16 PA3↲
8-9 PA4↲
7-10 PA5↲
6-11 PA6↲
5-12 PA7↲
↲
W27: 1-2 8251A receive clock from ext. source↲
2-3 - - - - 80186 timer 1↲
↲
W28: 1-2 8251A transm. clock from ext. source↲
2-3 - - - - 80186 timer 1↲
↲
┆84┆The W29 jumper field defines the ↓
┆19┆┆9b┆┄┄Multibus slave address range for the ↓
┆19┆┆9b┆┄┄CPU602 dual-port RAM. The address ↓
┆19┆┆9b┆┄┄boundaries must correspond to the RAM ↓
┆19┆┆9b┆┄┄size.↲
A jumper corresponds to addr bit = 1↲
No jumper corresponds to addr. bit = 0↲
↲
W29: 6-7 Multibus ADR12↲
5-8 - 13↲
4-9 - 14↲
3-10 - 15↲
2-11 - 16↲
1-12 - 17↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆┆b0┆┆a1┆JUMPER DESCRIPTION ↲
┆84┆The configuration of the W30 strap ↓
┆19┆┆9b┆┄┄field depends on the dual-port RAM ↓
┆19┆┆9b┆┄┄size and the number of Multibus ↓
┆19┆┆9b┆┄┄address bits.↲
C = jumper mounted↲
O = no jumper mounted↲
↲
W30: 1-12 C 256kB 0 512 kB↲
2-11 C RAM C RAM↲
↲
3-10 0 C↲
4-9 0 20-bit C 24-bit↲
5-8 0 address C address↲
6-7 0 C↲
↲
↲
┆b0┆┆a1┆┆b0┆┆a1┆1.4 Connector Pin Assignments↲
┆19┆┄┆81┆┆86┆↲
┆b0┆┆a1┆1.4.1 Multibus Connector P1↲
↲
┆84┆Odd pin numbers : component side of PCB ↲
Even pin numbers: circuit side of PCB ↲
↲
┆b0┆┆a1┆PIN GEN. SIGNAL PIN GEN. SIGNAL↲
1 0V 2 0V ↲
3 +5V 4 +5V ↲
5 +5V 6 +5V ↲
7 +12V 8 +12V↲
9 Unused 10 Unused↲
11 0V 12 0V ↲
13 W4-4 -,BCLK 14 -,INIT↲
15 -,BPRN 16 W3-1 -,BPRO↲
17 1-11 -,BUSY 18 1-7 -,BREQ↲
19 2-7 -,MRDC 20 2-9 -,MWTC↲
21 2-13 -,IORC 22 2-11 -,IOWC↲
23 27-11 -,XACK 24 -,INH1 ↲
25 27-3 -,LOCK 26 Unused ↲
╱04002d4e0a0006000000000201443100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000201413140000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
27 27-5 -,BHEN 28 31-19 -,ADR10↲
29 W2-2 -,CBRQ 30 31-18 11 ↲
31 W4-3 -,CCLK 32 31-17 12 ↲
33 2-14 -,INTA 34 31-16 13 ↲
35 W12-7 -,INT6 36 W12-8 -,INT7 ↲
37 W12-5 4 38 W12-6 5 ↲
39 W12-3 2 40 W12-4 3 ↲
41 W12-1 0 42 W12-2 1 ↲
43 53-13 -,ADRE 44 53-12 -,ADRF ↲
45 53-15 C 46 53-14 D ↲
47 53-17 A 48 53-16 B ↲
49 53-19 8 50 53-18 9 ↲
51 63-13 6 52 63-12 7 ↲
53 63-15 4 54 63-14 5 ↲
55 63-17 2 56 63-16 3 ↲
57 63-19 0 58 63-18 1 ↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a0006000000000201443140000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000201443100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆b0┆┆a1┆PIN GEN. SIGNAL PIN GEN. SIGNAL↲
59 72-13 -,DATE 60 72-12 -,DATF ↲
61 72-15 C 62 72-14 D ↲
63 72-17 A 64 72-16 B ↲
65 72-19 8 66 72-18 9 ↲
67 74-13 6 68 74-12 7 ↲
69 74-15 4 70 74-14 5 ↲
71 74-17 2 72 74-16 3 ↲
73 74-19 0 74 74-18 1 ↲
75 0V 76 0V ↲
77 Unused 78 Unused ↲
79 -12V 80 -12V ↲
81 +5V 82 +5V ↲
83 +5V 84 +5V ↲
85 0V 86 0V ↲
↲
↲
┆b0┆┆a1┆1.4.2 Multibus Connector P2↲
↲
Odd pin numbers : component side of PCB ↲
Even pin numbers: circuit side of PCB ↲
↲
┆a1┆┆b0┆PIN GEN. SIGNAL PIN GEN. SIGNAL↲
1 Unused 2 Unused ↲
3 - 4 - ↲
5 - 6 - ↲
7 - 8 - ↲
9 - 10 - ↲
11 - 12 - ↲
13 - 14 - ↲
15 - 16 - ↲
17 - 18 - ↲
19 - 20 - ↲
21 - 22 - ↲
23 - 24 - ↲
25 - 26 - ↲
27 - 28 - ↲
29 - 30 - ↲
31 - 32 - ↲
33 - 34 - ↲
35 - 36 - ↲
37 - 38 - ↲
39 - 40 - ↲
41 - 42 - ↲
43 - 44 - ↲
45 - 46 - ↲
47 - 48 - ↲
49 - 50 - ↲
51 - 52 - ↲
53 - 54 - ↲
55 31-13 -,ADR16 56 31-12 -,ADR17 ↲
57 31-15 14 58 31-14 15 ↲
59 Unused 60 Unused ↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆1.4.3 SBX Connector J1↲
↲
┆a1┆┆b0┆PIN GEN. SIGNAL PIN GEN. SIGNAL↲
1 +12V 2 -12V ↲
3 0V 4 +5V ↲
5 26-5 RESET 6 26-3 MCLK ↲
7 65-9 MA2 8 -,MPST ↲
9 65-6 1 10 Unused ↲
11 65-5 0 12 MINTR1 ↲
13 16-6 -,IOWRT 14 MINTR0 ↲
15 16-3 -,IORD 16 -,MWAIT ↲
17 Unused 18 Unused ↲
19 77-11 MD7 20 28-6 -,MCS1 ↲
21 77-12 6 22 28-3 -,MCS0 ↲
23 77-13 5 24 Unused ↲
25 77-14 4 26 Unused ↲
27 77-15 3 28 W23-1 OPT1 ↲
29 77-16 2 30 W24-1 OPT0 ↲
31 77-17 1 32 35-31 -,MDACK ↲
33 77-18 0 34 MDRQT ↲
35 0V 36 +5V ↲
↲
37 67-12 MDE 38 67-11 MDF ↲
39 67-14 C 40 67-13 D ↲
41 67-16 A 42 67-15 B ↲
43 67-18 8 44 67-17 9 ↲
↲
↲
┆b0┆┆a1┆1.4.4 SBX Connector J2↲
↲
┆a1┆┆b0┆PIN GEN. SIGNAL PIN GEN. SIGNAL↲
1 +12V 2 -12V ↲
3 0V 4 +5V ↲
5 26-5 RESET 6 26-3 MCLK ↲
7 65-9 MA2 8 -,MPST ↲
9 65-6 1 10 Unused ↲
11 65-5 0 12 MINTR1 ↲
13 16-6 -,IOWRT 14 MINTR0 ↲
15 16-3 -,IORD 16 -,MWAIT ↲
17 Unused 18 Unused ↲
19 77-11 MD7 20 28-11 -,MCS1 ↲
21 77-12 6 22 28-8 -,MCS0 ↲
23 77-13 5 24 Unused ↲
25 77-14 4 26 Unused ↲
27 77-15 3 28 W21-2 OPT1 ↲
29 77-16 2 30 W22-2 OPT0 ↲
31 77-17 1 32 35-32 -,MDACK ↲
33 77-18 0 34 MDRQT ↲
35 0V 36 +5V ↲
↲
37 67-12 MDE 38 67-11 MDF ↲
39 67-14 C 40 67-13 D ↲
41 67-16 A 42 67-15 B ↲
43 67-18 8 44 67-17 9 ↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆1.4.5 Communication Interface Connector J3↲
↲
┆a1┆┆b0┆PIN GEN. SIGNAL PIN GEN. SIGNAL↲
1 0V 2 MRCCL ↲
3 - 4 MTRCL ↲
5 - 6 100-7 TTRCL ↲
7 CALL 8 RLSD ↲
9 0V 10 100-6 DTR ↲
11 - 12 DSR ↲
13 - 14 RFS ↲
15 - 16 110-7 RTS ↲
17 - 18 -,RCD ↲
19 - 20 110-6 -,TRD ↲
↲
↲
┆b0┆┆a1┆1.4.6 Internal Cable KBL551↲
↲
┆84┆KBL551 is an internal cable between connector J3 on the ↓
┆19┆┆89┆┄┄CPU602 PCB and the external standard 25-pin V.24/V.28 ↓
┆19┆┆89┆┄┄connector. ↲
↲
┆b0┆┆a1┆J3 EXT.CONN. SIGNAL ↲
1 GND ↲
2 17 REC. CLOCK, DCE ↲
3 GND ↲
4 15 TRM. CLOCK, DCE ↲
5 GND. ↲
6 24 TRM. CLOCK, DTE ↲
7 22 CALLING INDICATOR ↲
8 8 REC. LINE SIGNAL DET. ↲
9 ↲
10 20 DATA TERM. RDY. ↲
11 ↲
12 6 DATA SET RDY. ↲
13 ↲
14 5 RDY. FOR SENDING ↲
15 ↲
16 4 REQUEST TO SEND ↲
17 GND. ↲
18 3 REC. DATA ↲
19 7 GND. ↲
20 2 TRM. DATA ↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2. PROGRAMMING INFORMATION↲
↲
┆84┆This chapter provides the user with programming information ↓
┆19┆┆89┆┄┄for the CPU602 board. A block diagram with the major ↓
┆19┆┆89┆┄┄components of the CPU602 is shown on figure 3.1. ↓
┆19┆┆89┆┄┄Programming information for the 80186 microprocessor and ↓
┆19┆┆89┆┄┄the standard I/O devices (8251A, 8255A, 8259A) are limited ↓
┆19┆┆89┆┄┄to information depending on the application on the CPU602 ↓
┆19┆┆89┆┄┄board. For a detailed description of these devices the user ↓
┆19┆┆89┆┄┄is referred to the relevant Intel data sheets.↲
↲
↲
┆b0┆┆a1┆┆a1┆2.1 80186 Initialization↲
↲
┆84┆After POWER-UP or RESET the internal registers controlling ↓
┆19┆┆89┆┄┄the integrated peripherals and the chip select logic must ↓
┆19┆┆89┆┄┄be initialized.↲
↲
↲
┆b0┆┆a1┆2.1.1 Relocation Register↲
↲
┆84┆The contents of the relocation register determines the ↓
┆19┆┆89┆┄┄location of the control block (control registers) within ↓
┆19┆┆89┆┄┄the 80186 address space. At RESET the relocation register ↓
┆19┆┆89┆┄┄is set to 20FFH. This causes the control block to start at ↓
┆19┆┆89┆┄┄FF00H in I/O space. The contents of bits 0 to 14 should not ↓
┆19┆┆89┆┄┄be changed. Bit 15 controls the interrupt on ESC function. ↓
┆19┆┆89┆┄┄The relocation register is located in the control block at ↓
┆19┆┆89┆┄┄address FFFEH.↲
↲
↲
┆b0┆┆a1┆2.1.2 Upper Memory Chip Select Register↲
↲
Address: FFAOH↲
↲
┆84┆The contents of the Upper Memory Chip Select Register, ↓
┆19┆┆89┆┄┄UMCS, depends on the size and speed of the installed ↓
┆19┆┆89┆┄┄EPROM's.↲
↲
┆b0┆┆a1┆EPROM ADDRESS RANGE UMCS ↲
2764 FC000 to FFFFF FC3C + W↲
27128 F8000 to FFFFF F83C + W↲
27256 F0000 to FFFFF F03C + W↲
↲
┆84┆W is a number between 0 and 3, which selects the number of ↓
┆19┆┆89┆┄┄wait states inserted when EPROM address space is accessed. ↓
┆19┆┆89┆┄┄No. of wait states = W.↲
↲
┆a1┆8 MHz 80186↲
┆a1┆W CE to OUTPUT DELAY↲
0 max. 280 ns↲
1 max. 400 ns↲
2 max. 530 ns↲
3 max. 650 ns↲
↲
════════════════════════════════════════════════════════════════════════
↓
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↲
Figure 2.1: CPU602 Block Diagram↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆6 MHz 80186↲
┆a1┆W CE to OUTPUT DELAY↲
0 max. 400 ns↲
1 max. 550 ns↲
2 max. 700 ns ↲
3 max. 850 ns↲
↲
┆84┆After RESET the UMCS register is set to an 1 kB address ↓
┆19┆┆89┆┄┄range, FFC00 to FFFFF.↲
↲
↲
┆b0┆┆a1┆2.1.3 Lower Memory Chip Select Register↲
↲
┆84┆The Lower Memory Chip Select, LMCS, output is not used on ↓
┆19┆┆89┆┄┄the CPU602. The LMCS register should not be programmed, ↓
┆19┆┆89┆┄┄corresponding to an inactive chip select. ↲
LMCS register, address: FFA2H↲
↲
↲
┆b0┆┆a1┆2.1.4 Mid-Range Memory Chip Selects↲
↲
┆84┆The Mid-Range Memory Chip Select, MMCS, outputs are not ↓
┆19┆┆89┆┄┄used on the CPU602 board. The MMCS register should not be ↓
┆19┆┆89┆┄┄programmed, corresponding to inactive chip select outputs. ↓
┆19┆┆89┆┄┄MMCS register, address: FFA6H↲
↲
↲
┆b0┆┆a1┆2.1.5 Peripheral Chip Selects↲
↲
┆84┆The peripheral chip selects, PCS0 to PCS6, are controlled ↓
┆19┆┆89┆┄┄by the MPCS register and the PACS register.↲
MPCS register, address: FFA8H↲
PACS register, address: FFA4H ↓
↲
┆84┆These registers should be programmed as shown below:↲
↲
MPCS: 8079H↲
PACS: 0039H↲
↲
┆84┆This places the peripheral chip select addresses in the I/O ↓
┆19┆┆89┆┄┄address space from address 0000 to 03FF. 1 wait state is ↓
┆19┆┆89┆┄┄inserted for each I/O access.↲
↲
┆84┆Section 3.2.6 contains an I/O address list.↲
↲
↲
┆b0┆┆a1┆2.1.6 Timer 1↲
↲
┆84┆The 80186 provides three internal 16-bit programmable ↓
┆19┆┆89┆┄┄timers. One of these timers, timer 1, is used as baud rate ↓
┆19┆┆89┆┄┄generator for the 8251A communication controller. The ↓
┆19┆┆89┆┄┄frequency input to the timer is CPU clock/4 (2MHz for an ↓
┆19┆┆89┆┄┄8MHz CPU clock). The operational mode of the timer is ↓
┆19┆┆89┆┄┄controlled by the mode/control word. ↲
Mode/Control, address: FF5EH, contents: C003H↲
↲
════════════════════════════════════════════════════════════════════════
↓
The baud rate is controlled by the registers: ↓
↲
Max Count A, address: FF5AH↲
Max Count B, address: FF5CH↲
↲
┆84┆When the 8251A is initialized to clock = 16 x baud rate, ↓
┆19┆┆89┆┄┄the contents of the max count A and B registers may be ↓
┆19┆┆89┆┄┄calculated by the equation below.↲
↲
┆84┆Max Count A + Max. Count B = CPU freq./(4x16xbaud rate) ↲
↲
┆84┆The contents of A and B should be selected so that the max. ↓
┆19┆┆89┆┄┄difference is 1 (50% duty cycle).↲
↲
↲
┆b0┆┆a1┆2.1.7 Interrupt Controller↲
↲
┆84┆The 80186 internal interrupt controller should normally be ↓
┆19┆┆89┆┄┄used in the NON-RMX mode of operation. The number of ↓
┆19┆┆89┆┄┄interrupt inputs are expanded by means of an external 8259A ↓
┆19┆┆89┆┄┄slave interrupt controller, which is connected to the INT0 ↓
┆19┆┆89┆┄┄input and the INT2/INTA0 output.↲
↲
↲
┆b0┆┆a1┆2.2 CPU602 Address Space↲
↲
┆84┆The CPU602 address space consists of on-board memory ↓
┆19┆┆89┆┄┄address space (EPROM and dual-port RAM), on-board I/O ↓
┆19┆┆89┆┄┄address space (80186 control block and I/O devices), ↓
┆19┆┆89┆┄┄Multibus memory address space, and Multibus I/O address ↓
┆19┆┆89┆┄┄space.↲
↲
↲
┆b0┆┆a1┆2.2.1 EPROM Addressing↲
↲
┆84┆The EPROM is located at the top of the memory address ↓
┆19┆┆89┆┄┄space. The address range depends on the type of the ↓
┆19┆┆89┆┄┄installed EPROM as described below.↲
↲
┆b0┆┆a1┆EPROM ADDRESS RANGE↲
2764 FC000 to FFFFF↲
27128 F8000 to FFFFF↲
27256 F0000 to FFFFF↲
↲
↲
┆b0┆┆a1┆2.2.2 Dual-Port RAM Addressing↲
↲
┆84┆The dual-port RAM (DPRAM) address space starts at location ↓
┆19┆┆89┆┄┄0, when accessed from the on board 80186.↲
↲
┆b0┆┆a1┆RAM SIZE ADDRESS RANGE↲
256 kB 00000 to 3FFFF↲
512 kB 00000 to 7FFFF↲
↲
┆84┆The address range for Multibus access to the DPRAM is ↓
┆19┆┆89┆┄┄controlled by the jumper fields W29 and W30 as described in ↓
┆19┆┆89┆┄┄section 1.3.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.2.3 On Board I/O Addressing↲
↲
┆84┆The on board I/O addresses are devided into two blocks. One ↓
┆19┆┆89┆┄┄block of addresses for the control block, which controls ↓
┆19┆┆89┆┄┄the 80186 integrated peripherals, and one block of ↓
┆19┆┆89┆┄┄addresses for non integated I/O devices.↲
Control block: FF00 to FFFF↲
I/O devices: 0000 to 03FF↲
↲
↲
┆b0┆┆a1┆2.2.4 Multibus Memory Addressing↲
↲
┆84┆Addresses outside the on board RAM and EPROM address ranges ↓
┆19┆┆89┆┄┄will be accessed via the Multibus. The CPU602 generates a ↓
┆19┆┆89┆┄┄24-bit Multibus address, where the 4 most signifcant bits ↓
┆19┆┆89┆┄┄(bits 14 to 17) are 0. The Multibus access address range ↓
┆19┆┆89┆┄┄depends on the size of the on board RAM and EPROM.↲
↲
┆b0┆┆a1┆RAM EPROM MULTIBUS ADDRESS RANGE ↲
256 kB 16kB 040000 to 0FBFFFF↲
256 kB 32kB 040000 to 0F7FFFF↲
256 kB 64kB 040000 to 0EFFFFF↲
512 kB 16kB 080000 to 0FBFFFF↲
512 kB 32kB 080000 to 0F7FFFF↲
512 kB 64kB 080000 to 0EFFFFF↲
↲
↲
┆b0┆┆a1┆2.2.5 Multibus I/O Addressing↲
↲
┆84┆The following I/O address range provides access to the ↓
┆19┆┆89┆┄┄Multibus.↲
↲
0400 to FBFF↲
↲
↲
┆b0┆┆a1┆2.2.6 I/O Port Addresses↲
↲
┆84┆I/O port addresses are assigned to the non integrated I/O ↓
┆19┆┆89┆┄┄devices as described below.↲
↲
┆b0┆┆a1┆DEVICE ADDRESS FUNCTION ↲
8259A 0000 Wr: ICW1, OCW2, OCW3↲
Rd: Status, Poll↲
↲
- 0002 Wr: ICW2, ICW3, ICW4, OCW1↲
Rd: OCW1↲
↲
8251A 0080 Wr: Data↲
Rd: Data↲
↲
- 0082 Wr: Mode or Command↲
Rd: Status↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆DEVICE ADDRESS FUNCTION ↲
8255A 0100 Rd: Port A input↲
↲
- 0102 Rd: Port B input↲
↲
- 0104 Wr: Port C output↲
Rd: Port C input↲
↲
- 0106 Wr: Control↲
↲
SBX, J1 0190- Rd/Wr: Even byte transfer for both 8-bit↲
019E ┆84┆and 16-bit SBX modules. Word transfer ↓
┆19┆┆9c┆┄┄for 16-bit modules. Activates MCS0.↲
↲
- 0191- Rd/Wr: Odd byte trfansfer for 16-bit↲
019F modules. Activates MCS1.↲
↲
- 01AO- Rd/Wr: Even byte transfer for 8-bit ↲
01AE modules. Activates MCS1.↲
↲
- 0280 Rd: Generates DMA acknowledge, MDACK.↲
↲
SBX, J2 0250- Rd/Wr: Even byte transfer for both 8-bit↲
025E ┆84┆and 16-bit SBX modules. Word transfer ↓
┆19┆┆9c┆┄┄for 16-bit modules. Activates MCS0.↲
↲
- 0251- Rd/Wr: Odd byte transfor for 16-bit ↲
025F modules. Activates MCS1.↲
↲
- 0260- Rd/Wr: Even byte transfer for 8-bit ↲
026E modules. Activates MCS1.↲
↲
- 0300 Rd: Generates DMA acknowledge, MDACK.↲
↲
MULTIBUS 0270 Wr: Sets Multibus interrupt output.↲
INTERRUPT MBINTOUT1, 2 or 3, or pulses MBINTOUT0.↲
CONTROL↲
↲
- 0272 ┆84┆Wr: Clears Multibus interrupt output ↓
┆19┆┆9c┆┄┄MBINTOUT1, 2 or 3.↲
↲
↲
┆b0┆┆a1┆2.3 8255A Parallel I/O Ports↲
↲
┆84┆The 8255A must be initialized with ↲
Control byte (address 0106) = 9A.↲
↲
┆84┆This dedfines the mode of operation for the three I/O ports ↓
┆19┆┆89┆┄┄as described below↲
↲
Port A: input, mode 0↲
Port B: input, mode 0↲
Port C, bits 0 to 3: output↲
Port C, bits 4 to 7: input↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2┆a1┆.3.1 8255A Port A↲
↲
┆84┆Port A is used to read the contents of an 8-bit jumper ↓
┆19┆┆89┆┄┄field (W26). When a jumper is inserted the corresponding ↓
┆19┆┆89┆┄┄input bit is 0. No jumper corresponds to a 1. The W26 ↓
┆19┆┆89┆┄┄jumper positions are assigned to the port A inputs (PA) as ↓
┆19┆┆89┆┄┄described below:↲
↲
PA0: 4-13↲
PA1: 3-14↲
PA2: 2-15↲
PA3: 1-16↲
PA4: 8-9↲
PA5: 7-10↲
PA6: 6-11↲
PA7: 5-12↲
↲
↲
┆b0┆┆a1┆2.3.2 8255A Port B↲
↲
┆84┆Port B is used to read the state of different status ↓
┆19┆┆89┆┄┄signals as described below:↲
↲
PB0: ┆84┆-,RLSD. Received Line Signal Detector (carrier on) ↓
┆19┆┆8e┆┄┄from V.24/V.28 interface. ↲
0 = on.↲
↲
PB1: ┆84┆-,CALL. Calling Indicator from V.24/V28 interface.↲
0 = on.↲
↲
PB2: ┆84┆-,XAPST. Present (-,MPST) signal from SBX, J1 ↓
┆19┆┆8e┆┄┄connector.↲
↲
PB3: ┆84┆XAOPT0. User defined signal (OPT0) from SBX, J1 ↓
┆19┆┆8e┆┄┄connector.↲
↲
PB4: ┆84┆XAOPT1. User defined signal (OPT1) from SBX, J1 ↓
┆19┆┆8e┆┄┄connector.↲
↲
PB5: ┆84┆-,XBPST. Present (-,MPST) signal from SBX, J2 ↓
┆19┆┆8e┆┄┄connector.↲
↲
PB6: ┆84┆XBOPT0: User defined signal (OPT0) from SBX, J2 ↓
┆19┆┆8e┆┄┄connector.↲
↲
PB7: ┆84┆XBOPT1: User defined signal (OPT1) from SBX, J2 ↓
┆19┆┆8e┆┄┄connector.↲
↲
↲
┆b0┆┆a1┆2.3.3 8255A Port C↲
↲
┆84┆Port C, bits 0 to 3, is used to control the user definable ↓
┆19┆┆89┆┄┄SBX interface signals OPT0 and OPT1, when these are used as ↓
┆19┆┆89┆┄┄output signals (to SBX module). The jumpers W21, W22, W23 ↓
┆19┆┆89┆┄┄and W24 are used to connect the port C outputs to the SBX ↓
┆19┆┆89┆┄┄signals. See section 1.3.↲
↲
════════════════════════════════════════════════════════════════════════
↓
PC0: XAOUTP0. SBX,J1 connector OPT0 signal↲
PC1: XAOUTP1. SBX,J1 connector OPT1 signal↲
PC2: XBOUTP0. SBX,J2 connector OPT0 signal↲
PC3: XBOUTP1. SBX,J2 connector OPT1 signal↲
↲
┆84┆Port C, bits 4 to 7 are not used on the CPU602.↲
↲
↲
┆b0┆┆a1┆2.4 Multibus Interrupt Outputs↲
↲
┆84┆The CPU602 has 4 interrupt outputs (MBINTOUT0 through ↓
┆19┆┆89┆┄┄MBINTOUT3), which can be connected to any of the 8 Multibus ↓
┆19┆┆89┆┄┄interrupt lines (jumper field W12). The output MBINTOUT0 is ↓
┆19┆┆89┆┄┄pulsed and can only be used for edge triggered interrupt ↓
┆19┆┆89┆┄┄inputs. The interrupt outputs MBINTOUT1, MBINTOUT2 and ↓
┆19┆┆89┆┄┄MBINTOUT3 are latched and may be set and cleared from the ↓
┆19┆┆89┆┄┄on board 80186, or they may be set from the on board 80186 ↓
┆19┆┆89┆┄┄and cleared from another Multibus device. A Multibus I/O ↓
┆19┆┆89┆┄┄address is assigned to the reset input of the interrupt ↓
┆19┆┆89┆┄┄latches.↲
↲
↲
┆b0┆┆a1┆2.4.1 Set Multibus Interrupt Output↲
↲
┆84┆A write to on board I/O address 0270 activates the ↓
┆19┆┆89┆┄┄interrupt output addressed by data bits 1,0. Data bits 7 to ↓
┆19┆┆89┆┄┄2 are unused.↲
↲
DATA 1,0 = 0,0: pulses MBINTOUT0↲
= 0,1: sets MBINTOUT1↲
= 1,0: sets MBINTOUT2↲
= 1,1: sets MBINTOUT3↲
↲
↲
┆b0┆┆a1┆2.4.2 Clear Multibus Interrupt Output↲
↲
┆84┆A write to on board I/O address 0272 clears the interrupt ↓
┆19┆┆89┆┄┄output addressed by data bits 1,0. Data bits 7 to 2 are ↓
┆19┆┆89┆┄┄unused.↲
↲
DATA 1,0 = 0,0: no function↲
= 0,1: clears MBINTOUT1↲
= 1,0: clears MBINTOUT2↲
= 1,1: clears MBINTOUT3↲
↲
┆84┆A write to the Multibus address set up by the jumper fields ↓
┆19┆┆89┆┄┄W20 and W25 will clear the interrupt output addressed by ↓
┆19┆┆89┆┄┄Multibus data bits 1,0 as described above. Data 7 to 2 is ↓
┆19┆┆89┆┄┄unused.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆3. TECHNICAL DESCRIPTION↲
↲
┆84┆This chapter contains logic diagrams with signal ↓
┆19┆┆89┆┄┄descriptions, timing diagrams, PAL descriptions, and ↓
┆19┆┆89┆┄┄assembly drawing. ↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
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Figure 3.1: CPU602 Block Diagram ↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆3.1 Logic Diagrams and Signal Descriptions↲
↲
┆84┆The left hand pages of this chapter contains a description ↓
┆19┆┆89┆┄┄of the signals generated on the logic diagram on the ↓
┆19┆┆89┆┄┄corresponding right hand side. The column 'Destination' ↓
┆19┆┆89┆┄┄refers to the diagram number, where the signal in question ↓
┆19┆┆89┆┄┄is used. All references between logic diagrams make use of ↓
┆19┆┆89┆┄┄the diagram number in the lower right corner of the ↓
┆19┆┆89┆┄┄diagrams. ↲
↲
┆84┆Signal and diagram references are indicated on the logic ↓
┆19┆┆89┆┄┄diagram as shown below. ↲
↲
┆a1┆source diagram┆e1┆ ┆a1┆↲
┆a1┆position↲
↲
┆a1┆source (pos.-pin)┆e1┆ ┆a1┆↲
┆a1┆pin↲
↲
8 ↲
↲
↲
3 ┆a1┆26-14 CPUDEN 1┆e1┆ ┆a1┆ 3 -,IODEN↲
↲
┆a1┆ 2↲
↲
↲
Signals preceded with '-,' are active low. ↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
CPUCLK 3 ┆84┆8 MHz clock output from ↓
┆19┆┆ad┆┄┄CPU with 50% duty ↓
┆19┆┆ad┆┄┄cycle. CPU timing is ↓
┆19┆┆ad┆┄┄specified relative to ↓
┆19┆┆ad┆┄┄this signal. ↲
AD0-ADF 2,6,13 16-bit multiplexed↲
address/data bus. ↲
A10-A13 2 ┆84┆4 most significant ↓
┆19┆┆ad┆┄┄address bits.↲
-,BHE 2 ┆84┆Controls byte transfers ↓
┆19┆┆ad┆┄┄on bus lines 8-F.↲
-,S0--,S2 2,3 CPU bus cycle status↲
lines. ↲
-,CPULOCK 3,11,15 Used to give the CPU↲
┆84┆exclusive access to ↓
┆19┆┆ad┆┄┄DPRAM and multibus.↲
ALE 2,3 Strobes the address↲
┆84┆into the address ↓
┆19┆┆ad┆┄┄latches. ↲
-,CPURD 3 Memory and I/O read↲
command. ↲
-,CPUWRT 3 Memory and I/O write↲
command. ↲
-,CPUDEN 3 Controls enable↲
┆84┆signals for data bus ↓
┆19┆┆ad┆┄┄tranceivers. ↲
-,ROMCS 3,4,6 Chip select for EPROM↲
-,8259CS 7 Chip select for 8259A↲
intr. controller.↲
-,8251CS 8 Chip select for 8251A↲
USART. ↲
-,8255CS 9 Chip select for 8255A↲
parallel╞ I/O port↲
-,PCS3 9 Generates chip selects ↲
┆84┆for I/O expansion con- ↓
┆19┆┆ad┆┄┄nector J1. ↲
-,PCS4 9,12 Generates chip selects↲
┆84┆for I/O expansion ↓
┆19┆┆ad┆┄┄connector J2 and for↲
┆84┆Multibus interrupt ↓
┆19┆┆ad┆┄┄control logic.↲
-,XADACK 10 DMA acknowledge signals ↲
-,XBDACK 10 to I/O expansion con-↲
-,INTA0 7 nectors J1 and J2.↲
INTA to 8259A intr.↲
controller. ↲
INT3 7 NON RMX MODE: intr. ↲
input. ↲
RMX MODE: slave intr. ↲
output. ↲
BAUD 8 Transmit and receive ↲
clock for 8251A USART.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
PUADR0 4,9,14 PUADR0-PUADR13 is a 20-↲
PUADR1 6,7,8,9,10,12,14 bit address bus. Bits ↲
PUADR2 6,9,10,14 (0-F) are used for both ↲
PUADR3 6,10,14 memory and I/O addres-↲
PUADR4-PUADR5 6,9,14 sing. Bits (10-13) are↲
PUADR6 6,12,14 the 4 most significant ↲
PUADR7-PUADR9 6,14 memory address bits.↲
PUADRA-PUADRE 4,6,14 ↲
PUADRF 4,6,14 ↲
PUADR10-PUADR11 14 ↲
PUADR12-PUADR13 4,14 ↲
↲
-,LBHE 4,9,15 Latched BHE. Controls ↲
┆84┆bus transfers on bus ↓
┆19┆┆ad┆┄┄lines 8-F.↲
↲
-,LS0--,LS2 4 Latched CPU bus cycle ↲
status. ↲
↲
IODAT0-IODAT1 7,8,9,10,12 16 bit bidirectional ↲
IODAT2-IODAT7 7,8,9,10 data bus for on board↲
IODAT8-IODATF 10 I/O devices.↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a0006000000000201443140000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
╱04002d4e0a0006000000000201443140000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
╞ ↲
-,MBCMDEN 3 ┆84┆Delays start of Multi-↓
┆19┆┆ad┆┄┄bus commands to meet ↓
┆19┆┆ad┆┄┄address and data set-up ↓
┆19┆┆ad┆┄┄timing requirements.↲
-,MRDC 3,11 Multibus memory read↲
command. ↲
-,MWTC 3,11 Multibus memory write↲
command.↲
-,IORC 3,11 Multibus I/O read ↲
command. ↲
-,IOWC 3,11 Multibus I/O write ↲
command. ↲
-,INTA 3 Intr. acknowledge ↲
to Multibus.↲
MBDT/R 5 Controls data flow ↲
┆84┆direction through ↓
┆19┆┆ad┆┄┄Multibus transceivers, ↓
┆19┆┆ad┆┄┄when CPU602 is bus ↓
┆19┆┆ad┆┄┄master.↲
MBDEN 5 Enables Multibus data↲
┆84┆transceivers, when ↓
┆19┆┆ad┆┄┄CPU602 is bus master.↲
MBALE 4 Starts timeout timer ↲
for Multibus accesses.↲
-,MBMASTER 3,4,5,11 Indicates that CPU602 ↲
is bus master. ↲
-,BPRO 3 Control signals for ↲
-,BREQ 3 Multibus╞ master select-↲
-,BUSY 3 tion. ↲
-,CBRQ 3 ↲
-,OBRD 4,6,7,8,9,10,15 Buffered on board ↲
┆84┆memory and I/0 read ↓
┆19┆┆ad┆┄┄command. ↲
-,OBWRT 4,7,8,9,10,12,15 Buffered on board ↲
┆84┆memory and I/O write ↓
┆19┆┆ad┆┄┄command. ↲
-,CPUCLK 3,4,15 Buffered and inverted↲
-,CPUALE 4 control signals from↲
CPUDEN 5 80186 processor.↲
ROMCS 4 ↲
↲
MCLK 10,11 ┆84┆10 MHz clock signal. ↲
OBINIT 8,9,10 ┆84┆On board reset signal↲
┆84┆generated by Multibus ↓
┆19┆┆ad┆┄┄-,INIT. ↲
MBBHEN 5,15 ┆84┆Byte control signal ↓
┆19┆┆ad┆┄┄from Multibus.↲
OBIOADR 5 On board I/O device is↲
addressed. ↲
════════════════════════════════════════════════════════════════════════
↓
╞ ╞ ↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
TS2 3,4 ┆84┆Goes to 0 at the start ↓
┆19┆┆ad┆┄┄of T1, and changes to 1 ↓
┆19┆┆ad┆┄┄at the start of T2.↲
↲
TS3 4 Goes to 0 at the start↲
┆84┆of T1, and changes to 1 ↓
┆19┆┆ad┆┄┄at the start of T3. ↲
-,CPUDPADR 4,15 80186 addresses on ↲
board dual port RAM.↲
↲
MBACS 3,4 ┆84┆80186 address is an off ↓
┆19┆┆ad┆┄┄board address. ↲
┆84┆Multibus is accessed.↲
↲
DPBACS0 5 Used to enable DPRAM ↲
DPBACS1 5 ┆84┆data bus tranceivers ↓
┆19┆┆ad┆┄┄for DPRAM and Multibus ↓
┆19┆┆ad┆┄┄access.↲
↲
-,DPRAMADR 15 ┆84┆-, (-,LS2 and CPUDPADR) ↲
↲
-,OBIOADR 3 ┆84┆80186 addresses an on ↓
┆19┆┆ad┆┄┄board I/O device.↲
↲
ARDY 1 Asynchronous ready ↲
signal to 80186.↲
↲
SRDY 1 Synchronous ready ↲
┆84┆signal to 80186.↲
↲
-,CPUMEMCMD 15 Advanced 80186 memory↲
command.↲
↲
-,TIMEOUT 4 Time out signal. Used↲
┆84┆to terminate a Multibus ↓
┆19┆┆ad┆┄┄cycle if no XACK is ↓
┆19┆┆ad┆┄┄received within ↓
┆19┆┆ad┆┄┄approximately 10 ms. Is ↓
┆19┆┆ad┆┄┄also used to control ↓
┆19┆┆ad┆┄┄the RUN indicator.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
-,IODEN 2 Enable signal for on↲
┆84┆board I/O data bus ↓
┆19┆┆ad┆┄┄transceivers. ↲
↲
-,DPDEN0 13 Enable signals for ↲
-,DPDEN1 13 transceivers↲
between DPRAM data bus↲
┆84┆and CPU address/data ↓
┆19┆┆ad┆┄┄bus. ↲
↲
-,MBLBEN 13 Enable signals for↲
-,MBSWAP 13 data transceivers↲
-,MBHBEN 13 between Multibus↲
and DPRAM data bus.↲
↲
-,MBADREN 14 Enable signal for ↲
┆84┆address transceivers ↓
┆19┆┆ad┆┄┄between Multibus ↓
┆19┆┆ad┆┄┄and DPRAM address ↓
┆19┆┆ad┆┄┄bus. ↲
↲
MBDTRM 13 Direction control↲
┆84┆for Multibus data ↓
┆19┆┆ad┆┄┄data transceivers. ↲
↲
MBSEL 5,14 Indicates that ↲
┆84┆Multibus has ↓
┆19┆┆ad┆┄┄access to DPRAM. ↲
↲
-,DPA0 5 DPRAM address bit 0.↲
┆84┆Used to control byte ↓
┆19┆┆ad┆┄┄transfers. ↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
AD0-ADF 2,6,13 The contents of the ↲
┆84┆EPROM's are transfer- ↓
┆19┆┆ad┆┄┄red to the CPU address/ ↓
┆19┆┆ad┆┄┄data bus when -,ROMCS ↓
┆19┆┆ad┆┄┄and -,OBRD are low. ↓
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
INTO 1 Interrupt request from ↲
┆84┆8259A intr. controller ↓
┆19┆┆ad┆┄┄to 80186.↲
↲
-,SLAVESEL 7 Used only when the ↲
┆84┆80186 intr.system ↓
┆19┆┆ad┆┄┄operates in RMX86. ↓
┆19┆┆ad┆┄┄compatiblity mode. ↲
↲
MBINTO-MBINT7 7 Buffered interrupt ↲
requests from Multibus.↲
↲
INT1, INT3 1 Interrupt requests ↲
┆84┆to 80186 from inter- ↓
┆19┆┆ad┆┄┄rupt source jumper ↓
┆19┆┆ad┆┄┄matrix. ↲
↲
IR0-IR7 7 Interrupt requests ↲
┆84┆to 8259A from inter- ↓
┆19┆┆ad┆┄┄from interrupt source ↓
┆19┆┆ad┆┄┄jumper matrix.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
RECINT 7 8251A receiver intr. ↲
request. ↲
↲
TRMINT 7 8251A transmitter ↲
intr. request.↲
↲
TRD 8 Transmitted data. ↲
↲
RTS 8 Request to send. ↲
↲
DTR 8 Data terminal ready.↲
↲
TTRCL 8 Transmitter clock ↲
output. ↲
↲
RCD 8 Received data. ↲
↲
-,RFS 8 Ready for sending. ↲
↲
-,DSR 8 Data set ready. ↲
↲
-,RLSD 9 Data channel received↲
┆84┆line signal detector ↓
┆19┆┆ad┆┄┄(carrier on). ↲
↲
-,CALL 9 Calling indicator. ↲
↲
-,TRCL 8 Transmitter clock to↲
8251A. ↲
↲
RCCL 8 Receiver clock to↲
8251A. ↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
XAOUTP0 10 Optional output sig-↲
XAOUTP1 10 ┆84┆nals to I/O expansion ↓
┆19┆┆ad┆┄┄connector J1. ↲
↲
XBOUTP0 10 Optional output sig-↲
XBOUTP1 10 ┆84┆nals to I/O expansion ↓
┆19┆┆ad┆┄┄connector J2. ↲
↲
-,XACS0 10 Chip select signals↲
-,XACS1 10 ┆84┆to I/O expansion ↓
┆19┆┆ad┆┄┄connector J1. ↲
↲
-,XBCS0 10 Chip select signals↲
-,XBCS1 10 ┆84┆to I/O expansion ↓
┆19┆┆ad┆┄┄connector J2. ↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
XAOPT0 9 Optional input signals↲
XAOPT1 9 ┆84┆from I/O expansion ↓
┆19┆┆ad┆┄┄connector J1. ↲
↲
-,XAPST 9 A 0 indicates that ↲
┆84┆a module has been in- ↓
┆19┆┆ad┆┄┄stalled in J1.↲
↲
XAINT0 7 Interrupt requests↲
XAINT1 7 ┆84┆from connector J1.↲
↲
-,XAWAIT 4 Wait signal from J1.↲
┆84┆Controls ARDY to the ↓
┆19┆┆ad┆┄┄80186, when module ↓
┆19┆┆ad┆┄┄in J1 is addressed.↲
↲
XADRQ 1 DMA request from ↲
connector J1.↲
↲
XBOPT0 9╞ ╞ Optional input signals↲
XBOPT1 9 ┆84┆from I/O expansion ↓
┆19┆┆ad┆┄┄connector J2. ↲
↲
-,XBPST 9 A 0 indicates that a↲
module has been in-↲
stalled in J2.↲
↲
XBINT0 7 Interrupt requests ↲
XBINT1 7 from connector J2. ↲
↲
-,XBWAIT 4 Wait signal from J2.↲
┆84┆Controls ARDY to ↓
┆19┆┆ad┆┄┄80186, when module in ↓
┆19┆┆ad┆┄┄J2 is addressed. ↲
↲
XBDRQ 1 ┆84┆DMA request from ↓
┆19┆┆ad┆┄┄connector J2.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
-,MCLK 3,11 10 MHz clock signal.↲
↲
-,BLCK 3,11 Clock signal for the↲
8289 bus arbiter.↲
↲
-,OBINIT 1,3,12,15 Reset signal from ↲
Multibus. ↲
↲
-,MBMRD 5,11,15 Memory read command↲
from Multibus. ↲
↲
-,MBMWRT 11,15 Memory write command↲
from Multibus. ↲
↲
-,MBIOWC 12 I/O write command ↲
from Multibus. ↲
↲
-,MBXACK 4 Acknowledge from ↲
┆84┆Multibus. Generates ↓
┆19┆┆ad┆┄┄ARDY to the 80186, when ↓
┆19┆┆ad┆┄┄it accesses Multibus ↓
┆19┆┆ad┆┄┄devices. ↲
↲
-,MBIORC Not used I/O read command ↲
from Multibus. ↲
↲
-,LOCK 15 Used to obtain ↲
┆84┆exclusive access to ↓
┆19┆┆ad┆┄┄DPRAM from Multibus.↲
↲
-,BHEN 3 Byte control signal ↲
from Multibus. ↲
↲
-,XACK 11 Acknowledge from ↲
Multibus. ↲
↲
-,MBDPADR 11 A 0 indicates that the↲
┆84┆Multibus address is ↓
┆19┆┆ad┆┄┄within the DPRAM ↓
┆19┆┆ad┆┄┄address range. ↲
↲
-,MBDPRQ 11,15 Read or write request↲
to DPRAM from Multibus.↲
↲
-,DPXACK 11 Ack. from CPU602, when↲
┆84┆CPU602 is accessed from ↓
┆19┆┆ad┆┄┄Multibus. ↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
-,RSTMBINT 11,12 Decoded Multibus I/O↲
┆84┆write command. Resets ↓
┆19┆┆ad┆┄┄the intr. latch ↓
┆19┆┆ad┆┄┄(MBINTOUT1-2) addressed ↓
┆19┆┆ad┆┄┄by -,DATO, -,DAT1.↲
↲
-,MBINTOUT0 7 Pulsed intr. request↲
┆84┆output to Multibus. ↓
┆19┆┆ad┆┄┄Can only be used for ↓
┆19┆┆ad┆┄┄edge triggered intr. ↓
┆19┆┆ad┆┄┄inputs. ↲
↲
-,MBINTOUT1 7 Interrupt request ↲
-,MBINTOUT2 7 outputs to Multibus. ↲
-,MBINTOUT3 7 ┆84┆can be used for both ↓
┆19┆┆ad┆┄┄level and edge ↓
┆19┆┆ad┆┄┄triggered intr.inputs.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
DPD0-DPDF 13,17 Dual-Port RAM data bus.↲
┆84┆Transfers data between ↓
┆19┆┆ad┆┄┄80186, RAM array, and ↓
┆19┆┆ad┆┄┄Multibus. ↲
↲
-,DAT0--,DAT1 12,13 Multibus data lines.↲
-,DAT2--,DATF 13 ↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
DPA0 5,14,15 Dual Port RAM address↲
DPA1-DPA10 14,16 ╞ bus.↲
DPA11 14,15,16 ↲
DPA12 14,16 ↲
DPA13 14,15,16 ↲
↲
-,ADR0--,ADR3 14 Multibus address lines.↲
-,ADR4--,ADRF 12,14 ↲
-,ADR10--,ADR11 14 ↲
-,ADR12--,ADR17 11,14 ↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
-,RAS0 17 Row address strobes ↲
-,RAS1 17 for RAM array. ↲
RASEN 15 Enable signal for ↲
-,RAS0 and -,RAS1.↲
ROWADR 16 Controls RAM address↲
multiplexer. ↲
DASTB 13 Strobe signal for RAM↲
output latch.↲
-,CAS0 17 Column address strobes↲
-,CAS1 17 for RAM array. ↲
CAS 4,15 ┆84┆Generates -,CAS0 and↓
┆19┆┆ad┆┄┄-,CAS1. Controls SRDY ↓
┆19┆┆ad┆┄┄to the 80186, when it ↓
┆19┆┆ad┆┄┄accesses the DPRAM.↲
-,RASEN* 15 Input to flip-flop,↲
which generates RASEN. ↲
-,MBSEL 4,5,11,14,15 A 0 indicates that the↲
┆84┆Multibus has access to ↓
┆19┆┆ad┆┄┄the DPRAM. ↲
-,MBRQSYN 11 Synchronized DPRAM ↲
request from Multibus. ↲
-,RFCYC 15,16 Indicates that a RAM↲
refresh cycle is in ↲
progress. ↲
-,WE 11,15 Controls timing of ↲
┆84┆DPRAM write strobes ↓
┆19┆┆ad┆┄┄and Multibus XACK.↲
-,CAS* 15 Input to flip-flop,↲
which generates CAS. ↲
-,RFRQ 15 Refresh request. ↲
┆84┆Generated every 14.5 ↓
┆19┆┆ad┆┄┄microsec. ↲
2MHzCLK 8 2 MHz clock to 8251A↲
USART. ↲
RFA0-RFA7 16 RAM refresh address. ↲
↲
BANK0 15 Control signals for ↲
BANK1 15 -,RAS0 and -,RAS1. ↲
↲
-,DPREAD0 13 Output enable signals ↲
-,DPREAD1 13 ┆84┆for DPRAM data output ↓
┆19┆┆ad┆┄┄latches. ↲
-,MBBHE 11 Byte control signal to↲
Multibus. ↲
-,WELOW 17 RAM write strobe, bits ↲
0-7. ↲
-,WEHIGH 17 RAM write strobe, bits ↲
8-F. ↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
R/C0-R/C8 17 ┆84┆Multiplexed row/column ↓
┆19┆┆ad┆┄┄address lines to RAM ↓
┆19┆┆ad┆┄┄array. ↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Signal Destination Description ↲
↲
RD0-RD7 13 Data outputs from RAM↲
RD8-RDF 13 array.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆3.2 P┆a1┆┆b0┆AL Descriptions↲
↲
The following PAL's are used on the CPU602 board ↲
↲
┆b0┆┆a1┆PATTERN No. PAL TYPE POSITION↲
PAT007 PAL16R8 U38 ↲
PAT008 PAL16R6 U37 ↲
PAT009 PAL16L8 U42 ↲
PAT010 PAL16L8 U43 ↲
PAT011 PAL16L8 U44 ↲
PAT012 PAL16L8 U70 ↲
↲
┆84┆In this section the logical equations for the PAL outputs ↓
┆19┆┆89┆┄┄are listed. The following terminologi is used: ↲
↲
-, complement, prefix to signal name. ↲
x logical AND. ↲
+ logical OR. ↲
= combinatorial equality. ↲
:= sequential equality, register output after positive↲
transition of clock. ↲
↲
┆84┆All the used PAL types have inverting outputs. The ↓
┆19┆┆89┆┄┄equations therefore specifies the complemented output. For ↓
┆19┆┆89┆┄┄outputs, which only are used internally in the PAL, the ↓
┆19┆┆89┆┄┄signal names (Q or F) inside the PAL symbol are used. ↲
↲
↲
┆b0┆┆a1┆3.2.1 PAT007↲
↲
┆84┆This PAL is used as refresh timer for the dynamic RAM. It ↓
┆19┆┆89┆┄┄generates a refresh request every 14.5 microsec. (6 MHz ↓
┆19┆┆89┆┄┄clock). ↲
↲
RFRQ := -,Q7x-,Q5x-,Q3x-,2MHzCLKx-,Q1x-,OBINIT↲
+ RFRQx-,RFCYCx-,OBINIT ↲
↲
Q1 := -,Q7x-,Q5x-,Q3x-,2MHzCLKx-,Q1 ↲
+ -,Q1 ↲
↲
2MHzCLK := -,Q7x-,Q5x-,Q3x-,2MHzCLKx-,Q1↲
+ 2MHzCLKxQ1 ↲
+ -,2MHzCLKx-,Q1 ↲
↲
Q3 := OBINIT↲
+-,Q7x-,Q5x-,Q3x-,2MHzCLKx-,Q1↲
+ Q3x2MHzCLKx↲
+ Q3xQ1↲
+ -,Q3x-,2MHzCLKx-,Q1↲
↲
Q4 := OBINIT↲
+-,Q7x-,Q5x-,Q3x-,2MHzCLKx-,Q1↲
+ Q4xQ3↲
+ Q4x2MHzCLK↲
+ Q4xQ1↲
+ -,Q4x-,Q3x-,2MHzCLKx-,Q1↲
════════════════════════════════════════════════════════════════════════
↓
Q5 := OBINIT ↲
+ -,Q7x-,Q5x-,Q3x-,2MHzCLKx-,Q1 ↲
+ Q5xQ4 ↲
+ Q5xQ3 ↲
+ Q5x2MHzCLK ↲
+ -,Q5x-,Q4x-,Q3x-,2MHzCLKx-,Q1 ↲
↲
Q6 := OBINIT↲
+ -,Q7x-,Q5x-,Q3x-,2MHzCLKx-,Q1↲
+ Q6xQ5↲
+ Q6xQ4↲
+ Q6xQ3↲
+ Q6x2MHzCLK↲
+ Q6xQ1↲
+ -,Q6x-,Q5x-,Q4x-,Q3x-,2MHzCLKx-,Q1↲
↲
Q7 := -,Q7x-,Q5x-,Q3x-,2MHzCLKx-,Q1x-,OBINIT↲
+ Q7xQ6x-,OBINIT ↲
+ Q7xQ5x-,OBINIT ↲
+ Q7xQ4x-,OBINIT ↲
+ Q7xQ3x-,OBINIT ↲
+ Q7x2MHzCLKx-,OBINIT ↲
+ Q7xQ1x-,OBINIT ↲
↲
↲
┆b0┆┆a1┆3.2.2 PAT008↲
↲
┆84┆This PAL controls the access to the Dual-Port RAM and ↓
┆19┆┆89┆┄┄generates the timing control signals for the RAM. ↲
↲
RASEN* = RFCYCx-,Q4x-,OBINIT ↲
+ -,RFCYCx-,RASENx-,Q4x-,MBSELx-,RFRQxCPUDPADR ↲
xCPUMEMCMDx-,OBINIT ↲
+ -,RFCYCx-,RASENx-,Q4xMBSELx-,Q1x-,RFRQ↲
xMBRQSYNx-,0BINIT ↲
+ -,RFCYCxRASENx-,WEx-,0BINIT ↲
↲
MBSEL := -,CPUDPADRx-,CPULOCKxMBRQSYNx-,0BINIT ↲
+ -,CPUMEMCMDx-,CPULOCKxMBRQSYNx-,0BINIT ↲
+ MBSELxMBRQSYNx-,0BINIT ↲
+ MBSELxMBLOCKx-,0BINIT ↲
↲
Q1 := MBRQSYNxMBSELx-,RFCYCxRASENx-,0BINIT ↲
+ Q1xMBRQSYNx-,0BINIT ↲
↲
MBRQSYN := MBDPRQx-,0BINIT ↲
↲
RFCYC := -,RFCYCx-,RASENx-,Q4xRFRQx-,0BINIT ↲
+ RFCYCx-,Q4x-,0BINIT ↲
+ RFCYCxRASENx-,0BINIT ↲
↲
Q4 := RASENx-,0BINIT ↲
════════════════════════════════════════════════════════════════════════
↓
WE := -,RFCYCxRASENxQ4x-,WEx-,0BINIT ↲
↲
-,CAS* := -,RFCYCxRASENx-,0BINIT ↲
↲
↲
┆b0┆┆a1┆3.2.3 PAT009↲
↲
┆84┆This PAL generates the bank select (BANK0, BANK1) and the ↓
┆19┆┆89┆┄┄byte write (WELOW, WEHIGH) control signals for the RAM. In ↓
┆19┆┆89┆┄┄addition it generates the enable signals (DPREAD0, DPREAD1) ↓
┆19┆┆89┆┄┄for the RAM output latches and the Multibus byte control ↓
┆19┆┆89┆┄┄signal MBBHE. ↲
↲
↲
-,BANK0 = D9x-,RFCYC ↲
↲
-,BANK1 = -,D9x-,RFCYC ↲
↲
DPREAD0 = -,MBSELxDPRAMADRx0BRD ↲
+ MBSELxMBMRD ↲
↲
DPREAD1 = -,MBSELxDPRAMADRx0BRD ↲
+ MBSELxMBMRD ↲
↲
F4 = -,MBSELxDPRAMADRx-,DPA0x0BWRT ↲
+ MBSELx-,DPA0xMBMWRT ↲
↲
F5 = -,MBSELxDPRAMADRxLBHEx0BWRT ↲
+ MBSELxMBBHENxMBMWRT ↲
+ MBSELxDPA0xMBMWRT ↲
↲
MBBHE = -,LBHExDPA0 ↲
+ LBHEx-,DPA0 ↲
↲
↲
┆b0┆┆a1┆3.2.4 PAT010↲
↲
This PAL is used as address decoder. ↲
↲
-,MBACS = ROMCS ↲
+ -,LS2xCPUDPADR ↲
+ LS2xLS1xLS0 ↲
+ LS2xPUADRFxPUADRExPUADRDxPUADRCxPUADRBxPUADRA↲
+ LS2x-,PUADRFx-,PUADREx-,PUADRDx-,PUADRC↲
x-,PUADRBx-,PUADRA ↲
↲
-,DPBACS0= ROMCS ↲
+ LS2xLS1xLS0 ↲
+ LS2xPUADRFxPUADRExPUADRDxPUADRCxPUADRBxPUADRA↲
+ ┆84┆LS2x-,PUADRFx-,PUADREx-,PUADRDx-,PUADRC ↓
┆19┆┆96┆┄┄x-,PUADRBx-,PUADRA ↲
+ PUADR0 ↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
-,DPBACS1= ROMCS ↲
+ LS2xLS1xLS0 ↲
+ LS2xPUADRFxPUADRExPUADRDxPUADRCxPUADRBxPUADRA↲
+ ┆84┆LS2x-,PUADRFx-,PUADREx-,PUADRDx-,PUADRC ↓
┆19┆┆96┆┄┄x-,PUADRBx-,PUADRA ↲
+ -,LBHE ↲
↲
DPRAMADR = -,LS2xCPUDPADR ↲
↲
OBIOADR = LS2xLS1xLS0 ↲
+ LS2x-,PUADRFx-,PUADREx-,PUADRDx-,PUADRC↲
x-,PUADRBx-,PUADRA ↲
↲
↲
┆b0┆┆a1┆3.2.5 PAT011↲
↲
┆84┆This PAL generates the ARDY and SRDY ready signals for the ↓
┆19┆┆89┆┄┄80186 microprocessor. The memory command signal ,CPUMEMCMD, ↓
┆19┆┆89┆┄┄is decoded from LS2, LS1, and LS0. ↲
↲
-,ARDY = XAWAIT ↲
+ XBWAIT ↲
+ LS2xLS1xLS0 ↲
+ -,LS2xCPUDPADR ↲
+ MBACSx-,MBMASTER ↲
+ MBACSx-,MBXACKx-,TIMEOUT ↲
↲
-,SRDY = LS2x-,LS1 ↲
+ LS2x-,LS0 ↲
+ -,LS2x-,CPUDPADR ↲
+ LS2xLS1xLS0x-,TS3 ↲
+ -,LS2xCPUDPADRxMBSEL ↲
+ -,LS2xCPUDPADRx-,CAS ↲
↲
MCMD = -,LS2xLS1x-,TS3 ↲
+ -,LS2xLS1x0BRD ↲
+ -,LS2xLS0x-,TS3 ↲
+ -,LS2xLS0x0BWRT ↲
↲
↲
┆b0┆┆a1┆3.2.6 PAT012↲
↲
┆84┆This PAL is used to generate interrupt to the Multibus. It ↓
┆19┆┆89┆┄┄has one non-latched (MBINTOUT0), and three latched ↓
┆19┆┆89┆┄┄(MBINTOUT 1-3) interrupt outputs. ↲
↲
MBINTOUT0 = OBWRTxPCS4xPUADR6x-,PUADR1x-,IODAT1x-,IODAT0↲
↲
-,Q1 = OBWRTxPCS4xPUADR6x-,PUADR1x-,IODAT1xIODAT0↲
+ MBINTOUT1 ↲
↲
════════════════════════════════════════════════════════════════════════
↓
-,MBINTOUT1 = 0BINIT ↲
+ OBWRTxPCS4xPUADR6xPUADR1x-,IODAT1xIODAT0↲
+ RSTMBINTx-,DAT1xDAT0 ↲
+ Q1 ↲
↲
-,Q2 = OBWRTxPCS4xPUADR6x-,PUADR1xIODAT1x-,IODAT0↲
+ MBINTOUT2 ↲
↲
-,MBINTOUT2 = 0BINIT ↲
+ OBWRTxPCS4xPUADR6xPUADR1xIODAT1x-,IODAT0↲
+ RSTMBINTxDAT1x-,DAT0 ↲
+ Q2 ↲
↲
-,Q3 = OBWRTxPCS4xPUADR6x-,PUADR1xIODAT1xIODAT0↲
+ MBINTOUT3 ↲
↲
-,MBINTOUT3 = 0BINIT ↲
+ OBWRTxPCS4xPUADR6xPUADR1xIODAT1xIODAT0↲
+ RSTMBINTxDAT1xDAT0 ↲
+ Q3 ╞ ╞ ╞ ╞ ╞ ↲
↲
↲
┆b0┆┆a1┆3.3 State Diagrams↲
↲
┆b0┆┆a1┆3.3.1 Dual-Port RAM Access Control↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
F1 = MBRQSYNx-,CPUDPADRx-,CPULOCK↲
+ MBRQSYNx-,CPUMEMCMDx-,CPULOCK↲
↲
F2 = MBRQSYNxMBSELx-,RFCYCxRASEN↲
↲
F3 = -,MBRQSYNx-,MBLOCK↲
↲
F4 = MBSELxMBLOCK↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆3.3.2 Dual-Port RAM Timing Control↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
F1 = CPUDPADRxCPUMEMCMDx-,RFRQx-,MBSEL↲
+MBRQSYNx-,RFRQxMBSEL↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆3.4 Timing Diagrams↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆3.5 Assembly Drawing↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆1a┆┆1a┆