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Length: 8704 (0x2200)
Types: RcTekst
Names: »99109834.WP«
└─⟦dedaa6eab⟧ Bits:30005866/disk1.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99109834.WP«
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┆a2┆┆e2┆┆a1┆┆b0┆TABLE OF CONTENTS ┆05┆PAGE↲
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1. GENEREL .................................................. 1↲
↲
2. RC MIKRONET .............................................. 3↲
2.1 RC Mikronet blockdiagram ............................ 3↲
2.2 RC Mikronet jumper configuration .................... 3↲
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3. ETHERNET/CHEAPERNET ...................................... 5↲
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4. LOGIC DIAGRAMS ........................................... 7↲
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5. TIMING DIAGRAMS .......................................... 26 ↲
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┆a1┆┆b0┆APPENDIX↲
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A. REFERENCES ............................................... 32↲
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┆14┆┆b3┆┆06┆┆0b┆↲
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┆a1┆┆b0┆1. GENEREL↲
↲
This manual contains a hardware description of the NET751, net┄↓
controller board, which is used in the RC750 system supporting RC ↓
Mikronet, Ethernet and Cheapernet local area networks.↲
↲
RC Mikronet is a 1Mbit local area network. Ethernet and Cheaper┄↓
net are 10 Mbit local area networks. The NET751 board can be ↓
configured to support 1Mbit transmission rate or 10 Mbit trans┄↓
mission rate.↲
↲
Chapter 2 describes how to configure the board to support RC ↓
Mikronet.↲
↲
Chapter 3 describes how to configure the board to support Ether┄↓
net or Cheapernet.↲
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Fig. 1: NET751 block diagram, Micronet.↲
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┆b0┆┆a1┆2. RC MIKRONET↲
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┆a1┆┆b0┆2.1 RC Mikronet blockdiagram↲
↲
Figure 1 shows a blockdiagram of the NET751 board when configured ↓
to support RC Mikronet.↲
↲
The architecture is based on the Intel 82586 local communication ↓
controller.↲
↲
The serial interface may be divided into two parts:↲
↲
1. the transmitting circuit,↲
↲
2. the receiving circuit.↲
↲
The transmitter performs the Manchester encoding and data from ↓
the 82586. ↲
↲
A watch dog timer prevents the 872586 from transmitting too long ↓
frames (250 ms). When transmitting a frame, the 82586 controller ↓
may receive a collision signal from the transceiver indicating ↓
that another station transmits a frame.↲
↲
The receiver performs the Manchester decoding and a clock reco┄↓
very of the received signal from the transceiver.↲
↲
↲
┆b0┆┆a1┆2.2 RC Mikronet jumper configuration↲
↲
The 82586 may access up to 960 Kbytes of memory on the CPU board. ↓
The address space can be selected by two jumpers on the board. ↓
Table 1 shows how.↲
↲
W4 W3 Address space↲
↲
00000H - 0FFFFFH↲
↲
00000H - 07FFFFH↲
↲
00000H - 03FFFFH↲
↲
00000H - 3FFFFH and↲
80000H - 0BFFFFH↲
↲
┆06┆Table 1: Address range selection.↲
↲
In order to support RC Mikronet the jumpers must be placed as ↓
shown in figure 2 except the jumpers in position W3 and W4.↲
↲
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┆06┆Fig. 2: Jumpers in the Micronet configuration.↲
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┆b0┆┆a1┆3. ETHERNET/CHEAPERNET↲
↲
Figure 3 shows a block diagram of the board when configured to ↓
support Ethernet/Cheapernet.↲
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┆06┆Fig. 3: Block diagram, Ethernet/Cheapernet.↲
↲
Table 1 in chapter 2 shows how to configure the address space for ↓
the 82586 local communication controller.↲
↲
In order to support Ethernet/Cheapernet the jumpers (except in ↓
position W3 and W4) must be placed as shown in figure 4.↲
↲
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┆06┆Fig. 4: Jumpers in the Ethernet/Cheapernet configuration.↲
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┆b0┆┆a1┆4. LOGIC DIAGRAMS↲
↲
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┆a1┆┆b0┆ SIGNAL NAME┆06┆DESCRIPTION┆05┆↲
↲
TXD Data to be transmitted, NRZI.↲
↲
-,RTS Request to send to serial interface.↲
↲
NETHOLD ┆84┆Request to the CPU to access the ↓
┆19┆┆9b┆┄┄systembus.↲
↲
NETINT Interrupt to the CPU.↲
↲
-,S0*, -,S1* ┆84┆Status signals, defining the type of ↓
┆19┆┆9b┆┄┄DMA transfer.↲
↲
-,BHE ┆84┆Bus High Enable, enables data onto the ↓
┆19┆┆9b┆┄┄most significant half of the data bus.↲
↲
A16-19 Address bit 16 to 19.↲
↲
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┆b0┆┆a1┆ SIGNAL NAME┆06┆DESCRIPTION┆05┆↲
↲
-,DEN ┆84┆Data enable is activated by the net┄↓
┆19┆┆9b┆┄┄controller when access to systembus.↲
↲
A19*, A18* ┆84┆Address bits controlled by netcontrol┄↓
┆19┆┆9b┆┄┄ler.↲
↲
-,HOLD ┆84┆DMA request from netcontroller or 8087 ↓
┆19┆┆9b┆┄┄floating processor.↲
↲
NETHLDA* ┆84┆Latched DMA acknowledge signal from ↓
┆19┆┆9b┆┄┄CPU.↲
↲
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┆b0┆┆a1┆ SIGNAL NAME┆06┆DESCRIPTION┆05┆↲
┆81┆┆a1┆↲
NETHOLDA ┆84┆DMA acknowledge signal from CPU to ↓
┆19┆┆9b┆┄┄netcontroller through priority logic.↲
↲
NETHOLD* ┆84┆DMA request from netcontroller through ↓
┆19┆┆9b┆┄┄priority logic.↲
↲
8087HDLA ┆84┆DMA acknowledge signal from CPU to ↓
┆19┆┆9b┆┄┄8087 floating processor through prio┄↓
┆19┆┆9b┆┄┄rity logic.↲
↲
8087HOLD ┆84┆DMA request from 8087 floating proces┄↓
┆19┆┆9b┆┄┄sor through priority logic.↲
↲
INT ┆84┆Interrupt signal from netcontroller to ↓
┆19┆┆9b┆┄┄CPU board.↲
↲
-,82501 RXC* ┆84┆Delayed receiver clock signal from ↓
┆19┆┆9b┆┄┄82501 encoder/decoder.↲
↲
-,82501 CDT* ┆84┆Collision detect signal from 82501 ↓
┆19┆┆9b┆┄┄encoder/decoder.↲
↲
-,RESET Reset signal from CPU-board.↲
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┆a2┆┆a2┆┆e2┆┆a1┆┆b0┆ SIGNAL NAME┆06┆DESCRIPTION┆05┆↲
┆81┆┆a1┆↲
AD0-15 ┆84┆Time multiplexed memory address and ↓
┆19┆┆9b┆┄┄data bus.↲
↲
-,BHE* ┆84┆Bus high enable.↲
↲
A16*-19* ┆84┆Four most significant address lines.↲
↲
-,8087HOLD ┆84┆DMA request from 8087 floating proces┄↓
┆19┆┆9b┆┄┄sor board to netcontroller board (to ↓
┆19┆┆9b┆┄┄priority logic).↲
↲
HLDA ┆84┆DMA acknowledge signal to netcontrol┄↓
┆19┆┆9b┆┄┄ler board.↲
↲
QS0, QS1 ┆84┆Queue status signal to the 8087 floa┄↓
┆19┆┆9b┆┄┄ting processor board.↲
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ARDY ┆84┆Asynchronous ready signal from memory.↲
↲
TEST ┆84┆Test signal to the 8087 floating ↓
┆19┆┆9b┆┄┄processor board.↲
↲
CPUCLK ┆84┆Clock signal from CPU board.↲
↲
-,NETCA ┆84┆Channel attention signal to netcon┄↓
┆19┆┆9b┆┄┄troller.↲
↲
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┆a1┆┆b0┆ SIGNAL NAME┆06┆DESCRIPTION┆05┆↲
┆81┆┆a1┆↲
Transmit+, Transmit- Transmit pair to transceiver.↲
↲
-,82501 RXC ┆84┆Receiver clock from 82501 encoder/de┄↓
┆19┆┆9b┆┄┄coder↲
-,82501CRS ┆84┆Carrier sense from 82501 encoder/de┄↓
┆19┆┆9b┆┄┄coder↲
82501RXD ┆84┆Receive data from 82501 encoder/de┄↓
┆19┆┆9b┆┄┄coder↲
-,82501 CDT ┆84┆Collision detect from 82501 encoder/┄ ↓
┆19┆┆9b┆┄┄decoder↲
-,82501 TXC ┆84┆Transmitterclock from 82501 encoder/┄ ↓
┆19┆┆9b┆┄┄decoder↲
-,RXC Receiver clock to netcontroller↲
-,CRS Carrier sense to netcontroller↲
RXD Receive data to netcontroller↲
-,CDT Collision detect to netcontroller↲
-,TXC Transmitter clock to netcontroller↲
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┆a1┆┆b0┆ SIGNAL NAME┆06┆DESCRIPTION┆05┆↲
┆81┆┆a1┆↲
-,MRXC ┆84┆Micronet receiver clock generated from ↓
┆19┆┆9b┆┄┄received manchester encoded signal.↲
↲
MRXDD ┆84┆Micronet receive data signal.↲
↲
DATATR ┆84┆Data transitions, transitions low to ↓
┆19┆┆9b┆┄┄high indicates that data is being ↓
┆19┆┆9b┆┄┄received.↲
↲
10MHz ┆84┆10MHz clock for the mikronet clock and ↓
┆19┆┆9b┆┄┄data recovery.↲
↲
2MHz 2MHz clock for micronet data encoding.↲
↲
-,MTXC Micronet transmit clock.↲
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┆b0┆┆a1┆ SIGNAL NAME┆06┆DESCRIPTION┆05┆↲
┆81┆┆a1┆↲
TXDE ┆84┆Micronet Manchester encoded transmit ↓
┆19┆┆9b┆┄┄data.↲
↲
MCRS, -,MCRS Micronet carrier sense signal.↲
↲
EOF End of frame signal.↲
↲
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┆b0┆┆a1┆ SIGNAL NAME┆06┆DESCRIPTION┆05┆↲
┆81┆┆a1┆↲
-,MCDT Micronet collision detect.↲
↲
MRXD ┆84┆Micronet Manchester encoded data ↓
┆19┆┆9b┆┄┄received from transceiver.↲
↲
TRANSMIT+, TRANSMIT- ┆84┆Micronet transmit pair signals to ↓
┆19┆┆9b┆┄┄transceiver.↲
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┆a2┆┆e2┆┆b0┆┆a1┆ SIGNAL NAME┆06┆DESCRIPTION┆05┆↲
┆81┆┆a1┆↲
COLDET+, COLDET- ┆84┆Collision detect signal pair.↲
↲
RECEIVE+, RECEIVE- Receive data signal pair.↲
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┆b0┆┆a1┆5. TIMING DIAGRAMS↲
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┆b0┆┆a1┆A. REFERENCES↲
↲
(1) ┆84┆RCSL No 44-RT2058.↲
┆84┆RC750, CPU board, Reference Manual,↲
Jens Peter Jakobsen and Peter Kock Andersson, Sept. 83.↲
↲
(2) RCSL No 991 09819.↲
Drawings for RC750, ↲
Peter Kock Andersson.↲
↲
(3) 82586 Reference Manual, Jan 83.↲
Intel Corporation.↲
↲
(4) 82501 Ethernet Serial Interface, Data sheet.↲
↲
(5) LAN Components User's Manual,↲
Intel, March 1984.↲
↲
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