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Length: 17920 (0x4600)
Types: RcTekst
Names: »99109964.WP«
└─⟦670c8f5a6⟧ Bits:30005866/disk2.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99109964.WP«
╱04002d4c0a00050000000002013c3140000000000000000000000000000000000000000000000000050a0f19232d37414b555f69737d87ff04╱
┆06┆i↲
↲
┆b0┆┆a1┆TABLE OF CONTENTS┆05┆PAGE↲
↲
1. INTRODUCTION ....................................... 1↲
↲
2. FUNCTIONAL DESCRIPTION ............................. 2↲
2.1 Block Diagram .................................. 2↲
2.2 Pin Out ........................................ 3↲
2.3 Pin Designation ................................ 4↲
2.4 Register Addressing ............................ 7↲
2.5 Register Definitions ........................... 7↲
2.5.1 Control Register a ....................... 7↲
2.5.2 Control Register b ....................... 8↲
2.5.3 Transmit Register ........................ 8↲
2.5.4 Master Transmit Register ................. 8↲
2.5.5 Receive Register ......................... 8↲
2.5.6 Status Register .......................... 9↲
↲
3. MASTER MODE CONFIGURATION .......................... 10↲
3.1 Initializing ................................... 10↲
3.2 Running ........................................ 10↲
↲
4. SLAVE MODE CONFIGURATION ........................... 11↲
4.1 Initializing ................................... 11↲
4.2 Running ........................................ 11↲
4.3 Broadcast Options .............................. 11↲
↲
5. SELFTEST MODE CONFIGURATION ........................ 12↲
5.1 Initializing ................................... 12↲
5.2 Running ........................................ 12↲
↲
6. ABSOLUTE MAXIMUM RATINGS ........................... 13↲
↲
7. DC CHARACTERISTICS ................................. 14↲
↲
8. AC CHARACTERISTICS ................................. 15↲
════════════════════════════════════════════════════════════════════════
↓
┆06┆ii↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆┆06┆┆0b┆↲
↲
┆b0┆┆a1┆1. INTRODUCTION↲
↲
The Circuit II Protocol Communications Controller (CPCC) is ↓
made as a peripheral device to interface be┄tween a CPU and ↓
the CIRCUIT II protocol developed by RC. This character ↓
oriented protocol is based on a polling mas┄ter and up to 32 ↓
slaves with the data transfer only between the Mas┄ter and ↓
one Slave device at a time. In the CPCC how┄ever a Broadcast ↓
option is implemented to make it possible for the Master to ↓
transfer data to several Slaves simultan┄ously.↲
↲
A selftest option is implemented to make it possible to test ↓
the entire interface circuit by echoing transmitted data via ↓
the driving transformer into the receiver.↲
↲
The CPCC is implemented in an 1116 gate Shrinked High Speed ↓
CMOS Array from Philips and is in- and output compatible to ↓
HC/HCT logic.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
┆b0┆┆a1┆2. FUNCTIONAL DESCRIPTION↲
↲
┆b0┆┆a1┆2.1 Block Diagram↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.2 Pin Out↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.3 Pin Designation↲
↲
┆a1┆Mnemonic Pin no Type Name and Function┆05┆↲
↲
┆b0┆D0..D7┆f0┆ 1-8 I/O ┆84┆This 3-state bidirectional 8 bit ↓
┆19┆┆9b┆┆81┆┄buffer is used to interface to ↓
┆19┆┆9b┆┆81┆┄the Control-, Data- and Statusre┄┄↓
┆19┆┆9b┆┆81┆┄gister.↲
↲
┆b0┆-,RD┆f0┆ 9 I ┆84┆A "low" on this input informs the ↓
┆19┆┆9b┆┆81┆┄CPCC that the CPU is reading data ↓
┆19┆┆9b┆┆81┆┄or status informations from the ↓
┆19┆┆9b┆┆81┆┄CPCC.↲
↲
┆b0┆-,WR┆f0┆ 10 I ┆84┆A "low" on this input informs the ↓
┆19┆┆9b┆┆81┆┄CPCC that the CPU is writing Con┄↓
┆19┆┆9b┆┆81┆┄trol or Data informations to the ↓
┆19┆┆9b┆┆81┆┄CPCC.↲
↲
┆b0┆-,CS┆f0┆ 11 I ┆84┆A "low" on this input selects the ↓
┆19┆┆9b┆┆81┆┄CPCC. No reading or writing will ↓
┆19┆┆9b┆┆81┆┄occur unless the device is selec┄↓
┆19┆┆9b┆┆81┆┄ted. When -,CS is high, the Data ↓
┆19┆┆9b┆┆81┆┄bus condition will have no effect ↓
┆19┆┆9b┆┆81┆┄on the chip.↲
↲
┆b0┆A0..A1┆f0┆ 12,13 I ┆84┆These inputs in conjunction with ↓
┆19┆┆9b┆┆81┆┄the -,RD and -,WR inputs, informs ↓
┆19┆┆9b┆┆81┆┄the CPCC that the word on the da┄↓
┆19┆┆9b┆┆81┆┄ta bus is either control data or ↓
┆19┆┆9b┆┆81┆┄Status information.↲
↲
┆b0┆Gnd ┆f0┆ 14 ┆84┆Ground: 0V reference↲
↲
┆b0┆XTAL2,┆f0┆ 15,16 XTAL1 and XTAL2 are the output ↲
┆19┆┄┆81┆┄┆b0┆XTAL1┆f0┆ ┆84┆and input respectively of an in┄↓
┆19┆┆9b┆┆82┆┄verting amplifier which is inten┄↓
┆19┆┆9b┆┆82┆┄ded for use as a crystal oscilla┄↓
┆19┆┆9b┆┆82┆┄tor. To drive the CPCC with an ↓
┆19┆┆9b┆┆82┆┄external oscillator XTAL1 must be ↓
┆19┆┆9b┆┆82┆┄used as input while XTAL2 must be ↓
┆19┆┆9b┆┆82┆┄left open.↲
↲
┆b0┆TxRDY ┆f0┆ 17 0 ┆84┆Transmitter Ready.↲
┆84┆In Slave mode this output signals ↓
┆19┆┆9b┆┄┄the CPU that the transmitter is ↓
┆19┆┆9b┆┄┄ready to ac┄┄cept a data character. ↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Mnemonic Pin no Type Name and Function┆05┆↲
↲
┆84┆The TxRDY output pin can be used ↓
┆19┆┆9b┆┄┄as an in-terrupt to the system ↓
┆19┆┆9b┆┄┄or, for Polled operation, the CPU ↓
┆19┆┆9b┆┄┄can check TxRDY using a Status ↓
┆19┆┆9b┆┄┄Read operation. TxRDY is automa┄↓
┆19┆┆9b┆┄┄tically reset by the leading edge ↓
┆19┆┆9b┆┄┄of WR when a data character is ↓
┆19┆┆9b┆┄┄loaded from the CPU. The TxRDY ↓
┆19┆┆9b┆┄┄output pin is masked by the TxEN ↓
┆19┆┆9b┆┄┄control bit. ↲
↲
┆84┆In Master mode if this pin is ↓
┆19┆┆9b┆┄┄asserted together with the TxRDY ↓
┆19┆┆9b┆┄┄pin it indicates that a proper ↓
┆19┆┆9b┆┄┄answer with no data has been ↓
┆19┆┆9b┆┄┄received.↲
↲
┆b0┆RxRDY ┆f0┆ 18 0 Receiver Ready.↲
┆84┆This output indicates that the ↓
┆19┆┆9b┆┄┄CPCC contains a character that is ↓
┆19┆┆9b┆┄┄ready to be input to the CPU. ↓
┆19┆┆9b┆┄┄RxRDY can be connected to the in┄↓
┆19┆┆9b┆┄┄terrupt structure of the CPU or, ↓
┆19┆┆9b┆┄┄for Polled operation, the CPU can ↓
┆19┆┆9b┆┄┄check the condition of RxRDY ↓
┆19┆┆9b┆┄┄using a Status Read operation. ↓
┆19┆┆9b┆┄┄RxRDY is automatically reset by ↓
┆19┆┆9b┆┄┄the leading edge of RD. The RxRDY ↓
┆19┆┆9b┆┄┄output pin is masked by the RxEN ↓
┆19┆┆9b┆┄┄control bit.↲
↲
┆84┆Failure to read the received ↓
┆19┆┆9b┆┄┄character from the Rx Data Output ↓
┆19┆┆9b┆┄┄Register prior to the assembly of ↓
┆19┆┆9b┆┄┄the next Rx Data character will ↓
┆19┆┆9b┆┄┄set overrun condition error and ↓
┆19┆┆9b┆┄┄the previous character will be ↓
┆19┆┆9b┆┄┄written over and lost. If the Rx ↓
┆19┆┆9b┆┄┄Data is being read by the CPU ↓
┆19┆┆9b┆┄┄when the internal transfer is oc┄↓
┆19┆┆9b┆┄┄curing, overrun error will be set ↓
┆19┆┆9b┆┄┄and the old character will be ↓
┆19┆┆9b┆┄┄lost.↲
↲
┆b0┆X0, X1┆f0┆ 19,20 0 ┆84┆these outputs contains the values ↓
┆19┆┆9b┆┆81┆┄of the don't care bits in the Ad┄↓
┆19┆┆9b┆┆81┆┄dress Header of the protocol, and ↓
┆19┆┆9b┆┆81┆┄changes value just prior to RxRDY ↓
┆19┆┆9b┆┆81┆┄dependent of the received frame.↲
↲
┆b0┆↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆e1┆↲
┆a1┆Mnemonic Pin no Type Name and Function┆05┆↲
↲
┆b0┆BRC ┆f0┆ 21 0 ┆84┆If Broadcast option is chosen, ↓
┆19┆┆9b┆┆81┆┄this output indicates whether the ↓
┆19┆┆9b┆┆81┆┄received data is normally addres┄↓
┆19┆┆9b┆┆81┆┄sed to the CPCC or is of Broad┄┄┄↓
┆19┆┆9b┆┆81┆┄cast type (BRC = "high"); other┄↓
┆19┆┆9b┆┆81┆┄wise it remains low.↲
↲
┆b0┆-,RESET ┆f0┆ 22 I ┆84┆A "low" on this input forces the ↓
┆19┆┆9b┆┆81┆┄CPCC into an "Idle" mode. The de┄↓
┆19┆┆9b┆┆81┆┄vice will remain at "Idle" until ↓
┆19┆┆9b┆┆81┆┄a new set of control words is ↓
┆19┆┆9b┆┆81┆┄written into the CPCC to program ↓
┆19┆┆9b┆┆81┆┄its functional defintion. Minimum ↓
┆19┆┆9b┆┆81┆┄RESET pulse width is XtCY (clock ↓
┆19┆┆9b┆┆81┆┄must be running).↲
↲
┆b0┆M/-,S┆f0┆ 23 ┆84┆Master -,Slave mode selection. ↓
┆19┆┆9b┆┆81┆┄This pin determines whether the ↓
┆19┆┆9b┆┆81┆┄CPCC is to be used as a Master or ↓
┆19┆┆9b┆┆81┆┄a Slave device on the circuit li┄↓
┆19┆┆9b┆┆81┆┄ne. The level of this input pin ↓
┆19┆┆9b┆┆81┆┄must not be changed without a re┄↓
┆19┆┆9b┆┆81┆┄initialization of the CPCC.↲
↲
┆b0┆FMDIN ┆f0┆ 24 I ┆84┆Frequence MoDulated INput.↲
┆84┆The NRZ encoded incomming data ↓
┆19┆┆9b┆┄┄from the CIRCUIT II line must be ↓
┆19┆┆9b┆┄┄fed to this input.↲
↲
25 No connection↲
↲
┆b0┆NFMDO┆f0┆ 26 0 ┆84┆Negated Frequence MoDulated Out┄↓
┆19┆┆9b┆┆81┆┄put.↲
┆84┆This output contains the negative ↓
┆19┆┆9b┆┄┄part of the NRZ encoded data to ↓
┆19┆┆9b┆┄┄be transmitted on the CIRCUIT II ↓
┆19┆┆9b┆┄┄line.↲
↲
┆b0┆FMDO┆f0┆ 27 0 Frequence MoDulated Output.↲
┆84┆This output contains the positive ↓
┆19┆┆9b┆┄┄part of the NRZ encoded data to ↓
┆19┆┆9b┆┄┄be transmitted on the CIRCUIT II ↓
┆19┆┆9b┆┄┄line.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.4 Register Addressing↲
↲
┆a1┆┆e1┆ -,CS -,WR -,RD A┆82┆1 ┆81┆A┆82┆0┆81┆ ↲
┆a1┆┆81┆┆05┆↲
0 0 1 1 0 CPU->Control register a↲
↲
0 0 1 1 1 CPU->Control register b↲
↲
0 0 1 0 1 CPU->Master Tx data register↲
↲
0 0 1 0 0 CPU->Tx data register↲
↲
0 1 0 0 0 Rx data register->CPU↲
┆a1┆↲
┆a1┆┆a1┆┆e1┆ 0 1 0 0 1 Status register->CPU┆05┆↲
┆a1┆╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ↲
↲
↲
┆b0┆┆a1┆2.5 Register Definitions↲
↲
Upon power up the CPCC must be initialized before it is al┄↓
lowed to initiate any communication on the serial bus. This ↓
is done to prohibit the CPCC to answer an unspecified Ad┄┄┄↓
dress and thus violate communication on the bus. ↲
↲
↲
┆b0┆┆a1┆2.5.1 Control Register a↲
↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! !↲
! CCEN ! RXEN ! TXEN ! Device Address !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
This register contains the recognition address of which the ↓
CPCC is to answer.↲
↲
┆b0┆CCEN ┆f0┆ ┆84┆The Communication ENable is the overall enable of the ↓
┆19┆┆87┆┆81┆┄CPCC. When all other registers have been initiated ↓
┆19┆┆87┆┆81┆┄this bit must be set high to enable the CPCC recep┄┄↓
┆19┆┆87┆┆81┆┄tion/transmission on the bus. Upon Reset CCEN is set ↓
┆19┆┆87┆┆81┆┄to 0 (disable).↲
↲
┆b0┆RXEN┆f0┆ ┆84┆Receive is enable/-,disable of the RxRDY output pin ↓
┆19┆┆87┆┆81┆┄to give the ability to chose either polled or inter┄↓
┆19┆┆87┆┆81┆┄rupt mode.↲
↲
┆b0┆TXEN┆f0┆ ┆84┆Transmit ENable is similar to RxEN concerning TXRDY. ↓
┆19┆┆87┆┆81┆┄Since the CIRCUIT II protocol allways requires an an┄↓
┆19┆┆87┆┆81┆┄swer to a poll, the TXEN only concerns the TXEN out┄↓
┆19┆┆87┆┆81┆┄put and not the required "no data" answer provided by ↓
┆19┆┆87┆┆81┆┄the Tx-part.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.5.2 Control Register b↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! !↲
! BREN ! ER ! STST ! Broadcast Address !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
The b register contains the recognition address at which the ↓
CPCC is not to answer. This Broadcast address can be used by ↓
the master of the bus to transmit messages to several slaves ↓
at a time. ↲
↲
┆b0┆BREN ┆f0┆ ┆84┆is used to determine whether the CPCC is to use this ↓
┆19┆┆87┆┆81┆┄second address recognition or not. ↲
↲
┆b0┆ER ┆f0┆ ┆84┆is a reset bit which resets the content of status re┄↓
┆19┆┆87┆┆81┆┄gister bits FE OE and PE (error codes).↲
↲
┆b0┆STST ┆f0┆┆84┆Self TeST mode if choosen, must be set upon Reset to ↓
┆19┆┆87┆┆81┆┄select this mode. The mode requires no Address since ↓
┆19┆┆87┆┆81┆┄the Re┄ceiver receives the echo of the transmitted da┄↓
┆19┆┆87┆┆81┆┄ta of the CPCC. To use this mode the CPCC with its ↓
┆19┆┆87┆┆81┆┄peripheral drivers must not be attached to any active ↓
┆19┆┆87┆┆81┆┄CIRCUIT II bus.↲
↲
↲
┆b0┆┆a1┆2.5.3 Transmit register↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! !↲
! Tx-data !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
To this register the CPU must write the data to be transmit┄↓
ted on CIRCUIT II. If master mode is chosen this register ↓
must contain the leading byte.↲
↲
↲
┆b0┆┆a1┆2.5.4 Master Transmit Register↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! !↲
! MTx data !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
To this register the CPU must write the data byte to follow ↓
the leading byte if Master mode is chosen.↲
┆b0┆┆a1┆↲
↲
┆b0┆┆a1┆2.5.5 Receive Register↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! ! ↲
! Rx-Data !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
From this register the CPU can read the data received from ↓
CIRCUIT II.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.5.6 Status Register↲
↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! ! ↲
! X┆82┆1┆81┆ ! X┆82┆0┆81┆ ! FE ! OE ! PE ! BRC !RxRDY !TxRDY !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
┆e1┆┆e1┆┆b0┆RxRDY┆e1┆ ┆f0┆ ┆84┆This bit indicates that the CPCC contains a character ↓
┆19┆┆87┆┆81┆┄that is ready to be input to the CPU.↲
↲
┆a1┆┆e1┆┆b0┆TxRDY┆e1┆┆f0┆ ┆84┆This bit, in the slave mode indicates that the CPCC ↓
┆19┆┆87┆┆81┆┄is ready to accept a data character from the CPU. In ↓
┆19┆┆87┆┆81┆┄the Master mode when this bit is asserted together ↓
┆19┆┆87┆┆81┆┄with TxRDY it indicates that an answer with no data ↓
┆19┆┆87┆┆81┆┄has been received.↲
↲
┆84┆Note that when using the Polled operation, the TxRDY ↓
┆19┆┆87┆┄┄status bit is not masked by Tx Enabled, but will only ↓
┆19┆┆87┆┄┄indicate the Empty/Full Status of the Tx Data input ↓
┆19┆┆87┆┄┄Register.↲
↲
┆a1┆┆e1┆┆b0┆BRC┆e1┆ ┆f0┆ ┆84┆If BRoadCast bit is high it indicates that the broad┄↓
┆19┆┆87┆┆81┆┄cast option has been chosen and that the character in ↓
┆19┆┆87┆┆81┆┄the Receive register is received via the broadcast ↓
┆19┆┆87┆┆81┆┄ad┄dress. The BRC bit is identical to the BRC output ↓
┆19┆┆87┆┆81┆┄pin.↲
↲
┆b0┆┆e1┆PE┆e1┆ ┆b0┆┆f0┆┆84┆The Parity Error flag is set when a parity error is ↓
┆19┆┆87┆┆82┆┄detected. It is reset by the ER bit of the Command ↓
┆19┆┆87┆┆82┆┄Instruction. PE does not inhibit operation of the ↓
┆19┆┆87┆┆82┆┄CPCC but the frame containing the Parity error is ↓
┆19┆┆87┆┆82┆┄lost.↲
↲
┆a1┆┆e1┆┆b0┆OE┆e1┆ ┆f0┆ ┆84┆The Overrun Error flag is set when the CPU does not ↓
┆19┆┆87┆┆81┆┄read a char┄acter before the next one becomes avail┄┄↓
┆19┆┆87┆┆81┆┄able. It is re┄set by the ER bit of the Command In┄┄↓
┆19┆┆87┆┆81┆┄struction. OE does not inhibit operation of the CPCC ↓
┆19┆┆87┆┆81┆┄however, the pre┄viously overrun character is lost.↲
↲
┆b0┆FE┆f0┆ ┆84┆The Framing Error flag is set when a valid Stop bit ↓
┆19┆┆87┆┆81┆┄is not detec┄ted at the end of every character. It is ↓
┆19┆┆87┆┆81┆┄reset by the er bit of the Command Instruction. FE ↓
┆19┆┆87┆┆81┆┄does not inhibit the operation of the CPCC, but the ↓
┆19┆┆87┆┆81┆┄frame containing the framing error is lost.↲
↲
┆b0┆X ,X ┆f0┆These bit contains the values of the don't care bits ↲
┆81┆┆b0┆ 0 1 ┆f0┆ ┆82┆in the Address Header of the protocol, and changes ↲
┆84┆value just prior to RxRDY dependent of the received ↓
┆19┆┆87┆┄┄frame. These bits is identical to the output pins.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆a1┆3. MASTER MODE CONFIGURATION↲
↲
When Master Mode has been selected (M/-,S pin is high) the ↓
CPCC typically has to Run allmost full speed since it has to ↓
support up to 32 slaves and therefore a close correlation to ↓
a CPU will be necessary.↲
↲
↲
┆b0┆┆a1┆3.1 Initializing↲
↲
Since the answers from the slaves contains only a data byte, ↓
the Control registers A and B has only to be initializaed in ↓
the matter of CCEN, TXEN and RxEN. CCEN must be high before ↓
the Address header byte is written to the Tx-register↲
↲
↲
┆b0┆┆a1┆3.2 Running↲
↲
When the CPCC is initialized the Transmission can be star┄↓
ted. To transmit a full frame containing data, the data must ↓
be written into the Master Tx-register prior to the Address ↓
header which is written into the Tx-register. Between 2 and ↓
10 tCY after the Address header has been written to the Tx-↓
register the transmission on the line will begin. The recep┄↓
tion of the answer from the slave is automatically initiated ↓
after the transmission but if a timeout generator to watch ↓
the communication is necessary it has to be implemented ↓
elsewhere (at the CPU). When a proper reception has been ma┄↓
de, the RxRDY is asserted. If the answer contains data, the ↓
TxRDY is left at zero. If there is no data the TxRDY is as┄↓
serted together with the RxRDY and will be cleared by a ↓
writing to the Tx-register.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4. SLAVE MODE CONFIGURATION↲
↲
When the Slave Mode has been Selected (M/-,S pin is low) the ↓
CPCC typically runs in a system with many peripherals to be ↓
serviced by the same CPU. Therefore the RxRDY and TxRDY pins ↓
has been implemented to give the ability of making a clean ↓
interrupt interface.↲
↲
↲
┆b0┆┆a1┆4.1 Initializing↲
↲
Prior to operation the Control registers must be initiali┄↓
zed. The STST bit of Control register B must be low and the ↓
BREN must be low unless Broadcast option is chosen (explai┄↓
ned below). If the Control register A is loaded after the B ↓
register, the CCEN may be made high together with the wri┄↓
ting of the device address, RxEN and TxEN, the reception ↓
will be initiated upon CCEN high.↲
↲
↲
┆b0┆┆a1┆4.2 Running↲
↲
When the CPCC is initiated and CCEN is high the Reception is ↓
enabled and upon reception of a frame for the device, the ↓
transmission is initiated either with the previously loaded ↓
data byte or with the "no data" answer. Upon reception of a ↓
valid frame with a data byte the RxRDY is asserted and upon ↓
load of a byte to be transmitted TxRDY is asserted. Both ↓
RxRDY and TxRDY are cleared by the leading edge of read from ↓
the Rx-register and write to the Tx-register respectively.↲
↲
↲
┆b0┆┆a1┆4.3 Broadcast Options↲
↲
If BREN is set to high level during Initialization the ↓
Broadcast Recognition Address too has to be loaded to the ↓
Control register B. If this Broadcast address is recognized ↓
and followed by a data byte during the communication on the ↓
line, RxRDY is asserted together with BRC to indicate that ↓
the data byte has been received via the Broadcast Address. ↓
No Transmission are initiated upon reception of a broadcast ↓
frame.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5. SELFTEST MODE CONFIGURATION↲
↲
This Mode have been implemented to gain the ability to have ↓
the CPCC and surrounded circuitry to test it self. To do ↓
this the CPCC must not be attached to any active Circuit II ↓
line since the format of the selftest frames transmitted by ↓
the device under test to the line would violate all other ↓
communication on the line. The selftest function is merely ↓
an echoing of transmitted data via the line transformer to ↓
the Receive buffer of the CPCC. All status informationis ac┄↓
tive during this mode as well as the interrupt generation.↲
↲
↲
┆b0┆┆a1┆5.1 Initializing↲
↲
Since no Address header is necessary, Control register A and ↓
B are only to be initialized in the matter of RxEN, TxEN, ↓
STST (STST="1") and CCEN. M/-,S must be held low.↲
↲
↲
┆b0┆┆a1┆5.2 Running↲
↲
To initiate Communication data must be written to the Tx-re┄↓
gister, but by using TxRDY and RxRDY, running the selftest ↓
will be similar to the Slave mode when only remembering that ↓
nothing is received unless data is written to the Tx-regis┄↓
ter.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6. ABSOLUTE MAXIMUM RATINGS↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆7. DC CHARACTERISTICS↲
↲
T.B.D.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆8. AC CHARACTERISTICS↲
↲
T.B.D.↲
════════════════════════════════════════════════════════════════════════
↓
↲
┆1a┆┆1a┆de, the RxRDY