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Length: 15104 (0x3b00)
Types: RcTekst
Names: »44RT2155.WP«
└─⟦481be0aa0⟧ Bits:30008870 Diskette med 42-I og 44-RT dokumenter
└─⟦this⟧ »44RT2155.WP«
╱04002d440a0006000000000201413140000000000000000000000000000000000000000000000000050a0f14191e23282d37414b555f69ff04╱
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┆b0┆┆a1┆TABLE OF CONTENTS PAGE↲
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┆b0┆1. GENERAL INFORMATION ┆f0┆..................................... 1↲
1.1 Introduction ....................................... 1↲
1.2 Specifications ..................................... 1↲
1.2.1 Power Requirements .......................... 1↲
1.2.2 Environmental Requirements .................. 1↲
1.2.3 Physical Characteristics .................... 1↲
1.2.4 SBX Interface Specifications ................ 1↲
1.2.5 Floppy Disk Interface Specifications ........ 2↲
1.2.6 Jumper Configuration ........................ 3↲
↲
┆b0┆2. PROGRAMMING INFORMATION┆f0┆ ................................. 4↲
2.1 I/O Addressing ..................................... 4↲
2.2 Control Register ................................... 4↲
↲
┆b0┆3. TECHNICAL DESCRIPTION ┆f0┆................................... 6↲
3.1 Block Diagram ...................................... 6↲
3.2 Logic Diagrams and Signal Descriptions ............. 7↲
3.3 PAL Description .................................... 12↲
3.3.1 PAL016 ...................................... 12↲
3.3.2 PAL017 ...................................... 12↲
3.4 Circuit Board Assembly Drawing ..................... 13↲
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┆14┆┆b3┆┆e1┆ ┆0b┆↲
┆b0┆┆a1┆1. GENERAL INFORMATION↲
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┆b0┆┆a1┆1.1 Introduction↲
↲
┆84┆The FDC601 is a floppy disk controller module designed ↓
┆19┆┆89┆┄┄to be mounted on host boards provided with a standard ↓
┆19┆┆89┆┄┄iSBX bus connector. The FDC601 provides the following ↓
┆19┆┆89┆┄┄major features:↲
↲
┆84┆Handels up to four single/double sided drives.↲
↲
┆84┆Supports 8" and 5 1/4", single/double density drives, ↓
┆19┆┆89┆┄┄with programmable selection of drive type and density.↲
↲
Programmable motor on/off control.↲
↲
IBM compatible recording format.↲
↲
DMA or programmed data transfers.↲
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┆b0┆┆a1┆1.2 Specifications↲
↲
┆b0┆┆a1┆1.2.1 Power Requirements↲
↲
+5VDC ┆a1┆+┆e1┆ 0.25V, 1,1 A max.↲
+12VDC ┆a1┆+┆e1┆ 0.6V, 15 mA max.↲
↲
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┆b0┆┆a1┆1.2.2 Environmental Requirements↲
↲
┆84┆Operating temperature 0┆81┆o┆82┆C - 55┆81┆o┆82┆C (32┆81┆o┆82┆F - 131┆81┆o┆82┆F)↲
Relative humidity 20-80% without condensation↲
↲
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┆b0┆┆a1┆1.2.3 Physical Characteristics↲
↲
Width 79 mm (3.11 inches)↲
Length 94 mm (3.70 inches)↲
Component height 10 mm (0.39 inches)↲
Weight 75 g.↲
↲
↲
┆b0┆┆a1┆1.2.4 SBX Interface Specifications↲
↲
┆84┆The SBX interface of the FDC601 is compatible with ↓
┆19┆┆89┆┄┄Intel's iSBX BUS SPECIFICATION for 8-bit SBX modules. ↓
┆19┆┆89┆┄┄The SBX interface signals used by the FDC601 are listed ↓
┆19┆┆89┆┄┄in the table below.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆e1┆┆b0┆SBX Connector, P1↲
↲
┆b0┆PIN GEN. SIGNAL PIN GEN. SIGNAL↲
1 +12V 2 Unused↲
3 0V 4 +5V↲
5 Reset 6 Unused↲
7 Unused 8 0V -,MPST↲
9 MA1 10 Unused↲
11 MA0 12 Unused↲
13 -,IOWRT 14 1-39 MINTR0↲
15 -,IORD 16 Unused↲
17 0V 18 +5V↲
19 1-14 MD7 20 -,MCS1↲
21 1-13 6 22 -,MCS0↲
23 1-12 5 24 Unused↲
25 1-11 4 26 Unused↲
27 1-10 3 28 Unused↲
29 1-9 2 30 Unused↲
31 1-8 1 32 Unused↲
33 1-7 0 34 1-38 MDRQT↲
35 0V 36 +5V↲
↲
MD0-MD7 are bidirectional data lines.↲
↲
┆84┆During DMA data transfers, a read or a write to FDC data ↓
┆19┆┆89┆┄┄register, performs the same function as the DMA ↓
┆19┆┆89┆┄┄acknowleded signal.↲
↲
↲
┆b0┆┆a1┆1.2.5 Floppy Disk Interface Specifications↲
↲
┆84┆The FDC601 interfaces to the disk drives through the 34-↓
┆19┆┆89┆┄┄pin connector J1.↲
↲
J1 mating connector: ┆84┆ITT-CANNON G08D34A3B or equivalent.↲
↲
┆84┆The drive interface is compatible with a standard 5 1/4" ↓
┆19┆┆89┆┄┄floppy disk drive interface. The J1 connector pin ↓
┆19┆┆89┆┄┄assignments are shown in the table below.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆e1┆┆b0┆Disk Drive Interface Connector, J1↲
↲
┆b0┆PIN GEN. SIGNAL PIN SIGNAL↲
1 -,READY 2 0V↲
3 9-7 -,SIDE1SEL 4 0V↲
5 -,RDDATA 6 0V↲
7 -,WRTPROT 8 0V↲
9 -,TRACK00 10 0V↲
11 9-5 -,WRTGATE 12 0V↲
13 9-3 -,WRTDATA 14 0V↲
15 9-18 -,STEP 16 0V↲
17 9-16 -,DIRSEL 18 0V↲
19 9-14 -,MOTORON 20 0V↲
21 5-9 -,DRVSEL2 22 0V↲
23 5-7 -,DRVSEL1 24 0V↲
25 5-5 -,DRVSEL0 26 0V↲
27 -,INDEX 28 0V↲
29 5-3 -,DRVSEL3 30 0V↲
31 9-12 -,HDLOAD 32 0V↲
33 Unused 34 0V↲
↲
Pin 1 is located at the triangle symbol on J1.↲
↲
↲
┆b0┆┆a1┆1.2.6 Jumper Configuration↲
↲
┆84┆The FDC601 requires a READY signal from the disk drives ↓
┆19┆┆89┆┄┄for proper operation. By means of jumper W1 this signal ↓
┆19┆┆89┆┄┄may be selected to be permanently true, allowing the ↓
┆19┆┆89┆┄┄FDC601 to be used with drives which do not provide the ↓
┆19┆┆89┆┄┄READY signal.↲
↲
W1 1-2 READY from drive.↲
2-3 READY always true.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2. PROGRAMMING INFORMATION↲
↲
┆84┆The FDC601 is based on the 1797-02 Floppy Disk ↓
┆19┆┆89┆┄┄Controller IC. Programming of this device is not covered ↓
┆19┆┆89┆┄┄here. Refer to the data sheet for additional ↓
┆19┆┆89┆┄┄information. In addition the FDC601 contains a Control ↓
┆19┆┆89┆┄┄Register which is used to control different programmable ↓
┆19┆┆89┆┄┄features.↲
↲
↲
┆b0┆┆a1┆2.1 I/O Addressing↲
↲
┆84┆The actual I/O addresses for the FDC601 depends on the ↓
┆19┆┆89┆┄┄addresses assigned to the SBX chip select signals MCS0 ↓
┆19┆┆89┆┄┄and MCS1, and to the address lines MA0 - MA2 by the host↓
┆19┆┆89┆┄┄board.↲
↲
┆b0┆-,MCS0, -,MCS1 DEVICE SELECTED↲
00 Not allowed↲
01 FD1797↲
10 Control Register↲
11 None↲
↲
┆b0┆DEVICE MA2-MA0 FUNCTION↲
FD1797 X00 Rd: Status Register↲
Wr: Command Register↲
↲
- X01 Rd: Track Register↲
Wr: Track Register↲
↲
- X10 Rd: Sector Register↲
Wr: Sector Register↲
↲
- X11 Rd: Data Register↲
Wr: Data Register↲
↲
CONTROL XXX Rd: No function↲
REGISTER Wr: Load Control Register↲
↲
X = don't care↲
↲
↲
┆b0┆┆a1┆2.2 Control Register↲
↲
┆84┆The format of the Control Register is described below.↲
↲
┆b0┆Bit 1,0↲
00 Select drive 0↲
01 Select drive 1↲
10 Select drive 2↲
11 Select drive 3↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆Bit 2↲
0 Drive motor off↲
1 Drive motor on↲
↲
┆b0┆Bit 4,3↲
00 No write precompensation↲
01 No write precompensation↲
10 125 ns write precompensation↲
11 250 ns write precompensation↲
↲
┆b0┆Bit 6,5↲
00 5 1/4" dual density drive, 1 MHz FDC clock↲
01 5 1/4" single density drive, 1 MHz FDC clock↲
10 8" dual density drive, 2 MHz FDC clock↲
11 8" single density drive, 2 MHz FDC clock↲
↲
┆b0┆Bit 7↲
X Not used↲
↲
════════════════════════════════════════════════════════════════════════
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┆b0┆┆a1┆3. TECHNICAL DESCRIPTION↲
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┆b0┆┆a1┆3.1 Block Diagram↲
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════════════════════════════════════════════════════════════════════════
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┆b0┆┆a1┆3.2 Logic Diagrams and Signal Descriptions↲
↲
┆84┆The left hand pages of this chapter contains a ↓
┆19┆┆89┆┄┄description of the signals generated on the logic ↓
┆19┆┆89┆┄┄diagram on the corresponding right hand side. The column ↓
┆19┆┆89┆┄┄'Destination' refers to the diagram number, where the ↓
┆19┆┆89┆┄┄signal in question is used. All references between logic ↓
┆19┆┆89┆┄┄diagrams make use of the diagram number in the lower ↓
┆19┆┆89┆┄┄right corner of the diagrams.↲
↲
┆84┆Signal and diagram references are indicated on the logic ↓
┆19┆┆89┆┄┄diagrams as shown below.↲
↲
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Signals preceded with '-,' are active low.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆ SIGNAL DESTINATION DESCRIPTION↲
↲
-,IOWRT╞ 1 ┆84┆I/O Write signal from SBX ↓
┆19┆┆a5┆┄┄connector.↲
↲
MINTR0 1 Interrupt request from FDC↲
↲
MDRQT 1 ┆84┆DMA request from FDC↲
↲
-,MPST 1 ┆84┆Present signal to SBX ↓
┆19┆┆a5┆┄┄connector.↲
↲
WRTGT 2 Write gate signal.↲
↲
FDCWD 2 Write data signal.↲
↲
EARLY 2 Controls the write precom-↲
LATE 2 pensation.↲
↲
STEP 2 ┆84┆Controls the motion of the ↓
┆19┆┆a5┆┄┄R/W heads.↲
↲
DIRC 2 Direction control.↲
↲
SIDE1SEL 2 Side select signal.↲
↲
HDLD 2 Head load signal.↲
↲
DRV0 1 Encoded drive select ↲
DRV1 1 signals.↲
↲
MOTORON 2 ┆84┆Drive motor on/off signal.↲
↲
PRCEN 2 ┆84┆A1 enables the precompensa-↲
╞ ╞ ╞ ╞ ╞ ╞ tion.↲
↲
PRC250 2 ┆84┆Precompensation control.↲
0 = 125ns, 1 = 250ns.↲
↲
-,DDEN 1,2 Dual density select signal.↲
↲
CLKSEL 2 ┆84┆Selects 1/2 MHz clock for ↓
┆19┆┆a5┆┄┄FDC, and controls WD9216 ↓
┆19┆┆a5┆┄┄operation.↲
↲
-,RESET 1 Reset signal.↲
↲
-,DRIVE3 2 Decoded drive select ↲
-,DRIVE0 2 signals.↲
-,DRIVE1 2↲
-,DRIVE2 2↲
↲
════════════════════════════════════════════════════════════════════════
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↲
════════════════════════════════════════════════════════════════════════
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┆b0┆ SIGNAL DESTINATION DESCRIPTION↲
↲
-,DRVSEL3 2 Drive select signals.↲
-,DRVSEL0 2↲
-,DRVSEL1 2↲
-,DRVSEL2 2↲
↲
-,IDXPLS 1 Index pulse.↲
↲
-,TR00 1 Track zero signal.↲
↲
-,WPRT 1 Write protect signal.↲
↲
-,DSKD 2 ┆84┆Read data (data and clock) ↓
┆19┆┆a5┆┄┄from diskette.↲
↲
-,WRTDATA 2 ┆84┆Write data to be written on ↓
┆19┆┆a5┆┄┄the diskette.↲
↲
-,WRTGATE 2 Write gate signal.↲
↲
-,SIDE1SEL 2 ┆84┆Side one select. A 0 selects ↓
┆19┆┆a5┆┄┄side 1 of the diskette.↲
↲
-,STEP 2 ┆84┆Step signal for head ↓
┆19┆┆a5┆┄┄positioning.↲
↲
-,DIRSEL 2 Step direction control.↲
↲
-,MOTORON 2 Drive motor on/off signal.↲
↲
-,HDLOAD 2 Head load signal.↲
↲
REFCLK 2 ┆84┆8 MHz clock for data ↓
┆19┆┆a5┆┄┄separator and write ↓
┆19┆┆a5┆┄┄precompensation circuit.↲
↲
-,SEPD 1 Separated data and clock ↲
SEPCLK 1 from data separator.↲
↲
FDCLK 1 1/2 MHz clock signal to FDC.↲
1 MHz for 5 1/4" drives.↲
2 MHz for 8" drives.↲
↲
WRTDATA 2 Precompensated write data.↲
↲
════════════════════════════════════════════════════════════════════════
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════════════════════════════════════════════════════════════════════════
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┆b0┆┆a1┆3.3 PAL Description↲
↲
┆84┆The following PAL's are used on the FDC601 board.↲
↲
┆b0┆PATTERN No. PAL TYPE POSITION↲
PAT016 PAL16L8 U4↲
PAT017 PAL16R6 U8↲
↲
┆84┆In this section the logical equations for the PAL ↓
┆19┆┆89┆┄┄outputs are listed. The following terminologi is used:↲
↲
-, complement, prefix to signal name.↲
x logical AND↲
+ logical OR↲
= combinatorial equality↲
:= ┆84┆sequential euality, register output after positive ↓
┆19┆┆8d┆┄┄transistion of clock.↲
↲
┆84┆The used PAL types have inverting outputs. The equations ↓
┆19┆┆89┆┄┄therefore specifies the complemented output.↲
↲
↲
┆b0┆┆a1┆3.3.1 PAL016↲
↲
┆84┆This PAL generates write strobe for the control register ↓
┆19┆┆89┆┄┄and decodes the drive select field in the control ↓
┆19┆┆89┆┄┄register.↲
↲
RESET = RESET↲
CTRWRT = I0WRTxMCS1↲
DRIVE3 = DRV1xDRV0↲
DRIVE0 = -,DRV1x-,DRV0↲
DRIVE1 = -,DRV1xDRV0↲
DRIVE2 = DRV1x-,DRV0↲
↲
↲
┆b0┆┆a1┆3.3.2 PAL017↲
↲
┆84┆The PAL generates the control signals CD0 and CD1 for ↓
┆19┆┆89┆┄┄the WD9216 data separator. FDCLK is a 2 MHz (CLKSEL = 1) ↓
┆19┆┆89┆┄┄or a 1 MHZ (CLKSEL = 0) CLOCK for the FDC. WRTDATA is a ↓
┆19┆┆89┆┄┄write pulse with 0, 125 ns or 250 ns precompensation.↲
↲
-,CD0 = DDENxCLKSEL↲
+-,DDENx-,CLKSEL↲
↲
-,CD1 = CLKSEL↲
+DDEN↲
↲
Q0: = -,Q0↲
↲
Q1: = -,Q1x-,Q0↲
+Q1xQ0↲
↲
════════════════════════════════════════════════════════════════════════
↓
FDCLK:= -,Q1x-,Q0xCLKSEL↲
+Q1xQ0xCLKSEL↲
+-,FDCLKx-,Q1x-,Q0x-,CLKSEL↲
+FDCLKxQ1x-,CLKSEL ↲
+FDCLKxQ0x-,CLKSEL↲
↲
╱04002d440a0006000000000201473100000000000000000000000000000000000000000000000000050a0f14191e23282d37414b555f69ff04╱
╱04002d440a0006000000000201413140000000000000000000000000000000000000000000000000050a0f14191e23282d37414b555f69ff04╱
↓
A:= -,WRTDATAx-,Bx-,Ax-,FDCLKx-,Q1x-,QxWDx-,PRCENxWRTGT↲
┆84┆+-,WRTDATAx-,Bx-,Ax-,FDCLKx-,Q1x-,Q0xWDxPRCENxEARLYxWRTGT↲
+-,WRTDATAx-,BxAxWRTGT↲
+-,WRTDATAxBxAxPRCENxPRC250xQ0xWRTGT↲
+WRTDATAx-,AxWRTGT↲
↲
╱04002d440a00060000000002014c3100000000000000000000000000000000000000000000000000050a0f14191e23282d37414b555f69ff04╱
╱04002d440a0006000000000201473100000000000000000000000000000000000000000000000000050a0f14191e23282d37414b555f69ff04╱
↓
B:= -,WRTDATAx-,Bx-,Ax-,FDCLKx-,Q1x-,Q0xWDx-,PRCENxWRTGT↲
┆84┆+-,WRTDATAx-,Bx-,Ax-,FDCLKx-,Q1x-,Q0xWDxPRCENx-,LATExWRTGT↲
╱04002d440a0006000000000201413100000000000000000000000000000000000000000000000000050a0f14191e23282d37414b555f69ff04╱
╱04002d440a00060000000002014c3100000000000000000000000000000000000000000000000000050a0f14191e23282d37414b555f69ff04╱
↓
+-,WRTDATAx-,BxAx-,PRC250xWRTGT↲
+-,WRTDATAx-,BxAxPRC250x-,QxWRTGT↲
+-,WRTDATAxBxAxWRTGT↲
↲
-,WRTDATA:= -,WRTGT↲
+-,WRTDATAx-,B↲
+-,WRTDATAxA↲
+WRTDATAxA↲
↲
╱04002d440a0006000000000201413140000000000000000000000000000000000000000000000000050a0f14191e23282d37414b555f69ff04╱
╱04002d440a0006000000000201413100000000000000000000000000000000000000000000000000050a0f14191e23282d37414b555f69ff04╱
↓
↲
┆b0┆┆a1┆3.4 Circuit Board Assembly Drawing.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
┆1a┆┆1a┆ Rd: Data Register↲